Product Folder Order Now Support & Community Tools & Software Technical Documents LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 LM26480 Dual 2-MHz, 1.5-A Buck Regulators and Dual 300-mA LDOs With Individual Enable and Power Good 1 Features 2 Applications * * * * * * * * * 1 * * * * * * * * Input Voltage: 2.8 V to 5.5 V Compatible with Advanced Applications Processors and FPGAs Two LDOs for Powering Internal Processor Functions and I/Os Precision Internal Reference Thermal Overload Protection Current Overload Protection External Power-On-Reset Function for Buck1 and Buck2 Undervoltage Lockout Detector to Monitor Input Supply Voltage Step-Down DC-DC Converters (Buck) - 1.5-A Output Current - VOUT from: - Buck1 : 0.8 V to 2 V at 1.5 A - Buck2 : 1 V to 3.3 V at 1.5 A - Up to 96% efficiency - 3% FB Voltage Accuracy - 2-MHz PWM Switching Frequency - PWM-to-PFM Automatic Mode Change Under Low Loads - Automatic Soft Start Linear Regulators (LDO) - VOUT of 1 V to 3.5 V - 3% FB Voltage Accuracy - 300-mA Output Current - 25-mV (Typical) Dropout Core Digital Power Applications Processors Peripheral I/O Power Digital Radios Robot Drives Image Transmission Module Low-Power Digital Applications 3 Description The LM26480 is a multi-functional power management unit (PMU), optimized for low-power digital applications. This device integrates two highly efficient 1.5-A step-down DC-DC converters and two 300-mA linear regulators. The DC-DC buck converters provide typical efficiencies of 96%, allowing for minimal power consumption. Features include soft start, undervoltage lockout, current overload protection, thermal overload protection, and an internal power-on-reset (POR) circuit, which monitors the output voltage levels on bucks 1 and 2. Device Information(1) PART NUMBER LM26480 PACKAGE WQFN (24) BODY SIZE (NOM) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VINLDO12 SYNC 1 F ENLDO1 nPOR 100 kY ENLDO2 VIN1 10 F ENSW1 2.2 H ENSW2 SW1 VOUTLDO1 0.47 F R1 C1 R1 C2 R2 10 F FB1 LDO1_FB R2 GND_SW1 VINLDO1 1 F LM26480 VIN2 VINLDO2 10 F 1 F 2.2 H VOUTLDO2 SW2 R1 0.47 F C1 R1 C2 R2 FB2 LDO2_FB R2 10 F GND_SW2 GND_L GND_C DAP AVDD 1 F Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Options....................................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 1 1 1 2 4 5 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions: Bucks ........... 6 Thermal Information .................................................. 6 General Electrical Characteristics............................. 7 Low Dropout Regulators, LDO1 and LDO2 .............. 7 Buck Converters SW1, SW2..................................... 8 I/O Electrical Characteristics..................................... 9 Power On Reset Threshold/Function (POR)............. 9 Typical Characteristics -- LDO............................. 10 Typical Characteristics -- Buck 2.8 V to 5.5 V ..... 11 Typical Characteristics -- Bucks 1 and 2 ............. 12 Typical Characteristics -- Buck 3.6 V................... 13 Detailed Description ............................................ 14 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 14 14 15 22 Application and Implementation ........................ 23 9.1 Application Information............................................ 23 9.2 Typical Application ................................................. 25 10 Power Supply Recommendations ..................... 32 11 Layout................................................................... 32 11.1 Layout Guidelines ................................................. 32 11.2 Layout Example .................................................... 33 12 Device and Documentation Support ................. 34 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support .................................................... Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 34 34 34 34 34 34 34 13 Mechanical, Packaging, and Orderable Information ........................................................... 34 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision M (December 2016) to Revision N Page * Deleted the maximum lead temperature (soldering) from the Absolute Maximum Ratings table .......................................... 6 * Changed the PBUCK1 and PBUCK2 equations in the Junction Temperature section........................................................ 26 * Changed the Electrostatic Discharge Caution statement .................................................................................................... 34 Changes from Revision L (June 2016) to Revision M Page * Changed title of data sheet; add content to Description section ............................................................................................ 1 * Deleted SQ-BF option from Table 1 ...................................................................................................................................... 4 Changes from Revision K (January 2015) to Revision L Page * Added additional items to Applications .................................................................................................................................. 1 * Changed "n" to "eN" as symbol for supply output noise in Low Dropout Regulators EC table............................................. 7 Changes from Revision J (October 2014) to Revision K Page * Changed Handling Ratings table to ESD Ratings table ........................................................................................................ 6 * Added full Thermal Information values. .................................................................................................................................. 6 * Added additional paragraph to Functional Description subsection to describe enable signal. ............................................ 16 2 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 Changes from Revision I (May 2013) to Revision J * Page Added Device Information and ESD Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section. ................................ 1 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 3 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 5 Device Options Table 1. Default Options ORDER SUFFIX SPEC OSCILLATOR FREQUENCY BUCK MODES nPOR DELAY UVLO SYNC AECQ SQ-AA NOPB 2 MHz Auto-Mode 60 ms Enabled Disabled No Table 2. Power Block Operation (1) 4 POWER BLOCK INPUT (1) ENABLED DISABLED NOTE VINLDO12 VIN+ VIN+ Always powered AVDD VIN+ VIN+ Always powered VIN1 VIN+ VIN+ or 0V VIN2 VIN+ VIN+ or 0V VINLDO1 VIN+ VIN+ If enabled, minimum VIN is 1.74 V VINLDO2 VIN+ VIN+ If enabled, minimum VIN is 1.74 V VIN+ is the largest potential voltage on the device. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 6 Pin Configuration and Functions RTW Package 24-Pin WQFN Top View 18 17 16 15 14 13 19 12 20 11 21 10 22 9 23 8 24 7 1 2 3 4 5 6 Pin Functions PIN NO. NAME I/O TYPE (1) DESCRIPTION Analog power for internal functions (VREF, BIAS, I2C, Logic) 1 VINLDO12 I P 2 SYNC I G/(D) 3 NPOR O D nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100-k pullup resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See Flexible Power-On Reset (Power Good with Delay) for more information. 4 GND_SW1 G G Buck1 NMOS power ground 5 SW1 O P Buck1 switcher output pin 6 VIN1 I P Power in from either DC source or battery to Buck1 7 ENSW1 I D Enable pin for Buck1 switcher, a logic HIGH enables Buck1. Pin cannot be left floating. Frequency synchronization pin, which allows the user to connect an external clock signal to synchronize the PMIC internal oscillator. Default OFF and must be grounded when not used. Part number LM26480SQ-BF has this feature enabled. Contact Texas Instruments Sales Office/Distributors for availability of LM26480SQ-BF. 8 FB1 I A Buck1 input feedback terminal 9 GND_C G G Non-switching core ground pin 10 AVDD I P Analog Power for Buck converters 11 FB2 I A Buck2 input feedback terminal 12 ENSW2 I D Enable pin for Buck2 switcher, a logic HIGH enables Buck2. Pin cannot be left floating. 13 VIN2 I P Power in from either DC source or Battery to Buck2 14 SW2 O P Buck2 switcher output pin 15 GND_SW2 G G Buck2 NMOS 16 ENLDO2 I D LDO2 enable pin, a logic HIGH enables LDO2. Pin cannot be left floating. 17 ENLDO1 I D LDO1 enable pin, a logic HIGH enables LDO1. Pin cannot be left floating. 18 GND_L G G LDO ground 19 VINLDO1 I P Power in from either DC source or battery to LDO1 20 LDO1 O P LDO1 Output 21 FBL1 I A LDO1 feedback terminal 22 FBL2 I A LDO2 feedback terminal 23 LDO2 O P LDO output 24 VINLDO2 I P Power in from either DC source or battery to LDO2. DAP G G Connection is not necessary for electrical performance, but it is recommended for better thermal dissipation. DAP (1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin, D: Digital. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 5 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VINLDO12, VIN1, AVDD, VIN2, VINLDO1, VINLDO2, ENSW1, FB1, FB2, ENSW2, ENLDO1, ENLDO2, SYNC, FBL1, FBL2 MIN MAX -0.3 6 UNIT V GND to GND SLUG 0.3 Power dissipation, PD_MAX (TA = 85C, TMAX = 125C) (3) 1.17 W 150 C 150 C Junction temperature, TJ-MAX -65 Storage temperature, Tstg (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions: Bucks. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (RJA), as given by the following equation: TA-MAX = TJ-MAX-OP - (RJA x PD-MAX). See Application and Implementation. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions: Bucks over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN 2.8 5.5 VEN 0 (VIN + 0.3 V) Junction temperature, TJ -40 125 C Ambient temperature, TA (1) -40 85 C (1) V Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. 7.4 Thermal Information LM26480 THERMAL METRIC (1) RTW (WQFN) UNIT 24 PINS RJA Junction-to-ambient thermal resistance 32.7 C/W RJC(top) Junction-to-case (top) thermal resistance 31.2 C/W RJB Junction-to-board thermal resistance 11.2 C/W JT Junction-to-top characterization parameter 0.2 C/W JB Junction-to-board characterization parameter 11.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 0.4 C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 7.5 General Electrical Characteristics Unless otherwise noted, VIN = 3.6 V. Values and limits apply for TJ = 25C. (1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ VINLDO12 shutdown current VIN = 3.6 V 0.5 A VPOR Power-on reset threshold VDD falling edge (4) 1.9 V TSD Thermal shutdown threshold See (5) 160 TSDH Thermal shutdown hysteresis See (5) 20 UVLO Undervoltage lockout Rising 2.9 Failing 2.7 (1) (2) (3) (4) (5) C V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm. VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range. Specified by design. Not production tested. 7.6 Low Dropout Regulators, LDO1 and LDO2 Unless otherwise noted, VIN = 3.6 V, CIN = 1 F, COUT = 0.47 F, and values and limits apply for TJ = 25C, unless otherwise specified. (1) (2) (3) (4) PARAMETER VIN VFB MIN TYP 1.74 5.5 FB voltage accuracy TJ = -40C to 125C -3% 3% Line regulation VIN = (VOUT + 0.3 V) to 5 V Load current = 1 mA TJ = -40C to 125C Load regulation VIN = 3.6 V, TJ = -40C to 125C Load current = 1 mA to IMAX Short circuit current limit LDO1-2, VOUT = 0 V VIN - VOUT Dropout voltage Load current = 50 mA (7) TJ = -40C to 125C PSRR Power supply ripple rejection F = 10 kHz, load current = IMAX eN Supply output noise 10 Hz < F < 100 kHz Quiescent current on IOUT = 0 mA IOUT = 300 mA (1) (2) (3) (4) (5) (6) (7) %/V 0.011 %/mA mA 25 200 mV 45 dB 150 VRMS 40 150 60 IOUT = 300 mA, -40C TJ 125C TON V 0.15 500 IOUT = 0 mA, -40C TJ 125C Quiescent current on UNIT (6) Load current = 50 mA (7) IQ MAX VINLDO1 and VINLDO2 PMOS pins (5) TJ = -40C to 125C VOUT ISC TEST CONDITIONS Operational voltage range A 200 Quiescent current off EN is de-asserted 0.03 Turnon time Start-up from shutdown 300 1 A sec All voltages are with respect to the potential at the GND pin. Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the most likely norm. CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The device maintains a stable, regulated output voltage without a load. Pins 24, 19 can operate from VIN min of 1.74 V to a VIN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. VIN minimum for line regulation values is 1.8 V. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 7 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com Low Dropout Regulators, LDO1 and LDO2 (continued) Unless otherwise noted, VIN = 3.6 V, CIN = 1 F, COUT = 0.47 F, and values and limits apply for TJ = 25C, unless otherwise specified. (1)(2)(3)(4) PARAMETER TEST CONDITIONS MIN Capacitance for stability 0C TJ 125C COUT Output capacitor TYP MAX UNIT 0.47 -40C TJ 125C 0.33 -40C TJ 125C 0.68 Equivalent series resistance (ESR) TJ = -40C to 125C F 1 5 500 m 7.7 Buck Converters SW1, SW2 Unless otherwise noted, VIN = 3.6 V, CIN = 10 F, COUT = 10 F, LOUT = 2.2 H, and limits apply for TJ = 25C, unless otherwise specified. (1) (2) (3) (4) PARAMETER VFB (5) TEST CONDITIONS VOUT Line regulation 2.8 V < VIN < 5.5 V IOUT = 10 mA Load regulation 100 mA < IOUT < IMAX Eff Efficiency Load current = 250 mA ISHDN Shutdown supply current EN is de-asserted MAX 0.089 %/V 0.0013 %/mA 96% 1 2.4 2.1 2.5 Buck1 peak switching current limit 2 2.4 Buck2 peak switching current limit 2 2.4 1.6 Default oscillator frequency = 2.1 MHz Default oscillator frequency = 2.1 MHz TJ = -40C to 125C No load PFM mode 33 A 2 mA RDSON (P) Pin-pin resistance PFET 200 400 RDSON (N) Pin-pin resistance NFET 180 400 TON Turnon time Start-up from shutdown CIN Input capacitor Capacitance for stability 10 COUT Output capacitor Capacitance for stability 10 8 MHz A Quiescent current on (6) (3) (4) (5) (6) A 1.7 IQ (1) (2) UNIT 3% 2 Internal oscillator frequency IPEAK TYP 0.01 Default oscillator frequency = 2 MHz OSC MIN -3% Feedback voltage No load PWM mode (forced PWM) 500 m sec F All voltages are with respect to the potential at the GND pin. Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the most likely norm. CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The device maintains a stable, regulated output voltage without a load. VIN VOUT + RDSON(P) (IOUT + 1/2 IRIPPLE). If these conditions are not met, voltage regulation will degrade as load increases. Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 7.8 I/O Electrical Characteristics Limits apply over the entire junction temperature range for operation, TJ = -40C to +125C. PARAMETER VIL Input low level VIH Input high level TEST CONDITIONS MIN TYP MAX UNIT 0.4 0.7 x VDD V 7.9 Power On Reset Threshold/Function (POR) PARAMETER TEST CONDITIONS MIN TYP nPOR nPOR = Power-on reset for Buck1 and Buck2 Default = 60 ms nPOR Threshold Percentage of target voltage Buck1 or Buck2 VBUCK1 AND VBUCK2 rising 92% VBUCK1 OR VBUCK2 falling 82% VOL Output level low Load = IOL = 500 A 0.23 MAX UNIT 60 ms Default = 130 s 130 s 0.5 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 V 9 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 2.00 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 VOUT CHANGE (%) VOUT CHANGE (%) 7.10 Typical Characteristics -- LDO 2.00 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (C) TEMPERATURE (C) VIN = 3.6 V VOUT = 2.5 V Load = 100 mA Figure 1. Output Voltage Change vs Temperature (LDO1) VIN = 3.6 V VOUT = 2.5 V Load = 0 to 150 mA VIN = 3.6 V VOUT = 2.5 V VIN = 3.6 V VOUT = 2.5 V Load = 150 to 300 mA Figure 4. Load Transient Load = 100 mA VIN = 3.6 to 4.2 V Figure 5. Line Transient (LDO1) 10 Load = 100 mA Figure 2. Output Voltage Change vs Temperature (LDO2) Figure 3. Load Transient VIN = 3.6 to 4.2 V VOUT = 1.8 V Submit Documentation Feedback VOUT = 1.8 V Load = 150 mA Figure 6. Line Transient (LDO2) Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 7.11 Typical Characteristics -- Buck 2.8 V to 5.5 V 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -40 VIN = 5.5V VOUT (V) TEMPERATURE (C) VIN = 2.8 V to 5.5 V, TA = 25C VIN = 3.6V VIN = 2.8V -20 0 20 40 60 80 1.250 1.245 1.240 1.235 1.230 1.225 1.220 1.215 1.210 100 LOAD = 1.5A LOAD = 750 mA LOAD = 20 mA 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) SHUTDOWN CURRENT (nA) VOUT = 1.2 V Figure 7. Shutdown Current vs. Temp Figure 8. Output Voltage vs. Supply Voltage 2.10 2.09 2.08 2.07 2.06 2.05 2.04 2.03 2.02 2.01 2.00 LOAD = 1.5A 3.080 LOAD = 750 mA LOAD = 750 mA VOUT (V) VOUT (V) 3.090 LOAD = 1.5A LOAD = 20 mA 3.070 3.060 3.050 LOAD = 20 mA 3.040 3.0 3.5 4.0 4.5 5.0 5.5 4.0 4.3 4.6 4.9 5.2 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VOUT = 2 V VOUT = 3 V Figure 9. Output Voltage vs. Supply Voltage Figure 10. Output Voltage vs. Supply Voltage Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 11 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 7.12 Typical Characteristics -- Bucks 1 and 2 Output current transitions from PFM mode to PWM mode for Buck 1. 100 100 VIN = 2.8V EFFICIENCY (%) EFFICIENCY (%) 90 VIN = 3.6V 80 70 VIN = 5.5V 60 50 90 VIN = 2.8V VIN = 3.6V 80 VIN = 5.5V 70 60 50 1 10 100 1000 10000 1 10 OUTPUT CURRENT (mA) VOUT = 1.2 V 100 1000 10000 OUTPUT CURRENT (mA) L = 2.2 H VOUT = 2 V Figure 11. Efficiency vs. Output Current L = 2.2 H Figure 12. Efficiency vs. Output Current Output Current transitions from PWM mode to PFM mode for Buck 2. 100 100 90 VIN = 5.5V EFFICIENCY (%) EFFICIENCY (%) 90 VIN = 3.6V VIN = 4.2V VIN = 5.5V 80 70 60 VIN = 4.2V 80 70 60 50 1 10 100 1000 10000 50 1 10 OUTPUT CURRENT (mA) VOUT = 3 V L = 2.2 H VOUT = 3.5 V Figure 13. Efficiency vs. Output Current 12 100 1000 10000 OUTPUT CURRENT (mA) Submit Documentation Feedback L = 2.2 H Figure 14. Efficiency vs. Output Current Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 7.13 Typical Characteristics -- Buck 3.6 V VIN= 3.6 V, TA = 25C, VOUT = 1.2 V unless otherwise noted VOUT = 1.2 V (PWM To PFM) VOUT = 1.2 V (PWM Mode) Figure 15. Load Transient Response VIN = 3.6 to 4.2 V VOUT = 1.2 V Load = 250 mA Figure 16. Mode Change By Load Transients VIN = 3 to 3.6 V VOUT = 3 V Load = 250 mA Figure 18. Line Transient Response Figure 17. Line Transient Response Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 13 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 8 Detailed Description 8.1 Overview The LM26480 is a multi-functional power management unit (PMU), optimized for low-power digital applications. This device integrates two highly efficient 1.5-A step-down DC-DC converters and two 300-mA linear regulators. 8.2 Functional Block Diagram 10 F 10 F 19 VIN1 10 1 F VIN2 24 1 F VINLDO1 1 1 F AVDD 1 F VINLDO2 CVDD 4.7 F VINLDO12 Input Voltage 13 6 LSW 1 2.2 H OSC BUCK1 AVDD 2 SYNC VBUCK1 5 SW1 FB1 8 C1 R1 C2 R2 1.2V CSW1 10 F 17 ENLDO1 LSW 2 2.2 H Power ONOFF Logic 16 ENLDO2 7 ENSW1 BUCK2 AVDD VBUCK2 14 SW2 FB2 11 C1 R1 C2 R2 3.3V CSW2 10 F 12 VINLDO1 ENSW2 Thermal Shutdown LDO1 LDO1 RESET VINLDO12 20 FBL1 21 R1 3.3V CLDO1 0.47 F R2 BIAS VINLDO2 LDO2 LDO2 Logic Control and registers 23 FBL2 22 FB1 FB2 1.8V R1 CLDO2 0.47 F R2 VDD 100k Power On Reset 4 GND_SW1 15 GND_SW2 9 GND_C 3 nPOR 18 GND_L Copyright (c) 2016, Texas Instruments Incorporated 14 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 8.3 Feature Description 8.3.1 DC-DC Converters The LM26480 provides the DC-DC converters that supply the various power needs of the application by means of two linear low dropout regulators, LDO1 and LDO2, and two buck converters, SW1 and SW2. Table 3 lists the output characteristics of the various regulators. Table 3. Supply Specification OUTPUT SUPPLY LOAD LDO1 LDO2 VOUT RANGE (V) IMAX MAXIMUM OUTPUT CURRENT (mA) analog 1 to 3.5 300 analog 1 to 3.5 300 SW1 digital 0.8 to 2 1500 SW2 digital 1 to 3.3 1500 8.3.1.1 Linear Low Dropout Regulators (LDOs) LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements. LDO1 and LDO2 are enabled through the ENLDO pin. VLDO VIN LDO_FB + ENLDO VREF GND Figure 19. LDO Block Diagram 8.3.1.1.1 No-Load Stability The LDOs remain stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications. 8.3.1.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters 8.3.1.2.1 Functional Description The LM26480 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 1500 mA depending on the input voltage and output voltage (voltage headroom), and the inductor chosen (maximum current capability). There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode handles current loads of approximately 70 mA or higher, delivering voltage precision of 3% with 90% efficiency or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current consumption (IQ = 33 A typical) and a longer battery life. The Standby operating mode turns off the device, offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced through the setting of the buck control register. Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. Additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload protection. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 15 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com The enable signal may be employed immediately after VIN is applied to the device. However, VIN must be stable for approximately 8 ms before enable single be asserted high to ensure internal bias, reference, and the flexible POR timing are stabilized. This initial delay is necessary only upon first time device power on. 8.3.1.2.2 Circuit Operation Description A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of VIN - VOUT (1) L by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of -VOUT (2) L The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. 8.3.1.2.3 Sync Function The LM26480SQ-BF is the only version of the part that has the ability to use an external oscillator. The source must be 13 MHz nominal and operate within a range of 15.6 MHz and 10.4 MHz, proportionally the same limits as the 2-MHz internal oscillator. The LM26480SQ-BF has an internal divider which will divide the speed down by 6.5 to the nominal 2 MHz and use it for the regulators. This SYNC function replaces the internal oscillator and works in forced PWM only. The buck regulators no longer have the PFM function enabled. When the LM26480SQ-BF is sold with this feature enabled, the part will not function without the external oscillator present. Contact Texas Instruments Sales Office/Distributors for availability of LM26480SQ-BF. 8.3.1.2.4 PWM Operation During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input voltage is introduced. 8.3.1.2.5 Internal Synchronous Rectification While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 8.3.1.2.6 Current Limiting A current limit feature allows the converter to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 2 A for both bucks (typical). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. 8.3.1.2.7 PFM Operation At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: 1. The inductor current becomes discontinuous, or 16 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 2. The peak PMOS switch current drops below the IMODE level. (Typically IMODE < 66 mA + VIN ) 160: (3) During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the `high' PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the high PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: IPFM = 66 mA + VIN 80: (4) Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the `high' PFM comparator threshold (see Figure 20), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the `high' PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this `sleep' mode is less than 30 A, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the low PFM threshold, the cycle repeats to restore the output voltage to approximately 1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode (see Figure 20) causing the output voltage to fall below the `low2' PFM threshold, the part will automatically transition into fixed-frequency PWM mode. 8.3.1.2.8 SW1, SW2 Control SW1 and SW2 are enabled/disabled through the external enable pins. The Modulation mode PWM/PFM is by default automatic and depends on the load (see Functional Description). The modulation mode can be factory trimmed, forcing the buck to operate in PWM mode regardless of the load condition. High PFM Threshold ~1.016 * Vout PFM Mode at Light Load Load current increases Low1 PFM Threshold ~1.008 * Vout ZA xi s High PFM Voltage Threshold reached, go into sleep mode Low PFM Threshold, turn on PFET Low2 PFM Threshold, switch back to PWMmode Zs Axi Pfet on until Ipfm limit reached Nfet on drains inductor current until I inductor = 0 Current load increases, draws Vout towards Low2 PFM Threshold Low2 PFM Threshold Vout PWM Mode at Moderate to Heavy Loads Figure 20. PWM/PFM Modulation 8.3.1.2.9 Shutdown Mode During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is activated. Disabling the converter during the system power up and undervoltage conditions is recommended when the supply is less than 2.8 V. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 17 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 8.3.1.2.10 Soft Start The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The two LM26480 buck converters have a soft-start circuit that limits inrush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches 2.8 V. Soft start is implemented by increasing switch current limit in steps of 250 mA, 500 mA, 950 mA, and 2 A for both bucks (typical switch current limit). The startup time thereby depends on the output capacitor and load current demanded at start-up. 8.3.1.2.11 Low Dropout Operation The LM26480 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD x (RDSON, PFET + RINDUCTOR) + VOUT where * * * ILOAD = Load current RDSON, PFET = Drain to source resistance of RINDUCTOR = Inductor resistance PFET switch in the triode region (5) 8.3.1.2.12 Flexible Power-On Reset (Power Good with Delay) The LM26480 is equipped with an internal Power-On-Reset (POR) circuit which monitors the output voltage levels on bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs are below 92% of the rising value, or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and nPOR is enabled is (130 s, 60 ms, 100 ms, 200 ms), 60 ms by default. For any other delay option, other than the default, please consult a Texas Instruments Sales Representative. The system designer can choose the external pull-up resistor (value such as 100 k) for the nPOR pin. 18 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 t1 t2 Case 1 EN1 EN2 RDY1 RDY2 0V Counter delay NPOR t1 t2 Case 2 EN1 EN2 0V RDY1 RDY2 Counter delay NPOR t1 t2 Case 3 EN1 EN2 RDY1 RDY2 Counter delay NPOR Figure 21. nPOR with Counter Delay Figure 21 shows the simplest application of the POR where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR will stay LOW, indicating a power fail mode. Case 2 indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW. Case 3 shows a typical application of the POR, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), the nPOR signal will trigger a programmable delay before going HIGH, as explained below. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 19 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 t0 t1 www.ti.com t2 t3 t4 EN1 RDY1 NPOR Counter delay Counter delay EN2 RDY2 Figure 22. Faults Occurring in Counter Delay after Start-Up Figure 22 details the Power Good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows: Table 4. Comparator Trim COMPARATOR LEVEL BUCK SUPPLY LEVEL HIGH Greater than 92% LOW Less than 82% The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also work for EN2 and RDY2 and vice versa. If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (130 s, 60 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. NPOR is then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this interval the nPOR signal ignores this event. If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again. 20 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 t0 t1 t2 t3 t4 EN1 RDY1 Counter delay NPOR Case 1: EN2 RDY2 Mask Time Counter delay Mask Window NPOR Case 2: EN2 RDY2 0V Mask Window Mask Time Counter delay NPOR Figure 23. nPOR Mask Window In Case 1 (Figure 23), we see that case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. NPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards will depend on the status of both RDY1 and RDY2 lines. In Case 2, we see the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 21 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com Delay Mask Counter EN1 RDY1 EN2 RDY2 S Q R Q Delay NPOR POR Delay Mask Counter Figure 24. Design Implementation of the Flexible Power-On Reset Design implementation of the flexible power-on reset. An internal power-on reset of the IC is used with EN1 and EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S = R = 1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to generate outputs to the final AND gate to generate the nPOR. 8.3.1.2.13 Undervoltage Lockout The LM26480 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the raw input supply voltage (VINLDO12) and automatically disable the four voltage regulators whenever this supply voltage is less than 2.8 VDC. The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC trip point for a VIN OK - Not OK detector. This VIN OK signal is then used to gate the enable signals to the four regulators of the LM26480. When VINLDO12 is greater than 2.8 VDC the four enables control the four regulators; when VINLDO12 is less than 2.8 VDC the four regulators are disabled by the VIN detector being in the Not OK state. The circuit has built-in hysteresis to prevent undesired signal variations. 8.4 Device Functional Modes * * * 22 External Programmable Output Up to 1.5 A output current for both Bucks External Power-on-Reset function for Buck1 and Buck2 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 External Component Selection Buck LDO 0.47 F R1 LM26480 Buck_ FB LDO_FB R2 10 F R1 C1 C2 R2 Copyright (c) 2016, Texas Instruments Incorporated Figure 25. LDO Block Diagram Table 5. Buck External Component Selection TARGET VOUT (V) IDEAL RESISTOR VALUES COMMON R VALUES FEEDBACK CAPACITORS ACTUAL VOUT w/ COM/R (V) ACTUAL VOUT DELTA FROM TARGET (V) C1 (pF) C2 (pF) POWER RAIL R1 (K) R2 (K) R1 (K) R2 (K) 0.8 120 200 121 200 0.803 0.002 15 none Buck1 0.9 160 200 162 200 0.905 0.005 15 none Only 1 200 200 200 200 1 0 15 none ^ 1.1 240 200 240 200 1.1 0 15 none | 1.2 280 200 280 200 1.2 0 12 none | 1.3 320 200 324 200 1.31 0.01 12 none Buck1 1.4 360 200 357 200 1.393 -0.008 10 none And 1.5 400 200 402 200 1.505 0.005 10 none Buck2 1.6 440 200 442 200 1.605 0.005 8.2 none | 1.7 427 178 432 178 1.713 0.013 8.2 none | 1.8 463 178 464 178 1.803 0.003 8.2 none | 1.9 498 178 499 178 1.902 0.002 8.2 none | 2 450 150 453 150 2.01 0.01 8.2 none > 2.1 480 150 475 150 2.083 -0.017 8.2 none ^ 2.2 422 124 422 124 2.202 0.002 8.2 none | 2.3 446 124 442 124 2.282 -0.018 8.2 none | 2.4 471 124 475 124 2.415 0.015 8.2 none | 2.5 400 100 402 100 2.51 0.01 8.2 none | 2.6 420 100 422 100 2.61 0.01 8.2 none | 2.7 440 100 442 100 2.71 0.01 8.2 33 Buck2 2.8 460 100 464 100 2.82 0.02 8.2 33 Only 2.9 480 100 475 100 2.875 -0.025 8.2 33 | 3 500 100 499 100 2.995 -0.005 6.8 33 | 3.1 520 100 523 100 3.115 0.015 6.8 33 | 3.2 540 100 536 100 3.18 -0.02 6.8 33 | 3.3 560 100 562 100 3.31 0.01 6.8 33 | Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 23 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com The output voltages of the bucks of the LM26480 are established by the feedback resistor dividers R1 and R2 shown on the application circuit above. Equation 6 shows how to determine what value of V is: VOUT = VFB (R1+R2)/R2 where * VFB is the voltage on the Buck FBx pin. (6) The Buck control loop will force the voltage on VFB to be 0.50 V 3%. Table 5 shows ideal resistor values to establish buck voltages from 0.8 V to 3.3 V along with common resistor values to establish these voltages. Common resistors do not always produce the target value, error is given in the delta column. In addition to the resistor feedback, capacitor feedback C1 is always required, and depending on the output voltage capacitor C2 is also required. INDUCTOR VALUE UNIT DESCRIPTION NOTES LSW1,2 2.2 H SW1,2 inductor DCR 70 m 9.1.2 Feedback Resistors for LDOs See Figure 25. Table 6. LDO External Component Selection TARGET VOUT (V) 24 IDEAL RESISTOR VALUES COMMON R VALUES ACTUAl VOUT W/Com/R (V) R1 (K) R2 (K) R1 (K) R2 (K) 1 200 200 200 200 1 1.1 240 200 240 200 1.1 1.2 280 200 280 200 1.2 1.3 320 200 324 200 1.31 1.4 360 200 357 200 1.393 1.5 400 200 402 200 1.505 1.6 440 200 442 200 1.605 1.7 480 200 562 232 1.711 1.8 520 200 604 232 1.802 1.9 560 200 562 200 1.905 2 600 200 604 200 2.01 2.1 640 200 715 221 2.118 2.2 680 200 681 200 2.203 2.3 720 200 806 226 2.283 2.4 760 200 845 221 2.412 2.5 800 200 750 187 2.505 2.6 840 200 909 215 2.614 2.7 880 200 1100 249 2.709 2.8 920 200 1150 249 2.809 2.9 960 200 1210 255 2.873 3 1000 200 1000 200 3 3.1 1040 200 1000 191 3.118 3.2 1080 200 1000 187 3.174 3.3 1120 200 1210 215 3.314 3.4 1160 200 1210 210 3.381 3.5 1200 200 1210 200 3.525 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 The output voltages of the LDOs of the LM26480 are established by the feedback resistor dividers R1 and R2 shown on Figure 25 above. Equation 7 shows calculation for VOUT: VOUT = VFB(R1+R2)/R2 where * VFB is the voltage on the LDOX_FB pin. (7) The LDO control loop will force the voltage on VFB to be 0.50 V 3%. The above table shows ideal resistor values to establish LDO voltages from 1 V to 3.5 V along with common resistor values to establish these voltages. Common resistors do not always produce the target value, error is given in the final column. To keep the power consumed by the feedback network low it is recommended that R2 be established as about 200 k. Lesser values of R2 are okay at the users discretion. 9.2 Typical Application VINLDO12 SYNC 1 F ENLDO1 nPOR 100 kY ENLDO2 VIN1 10 F ENSW1 2.2 H ENSW2 SW1 VOUTLDO1 0.47 F C1 R1 C2 R2 10 F FB1 R1 LDO1_FB R2 GND_SW1 VINLDO1 1 F LM26480 VIN2 VINLDO2 10 F 1 F 2.2 H VOUTLDO2 SW2 R1 0.47 F C1 R1 C2 R2 FB2 LDO2_FB R2 10 F GND_SW2 GND_L GND_C DAP AVDD 1 F Copyright (c) 2016, Texas Instruments Incorporated Figure 26. LM26480 Application Circuit Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 25 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com Typical Application (continued) 9.2.1 Design Requirements 9.2.1.1 High VIN- High Load Operation Additional information is provided when the device is operated at extremes of VIN and regulator loads. These are described in terms of the junction temperature and buck output ripple management. 9.2.1.2 Junction Temperature The maximum junction temperature TJ-MAX-OP of 125C of the device package. Equation 8 and Equation 9 demonstrate junction temperature determination, ambient temperature TA-MAX, and total chip power must be controlled to keep TJ below this maximum: TJ-MAX-OP = TA-MAX + (RJA) [C/Watt] x (PD-MAX) [Watts] (8) Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor amount for chip overhead. Chip overhead is bias, TSD, and LDO analog. PD MAX PLDO1 PLDO2 PBUCK1 PBUCK2 (0.0001A VIN) [Watts] Power dissipation of LDO1(PLDO1) (VINLDO1 VOUTLDO1) IOUTLDO1 [V A] Power dissipation of LDO2 (PLDO2) (VINLDO2 VOUTLDO2) IOUTLDO2 [V A] Power dissipation of Buck1 (PBuck1) PIN POUT VOUTBUCK1 IOUTBUCK1 (1/ K1 1) [V A] K1 efficiency of Buck1 Power dissipation of Buck2 (PBuck2) PIN POUT VOUTBUCK2 IOUTBUCK2 (1/ K2 1) [V A] K2 efficiency of Buck2 where * is the efficiency for the specific condition is taken from efficiency graphs. (9) If VIN and ILOAD increase, the output ripple associated with the buck regulators also increases. This mainly occurs with VIN > 5.2 V and a load current greater than 1.2 A. To ensure operation in this area of operation, TI recommends that the system designer circumvents the output ripple issues by installing Schottky diodes on the bucks(s) that are expected to perform under these extreme conditions. 9.2.2 Detailed Design Procedure 9.2.2.1 Output Inductors and Capacitors for SW1 AND SW2 There are several design considerations related to the selection of output inductors and capacitors: * Load transient response; * Stability; * Efficiency; * Output ripple voltage; and * Overcurrent ruggedness. The LM26480 has been optimized for use with nominal values 2.2 H and 10 F. If other values are needed for the design, please contact Texas Instruments sales with any concerns. 9.2.2.1.1 Inductor Selection for SW1 and SW2 TI recommends a nominal inductor value of 2.2 H. It is important to ensure the inductor core does not saturate during any foreseeable operational situation. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25C, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. There are two methods to choose the inductor saturation current rating: Recommended method: 26 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 Typical Application (continued) The best way to ensure the inductor does not saturate is to choose an inductor that has saturation current rating greater than the maximum LM26480 current limit of 2.4 A. In this case the device prevents inductor saturation. Alternate method: If the recommended approach cannot be used, care must be taken to ensure that the saturation current is greater than the peak inductor current: ISAT > ILPEAK ILPEAK = IOUTMAX + IRIPPLE 2 D x (VIN VOUT) LxF VOUT D= VIN x EFF IRIPPLE = * * * * * * * * * * ISAT: Inductor saturation current at operating temperature ILPEAK: Peak inductor current during worst case conditions IOUTMAX: Maximum average inductor current IRIPPLE: Peak-to-peak inductor current VOUT: Output voltage VIN: Input voltage L: Inductor value in Henries at IOUTMAX F: Switching frequency, Hertz D: Estimated duty factor EFF: Estimated power supply efficiency (10) ISAT may not be exceeded during any operation, including transients, start-up, high temperature, worst-case conditions, etc. 9.2.2.1.2 Suggested Inductors and Their Suppliers MODEL MANUFACTURER DIMENSIONS (mm) DCR (max) (m) ISATURATION (A) (values approx.) DO3314-222MX Coilcraft 3.3 x 3.3 x 1.4 200 1.8 LPO3310-222MX Coilcraft 3.3 x 3.3 x 1 150 1.3 ELL6PG2R2N Panasonic 6x6x2 37 2.2 ELC6GN2R2N Panasonic 6 x 6 x 1.5 53 1.9 CDRH2D14NP-2R2NC Sumida 3.2 x 3.2 x 1.5 94 1.5 9.2.2.2 Output Capacitor Selection for SW1 and SW2 TI recommends a ceramic output capacitor of 10 F, 6.3 V with an ESR of less than 500 m. Output ripple can be estimated from the vector sum of the reactive (capacitor) voltage component and the real (ESR) voltage component of the output capacitor. IRIPPLE 8 x F x COUT VCOUT = VROUT = IRIPPLE x ESRCOUT VPPOUT = * * * VCOUT2 + VROUT2 VCOUT: Estimated reactive output ripple VROUT: Estimated real output ripple VPPOUT: Estimated peak-to-peak output ripple (11) The output capacitor needs to be mounted as close as possible to the output pin of the device. For better temperature performance, X7R or X5R types are recommended. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 27 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com DC bias characteristics vary from manufacturer to manufacturer and by case size. DC bias curves should be requested from them as part of the capacitor selection process. ESR is typically higher for smaller packages. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (ESRCOUT). ESRCOUT is frequency dependent as well as temperature dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature. 9.2.2.3 Input Capacitor Selection for SW1 and SW2 It is required to use a ceramic input capacitor of at least 4.7 F and 6.3 V with an ESR of less than 500 m. The input power source supplies average current continuously. During the PFET switch on-time, however, the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by the input capacitor. A simplified "worst case" assumption is that all of the PFET current is supplied by the input capacitor. This will result in conservative estimates of input ripple voltage and capacitor RMS current. Input ripple voltage is estimated in Equation 12: IOUT x D VPPIN = C x F + IOUT x ESRCIN IN * * * * VPPIN: Estimated peak-to-peak input ripple voltage IOUT: Output current, Amps CIN: Input capacitor value, Farads ESRIN: Input capacitor ESR, Ohms (12) This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate RMS current rating. Capacitor RMS current estimated as follows: * D x IOUT2 + (c) IRIPPLE 12 2 (c) IRMSCIN = IRSCIN: Estimated input capacitor RMS current (13) Table 7. Suggested Capacitors and Their Suppliers MODEL TYPE VENDOR VOLTAGE RATING (V) CASE SIZE C2012X5R0J475K Ceramic, X5R TDK 6.3 0805, (2012) 4.7 F for CIN JMK212BJ475K Ceramic, X5R Taiyo-Yuden 6.3 0805, (2012) GRM21BR60J475K Ceramic, X5R Murata 6.3 0805, (2012) C1608X5R0J475K Ceramic, X5R TDK 6.3 0603, (1608) 10 F for COUT GRM21BR60J106K Ceramic, X5R Murata 6.3 0805, (2012) JMK212BJ106K Ceramic, X5R Taiyo-Yuden 6.3 0805, (2012) C2012X5R0J106K Ceramic, X5R TDK 6.3 0805, (2012) C1608X5R0J106K Ceramic, X5R TDK 6.3 0603, (1608) 9.2.2.4 LDO Capacitor Selection 9.2.2.4.1 Input Capacitor An input capacitor is required for stability. TI recommends that a 1-F capacitor be connected between the LDO input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. 28 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 CAUTION Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be specified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approximately 1 F over the entire operating temperature range. 9.2.2.4.2 Output Capacitor The LDOs on the LM26480 are designed specifically to work with very small ceramic output capacitors. A 1-F ceramic capacitor (temperature types Z5U, Y5V, or X7R) with ESR between 5 m to 500 m, are suitable in the application circuit. It is also possible to use tantalum or film capacitors at the device output COUT (or VOUT), but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 m to 500 m for stability. 9.2.2.4.3 Capacitor Characteristics The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 F to 4.7 F, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-F ceramic capacitor is in the range of 20 m to 40 m, which easily meets the ESR requirement for stability for the LDOs. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. CAP VALUE (% of NOMINAL 1 PF) In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 27 shows a typical graph comparing different capacitor case sizes in a capacitance vs. DC bias plot. 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 27. Capacitance vs DC Bias As shown in Figure 27, increasing the DC bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (such as 0402) may not be suitable in the actual application. Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 29 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com The ceramic capacitor's capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55C to 125C, will only vary the capacitance to within 15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55C to 85C. Many large value ceramic capacitors, larger than 1 F are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25C to 85C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47-F to 4.7-F range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. Table 8. Capacitor Characteristics 30 CAPACITOR MIN VALUE (F) DESCRIPTION RECOMMENDED TYPE CLDO1 0.47 LDO1 output capacitor Ceramic, 6.3V, X5R CLDO2 0.47 LDO2 output capacitor CSW1 10 SW1 output capacitor CSW2 10 SW2 output capacitor Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 9.2.3 Application Curves VIN = 0 to 3.6 V VOUT = 2.5 V Load = 1 mA VIN = 0 to 3.6 V Figure 28. Enable Start-Up Time (LDO1) VIN = 1.2 V Load = 1.5 A VIN = 3 V Load = 30 mA Load = 1 mA Figure 29. Enable Start-Up Time (LDO2) Figure 30. Start-Up Into PWM Mode VIN = 1.2 V VOUT = 1.8 V Load = 1.5 A Figure 31. Start-Up Into PWM Mode VIN = 3 V Figure 32. Start-Up Into PFM Mode Load = 30 mA Figure 33. Start-Up Into PFM Mode Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 31 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 10 Power Supply Recommendations All power inputs should be tied to the main VDD source (that is, a battery), unless the user wishes to power it from another source. (that is, powering LDO from Buck output). The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended Operating Conditions: Bucks section of this datasheet. The other VIN pins (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.8 V, as long as they are higher than the programmed output (0.3 V). The analog and digital grounds should be tied together outside of the chip to reduce noise coupling. 11 Layout 11.1 Layout Guidelines PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss ii the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints, which can result in erratic or degraded performance. Good layout for the LM26480 bucks can be implemented by following a few simple design rules, as shown in Figure 34. 1. Place the buck inductor and filter capacitors close together and make the trace short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Place the capacitors and inductor close to the buck. 2. Arrange the components so that the switching current loops curl in the same direction. During the first halt of each cycle, current flows from the input filter capacitor, through the buck and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the buck by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the buck, and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the buck by giving it a low-impedance ground connection. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces 5. ROUT noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the buck circuit and should be routed directly from FB to VOUT at the output capacitor and must be routed opposite to noise components. This reduces EMI radiated onto the DC-DC converter's own voltage feedback trace. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (because this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators. For more information on board layout techniques, refer to AN-1187 Leadless Leadframe Package (LLP) on TI's website. This application note also discusses package handling, solder stencil, and the assembly process. 32 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 LM26480 www.ti.com SNVS543N - JANUARY 2008 - REVISED JUNE 2017 11.2 Layout Example VIN, SW, VOUT, GND, Cin and Cout traces should be thick and carry high currents. Cin and Cout caps should be placed very close to VIN and GND pads. Route feedback network and traces away from switch node and inductor to reduce noise injection from SW node Figure 34. Board Layout Design Rules for the LM26480 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 33 LM26480 SNVS543N - JANUARY 2008 - REVISED JUNE 2017 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see the following: * AN-1187 Leadless Leadframe Package (LLP) * Enhancing Bit-Flip Recovery and PMU Design for Defense/Industrial Applications * Power Supply Design Considerations for Modern FPGAs * AN-1800 Evaluation Kit for LM26480 - Dual DC/DC Buck Regulators with Dual Low-Noise Linear Regulators 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 34 Submit Documentation Feedback Copyright (c) 2008-2017, Texas Instruments Incorporated Product Folder Links: LM26480 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM26480SQ-AA/NOPB ACTIVE WQFN RTW 24 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 26480AA LM26480SQX-AA/NOPB ACTIVE WQFN RTW 24 4500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 26480AA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 OTHER QUALIFIED VERSIONS OF LM26480 : * Automotive: LM26480-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2021 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM26480SQ-AA/NOPB WQFN RTW 24 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 LM26480SQX-AA/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2021 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM26480SQ-AA/NOPB WQFN RTW 24 1000 200.0 183.0 25.0 LM26480SQX-AA/NOPB WQFN RTW 24 4500 346.0 346.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE RTW0024A WQFN - 0.8 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 4.1 3.9 C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 2.5 7 20X 0.5 6 13 2X 2.5 25 2.6 0.1 1 PIN 1 ID (OPTIONAL) (0.1) TYP EXPOSED THERMAL PAD 12 18 24 19 0.5 24X 0.3 24X 0.3 0.2 0.1 0.05 C A B C 4222815/A 03/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 2.6) SYMM 24 19 24X (0.6) 1 18 24X (0.25) (1.05) 25 SYMM (3.8) 20X (0.5) (R0.05) TYP 13 6 ( 0.2) TYP VIA 7 12 (1.05) (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4222815/A 03/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.15) (0.675) TYP (R0.05) TYP 24 19 24X (0.6) 1 18 24X (0.25) (0.675) TYP 25 20X (0.5) SYMM (3.8) 13 6 METAL TYP 7 SYMM 12 (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4222815/A 03/2016 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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