1
LTC1642A
1642af
Hot Swap Controller
■
Adjustable Undervoltage and Overvoltage
Protection
■
Foldback Current Limit
■
Adjustable Current Limit Time-Out
■
V
CC
: 2.97V to 16.5V Normal Operation, Protected
Against Surges to 33V
■
Single Channel NFET Driver
■
Latch Off or Automatic Retry on Current Fault
■
Driver for SCR Crowbar on Overvoltage
■
Adjustable Reset Timer
■
Reference Output with Uncommitted Comparator
■
16-Pin SSOP Package
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
InfiniBand
TM
Systems
1N4705
18V
12V
BACKPLANE
(SHORT PIN)
PLUG-IN CARD
VCC SENSE GATE
GND BRK TMR
LTC1642A
RST TMR
ON
FAULT
OV
RESET
FB
CRWBR
COMP+
COMP–
0.33µF 0.33µF
2N2222
MCR
12DC
REF
0.1µF
2.87k
1%
110k
1%
100Ω
5%
107k
1%
13k
1%
FDS6630A
0.01µF
0.047µF
CLOAD
12V
AT 2.5A
330Ω
5%
0.010Ω
5%
11.3k
1%
POWER-GOOD = 11.4V
1642a TA01
+
COMPOUT
GND
UV = 10.8V
OV = 13.2V
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
The LTC
®
1642A is a 16-pin Hot Swap
TM
controller that
allows a board to be safely inserted and removed from a
live backplane. Using an external N-Channel pass transis-
tor, the board supply voltage can be ramped up at an
adjustable rate. A high side switch driver controls the
N-Channel gate for supply voltages ranging from 2.97V
to 16.5V.
The SENSE pin allows foldback limiting of the load current,
with circuit breaker action after an adjustable delay time.
The delay allows the part to power-up in current limit. The
CRWBR output can be used to trigger an SCR for crowbar
protection of the load if the input supply exceeds an
adjustable threshold. The RESET output can generate a
system reset with adjustable delay when the supply volt-
age falls below an adjustable threshold. The ON pin cycles
the board power. The LTC1642A is available in the 16-pin
SSOP package.
DESCRIPTIO
U
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Hot Swap is a trademark of Linear
Technology Corporation.
2
LTC1642A
1642af
Supply Voltage (V
CC
) .................................–0.3V to 33V
SENSE Pin ................................... –0.3V to (V
CC
+ 0.3V)
ON, FB, OV, COMP
+
, COMP
–
RESET, FAULT, COMPOUT .....................–0.3V to 18.5V
Operating Temperature Range
LTC1642AC ............................................. 0°C to 70°C
LTC1642AI ......................................... –40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ORDER PART
NUMBER
LTC1642ACGN
LTC1642AIGN
Consult LTC Marketing for parts specified with wider operating temperature ranges.
T
JMAX
= 150°C, θ
JA
= 130°C/W
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Operating Voltage Range ●2.97 16.5 V
I
CC
V
CC
Supply Current ON = V
CC
●1.25 3.0 mA
V
LKHI
V
CC
Undervoltage Lockout V
CC
Rising ●2.55 2.73 2.95 V
V
LKLO
V
CC
Undervoltage Lockout V
CC
Falling ●2.35 2.50 2.95 V
V
LKHYST
V
CC
Undervoltage Lockout Hysteresis 230 mV
V
FB
FB Pin Voltage Threshold FB Falling ●1.208 1.220 1.232 V
∆V
FB
FB Pin Threshold Supply Variation FB Falling,
2.97V ≤ V
CC
≤ 16.5V ●515 mV
V
FBHST
FB Pin Voltage Threshold Hysteresis 3 mV
I
FB(IN)
FB Pin Input Current V
OV
= 5V ●0±1µA
V
OV
OV Pin Voltage Threshold OV Rising ●1.208 1.220 1.232 V
∆V
OV
OV Pin Threshold Supply Variation OV Rising,
2.97V ≤ V
CC
≤ 16.5V ●515 mV
V
OVHYST
OV Pin Voltage Theshold Hysteresis 3 mV
I
OV(IN)
OV Pin Input Current V
FB
= 5V ●0±1µA
V
RST
RST TMR Pin Voltage Threshold RST TMR Rising ●1.200 1.220 1.250 V
∆V
RST
RST TMR Pin Threshold Supply Variation RST TMR Rising, 2.97V ≤ V
CC
≤ 16.5V ●515 mV
I
RST
RST TMR Pin Current Timer On ●–1.5 –2.0 –2.5 µA
Timer Off, V
RSTTMR
= 1.5V 10 mA
V
BRK
BRK TMR Pin Voltage Threshold BRK TMR Rising ●1.200 1.220 1.250 V
∆V
BRK
BRK TMR Pin Threshold Supply Variation BRK TMR Rising, 2.97V ≤ V
CC
≤ 16.5V ●515 mV
I
BRK
BRK TMR Pin Current Timer On ●–15 –20 –30 µA
Timer Off, V
BRKTMR
= 1.5V 10 mA
V
CR
CRWBR Pin Voltage Theshold CRWBR Rising ●375 410 425 mV
∆V
CR
CRWBR Pin Threshold Supply Variation 2.97V ≤ V
CC
≤ 16.5V ●415 mV
I
CR
CRWBR Pin Current CRWBR On, V
CRWBR
= 0V ●–30 –45 –60 µA
CRWBR On, V
CRWBR
= 2.1V ●–1000 –1500 µA
CRWBR Off, V
CRWBR
= 1.5V 2.3 mA
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V unless otherwise specified.
GN PART
MARKING
1642A
1642AI
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
CRWBR
BRK TMR
RST TMR
ON
RESET
FAULT
FB
GND
VCC
SENSE
GATE
REF
COMP–
COMP+
COMPOUT
OV
GN PACKAGE
16-LEAD PLASTIC SSOP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC1642A
1642af
V
CB
Circuit Breaker Trip Voltage V
CB
= (V
CC
– V
SENSE
), V
FB
= GND ●15 25 36 mV
V
CB
= (V
CC
– V
SENSE
), V
FB
= 1V ●45 52.5 60 mV
2.97V ≤ V
CC
≤ 16.5V,
V
CB
= (V
CC
– V
SENSE
), V
FB
= GND ●12 25 39 mV
V
CB
= (V
CC
– V
SENSE
), V
FB
= 1V ●42 52.5 63 mV
I
SENSE
SENSE Pin Input Bias Current V
CC
= V
SENSE
= 16.5V ●0.5 µA
I
GATE
GATE Pin Output Current Charge Pump On, V
GATE
= GND ●–20 –25 –30 µA
Charge Pump Off, V
GATE
= 5V 10 mA
∆V
GATE
External N-Channel Gate Drive V
GATE
– V
CC,
V
CC
= 2.97V ●4.5 5.9 8.0 V
V
GATE
– V
CC,
V
CC
= 5V ●10 11.5 14 V
V
GATE
– V
CC,
V
CC
= 15V (0°C to 70°C) ●6.5 8.5 18 V
V
GATE
– V
CC,
V
CC
= 15V (–40°C to 85°C) ●6 8.5 18 V
V
ONHI
ON Pin Threshold ON Rising 1.30 1.34 1.38 V
V
ONLO
ON Pin Threshold ON Falling ●1.20 1.22 1.26 V
V
ONHYST
ON Pin Hysteresis 110 mV
I
ON(IN)
ON Pin Input Current V
ON
= 5V ●0±1µA
V
OL
Output Low Voltage RESET, FAULT, COMPOUT I
OL
= 1.54mA ●0.4 V
RESET, FAULT I
O
= 5mA 2 V
I
PU
Logic Output Pull-Up Current RESET, FAULT = GND – 15 µA
V
REF
Reference Output Voltage No Load ●1.208 1.220 1.232 V
∆V
LNR
Reference Supply Variation 2.97V ≤ V
CC
≤ 16.5V, No Load ●515 mV
∆V
LDR
Reference Load Regulation I
O
= 0mA to –1mA, Sourcing Only ●2.5 7.5 mV
I
RSC
Reference Short-Circuit Current V
REF
= 0V 4.5 mA
V
COS
Comparator Offset Voltage V
CM
= V
REF
●±10 mV
V
CHYST
Comparator Hysteresis V
CM
= V
REF
3mV
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
∆VGATE (V)
1642a G03
16
14
12
10
8
6
4
2
0
VCC = 12V
VCC = 5V
VCC = 15V
VCC = 3V
∆VGATE vs Temperature
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
IGATE (µA)
1642a G04
30
29
28
27
26
25
24
23
22
21
20
VGATE = 0V
VCC = 3V
VCC = 5V
VCC = 12V
VCC = 15V
IGATE vs Temperature
VCC (V)
36 9 12 15
∆VGATE (V)
1642a G26
15
12
9
6
3
0
TA = 25°C
∆VGATE vs VCC
4
LTC1642A
1642af
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
FB THRESHOLD VOLTAGE (V)
1642a G06
1.226
1.224
1.222
1.220
1.218
1.216
1.214
V
CC
= 5V
FB FALLING
FB RISING
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
OV THRESHOLD VOLTAGE (V)
1642a G07
1.226
1.224
1.222
1.220
1.218
1.216
1.214
V
CC
= 5V
OV FALLING
OV RISING
OV Threshold Voltage vs
Temperature
FB Threshold Voltage vs
Temperature
VCC (V)
36 9 12 15
CRWBR DRIVER CURRENT (mA)
1642a G35
2.0
1.6
1.2
0.8
0.4
0
TA = 25°C
CRWBR Driver Current vs VCC
V
CC
(V)
36 9 12 15
FB THRESHOLD VOLTAGE (V)
1642a G27
1.232
1.228
1.224
1.220
1.216
1.212
1.208
FB RISING
FB FALLING
T
A
= 25°C
FB Threshold Voltage vs VCC OV Threshold Voltage vs VCC
V
CC
(V)
36 9 12 15
OV THRESHOLD VOLTAGE (V)
1642a G28
1.232
1.228
1.224
1.220
1.216
1.212
1.208
OV RISING
OV FALLING
T
A
= 25°C
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
CRWBR DRIVER CURRENT (mA)
1642a G13
1.45
1.44
1.43
1.42
1.41
1.40
1.39
1.38
VCC = 5V
CRWBR Driver Current vs
Temperature
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
CRWBR–TMR THRESHOLD VOLTAGE (mV)
1642a G05
405
404
403
402
401
400
399
398
397
396
395
VCC = 5V
CRWBR-TMR Threshold Voltage
vs Temperature
VCC (V)
36 9 12 15
IGATE (µA)
1642a G23
25
20
15
10
5
0
VGATE = 0V
TA = 25°C
IGATE Pull-Up Current vs VCC
V
GATE
(V)
048 12 16 20 24
I
GATE
(A)
1642a G36
128
112
96
80
64
48
32
16
0
V
CC
= 12VT
A
= 25°C
V
CC
= 3.3V
V
CC
= 5V
GATE Pull-Down Current (Current
Limit Active)
5
LTC1642A
1642af
VCC (V)
02550
ICC (mA)
1642a G25
20
10
0
VON = 5V
TA = 25°C
VON = 0V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ICC vs VCC
ON Pin Threshold Voltage vs
Temperature
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
ON PIN THRESHOLD VOLTAGE (V)
1642a G22
1.40
1.36
1.32
1.28
1.24
1.20
V
CC
= 12V
ON RISING
ON FALLING
VCC (V)
36 9 12 15
VREF (V)
1642a G24
1.232
1.228
1.224
1.220
1.216
1.212
1.208
TA = 25°C
VREF vs VCC
VCC (V)
36 9 12 15
PULL-UP CURRENT (µA)
1642a G14
160
140
120
100
80
60
40
20
0
TA = –55°C
TA = 125°C
TA = 25°C
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VOLTAGE (mV)
1642a G16
600
500
400
300
200
100
0
V
CC
= 12V
V
CC
= 5V
V
CC
= 15V
V
CC
= 3V
I
OL
= 1.54mA
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VOLTAGE (V)
1642a G17
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VCC = 12V
VCC = 5V
VCC = 15V
VCC = 3V
IOL = 5mA
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
CURRENT LIMIT THRESHOLD VOLTAGE (mV)
1642a G20
27.5
27.0
26.5
26.0
25.5
25.0
24.5
V
CC
= 3V
FB = 0V
V
CC
= 15V
V
CC
= 12V
V
CC
= 5V
FAULT and RESET Pull-Up Current
(IOH) vs VCC
FAULT and RESET VOL vs
Temperature
FAULT and RESET VOL vs
Temperature
Current Limit Threshold Voltage
(Full Foldback) vs Temperature
Current Limit Threshold Voltage
(Nominal) vs Temperature
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
CURRENT LIMIT THRESHOLD VOLTAGE (mV)
1642a G21
57.0
56.5
56.0
55.5
55.0
54.5
54.0
53.5
V
CC
= 3V
FB = 1V
V
CC
= 15V
V
CC
= 5V
V
CC
= 12V
Reference O/P Impedance
IREF (mA)
0 2.5 5 7.5 10 12.5 15 17.5 20
∆VREF (mV)
1642a G37
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
–42
VCC = 12V,
15V
TA = 25°C
VCC = 5V
VCC = 3.3V
6
LTC1642A
1642af
PI FU CTIO S
UUU
CRWBR (Pin 1): Overvoltage Crowbar Circuit Timer and
Trigger. This pin controls an external overvoltage crowbar
circuit. A capacitor from the pin to ground sets a 9ms/µF
delay after an overvoltage occurs until an external SCR is
triggered. See Applications Information. Ground the
CRWBR pin if unused.
BRK TMR (Pin 2): Circuit Breaker Timer. Connect a
capacitor from BRK TMR to ground to set a 60ms/µF delay
from the time the sense resistor current reaches its limit
until the FET is shut off. FAULT output is then asserted and
the FET remains off until the chip is reset. Ground BRK
TMR to allow the part to remain in current limit indefinitely.
RST TMR (Pin 3): Analog System/Reset Timer. A capaci-
tor from this pin to ground sets a 0.6s/µF delay from the
ON pin going high to the start of the GATE pin’s ramp. It
also sets the delay from output voltage good, as sensed by
the FB pin, to RESET going high.
ON (Pin 4): ON Control Input. When ON is low the GATE
pin is grounded and FAULT goes high. The GATE pin
voltage starts ramping up one RST TMR timing cycle after
ON goes high. Pulsing the ON pin low for at least 2µs resets
the chip if it latches off after a sustained overvoltage or
current limit. The threshold for a low to high transition is
1.34V with 110mV of hysteresis. A 21V zener clamp limits
the voltage at this pin. The pin can be safely tied to V
CC
>
21V through a series resistor that limits the current below
1mA.
RESET (Pin 5): Open Drain Reset Output. RESET is pulled
low if the voltage at the FB pin is below its trip point. RESET
goes high one RESET timing cycle after the FB voltage
exceeds its trip point plus 3mV of hysteresis. RESET has
a weak pull-up to one diode drop below V
CC
and an external
resistor can pull the pin above V
CC
. A 21V zener clamp
limits the voltage at this pin. The pin can be safely tied to
V
CC
> 21V through a series resistor that limits the current
below 1mA.
FAULT (Pin 6): Open Drain Fault Output. FAULT is pulled
low when the part turns off following a sustained overvolt-
age or current limit. It goes high 2µs after the ON pin goes
low. FAULT has a weak pull-up to one diode drop below
V
CC
and an external resistor can pull the pin above V
CC
. A
21V zener clamp limits the voltage at this pin. The pin can
be safely tied to V
CC
> 21V through a series resistor that
limits the current below 1mA.
FB (Pin 7): Output Voltage Monitor and Foldback Input.
The FB comparator can be used with an external resistive
divider to monitor the output supply voltage. When the FB
voltage is lower than 1.22V the RESET pin is pulled low.
RESET goes high one system timing cycle after the voltage
at FB exceeds its threshold by 3mV of hysteresis. A low
pass filter at the comparator’s output prevents negative
voltage glitches from triggering a false reset.
GND (Pin 8): Chip Ground.
7
LTC1642A
1642af
OV (Pin 9): Overvoltage Input. When the voltage on OV
exceeds its trip point the GATE pin is pulled low immedi-
ately and the CRWBR timer starts. If OV remains above its
trip point (minus 3mV of hysteresis) long enough for
CRWBR to reach its trip point, then the part turns off until
reset by pulsing the ON pin low. Otherwise, the GATE pin
begins ramping up one RST TMR timing cycle after OV
goes below its trip point. Ground the OV pin to disable
overvoltage protection.
COMPOUT (Pin 10): Uncommitted Comparator’s Open
Drain Output.
COMP
+
(Pin 11): Uncommitted Comparator’s Noninvert-
ing Input.
COMP
–
(Pin 12): Uncommitted Comparator’s Inverting
Input.
REF (Pin 13): Reference Voltage Output. The 1.22V ±1%
reference should be bypassed with a 0.1µF compensation
capacitor. For V
CC
= 5V it can source 1mA.
GATE (Pin 14): Gate Drive for the External N-Channel
MOSFET. An internal charge pump provides at least 4.5V
of gate drive and sources 25µA. The pin requires an
external series RC network to ground to compensate the
current limit loop and to limit the ramp rate. A resistor of
100Ω is also recommended in series with the MOSFET
gate to suppress high frequency oscillations. GATE is
PI FU CTIO S
UUU
immediately pulled to ground when the overvoltage com-
parator trips or the input supply is below the undervoltage
lockout trip point. During current limit the GATE voltage is
adjusted to maintain constant load current until the circuit
breaker timer trips. At that point GATE is pulled to ground
until the chip is reset. Clamp the GATE pin with a zener
diode to ground if the supply is 8V or higher. For the 8V to
12V range use an 18V zener (1N4705), and for supplies
exceeding 12V use a 20V zener (TOSHIBA 02DZ20Y).
SENSE (Pin 15): Current Sense Input. To use the current
limit place a sense resistor in the supply path between V
CC
and SENSE. When the drop across the resistor exceeds a
threshold voltage, the GATE pin is adjusted to maintain a
constant load current and the circuit breaker timer is
started. A foldback feature reduces the current limit as the
voltage at FB approaches ground. Short SENSE to V
CC
to
disable the current limiting.
V
CC
(Pin 16): Positive Supply Voltage. An internal under-
voltage lockout circuit holds the GATE pin at ground until
V
CC
exceeds 2.73V. If V
CC
exceeds 16.5V an internal shunt
regulator protects the chip from V
CC
and SENSE pin
voltages up to 33V. In this case the GATE pin voltage will
usually be low but this is not guaranteed; use the OV pin
to ensure that the pass device is off. The V
CC
pin also
provides a high side connection to the SENSE resistor.
8
LTC1642A
1642af
+
–
7FB
1.22V
0.41V
1.22V
+
–
16VCC
14
GATE
CHARGE PUMP
25µA
23mV TO 53mV
–
+
9OV
1.22V
–
+
4ON
1.22V
–
+
VCC
VCC
2.7V
–
+
11
12COMP–
COMP+
RISING
DELAY
15µs TO
100µs
RISING
DELAY
15µs TO
100µs
RISING
DELAY
2µs
RISING
DELAY
10µs
1
CRWBR
45µA
1.5mA
1.22V
2
BRK TMR
20µA
1.22V
3
RST TMR 1642a BD
2µA
6FAULT
10µA AT 5V
VCC
15
–
+
–
+
SENSE
+
–
5RESET
10µA AT 5V
VCC
13 REF
LOGIC
–
+
–
+
10 COMPOUT
21V
21V
21V
21V
21V
21V
21.5V 21V
21V
21V
21V
21V
21V
BLOCK DIAGRA
W
9
LTC1642A
1642af
APPLICATIO S I FOR ATIO
WUUU
Hot Circuit Insertion
When a circuit board is inserted into a live backplane its
supply bypass capacitors can draw large currents from the
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642A limits the charging currents drawn by a
board’s capacitors, allowing safe insertion into a live
backplane.
In the circuit shown in Figure 1 the LTC1642A and the
external NMOS pass transistor Q1 work together to limit
charging currents. Waveforms at board insertion are
shown in Figure 2. When power is first applied to V
CC
the
chip holds Q1’s gate at ground. After an adjustable delay
a 25µA current source begins to charge the external
capacitor C2, so choose C2 to limit the inrush current
I
INRUSH
charging the board’s bypass capacitance C
LOAD
according to the equation:
C2 C • 25 A
I
LOAD INRUSH
=µ
An internal charge pump supplies the 25µA gate current,
ensuring sufficient gate drive to Q1. At 3V V
CC
the minimum
gate drive is 4.5V; at 5V V
CC
the minimum is 10V; at 15V V
CC
the minimum is again 6.5V, due to an internal zener clamp
from the GATE pin to ground. Resistor R3 limits this zener’s
transient current during board insertion and removal and
protects against high frequency oscillations in Q1. D1
provides additional protection against supply spikes.
The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
2µA current source feeding RST TMR from V
CC
; an internal
comparator, with the noninverting input tied to RST TMR
and the inverting input tied to the 1.22V reference; and an
internal NMOS pull-down. In standby, the NMOS holds
RST TMR at ground. When the timer starts the NMOS
turns off and the RST TMR voltage ramps up as the current
source charges the capacitor. When RST TMR reaches
1.22V the timer comparator trips, the GATE voltage begins
ramping up and RST TMR returns to ground. The timer
delay is:
t
RSTTMR
= (615ms/µF) C1.
The second RST TMR cycle indicates that V
OUT
is within
tolerance; it is discussed in the Undervoltage Monitor
section.
Figure 1. Supply Control Circuitry
Powering-Up in Current Limit
Ramping the GATE pin voltage limits the current to I =
25µA • C
LOAD
/C2, where C2 is the external capacitor
connected to the GATE and C
LOAD
is the load capacitance.
If the value of C
LOAD
is uncertain, then a worst-case design
can often result in needlessly long ramp times, and it may
be better to limit the charging current by powering up in
current limit.
Current Limiting and Solid-State Circuit Breaker
The current can be limited by connecting a sense resistor
between the LTC1642A’s V
CC
and SENSE pins. When the
voltage drop across this resistor reaches a limiting value,
Figure 2. Timing at Board Insertion
100ms/DIV 1642a F02
OV
10V/DIV
RST TMR
2V/DIV
GATE
20V/DIV
V
OUT
20V/DIV
GATEON 14
SENSE
15
FAULT 6
4
BRK TMR
2
V
CC
16
R2
0.010Ω
Q1
FDS6630A
GND
LTC1642A
8
RST TMR
3
1642a F01
R3
100Ω
R4
330Ω
D1
1N4705
18V
C2
0.047µF
C
LOAD
+
C1
0.33µF
C4
0.33µF
ALL RESISTORS ±5% UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 10ms
V
IN
12V
2.5A
V
OUT
R7
24k
R10
30k
10
LTC1642A
1642af
APPLICATIO S I FOR ATIO
WUUU
an internal servo loop adjusts the GATE pin voltage such
that Q1 acts as a constant current source. The voltage limit
across R2 increases as the output charges; this foldback
in the current limit helps to even out Q1’s power dissipa-
tion. The output is sensed at the FB pin. When FB is
grounded, the sense voltage is limited to 26mV. When FB
is greater than 0.7V, the limit is 56mV and the full depen-
dence is shown in Figure 3.
When the sense resistor voltage is 3mV below its limit, the
circuit breaker timer starts. Once BRK TMR reaches its
threshold, the circuit breaker opens, the GATE pin is pulled
to ground (cutting off Q1) and FAULT is asserted.
The parameter V
CB
specified in the DC electrical character-
istics refers to the voltage difference between the V
CC
and
SENSE pins needed to start the circuit breaker timer. The
limiting value maintained by the servo loop is 3mV higher
than V
CB
.
Should the sense resistor voltage drop below its limit
before the timer trips, the GATE voltage begins ramping
back up immediately and the BRK TMR pin returns to
ground. However, due to the slow gate ramp, Q1 continues
to dissipate substantial power for some time. Connecting
R10 in series with timing capacitor C4 (as shown in
Figure 1) ensures that the circuit breaker trips in the event
of repetitive, but brief, load shorts. The delay before the
circuit breaker opens is:
t
BRKTMR
= C4 (61kΩ – R10).
Once the circuit breaker trips, GATE and FAULT remain at
ground until the chip is restarted. To restart, hold the ON
pin low for at least 2µs and FAULT will go high. Then take
ON high again and the GATE will ramp up after a system
timing cycle. Or, configure the LTC1642A to restart itself
after the circuit breaker trips by connecting FAULT to the
ON pin, as shown in the next section.
The servo loop controlling Q1 during current limit has a
unity-gain frequency of about 125kHz. In Figure 1, R4 and
C2 provide compensation. To ensure stability the product
1/(2 • π • R4 • C2) should be kept below the unity-gain
frequency, and C2 should be more than Q1’s input capaci-
tance C
ISS
. A good starting point for C2 is 0.047µF and R4
is 330Ω. Keep R4 ≥ 100Ω.
Typical waveforms during a load short to ground are
shown in Figure 4. The load is shorted to ground at time 1.
The GATE voltage drops until the load current equals its
maximum limit, and the circuit breaker timer starts. The
short is cleared at time 2, before the timer trips. The BRK
TMR pin returns to ground, and the GATE voltage begins
ramping up. At time 3 the load is shorted again and at time
4 the timer trips, pulling the GATE to ground and asserting
FAULT. Although the short is cleared at time 5, FAULT
doesn’t go high until the ON pin is pulled low at time 6. At
time 7 ON goes high and the system timer starts. When it
trips at time 8 the GATE voltage begins ramping.
To disable current limit and electronic circuit breaker
protection, tie the SENSE pin to V
CC
, the BRK TMR pin to
GND and omit compensating resistor R4.
FB PIN VOLTAGE (mV)
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
MAXIMUM SENSE RESISTOR VOLTAGE (mV)
1642a F03
70
60
50
40
30
20
10
0
Figure 3. Foldback Current Limit
Figure 4. Current Limit and Circuit Breaker Timing
40ms/DIV 1642a F04
t1
t2t3
t4t5t7
t6t8
RST TMR 2V/DIV
ON 20V/DIV
FAULT 20V/DIV
BRK TMR 2V/DIV
V
OUT
20V/DIV
GATE 20V/DIV
I
LOAD
5A/DIV
11
LTC1642A
1642af
APPLICATIO S I FOR ATIO
WUUU
Automatic Restart After the Circuit Breaker Opens
The LTC1642A will automatically attempt to restart itself
after the circuit breaker opens if the FAULT output is tied
to the ON pin. The circuit is shown in Figure 5. Diode D1
blocks the weak FAULT pull-up current source from unbal-
ancing the R6-R5 divider.
During a continuous current limit such as a load short,
Q1’s duty cycle is equal to the circuit breaker timer period,
divided by the sum of the circuit breaker and system timer
periods:
Short - Circuit Duty Cycle =+
C
CC
4
410 1•
The duty cycle is 9% for the Figure 5 circuit. Waveforms
during a load short are shown in Figure 6.
Undervoltage Lockout
An internal undervoltage lockout circuit holds the charge
pump off until V
CC
exceeds 2.73V. If V
CC
falls below 2.5V,
it turns off the charge pump and clears overvoltage and
current limit faults.
For higher lockout thresholds tie the ON pin to a resistor
divider driven from V
CC
, as shown in Figure 7. This
circuit keeps the charge pump off until V
CC
exceeds
(1+R6/R5) • 1.34V, and also turns it off if V
CC
falls below
(1+R6/R5) • 1.22V.
D1
1N4148
D2
1N4705
18V
GATEON 14
SENSE
15
4
FAULT
6
BRK TMR
2
V
CC
16
R2
0.015Ω
Q1
FDS6630A
GND
LTC1642A
8
RST TMR
3
R5
60.4k
1%
R6
464k
1%
R10
30k
1642a F05
R3
100Ω
R4
330Ω
C2
0.047µF
+
C1
0.33µF
C4
0.33µF
ALL RESISTORS ±5% UNLESS NOTED
V
IN
12V
2.5A
V
OUT
C
LOAD
Figure 5. Automatic Restart Circuit
Figure 6. Automatic Retry Following a Load Short
V
GATE
20V/DIV
V
OUT
10V/DIV
V
BRKTMR
1V/DIV
V
RSTTMR
1V/DIV
40ms/DIV 1642a F06
D1
1N4705
18V
GATE 14
SENSE
15
ON
4
V
CC
16
R2
0.015Ω
Q1
FDS6630A
GND
LTC1642A
8
RST TMR
3
R6
464k
1%
R5
60.4k
1%
V
IN
12V
2.5A
1642a F07
R3
100Ω
R4
330Ω
C2
0.047µF
+
C1
0.33µF
ALL RESISTORS ±5% UNLESS NOTED
V
OUT
UNDERVOLTAGE
LOCKOUT
THRESHOLD = 10.7V
C
LOAD
Figure 7. Setting a Higher Undervoltage Lockout
12
LTC1642A
1642af
Overvoltage Protection
The LTC1642A can protect a load from overvoltages by
turning off the pass transistor if the supply voltage ex-
ceeds an adjustable limit, and by triggering a crowbar SCR
if the overvoltage lasts longer than an adjustable time. The
part can also be configured to automatically restart when
the overvoltage clears.
The overvoltage protection circuitry is shown in Figure 8.
The external components comprise a resistor divider
driving the OV pin, timing capacitor C5, NPN emitter
follower Q2, and crowbar SCR Q3. Because the MCR12DC
is not a sensitive-gate device, the optional resistor shunt-
ing the SCR gate to ground is omitted. The internal
components comprise a comparator, 1.22V bandgap ref-
erence, two current sources, and a timer at the CRWBR
pin. When V
CC
exceeds (1+R6/R5) • 1.22V the comparator’s
output goes high and internal logic turns off Q1 and starts
the timer. This timer has a 0.410V threshold and uses the
CRWBR pin; when CRWBR reaches 0.410V the timer
comparator trips, and the current sourced from V
CC
in-
creases to 1.5mA. Emitter follower Q2 boosts this current
to trigger crowbar SCR Q3. The ramp time ∆t needed to
trip the comparator is:
t
CRWBR
= 9.1(ms/µF) C5
D1
1N4705
18V
GATE
ON
14
SENSE
15
CRWBR 1
4
FAULT
6
OV
9VCC
16
R2
0.015Ω
Q1
FDS6630A
GND
LTC1642A
8
RST TMR
3
R6
127k
1%
R5
12.4k
1%
VIN
12V
2.5A
1642a F08
R3
100Ω
R4
330Ω
C2
0.047µF
+
C1
0.33µF
ALL RESISTORS ±5% UNLESS NOTED
OV COMPARATOR TRIPS AT VIN = 13.85V
RESET TIME = 200ms
CROWBAR DELAY TIME = 90µs
Q2
2N2222 Q3
MCR12DC
* ADD 220Ω RESISTOR IF
USING A SENSITIVE-GATE SCR
C5
0.01µF
VOUT
CLOAD
Figure 8. Overvoltage Protection Circuitry Figure 9. Overvoltage Timing (Input Side)
APPLICATIO S I FOR ATIO
WUUU
100ms/DIV 1642a F09
IN
OV
GATE
OUT
CRWBR
RST TMR
ON
FAULT
20V/DIV
2V/DIV
50V/DIV
20V/DIV
1V/DIV
2V/DIV
20V/DIV
20V/DIV
t
1
t
2
t
3
t
4
t
5
t
7
t
6
t
8
Once the CRWBR timer trips the LTC1642A latches off:
after the overvoltage clears GATE and FAULT remain at
ground and CRWBR continues sourcing 1.5mA. To restart
the part after the overvoltage clears, hold the ON pin low
for at least 2µs and then bring it high. The GATE voltage will
begin ramping up one system timing cycle later. The part
will restart itself if FAULT and ON are connected.
Figure 9 shows typical waveforms when the divider is
driven from V
CC
. The OV comparator goes high at time 1,
causing the chip to pull the GATE pin to ground and start
the CRWBR timer. At time 2, before the timer’s compara-
tor trips, OV falls below its threshold; the timer resets and
GATE begins charging one system timing cycle later at
time 3. Another overvoltage begins at time 4, and at time
5 the CRWBR timer trips; FAULT goes low and the CRWBR
pin begins sourcing 1.5mA. Even after OV falls below
1.22V at time 6, GATE and FAULT stay low, and CRWBR
continues to source 1.5mA. FAULT goes high when ON
goes low at time 7, and GATE begins charging at time 8,
one RST TMR cycle after FAULT goes high.
Figure 10 shows typical waveforms when the OV divider is
driven from the N-Channel’s output side. Because the
voltage driving the divider collapses after the OV compara-
tor trips, FAULT stays high and CRWBR stays near ground,
which prevents the pin from triggering an SCR. The GATE
voltage begins ramping up after a RST TMR timing cycle.
To disable overvoltage protection completely, tie the OV
and CRWBR pins to GND. For overvoltage protection at the
GATE pin, but without latch off or a crowbar SCR such as
Q3 in Figure 1, tie CRWBR to GND.
13
LTC1642A
1642af
The pull-up voltage on the RESET and FAULT pins follows
V
CC
until the shunt regulator turns on. When the regulator
is on the pull-up voltage is 14.4V.
Undervoltage Monitor
The LTC1642A will assert RESET if a monitored voltage
falls below an adjustable minimum. When the monitored
voltage has exceeded its minimum for at least one system
timing cycle, RESET goes high. The monitoring circuitry
comprises an internal 1.22V bandgap reference, an inter-
nal precision voltage comparator and an external resistive
divider to monitor the output supply voltage.
The circuit is shown in Figure 12, and typical waveforms
in Figure 13. When the voltage at the FB pin rises above its
reset threshold (1.22V), the comparator output goes low
and a timing cycle starts (times 1 and 5). Following the
cycle RESET is pulled high. At time 2 the voltage at FB
drops below the comparator’s threshold and RESET is
pulled low. If the FB pin rises above the reset threshold for
less than a timing cycle the RESET output will remain low
(time 3 to time 4). The 15µA pull-up current source to V
CC
on RESET has a series diode so the pin can be pulled above
V
CC
by an external pull-up resistor without forcing current
back into the supply.
Automatic Restart
If there is an overvoltage, and the resistor divider feeding
OV is connected to the output of the N-Channel pass
transistor, the LTC1642A will automatically restart even if
FAULT is not tied to ON. If the divider is connected to the
input side, the LTC1642A will restart itself only if FAULT is
tied to ON, and only after the overvoltage clears.
The OV and FB Comparators
The propagation delay through the OV and FB compara-
tors on low to high transitions depends strongly on the
differential input voltage. The relationship is shown in
Figure 11. The minimum propagation delay for large
overdrives is about 20µs. In addition the comparators
have 3mV of hysteresis.
Internal Voltage Clamp Protection
The LTC1642A includes a shunt regulator to protect itself
from V
CC
and SENSE pin voltages up to 33V. The regulator
turns on when V
CC
exceeds 16.5V and limits most of the
chip’s circuitry to 15V. When it is on the chip functions
normally with one exception: if the charge pump is on, the
GATE voltage is usually near ground but this is not
guaranteed. Use the OV pin to ensure that GATE is grounded.
APPLICATIO S I FOR ATIO
WUUU
Figure 10. Overvoltage Timing (Output Side)
OV OVERDRIVE (mV)
0 40 80 120 160 200 240
OV COMPARATOR PROPAGATION DELAY (µs)
1642a F11
70
60
50
40
30
20
10
0
Figure 11. OV Comparator Propagation Delay vs
Overdrive Voltage
100ms/DIV 1642a F10
IN
OV
GATE
OUT
CRWBR
RST TMR
FAULT
20V/DIV
2V/DIV
20V/DIV
20V/DIV
2V/DIV
2V/DIV
20V/DIV
14
LTC1642A
1642af
APPLICATIO S I FOR ATIO
WUUU
The undervoltage monitor behaves differently if FB is
above its threshold when the GATE begins ramping:
RESET goes high as soon as the GATE ramp begins.
RESET goes low immediately if V
CC
falls below the chip’s
2.5V internal undervoltage lockout threshold.
To disable the undervoltage monitor, tie FB to REF and
ground RESET.
D1
1N4705
18V
GATEON 14
SENSE
15
FB 7
RESET 5
4
VCC
16
R2
0.015Ω
Q1
FDS6630A
GND
LTC1642A
8
RST TMR
3
1642a F12
R3
100Ω
R4
330Ω
C2
0.047µFR9
95.3k
1%
R8
12.4k
1%
+
C1
0.33µF
ALL RESISTORS ±5% UNLESS NOTED.
FB COMPARATOR TRIPS AT VOUT = 10.7V
VIN
12V
2.5A
VOUT
CLOAD
Figure 12. Undervoltage Monitoring Circuitry Figure 13. Supply Monitor Waveforms
REFERENCE CURRENT
100µA 1mA 10mA
MINIMUM REF COMPENSATION (µF)
1642a F14
0.1
0.2
0.4
1.0
2.0
4.0
10.0
Figure 14. Minimum REF Compensation vs REF Current
Reference
The LTC1642A’s internal voltage reference is buffered and
brought out to the REF pin. The buffer amplifier should be
compensated with a capacitor connected between REF
and ground. If no DC current is drawn from REF, 0.1µF
ensures an adequate phase margin, but the minimum
compensation increases if REF sources a substantial DC
current, as shown in Figure 14.
t
1
t
2
t
3
t
4
t
5
250ms/DIV 1642a F13
V
IN
20V/DIV
V
RSTTMR
1V/DIV
V
RESET
10V/DIV
15
LTC1642A
1642af
Uncommitted Comparator
The uncommitted comparator has an open drain output.
The comparator has 3mV of hysteresis: the output goes
high when the differential input voltage exceeds 1.5mV
and goes low when the differential input is less than
–1.5mV.
The comparator’s input transistors are MOSFETs so the
input bias and offset currents are very small: typically
picoamps at 25°C, increasing to nanoamps at 90°C. If the
auxilliary comparator is unused, the COMP
+
, COMP
–
and
COMPOUT pins may be left floating.
APPLICATIO S I FOR ATIO
WUUU
R6
SENSE
RESISTOR, R2
TO SHORT
VCC PIN
R2
1642a F15
R5
VCC
SENSE
ON
GND
LT1642A
ILOAD
ILOAD
Figure 15. Recommended Layout for R1, R2 and R5
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Layout Considerations
One ounce copper exhibits a sheet resistance of 530µΩ
per square. To minimize self-heating, traces should be
at least 0.02" wide per ampere of current and 0.03" is
recommended.
In high current applications, the voltage drop along traces
can be appreciable. Connect the LTC1642A’s V
CC
and
SENSE pins
directly
across sense resistor R2 to prevent
the power trace’s resistance from adding to R2. It is also
a good practice to keep the resistor divider to the ON pin
close to the chip and the divider’s connections to the V
CC
and GND pins short. Figure 15 shows an example layout.
16
LTC1642A
1642af
© LINEAR TECHNOLOGY CORPORATION 1999
LT/TP 0605 500 • PRINTED IN USA
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TYPICAL APPLICATIO
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
12V Hot Swap Circuit for InfiniBand Modules
D2
1N4705
18V
REF COMP
–
CRWBR RST TMR BRK TMR GND
V
CC
SENSE GATE COMPOUT
RESET
FB
FAULT
ON
OV
COMP
+
LTC1642A
13 12 1 3 2 8
16 15 14 10
5
7
6
4
9
11
R3
100Ω
C2
0.047µF
R4
330Ω
5%
R12
84.5k
1%
R6
127k
1%
R5
10.2k 1%
R2 Q1
C7
0.01µF
R11
12.4k
1%
C6
0.1µF
C5
0.01µFC1*
0.033µF30k
C4
0.033µF
D1*
1N4148
10k
R9
681k
1%
R8
100k
1%
DC/DC
CONVERTER
INPUT
TO CONVERTER'S
RUN/SS
TO DC/DC RETURN
1642a TA02
VB_In
VBxEn_L
VB_Ret
InfiniBand
BACKPLANE
InfiniBand
MODULE
LOCAL POWER
ENABLE
UV
*INSTALL D1 FOR AUTOMATIC RESTART
IF USING D1, INCREASE C1
START-UP DELAY IS 20ms TYPICAL
CIRCUIT-BREAKER DELAY IS 1ms TYPICAL
†
FAIRCHILD (408) 822-2126
REWOPELUDOM2R1Q
W52%5,Ω510.02
†
166SDF
W05%5,Ω700.00
†
866SDF
LONG
SHORT
LONG
PACKAGE DESCRIPTIO
U
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8°
TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
