HTU21D(F) Sensor
Digital Relative Humidity sensor with Temperature output
HPC199_3 HTU21D(F) Sensor Datasheet www.meas-spec.com October 2013
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CRC Checksum
HTU21D(F) sensor provides a CRC-8 checksum for error detection. The polynomial used is X8 + X5 + X4 + 1.
Basic Considerations
CRC stands for Cyclic Redundancy Check. It is one of the most effective error detection schemes and requires
a minimal amount of resources.
The types of errors that are detectable with CRC that is implemented in HTU21D(F) sensors are:
Any odd number of errors anywhere within the data transmission
All double-bit errors anywhere within the transmission
Any cluster of errors that can be contained within an 8-bit window (1-8 bits incorrect)
Most larger clusters of errors
A CRC is an error-detecting code commonly used in digital networks and storage devices to detect accidental
changes to raw data.
Blocks of data entering these systems get a short check value attached, based on the remainder of a polynomial
division of their contents; on retrieval the calculation is repeated, and corrective action can be taken against
presumed data corruption if the check values do not match.
CRCs are so called because the check (data verification) value is a redundancy (it expands the message
without adding information) and the algorithm is based on cyclic codes. CRCs are popular because they are
simple to implement in binary hardware, easy to analyze mathematically, and particularly good at detecting
common errors caused by noise in transmission channels. Because the check value has a fixed length, the
function that generates it is occasionally used as a hash function.
CRC for HTU21D(F) sensors using I²C Protocol
When HTU21D(F) sensors are run by communicating with the standard I²C protocol, an 8-bit CRC can be used
to detect transmission errors. The CRC covers all read data transmitted by the sensor. CRC properties for
HTU21D(F) sensors communicating with I²C protocol are listed in the table below.
CRC calculation
To compute an n-bit binary CRC, line the bits representing the input in a row, and position the (n+1)-bit pattern
representing the CRC's divisor (called a "polynomial") underneath the left-hand end of the row.
This is first padded with zeroes corresponding to the bit length n of the CRC.
If the input bit above the leftmost divisor bit is 0, do nothing. If the input bit above the leftmost divisor bit is 1, the
divisor is XORed into the input (in other words, the input bit above each 1-bit in the divisor is toggled). The
divisor is then shifted one bit to the right, and the process is repeated until the divisor reaches the right-hand
end of the input row.