MCP2510T-I/SOG - Microchip Technology, Inc.

MCP2510

Features

• Implements Full CAN V2.0A and V2.0B at 1 Mb/s:

- 0 - 8 byte message length

- Standard and extended data frames

- Programmable bit rate up to 1 Mb/s

- Support for remote frames

- Two receive buffers with prioritized me ssage

storage

- Six full acceptance filters

- Two full ac ceptance filter masks

- Three transmit buffers with prioritization and

abort features

- Loop-back mode for self test operation

• Hardware Features:

- High Speed SPI Interface

(5 MHz at 4.5V I temp)

- Supports SPI modes 0,0 and 1,1

- Clock out pin w ith progra mmable pr escaler

- Interrupt output pin with selectable enables

- ‘Buffer full’ output pins configureable as inter-

rupt pins for each receive buf fer or as general

purpose digital outputs

- ‘Request to Send’ input pins co nfigureabl e as

control pins to request immediate message

transmission for each transmit buffer or as

general purpose digital inputs

- Low Power Sleep mode

• Low power CMOS technology:

- Operates from 3.0V to 5.5V

- 5 mA active current typical

- 10 µA standby current typical at 5.5V

• 18-pin PDIP/SOIC and 20-pin TSSOP packages

• Temperature ranges supported:

Description

The Micro chip Technology Inc. MCP2510 is a Full Con-

troller Area Network (CAN) protocol controller imple-

menting CAN specification V2.0 A/B. It supports CAN

1.2, CAN 2.0A, CAN 2.0B Passive, and CAN 2.0B

Active versions of the protocol, and is capable of trans-

mitting and receiving standard and extended mes-

sages. It is also capable of both acceptance filtering

and message management. It includes three transmit

buffers and tw o re ce ive buffers tha t reduce the amount

of microcontroller (MCU) management required. The

MCU communication is implemented via an industry

standard Serial Peripheral Interface (SPI) with data

rates up to 5 Mb/s.

Package Types

- Industrial (I): -40°C to +85°C

- Extended (E): -40°C to +125°C

TXCAN

RXCAN

VDD

RESET

MCP2510

SCK

INT

RX0BF

RX1BF10

OSC2

OSC1

CLKOUT

TX2RTS

VSS 9

MCP2510

TXCAN

RXCAN

TX0RTS

OSC1

CLKOUT

OSC2

VDD

RESET

SCK

INT

RX0BF

RX1BF

VSS

TX0RTS

TX1RTS

TX2RTS

NC NC

18 LEAD PDIP/SOIC

20 LEAD TSSOP

Stand-Alone CA N Controller with SPI™ Interfa ce

MCP2510

Table of Contents

1.0 Devi c e F u n c t io n ality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.0 Can Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.0 Mes sage Tr ansmis sion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.0 Mes sage Recept ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.0 Bit Ti m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.0 Erro r Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.0 Inte rr u p t s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.0 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.0 Regi s ter Ma p. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.0 SPI In t e r f a c e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.0 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

13.0 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

On-Line Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Reader Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Product Identi fi cati o n System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Worldwi d e S a l e s and Se r vi c e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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Customer Noti fic atio n Syst em

MCP2510

1.0 DEVICE FUNCTIONALITY

1.1 Overview

The MCP2510 is a stand-alone CAN controller devel-

oped to simplify applications that require interfacing

with a CAN bus. A simple block diagram of the

MCP2510 is shown in Figure 1-1. The device consists

of three main blocks:

1. The CAN protocol engine.

2. The control logic and SRAM registers that are

used to configure the device and its operation.

3. The SPI protocol block.

A typical system implementation using the device is

shown in Figure 1 -2.

The CAN protocol engine handles all functions for

receiving and transmitting messages on the bus. Mes-

sages are transmitted by first loading the appropriate

message buffer and control registers. Transmission is

initiate d by us ing con trol regi ste r bit s , v ia th e SPI int er-

face, or by using the transmit enable pins. Status and

errors can be checked by reading the appropriate reg-

isters. Any message detected on the CAN bus is

checked for errors and then matched against the user

defined filters to see if it should be moved into one of

the two receive buffers.

The MCU in terfaces to the device via the SPI interf ace.

Writing to and reading from all registers is done using

standard SPI read and write commands.

Interrupt pi ns are provided to al low greater system flex -

ibility. There is one multi-purpose interrupt pin as well

as specific interrupt pins for each of the receive regis-

ters that can be used to indicate when a valid message

has been received and loaded into one of the receive

buffers. Use of the specific interrupt pins is optional,

and the general purpose interrupt pin as well as status

registers (accessed via the SPI interface) can also be

used to determine when a valid message has been

received.

There are also three pins available to initiate immediate

transmission of a message that has been loaded into

one of the thre e transm it regis ters. Use o f these pi ns is

optional and initiating message transmission can also

be done by utilizing control registers accessed via the

SPI interface.

Table 1-1 gives a complete list of all of the pins on the

MCP2510.

FIGURE 1-1: BLOCK DIAGRAM

3 TX

Buffers

2 RX Buffe rs

Message Assembly

6 Acceptance

Filters

SPI

Interface

Logic SPI

Bus

INT

Buffer

SCK

CAN

Protocol

Engine

RXCAN

TXCAN

Control Logic

RX0BF

RX1BF

TX0RTS

TX1RTS

TX2RTS

MCP2510

FIGURE 1-2: TYPICAL SYSTEM IMPLEMENTATION

TABLE 1-1: PIN DESCRIPTIONS

Name DIP/

SOIC

Pin #

TSSOP

Pin # I/O/P

Type Description

TXCAN 1 1 O Transmit output pin to CAN bus

RXCAN 2 2 I Receive input pin from CAN bus

CLKOUT 3 3 O Cloc k output pin with programmable prescaler

TX0RTS 4 4 I Transmit buff er TXB0 request to send or general purpose digital input. 100 kΩ

internal pullup to VDD

TX1RTS 5 5 I Transmit buff er TXB1 request to send or general purpose digital input. 100 kΩ

internal pullup to VDD

TX2RTS 6 7 I Transmit buff er TXB2 request to send or general purpose digital input. 100 kΩ

internal pullup to VDD

OSC2 7 8 O Oscillator output

OSC1 8 9 I Oscillator input

VSS 9 10 P Ground reference for logic and I/O pins

RX1BF 10 11 O Receive buffer RXB1 interrupt pin or general purpose digital output

RX0BF 11 12 O Receive buffer RXB0 interrupt pin or general purpose digital output

INT 12 13 O Interrupt output pin

SCK 13 14 I Clock input pin for SPI interface

SI 14 16 I Data input pin for SPI interface

SO 15 17 O Data output pin for SPI interface

CS 16 18 I Chip select input pin for SPI interface

RESET 17 19 I Active low device reset input

VDD 18 20 P Positive supply for logic and I/O pins

NC — 6,15 — No internal connection

Note: Type Identification: I=Input; O=Output; P =Power

MCP2510

SPI

MCP2510 MCP2510 MCP2510

INTERFACE

CAN

BUS

MCP2510

Main

System

Controller

CAN

Transceiver

CAN

Transceiver CAN

Transceiver

Node

Controller Node

Controller

MCP2510

1.2 Transmit/Receive Buffers

The MCP2510 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a

total of six acc epta nce filte rs. Figure 1 -3 is a block diag ram of t hese buffers and th eir con necti on to th e protoc ol eng ine.

FIGURE 1-3: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

Acceptance Filter

RXF2

Identifier

Data Field Data Field

Identifier

Acceptance Mask

RXM1

Acceptance Filter

RXF3

Acceptance Filter

RXF4

Acceptance Filter

RXF5

Acceptance Filter

RXF0

Acceptance Filter

RXF1

TXREQ

TXB2

ABTF

MLOA

TXERR

MESSAGE

Message

Queue

Control Transm i t Byte Sequencer

TXREQ

TXB0

ABTF

MLOA

TXERR

MESSAGE

CRC<14:0>

Comparator

Receive<7:0>Transmit<7:0>

Receive

Error

Transmit

Error

Protocol

REC

TEC

ErrPas

BusOff

Finite

State

Machine

Counter

Shift<14:0>

{Transmit<5:0>, Receive<8:0>}

Transmit

Logic

Bit

Timing

Logic

TX RX Configuration

Registers

Clock

Generator

PROTOCOL

ENGINE

BUFFERS

TXREQ

TXB1

ABTF

MLOA

TXERR

MESSAGE

Acceptance Mask

RXM0

MCP2510

1.3 CAN Protocol Engine

The CAN protocol engine combines several functional

blocks, shown in Figure 1-4. These blocks and their

functio ns are des cri be d below.

1.4 Protocol Finite State Machine

The heart of the engine is the Finite State Machine

(FSM). This state machine sequences through mes-

sages on a bit by bit basis, changing sta tes as the fields

of the va rio us fra me ty pe s a re t r ansm it t e d or r e ceiv ed .

The FSM is a sequence r controlling t he sequential data

stream between the TX/RX Shift Register, the CRC

Error Management Logic (EML) and the parallel data

stream between the TX/RX Shift Registers and the

buffers. The FSM insures that the processes of recep-

tion, arbitration, transmission, and error signaling are

performed according to the CAN protocol. The auto-

matic retransmission of messages on the bus line is

also handled by the FSM.

1.5 Cyclic Redundancy Check

The Cycli c R edu nda nc y Chec k R eg is ter gen era t es the

Cyclic Redunda ncy Check (CRC) co de whi ch is trans-

mitted after either the Control Field (for messages with

0 data bytes) or the Data Field, and is used to check the

CRC field of incomi ng messages.

1.6 Error Management Logi c

The Error Management Logic is responsible for the

fault confinement of the CAN device. Its two counters,

the Receive Error Counter (REC) and the Transmit

Error Counter (TEC), are incremented and decre-

mented by commands from the Bit Stream Processor.

According to the values of the error counters, the CAN

controller is set into the states error-active, error-pas-

sive or bus-off.

1.7 Bit T iming Logic

The Bit Timing Logic (BTL) monitors the bus line input

and handles the bus related bit timing according to the

CAN protoco l. The BTL sync hroniz es on a re cess ive to

dominant bus transition at Start of Frame (hard syn-

chroniz ati on) and on any fu rther recessive t o do mi na nt

bus line transition if the CAN controller itself does not

transmit a dominant bit (resynchronization). The BTL

also provides programmable time segments to com-

pensate for the propagation delay time, phase shifts,

and to de fine the position of the Sample Point within the

bit time. The programming of the BTL depends upon

the baud rate and external physical delay times.

FIGURE 1-4: CAN PROTOCOL ENGINE BLOCK DIAGRAM

Bit T iming Logic

CRC<14:0>

Comparator

Receive<7:0> Transmit<7:0>

Sample<2:0>

Majority

Decision

StuffReg<5:0>

Comparator

Transmit Logic

Receive

Error Counter

Transmit

Error Counter

Protocol

FSM

SAM

BusMon

Rec/Trm Addr.

RecData<7:0> TrmData<7:0>

Shift<14:0>

(Transmit<5:0>, Receive<7:0>)

REC

TEC

ErrPas

BusOff

Interface to Standard Buffer

MCP2510

2.0 CAN MESSAGE FRAMES

The MCP2510 supports Standard Data Frames,

Extended Data Frames, and Remote Frames (Stan-

dard and Exten de d) as de fine d in the CAN 2.0B sp ec i-

fication.

2.1 Standard Data Frame

The CAN Standard D ata Frame is sho wn i n Figure 2-1.

In comm on with al l other fra mes, th e frame begi ns wi th

a Start Of Frame (SOF) bit, which is of the dominant

state, which allows hard synchronization of all nodes.

The SOF is followed by the arbitration field, consisting

of 12 bits; the 11-bit ldentifier and the Remote Trans-

mission R eq ues t (RTR) bit. The RTR bit is use d to di s-

tinguis h a data frame (RTR bit dominant ) from a remo te

frame (RTR bit recessive).

Following the arbitration field is the control field, con-

sistin g of six bits. The first bit of this fie ld is the Identifi er

Extension (IDE) bit which must be dominant to specify

a standard frame. The following bit, Reserved Bit Zero

(RB0), is reserved and is defined to be a dominant bit

by the can protocol. the remaining four bits of the con-

trol field are the Data Length Code (DLC) which speci-

fies the number of bytes of data contained in the

message.

After the control field is the data field, which contains

any data bytes that are being sent, and is of the len gth

defined by the DLC abo v e (0-8 bytes ).

The Cyclic Redundancy Check (CRC) Field follows the

data field and is used to detect transmission errors. The

CRC Field consists of a 15-bit CRC sequence, followed

by the recessive CRC Delimiter bit.

The final field is the two-bit acknowledge field. During

the ACK Slot bit, the transmitting node sends out a

recessive bit. Any node that has received an error free

frame acknowledges the correct reception of the frame

by sending back a dominant bit (regardless of whether

the node is c onfi gured to accept that specific message

or not). The recessive acknowledge delimiter com-

pletes the acknowledge field and may not be overwrit-

ten by a dominant bit.

2.2 Extended Data Frame

In the Extended CAN Data Frame, the SOF bit is fol-

lowed by the arbitration field w hich consists of 32 bits,

as shown in Figure 2-2. The first 11 bits are the most

signi ficant bits (Bas e-lD) of t he 29-bi t ident ifier. Th ese

11 bits are followed by the Substitute Remote Request

(SRR) bit w hich is defined to be recessive. Th e SRR bit

is followed by the lDE bit which is recessive to denote

an extended CAN frame.

It should be noted that if arbitration remains unresolved

after transmission of the first 1 1 bits of the ide ntifier , and

one of the nodes involved in the arbitration is sending

a standard CAN frame (11-bit identifier), then the stan-

dard CAN frame will win arbitration due to the as sertion

of a domi nant lD E bit. Als o, the SRR bit in an exte nded

CAN fram e must be rec essi ve to al low the asse rtio n of

a dominant RTR bit by a node that is sending a stan-

dard CAN remote fram e.

The SRR and lD E bits are foll owed by the remaining 18

bits of the identifier (Extended lD) and the remote trans-

mission request bit.

To enable standard and extended frames to be sent

across a shared network, it is necessary to split the 29-

bit extend ed mess age ide ntifier into 11-bit (most signif-

icant) and 18-bit (least significant) sections. This split

ensures that the lDE bit can remain at the same bit

position in both standard and extended frames.

Following the arbitration field is the six-bit control field.

the first two bits of this field are reserved and must be

domina nt. the re maining four bit s of the con trol field are

the Data Length Code (DLC) which specifies the num-

ber of data bytes contained in the message.

The remaining portion of the frame (data field, CRC

field, ac knowledg e field, end of frame and lnte rmission)

is constructed in the same way as for a standard data

frame (see Section 2.1).

2.3 Remote Frame

Normally, data transmission is performed on an auton-

omous basis by the data source node (e.g. a sensor

sending out a da ta f ram e). It is p ossible , how ever, for a

destination node to request data from the source. To

accomplish this, the destination node sends a remote

frame with an identifier that matches the identifier of the

required dat a frame. The a ppropriate data s ource node

will then send a data frame in response to the remote

frame re quest.

There are two differences between a remote frame

(shown in Figure 2-3) and a data frame. First, the RTR

bit is at the recessive state, and second, there is no

data field. In the event of a data frame and a remote

frame with the same identifier being transmitted at the

same time, the data frame wins arbitration due to the

dominant RTR bit following the identifier. In this way,

the node that transmitted the remote frame receives

the desired d ata immediatel y.

2.4 Error Frame

An Error Frame is generated by any node that detects

a bus error. An error frame, shown in Figure 2-4, con-

sists of two fields, an error flag field followed by an error

delimiter field. There are two types of error flag fields.

Which type of error flag field is sent depends upon the

error status of the node that detects and gen erates the

error flag field.

If an error-active node detects a bus error then the

node inte rrupts tr ansmission of t he current mes sage by

generating an active error flag. The active error flag is

composed of six consecutive dominant bits. This bit

MCP2510

sequen ce activel y violates the bit stu ffing rule. All other

stations recognize the resulting bit stuffing error and in

turn generate error frames themselves, called error

echo flags. The error flag field, therefore, consists of

between six and twelve consecutive dominant bits

(generated by one or more nodes). The error delimiter

field co mp letes the error fr ame. After completion of the

error frame, bus acti vity returns to norm al and the inter-

rupted node atte mpts to resend the aborted mess ag e.

If an error-passive node detects a bus error then the

node transmits an error-passive flag followed by the

error delimiter field. The error-passive flag consists of

six consecutive recessive bits, and the error frame for

an error-passive node consists of 14 recessive bits.

From this, it follows that unless the bus error is

detected by the node that is actually transmitting, the

transmission of an error frame by an error-passive

node will not affect any other node on the network. If

the transmitting node generates an error-passive flag

then this will cause other nodes to generate error

frames due to the resulting bit stuffing violation. After

transmission of an error frame, an error-passive node

must wait for six consecutive recessive bits on the bus

before attempting to rejoin bus communications.

The error delimiter consists of eight recessive bits and

allows the bus nodes to restart bus communications

cleanl y after an error has occu rred .

2.5 Overload Frame

An Overload Frame, shown in Figure 2-5, has the

same format as an active error frame. An overload

frame, howev er ca n onl y be generated during an lnt er-

frame sp ac e. In this way an ove r lo ad fram e can be dif-

ferentiated from an error frame (an error frame is sent

during the transmission of a message). The overload

fram e consi sts of two f ields, a n overl oad fla g follo wed

by an overl oad del imit er. The ov er load fla g con sis ts of

six dominant bits followed by overload flags generated

by other nodes (and, as for an active error flag, giving

a maximum of twelve dominant bits). The overload

delimiter consists of eight recessive bits. An overload

frame can be generated by a node as a result of two

conditions. First, the node detects a dominant bit d uring

the interframe space w hich is an illegal condition. S ec-

ond, due to internal conditions the node is not yet able

to start reception of the next message. A node may

generate a maximum of two sequential overload

frames to delay the start of the next message.

2.6 Inter frame Space

The lnterframe Space separates a preceeding frame

(of any type) from a subsequent data or remote frame.

The interframe space is composed of at least three

recessive bits called the Intermission. This is provided

to allow nodes time for internal processing before the

start of the next mes sage frame. Afte r the i ntermi ssion,

the bus line remains in the recessive state (bus idle)

until the next transmission starts.

MCP2510

FIGURE 2-1: STANDARD DATA FR AME

Start of Frame

Data Frame (number of bits = 44 + 8N)

Arbitration Field

ID 10

ID3

ID0

Identifier

Message

Filtering

Stored in Buffers

RTR

IDE

RB0

DLC3

DLC0

Control

Field

Data

Length

Code

Reserved Bit

8N (0≤N≤8)

Data Field

Stored in Tr ansm it/Receive Buffers

Bit Stuffing

CRC Field

CRC

End of

Frame

CRC Del

Ack Slot Bit

ACK Del

IFS

000 1 11111111111

MCP2510

FIGURE 2-2: EXTENDED DATA FRAME

0 1 1 0 0 0 1

Start of Frame

Arbitration Field

ID10

ID3

ID0

IDE

Identifier

Message

Filtering Stored in Buffers

SRR

EID17

EID0

RTR

RB1

RB0

DLC3

DLC0

Control

Field4

Reserved bits

Data

Length

Code

Stored in Transmit/Receive Buffers

8 8

Data Frame (number of bits = 64 + 8N)

8N (0≤N≤8)

Data Field

1 1 1 1 1 1 1 1

CRC Field

CRC

CRC Del

Ack Slot Bit

ACK Del

End of

Frame

Bit Stuffing

IFS

Extended Identifier

1 1 1

MCP2510

FIGURE 2-3: REMOTE DATA FRAME

0 1 1 1 0 0

Start of Frame

Arbitration Field

ID10

ID3

ID0

IDE

Identifier

Message

Filtering

SRR

EID17

EID0

RTR

RB1

RB0

DLC3

DLC0

Control

Field4

Reserved bits

Data

Length

Code

Extended Identifier

1 1 1 1 1 1 1 1 1

CRC Field

CRC

CRC Del

Ack Slot Bit

ACK Del

End of

Frame

1 1 1

IFS

Remote Data Frame with Exte nde d Iden tifi er

MCP2510

FIGURE 2-4: ERROR DATA FRAME

0 0 00

Start of Frame

Interrupted Data Frame

Arbitration Field

ID 10

ID3

ID0

Identifier

Message

Filtering

RTR

IDE

RB0

DLC3

DLC0

Control

Field

Data

Length

Code

Reserved Bit

8N (0≤N≤8)

Data Field

Bit Stuffing

0000000 00 1 1 1 1 1 1 1 1 0

Data Frame or

Remote Frame

Error Frame

Error

Flag

≤ 6

Echo

Error

Flag

Error

Delimiter

Inter-Frame Space or

Overload Frame

MCP2510

FIGURE 2-5: OVERLOAD FRAME

0 1 00111111111

Start of Frame

Remote Frame (number of bits = 44)

Arbitration Field

ID 10

ID0

RTR

IDE

RB0

DLC3

DLC0

Control

Field

CRC Field

CRC

End of

Frame

CRC Del

Ack Slot Bit

ACK Del

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Overload Frame

End of Frame or

Error Delimiter or

Overload Delimiter 6

Overload

Flag Overload

Delimiter

8Inter-Frame Space or

Error Frame

MCP2510

NOTES:

MCP2510

3.0 MESSAGE TRANSMISSION

3.1 Transmit Buffers

The MCP2510 implements three Transmit Buffers.

Each of these buffers occupies 14 bytes of SRAM and

are mapped into the device memory maps. The first

byte, TXBNCTRL, is a control register associated with

the message buffer. The information in this register

determines the conditions under which the message

will be tran sm itte d and indic ate s the status of the me s-

sage transmission. (see Register 3-2). Five bytes are

used to h old the s tandard and ex ten ded identifier s an d

other message arbitration information (see Register 3-

3 through R egister 3-8). Th e last eight byt es are for the

eight possible data bytes of the message to be trans-

mitted (see Register 3-8).

For the MCU to have write access to the message

buffe r, t he TX BNCTRL.TXREQ bit must be clear, indi-

cating that the message buffer is clear of any pending

message to be transmitted. At a minimum, the TXBN-

SIDH, TXBNSIDL, and TXBNDLC registers must be

loaded. If data bytes are present in the message, the

TXBNDm regi sters must also be loaded. If the message

is to use extended identifiers, the TXBNEIDm registers

must als o be load ed and th e TXBNSIDL.EXIDE bit set.

Prior to sending the message, the MCU must initialize

the CANINTE.TXINE bit to enable or disabl e the gener-

ation of an interrupt when the message is sent. The

MCU must also initialize the TXBNCTRL.TXP priority

bits (see Section 3.2).

3.2 Transmit Priority

T ransmit pri ority is a p rioritization , within the M CP2510,

of the pending transmittable messages. This is inde-

pendent from, and not nece ssarily related to, any pri or-

itizati on implicit in the messa ge arbitration scheme bui lt

into the CAN protocol. Prior to sending the SOF, the pri-

ority of all buffers that are queued for transmission is

compare d. The tr ansm it bu ffer w ith th e hig hes t prio ri ty

will be se nt first. For exa mple, if trans mit buf fer 0 has a

higher priority setting than tra nsmit buffer 1, buffer 0 will

be sent first. If two buffers have the same priority set-

ting, the buffer with the highest buffer number will be

sent fir st. For example, if transmit buffer 1 has the same

priority setting as transmit buffer 0, buffer 1 will be sent

first. There are four levels of tra nsmit priority. If TXBNC-

TRL.TXP< 1:0> for a p artic ular me ssage buf fer is se t to

11, that buffer has the highest possible priority. If

TXBNCTRL.TXP<1:0> for a particular message buffer

is 00, that buffer has the lowest possible priority.

3.3 Initi ating Transmission

To initiate message transmission the TXBNC-

TRL.TXREQ bit mus t be set for ea ch buf fer to be trans-

mitted. This can be done by writing to the register via

the SPI interface or by setting the TXNRTS pin low for

the particular transmit buffer(s) that are to be transmit-

ted. If tra nsmi ssion i s init iated via th e SPI in terface , the

TXREQ bi t can be set at th e same time as the TXP pri-

ority bits.

When TXBNCTRL.TXREQ is set, the

TXBNCTRL.ABTF, TXBNCTRL.MLOA and

TXBNCTRL.TXERR bits will b e cle ared .

Setting the TXBNCTRL.TXREQ bit does not initiate a

message transmission, it merely flags a message

buf fer as r eady f or transmi ssion. T ransmi ssion wi ll st art

when the device detects that the bus is available. The

device will then beg in transmiss ion of the highe st prior-

ity message that is ready.

When the transmi ssion ha s comp leted suc cessfu lly the

TXBNCTRL.TXREQ bit will be cleared, the CAN-

INTF.TXNIF bit will be set, and an interrupt will be gen-

erated if the CANINTE.TXNIE bit is set.

If the message transmission fails, the TXBNC-

TRL.TXREQ will remain set indicating that the mes-

sage is still pending for transmission and one of the

following condition flags will be set. If the message

started to transmit but encountered an error condition,

the TXBNCTRL. TXERR and the CANINTF.MERRF

bits will be set and an in terrupt will be generated on the

INT pin if the CANINTE.MERRE bit is set. If the mes-

sage lost arbitration the TXBNCTRL.MLOA bit will be

set.

3.4 TXnRTS Pins

The TXNRTS Pins are input pins that c an be confi gured

as reques t-to-se nd inpu ts, whic h provid es a secon dar y

means of initiating the tra ns mi ss ion o f a m es sa ge from

any of the transmit buffers, or as standard digital inputs.

Configuration and control of these pins is accomplishe d

using the TXR TSCTRL register (see Register 3-2). The

TXRTSCTRL register can only be modified when the

MCP2510 i s in confi guratio n mod e (see Sectio n 9.0). If

configured to operate as a request to send pin, the pin

is mapped into the respective TXBNCTRL.TXREQ bit

for the trans mit buf f er. The TXREQ bit is la tched b y the

falling edge of the TXNRTS pin. The TXNRTS pins are

designe d to allow th em to be tied di rectly to the RXNBF

pins to automatically initiate a message transmission

when the RXNBF pin goes l ow. The TXNRTS pins have

internal pullup resistors of 100 kΩ (nominal).

3.5 Aborting Transmission

The MCU c an re que st to abo rt a m es sage in a specific

message buffer by clearing the associated TXBnC-

TRL.TXREQ bit. Also, all pending messages can be

requested to be aborted by setting the CAN-

CTRL.ABAT bit. If the CANCTRL.ABAT bit is set to

abort all pending messages, the user MUST reset this

bit (typically after the user verifies that all TXREQ bits

have been cleared) to continue trasmi t m es sa ges . Th e

CANCTRL.ABTF flag will only be set if the abort was

requested via the CANCTRL.ABAT bit. Aborting a mes-

sage by re set ting the TXREQ b it doe s c au se the ATBF

bit to be set.

MCP2510

Only messages that have not already begun to be

transmitted can be aborted. Once a message has

begun transmission, it will not be possible for the user

to reset the TXBnCTRL.TXREQ bit. After transmission

of a message has begun, if an error occurs on the bus

or if the message l oses arbitra tion, the me ssage will be

retransmitted regardless of a request to abort.

FIGURE 3-1: TRANSMIT MESSAGE FLOWCHART

Start

CAN Bus available

to start transmission

Examine TXBnCTRL.TXP <1:0> to

Are any

TXBnCTRL.TXREQ

bits = 1

The message transmission

sequence begins when the

device determines that the

TXBnCTRL.TXREQ fo r any of

the transmit registers has been

set.

Clear:

TXBnCTRL.ABTF

TXBnCTRL.MLOA

TXBnCTRL.TXERR

Yes

TXBnCTRL.TXREQ=0

CANCTRL.ABAT=1

Clearing the TxBnCTRL.TXREQ

bit while it is set, or setting the

CANCTRL.ABAT bit before the

message has started tran sm ission

will abort the message.

Transmit Message

Was

Message Transmitted

Successfully?

Yes

Set TxBnCTRL.TXREQ =0

CANINTE.TXnIE=1?

Generate

Interrupt

Yes

Set

Did

a message erro r

occur?

Was

Arbitration lost during

transmission?

Set

TxBnCTRL.TXERR=1

Yes

Determine Highest Priority Message

TxBnCTRL.MLOA=1

The CANINTE.TXnIE bit

determines if an interrupt

should be gen er ate d when

a message is successfully

transmitted.

GOTO START

CANTINF.TXnIF=1

Yes

MCP2510

(ADDRESS: 30h, 40h, 50h)

U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0

— ABTF MLOA TXERR TXREQ — TXP1 TXP0

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 ABTF: Message Aborted Flag

1 = Message was aborted

0 = Message completed transmission successfully

bit 5 MLOA: Message Lost Arbitration

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

bit 4 TXERR: Transmission Error Detected

1 = A bus error occurred while the message was being transmitted

0 = No bus error occurred while the message was being transmit ted

bit 3 TXREQ: Message Transmit Request

1 = Buffer is currently pending transmission

(MCU sets this bit to request message be transmitted - bi t is automatically cleared when

the message is sent)

0 = Buffer is not currently pending transmission

(MCU can clear this bit to request a message abort)

bit 2 Unimplemented: Read as '0'

bit 1-0 TXP<1:0>: Transmit Buffer Priority

11 = Highest Message Priority

10 = High Interme dia te Me ss age Priority

11 = Low Intermediate Message Priority

00 = Lowest Message Priority

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 0Dh)

(ADDRESS: 31h, 41h, 51h)

U-0 U-0 R-x R-x R-x R/W-0 R/W-0 R/W-0

—— B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 Unimplemented: Read as '0'

bit 5 B2RTS: TX2RTS Pin State

- Reads state of TX2RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 4 B1RTS: TX1RTX Pin State

- Reads state of TX1RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 3 B0RTS: TX0RTS Pin State

- Reads state of TX0RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 2 B2RTSM: TX2RTS Pin Mode

1 = Pin is used to request message transmission of TXB2 buffer (on falling edge)

0 = Digital input

bit 1 B1RTSM: TX1RTS Pin Mode

1 = Pin is used to request message transmission of TXB1 buffer (on falling edge)

0 = Digital input

bit 0 B0RTSM: TX0RTS Pin Mode

1 = Pin is used to request message transmission of TXB0 buffer (on falling edge)

0 = Digital input

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10SID9SID8SID7SID6SID5SID4SID3

bit 7 bit 0

bit 7-0 SID<10:3>: Stand ard Ide ntif ier Bit s <10:3>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 32h, 42h, 52h)

(ADDRESS: 33h, 43h, 53h)

(ADDRESS: 34h, 44h, 54h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID2 SID1 SID0 — EXIDE —EID17EID16

bit 7 bit 0

bit 7-5 SID<2:0>: Standard Identifier Bits <2:0>

bit 4 Unimplemented: Reads as '0’

bit 3 EXIDE: Extended Identifier Enable

1 = Message will transmit extended identifier

0 = Message will transmit standard identifier

bit 2 Unimplemented: Reads as '0’

bit 1-0 EID<17:16>: Extended Identifier Bits <17:16>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID<15:8>: Extended Identifier Bits <15:8>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

bit 7-0 EID<7:0>: Extended Identifier Bits <7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 35h, 45h, 55h)

(ADDRESS: 36h-3Dh, 46h-4Dh, 56h-5Dh)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—RTR—— DLC3DLC2DLC1DLC0

bit 7 bit 0

bit 7 Unimplemented: Reads as '0’

bit 6 RTR: Remote Transmission Request Bit

1 = Transmitted Message will be a Remote Transmit Request

0 = Transmitted Message will be a Data Frame

bit 5-4 Unimplemented: Reads as '0’

bit 3-0 DLC<3:0>: Data Length Code

Sets the number of data bytes to be transmitted (0 to 8 bytes)

Note: It is possible to set the DLC to a value greater than 8, however only 8 bytes are trans-

mitted

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

TXBNDm

7TXBNDm

6TXBNDm

5TXBNDm

4TXBNDm

3TXBNDm

2TXBNDm

1TXBNDm

bit 7 bit 0

bit 7-0 TXBNDM7:TXBNDM0: Transm it Buf fe r N Data Field Byte m

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

4.0 MES SAGE RE CEPTION

4.1 Receive Message Buffe ring

The MCP2510 includes two full receive buffers with

multiple acceptance filters for each. There is also a

separate Message Assembly Buffer (MAB) which acts

as a third receive buffer (see Figure 4-1).

4.2 Receive Buffers

Of the three Receive Buffers, the MAB is always com-

mitted to receiv ing the ne xt mess age from t he bus. Th e

remaining two receive buffers are called RXB0 and

RXB1 and can receive a complete message from the

proto col e ngine. The M CU c an acce ss on e buf fer whil e

the other buffer is available for message reception or

holding a previously received message.

The MAB assembles all messages received. These

messages w il l be tran sfe rred to th e RX BN buffers (See

ter criteria are met.

When a message is moved into either of the receive

buffers the appropriate CANINTF.RXNIF bi t is se t. Thi s

bit must be cleared by the MCU, when it has complete d

processing the message in the buffer, in order to allow

a new message to be received into the buffer. This bit

provide s a posi tive l ockou t to ensu re that the MCU has

finished with the message before the MCP2510

attempt s to load a ne w message into the receive bu ffer .

If the CANINTE.RXNIE bit is set an interrupt will be gen-

erat ed on th e INT pin to indicate that a valid mess age

has been received.

4.3 Receive Priority

RXB0 is the highe r priority buff er and has two messag e

accept anc e filters associate d with it. RXB1 is the lower

priority buffer and has four acceptance filters associ-

ated with it. The lower number of acceptance filters

makes the match on RXB0 m ore restric tive and i mplies

a higher priority for that buffer. Additionally, the

RXB0CTRL register can be configured such that if

RXB0 contains a valid message, and another valid

message is received, an overflow error will not occur

and the new mess age will be moved i nto RXB1 rega rd-

less of th e accep tan ce crit eria of R XB1. There are also

two programmable acceptance filter masks available,

one for each receive buff er (see Section 4 .5).

When a m essage is rec eived, bit s <3:0> of th e RXBNC-

TRL Regis ter wil l indicate the accep tanc e filter nu mber

that enabl ed rece ption, an d whet her the rec eived mes-

sage is a remote transfer request.

The RXBNCTRL.RXM bits set special receive modes.

Normally, these bit s are se t to 00 to e nable rece ption of

all valid messages as determined by the appropriate

acceptance filters. In this case, the determination of

whether or not to receive standard or extended mes-

sages is determined by the RFXNSIDL.EXIDE bit i n the

acceptance filter register. If the RXBNCTRL.RXM bits

are set to 01 or 10, the receiver will accept only mes-

sages with standard or extended identifiers respec-

tively. If an accept ance fil ter has the RFXNSIDL.EXIDE

bit set such that it does not correspond with the

RXBNCTRL.RXM mode, that acceptance filter is ren-

dered useless. These two modes of RXBNCTRL.RXM

bit s can be us ed in s ystem s whe re it is k nown that onl y

standard or extended messages will be on the bus. If

the RXBNCTRL.RXM bits are set to 11, the buffer will

receive all messages regardless of the values of the

acceptance filters. Also, if a message has an error

before the end of frame, that portion of the message

assembled in the MAB before the error frame will be

loaded into the buffer. This mode has some value in

debuggi ng a CAN system an d would not be used in a n

actual system environment.

4.4 RX0BF and RX1BF Pins

In addition to the INT pin which provides an interrupt

signal to the MCU for many different conditions, the

receive buffer full pins (RX0BF and RX1BF) can be

used to i ndi cate that a valid m es sa ge h as bee n lo ade d

into RXB0 or RXB1, respectively.

The RXBNBF full pins can be configured to act as buffer

full in terrupt pins o r a s standard d igi tal output s . C o nfi g-

uration and status of these pins is available via the

BFPCTRL re gis ter (R egi ste r 4-3). W hen se t to op era te

in interrupt mode (by setting BFPCTRL.BxBFE and

BFPCTRL.Bx BFM bits to a 1), these pins are act ive low

and are mapped to the CANINTF.RXNIF bit for each

receive buffer. When this bit goes high for one of the

receive buffers, indicating that a valid message has

been loaded into the buffer, the corresponding RXNBF

pin wil l go low . When the CANI NTF.RXNIF bit is cl eared

by the MCU, then the corresponding interrupt pin will

go to the logic high state until the next message is

loaded into the receive buffer.

When used as digital outputs, the BFPCTRL.BxBFM

bits mu st be cleared to a ‘ 0’ a nd BFPCTR L. BxBFE bits

must be set to a ‘1’ for the associated buffer. In this

mode the state of the pin is controlled by the BFPC-

TRL.BxBFS bits. Writting a ‘1’ to the BxBFS bit will

cause a high level to be driven on the assicated buffer

full pin, and a ‘0’ will cause the pin to drive low. When

using the pins in this mode the state of the pin should

be mod ifie d only by us ing the Bit Modify SPI co mm and

to prevent glitches from occuring on either of the buffer

full pins.

Note: The entire contents of the MAB is moved

into the receive buffer once a message is

accepted. This means that regardless of

the type of identifier (standard or extended)

and the numb er of data bytes rec eived, the

entire receive buffer is overwritten with the

MAB contents. Therefore the contents of

all regis ters in the bu f fer mus t be assu med

to have bee n modified when an y m es sag e

is received.

MCP2510

FIGURE 4-1: RECEIVE BUFFER BLOCK DIAGRAM

Acceptance Mask

RXM1

Acceptance Filter

RXF2

Acceptance Filter

RXF3

Acceptance Filter

RXF4

Acceptance Filter

RXF5

Acceptance Mask

RXM0

Acceptance Filter

RXF0

Acceptance Filter

RXF1

Identifier

Data Field Data Field

Identifier

MCP2510

FIGURE 4-2: MESSAGE RECEPTION FLOWCHART

Set RXBF0

Start

Detect

Start of

Message

Valid

Message

Received

Generate

Error

Message

Ident ifi er mee ts

a filter criteria

CANINTF.RX0IF=0

Go to Start

Move message into RXB0

Set RXB0CTRL.FILHIT <2:0>

CANINTF.RX1IF = 0

Move message into RXB1

Set CANINTF. RX1IF=1

Yes, meets criteria

for RXBO

Generate

Interrupt on INT

Yes Yes

No No

Yes

Frame

The CANINTF.RXnIF bit

determines if the receive

to accept a n ew message

No Yes

Begin Loading Message into

Message Assembly Buffer (MAB)

according to which filter criteria

was met

Set RXB0CTRL.FILHIT <0>

according to which filter criteria

Set CANSTAT <3:0> accord-

ing to which receive buffer

the message was loaded into

RXB0CTRL.BUKT=1

The RXB0CTRL.BUKT

bit determines if RXB0

can roll over into RXB1

if it is full

Gen erate Overflow Error:

Set EFLG.R X1 O V R

CANINTE.ERRIE=1

Go to Start

Yes

ARE

BFPCTRL.B0BFM=1

BF1CTRL.B0BFE=1

AND Pin = 0

Set RXBF1

Pin = 0

Yes

CANINTE.RX0IE=1? CANINTE.RX1IE=1?

RXB1

RXB0

Yes, meets criteria

for RXB1

Set EFLG.RX0OVR

Generate Overflow Error:

Set CANINTF.RX0IF=1

ARE

BFPCTRL.B1BFM=1

BF1CTRL.B1BFE=1

AND

MCP2510

(ADDRESS: 60h)

U-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0

— RXM1 RXM0 — RXRTR BUKT BUKT1 FILHIT0

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6-5 RXM<1:0>: Receive Buffer Operating Mode

11 =Turn mask/filters off; receive any message

10 =Receive only valid messages with extended identifiers that meet filter criteria

01 =Receive only valid messages with standard identifiers that meet filter criteria

00 =Receive all valid messages using either standard or extended identifiers that meet filter

criteria

bit 4 Unimplemented: Read as '0'

bit 3 RXRTR: Received Remote Transfer Request

1 = Remote Transfer Request Received

0 = No Remote Transfer Request Received

bit 2 BUKT: Rollover Enable

1 = RXB0 message will rollover and be written to RXB1 if RXB0 is full

0 = Rollover disabled

bit 1 BUKT1: Read Only Copy of BUKT Bit (used internally by the MCP2510).

bit 0 FILHIT<0>: Filter Hit - indicates which acceptance filter enabled reception of message

1 = Acceptance Filter 1 (RXF1)

0 = Acceptance Filter 0 (RXF0)

Note: If a rollover from RXB0 to RXB1 occurs, the FILHIT bit will reflect the filter that accepted

the message that rolled over

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 70h)

U-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0

— RXM1 RXM0 — RXRTR FILHIT2 FILHIT1 FILHIT0

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6-5 RXM<1:0>: Receive Buffer Operating Mode

11 =Turn mask/filters off; receive any message

10 =Receive only valid messages with extended identifiers that meet filter criteria

01 =Receive only valid messages with standard identifiers that meet filter criteria

00 =Receive all valid messages using either standard or extended identifiers that meet filter

criteria

bit 4 Unimplemented: Read as '0'

bit 3 RXRTR: Receiv ed Remote Transfer Request

1 = Remote Transfer Request Received

0 = No Remote Transfer Request Received

bit 2-0 FILHIT<2:0>: Filter Hit - indicates which acceptance filter enabled reception of message

101 = Acceptance Filter 5 (RXF5)

100 = Acceptance Filter 4 (RXF4)

011 = Acceptance Filter 3 (RXF3)

010 = Acceptance Filter 2 (RXF2)

001 = Acceptance Filter 1 (RXF1) (Only if BUKT bit set in RXB0CTRL)

000 = Acceptance Filter 0 (RXF0) (Only if BUKT bit set in RXB0CTRL)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 0Ch)

(ADDRESS: 61h, 71h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 Unimplemented: Read as '0'

bit 5 B1BFS: RX1BF Pin State (digital output mode only)

- Reads as ‘0’ when RX1BF is configured as interrupt pin

bit 4 B0BFS: RX0BF Pin State (digital output mode only)

- Reads as ‘0’ when RX0BF is configured as interrupt pin

bit 3 B1BFE: RX1BF Pin Function Enable

1 = Pin function enabled, operation mode determined by B1BFM bit

0 = Pin function disabled, pin goes to high impedance state

bit 2 B0BFE: RX0BF Pin Function Enable

1 = Pin function enabled, operation mode determined by B0BFM bit

0 = Pin Function disabled, pin goes to high impedance state

bit 1 B1BFM: RX1BF Pin Operation Mode

1 = Pin is used as interrupt when valid message loaded into RXB1

0 = Digit al out put mo de

bit 0 B0BFM: RX0BF Pin Operation Mode

1 = Pin is used as interrupt when valid message loaded into RXB0

0 = Digit al out put mo de

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R-x R-x R-x R-x R-x R-x R-x R-x

SID10SID9SID8SID7SID6SID5SID4SID3

bit 7 bit 0

bit 7-0 SID<10:3>: Stand ard Ide ntif ier Bit s <10:3>

These bit s contain the eight mos t significant bits of the S ta ndard Identifier for the receive d mes-

sage

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 62h, 72h)

(ADDRESS: 63h, 73h)

R-x R-x R-x R-x R-x U-0 R-x R-x

SID2 SID1 SID0 SRR IDE —EID17EID16

bit 7 bit 0

bit 7-5 SID<2:0>: Standard Identifier Bits <2:0>

These bit s contai n the three least sign ificant bits of the S tandard Identifi er for the received mes-

sage

bit 4 SRR: Standard Frame Remote Transmit Request Bit (valid only if IDE bit = ‘0’)

1 = Standard Frame Remote Transmit Request Received

0 = Standard Data Frame Received

bit 3 IDE: Extended Identifier Flag

This bit indicates whether the received message was a Standard or an Extended Frame

1 = Received message was an Extended Frame

0 = Received message was a Standard Frame

bit 2 Unimplemented: Reads as '0'

bit 1-0 EID<17:16>: Extended Identifier Bits <17:16>

These bit s cont ain the two most si gnific ant bit s of the Ex tended Identifie r for the recei ved mes-

sage

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R-x R-x R-x R-x R-x R-x R-x R-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID<15:8>: Extended Identifier Bits <15:8>

These bits hold bits 15 through 8 of the Extended Identifier for the received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 64h, 74h)

(ADDRESS: 65h, 75h)

(ADDRESS: 66h-6Dh, 76h-7Dh)

R-x R-x R-x R-x R-x R-x R-x R-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

bit 7-0 EID<7:0>: Extended Identifier Bits <7:0>

These bits hold the least signific ant eight bits of the Extended Identifier for the received mes-

sage

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

U-0 R-x R-x R-x R-x R-x R-x R-x

— RTR RB1 RB0 DLC3 DLC2 DLC1 DLC0

bit 7 bit 0

bit 7 Unimplemented: Reads as '0'

bit 6 RTR: Exte nded Frame Remo te Tran smission Request Bi t (valid only when RXBnSIDL.IDE = 1)

1 = Extended Frame Remote Transmit Request Received

0 = Extended Data Frame Received

bit 5 RB1: Reserved Bit 1

bit 4 RB0: Reserved Bit 0

bit 3-0 DLC<3:0>: Data Length Code

Indicates number of data bytes that were received

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R-x R-x R-x R-x R-x R-x R-x R-x

RBNDm7 RBNDm6 RBNDm5 RBNDm4 RBNDm3 RBNDm2 RBNDm1 RBNDm0

bit 7 bit 0

bit 7-0 RBNDm7:RBNDm0: Receive Buffer N Data Field Byte m

Eight bytes containing the data bytes for the received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

4.5 Message Acceptance Filters and

Masks

The Message Acceptance Filters And Masks are used

to determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers (see Figure 4-3). Once a valid message has been

received into the MAB, the identifier fields of the mes-

sage are compared to the filter values. If there is a

match, that message will be loaded into the appropriate

receive buffer. The filter masks (see Register 4-10

through Register 4-17) are used to determine which

bits in the identi fier are examined with the filters . A truth

table is shown below in Table 4-1 that indicates how

each bit in the identifier is compared to the masks and

filters to determine if a the message should be loaded

into a receive buffer. The mask essentially determines

which bits to apply the acceptance filters to. If any mask

bit is set to a zero, then that bit will automatically be

accepted regardless of the filter bit.

TABLE 4-1: FILTER/MASK TRUTH TABLE

As shown in the Receive Buffers Block Diagram

(Figure 4-1), acceptance filters RXF0 and RXF1, and

filter mask RXM0 are associated with RXB0. Filters

RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are

associated with RXB1. When a filter matches and a

message is loaded into the receive buffer, the filter

number that enabled the message reception is loaded

into the RXBNCTRL register FILHIT bit(s). For RXB1

the RXB1CTRL register c ont ains the FILHIT<2:0 > bits .

They are coded as follows:

-101 = Acceptance Filter 5 (RXF5)

-100 = Acceptance Filter 4 (RXF4)

-011 = Acceptance Filter 3 (RXF3)

-010 = Acceptance Filter 2 (RXF2)

-001 = Acceptance Filter 1 (RXF1)

-000 = Acceptance Filter 0 (RXF0)

RXB0CTRL contains two copies of the BUKT bit and

the FILHIT<0> bit.

The coding of the BUKT bit enables these three bits to

be used similarly to the RXB1CTRL.FILHIT bits and to

distinguish a hit on filter RXF0 and RXF1 in either

RXB0 or after a roll over into RXB1.

-111 = Acceptance Filter 1 (RXF1)

-110 = Acceptance Filter 0 (RXF0)

-001 = Acceptance Filter 1 (RXF1)

-000 = Acceptance Filter 0

If the BUKT bi t is clear , there are six codes co rrespond-

ing to the six filters. If the BUKT bit is set, there are six

codes corresponding to the six filters plus two addi-

tional codes corresponding to RXF0 and RXF1 filters

that roll over into RXB1.

If more than one ac cept ance filter matc hes, the FILHIT

bits will encode the binary value of the lowest num-

bered filter that matched. In other words, if filter RXF2

and filter RXF4 match, FILHIT will be loaded with the

value for RXF2. This essentially prioritizes the accep-

ta nce filters wit h a lower number f ilter havi ng higher pri-

ority. Messages are compared to filters in ascending

order of filter number.

The mask and filter registers can only be modified

when the MCP2510 is in configuration mode (see

Section 9.0).

Mask Bit

nFilter Bit

Message

Identifier bit

n001

Accep t or

reject bit n

0X XAccept

10 0Accept

1 0 1 Reject

1 1 0 Reject

11 1Accept

Note: X = don’t care

Note: 000 and 001 can only occur if the BUKT bit

(see Table 4-1) is set in the RXB0CTRL

over into RXB1.

MCP2510

FIGURE 4-3: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

(ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10SID9SID8SID7SID6SID5SID4SID3

bit 7 bit 0

bit 7-0 SID<10:3>: Standard Identifier Filter Bits <10:3>

These bit s hold the fil ter bi ts to be applied to bits <10:3> of the Standard Id enti fie r porti on of a

received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

Acceptance Filter Register Acceptance Mask Register

RxRqst

Message Assembl y Buffer

RXFn0

RXFn1

RXFnn

RXMn0

RXMn1

RXMnn

Identifier

MCP2510

(ADDRESS: 01h, 05h, 09h, 11h, 15h, 19h)

(ADDRESS: 02h, 06h, 0Ah, 12h, 16h, 1Ah)

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE —EID17EID16

bit 7 bit 0

bit 7-5 SID<2:0>: Standard Identifier Filter Bits <2:0>

These bits hold the filter bits to be applied to bits <2:0> of the Standard Identifier portion of a

received message

bit 4 Unimplemented: Reads as '0'

bit 3 EXIDE: Extended Identifier Enable

1 = Filter is applied only to Extended Frames

0 = Filter is applied only to Standard Frames

bit 2 Unimplemented: Reads as '0

bit 1-0 EID<17:16>: Exended Identifier Filter Bits <17:16>

These bit s ho ld the filter bi t s to be ap pli ed to bi ts <17:16> of the Extende d Identifier portion of

a received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID<15:8>: Extended Identifier Bits <15:8>

These bit s hold the filter bit s to be app lied to bit s <15 :8> of the Exten ded Iden tifier port ion of a

received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 03h, 07h, 0Bh, 13h, 17h, 1Bh)

(ADDRESS: 20h, 24h)

(ADDRESS: 21h, 25h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

bit 7-0 EID<7:0>: Extended Identifier Bits <7:0>

These bit s hold the fil ter bits to be applied to the bi ts <7:0> of the Extended Ide ntifier porti on of

a received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10SID9SID8SID7SID6SID5SID4SID3

bit 7 bit 0

bit 7-0 SID<10:3>: Standard Identifier Mask Bits <10:3>

These bi ts hold the mask bit s to be app lied to bi ts <10:3> of t he S t and ard Id ent ifier p ortion of a

received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x U-0 U-0 U-0 R/W-x R/W-x

SID2 SID1 SID0 ———EID17EID16

bit 7 bit 0

bit 7-5 SID<2:0>: Standard Identifier Mask Bits <2:0>

These bits hold the mask bits to be applied to bits<2:0> of the Standard Identifier portion of a

received message

bit 4-2 Unimplemented: Reads as '0'

bit 1-0 EID<17:16>: Extended Identifier Mask Bits <17:16>

These bit s hold the mask bi ts to be appl ied to bits <17:1 6> of the Extended Identifier porti on of

a received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

(ADDRESS: 22h, 26h)

(ADDRESS: 23h, 27h)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID<15:8>: Extended Identifier Bits <15:8>

These bit s hold the filter bit s to be app lied to bit s <15 :8> of the Exten ded Iden tifier port ion of a

received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

bit 7-0 EID<7:0>: Extended Identifier Mask Bits <7:0>

These bits hold the mask bits to be applied to the bits <7:0> of the Extended Identifier portion

of a received message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

NOTES:

MCP2510

5.0 BIT TIMING

All nodes on a given CAN bus must have the same

nomina l bit rate . The CAN pro tocol use s Non Return to

Zero (NRZ) coding which does not encode a clock

within the data stream. Therefore, the receive clock

must be recovered by the receiving nodes and syn-

chronized to the transmitters clock.

As oscillators and transmission time may vary from

node to node, the receiver must have some type of

Phase Lock Loop (PLL) synchronized to data transmis-

sion edges to synchronize and maintain the receiver

clock. Since the data is NRZ coded, it is necessary to

include bit stuffing to ensure that an edge occurs at

least every six bit times, to maintain the Digital Phase

Lock Loop (DPLL) synchronization.

The bit timing of the MCP2510 is implemented using a

DPLL that is con figured to syn ch ronize to t he in com in g

data , and provide th e nominal tim ing for the tran smitted

data. The DPLL breaks each bit time into multiple seg-

ments made up of minimal periods of time called the

time quanta (TQ).

Bus tim ing fun ctions e xecuted w ithin th e bit ti me fram e,

such as synchronization to the local oscillator, network

transmission delay compensation, and sample point

positio ning, are defined by the pro grammable bit timin g

logic of the DPLL.

All devi ces on the CAN bu s must us e the same bi t rate.

Howeve r , a ll devic es are not req uired to have th e same

master oscillator clock frequency. For the different

cloc k fr e que nc i es of t h e i n divi d ua l devi ce s , th e bi t rat e

has to be adjusted by appropriately setting the baud

rate presca ler and number of time quant a in each se g-

ment.

The nominal bit rate is the number of bits transmitted

per seco nd assuming an ideal transmitte r w ith an i dea l

oscillator, in the absence of resynchronization. The

nominal bit rate is defined to be a maximum of 1 Mb/s.

Nominal Bit Time is defined as:

TBIT = 1 / NOMlNAL BlT RATE

The nomi nal bit time can be though t of as being div ided

into separate non-overlapping time segments. These

segments are shown in Figure 5-1.

- Synchronization Segment (Sync_Seg)

- Propagation Time S egment (Prop_Seg)

- Phase Buffer Segment 1 (Phase_Seg1)

- Phase Buffer Segment 2 [Phase_Seg2)

Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg +

Phase_Seg1 + Phase_Seg2)

The time segments and also the nominal bit time are

made up of integer units of time called time quanta or

TQ (see Figure 5-1). By definition, the nominal bit time

is programmable from a minimum of 8 TQ to a maxi-

mum of 25 TQ. Also, by defin ition the minimum nomina l

bit time is 1 µs, corresponding to a maximum 1 Mb/s

rate.

FIGURE 5-1: BIT TIME PARTITIONING

Input Signal

Sync Prop

Segment Phase

Segment 1 Phase

Segment 2

Sample Point

MCP2510

5.1 Time Quanta

The Time Quanta (TQ) is a fixed unit of time derived

from the oscillator period. There is a programmable

baud-rate prescaler , w ith integral values ranging from 1

to 64, in addition to a fixed divide by two for clock gen-

eration.

Time quanta is defined as:

where Baud Rate is the binary value represented by

CNF1.BRP<5:0>

For some examples:

If FOSC = 16 MHz, BRP<5:0> = 00h, and Nominal Bit

Ti me = 8 TQ;

then TQ= 125 nsec and Nominal Bit Rate = 1 Mb/s

If FOSC = 20 MHz, BRP<5:0> = 01h, and Nominal Bit

Ti me = 8 TQ;

then TQ= 200 nsec and Nominal Bi t Rate = 625 Kb/s

If FOSC = 25 MHz, BRP<5:0> = 3Fh, and Nominal Bit

Ti me = 25 TQ;

then TQ = 5.12 µsec and Nominal Bit Rate = 7.8 Kb/s

The frequen cies of the osc illators in the diffe rent nodes

must be coo rdi nated in order to provide a system -w id e

specified nominal bit time. This means that all oscilla-

tors must have a TOSC that is a integral diviso r of TQ. It

should also be n oted tha t althoug h the num ber of TQ is

programmable from 4 to 25, the usable minimum is 6

TQ. Attempting to a bit time of less than 6 TQ in len gth

is not guaranteed to operate correctly

5.2 Synchronization Segment

This part of the bit time is used to synchronize the var-

ious CAN nodes on the bus. The edge of the input sig-

nal is expected to occur during the sync segment. The

duration is 1 TQ.

5.3 Propagation Segment

This p art of the bit time is used to c ompensate for p hys-

ical delay times within the network. These delay times

consist of the signal propagation time on the bus line

and the internal delay time of the nodes. The delay is

calcul ated as be ing the roun d trip time from transmit ter

to receiver (twice the signal's propagation time on the

bus line), the input comparator delay, and the output

driver delay. The length of the Propagation Segment

can be programmed from 1 TQ to 8 TQ by setting the

PRSEG2:PRSEG0 bits of the CNF2 register

(Register 5-2).

The total delay is calculated from the following individ-

ual delays:

- 2 * physical bus end to end delay; TBUS

- 2 * input comparator delay; TCOMP (depends

on application circuit)

- 2 * output driver delay; TDRIVE (depends on

application circuit)

- 1 * input to output of CAN controller; TCAN

(maximum defined as 1 TQ + delay ns)

-TPROPOGATION = 2 * (TBUS + TCOMP +

TDRIVE) + TCAN

- Prop_Seg = TPROPOGATION / TQ

5.4 Phase Buffer Segments

The Phase Buffer Segments are used to optimally

locate the sampling point of the received bit within the

nominal bit time. The sampling point occurs between

phase segment 1 and phase segment 2. These seg-

ments can be lengthened or shortened by the resyn-

chronization process (see Section 5.7.2). Thus, the

variation of the values of the phase buffer segments

represent the DPLL functionality. The end of phase

segment 1 determines the sampling point within a bit

time. ph ase segm ent 1 is pro grammabl e from 1 TQ to 8

TQ in du ration. Phas e segme nt 2 provides delay b efore

the next transmitted data transition and is also pro-

grammable from 1 TQ to 8 TQ in d uration (howev er du e

to IPT requirements the actual minimum length of

phase se gment 2 is 2 TQ - see Section 5.6 below), or it

may be defined to be equal to the greater of pha se seg-

ment 1 or the Information Processing Time (IPT). (see

Section 5.6).

5.5 Sample Point

The Sample Point is the point of time at which the bus

level i s read and value of the rec eived bit is determined.

The Sampling point occurs at the end of phase seg-

ment 1. If the bit timing is slow and contains many TQ,

it is p ossible to spec ify multi ple sam pling of the bus line

at the sample point. The value of the received bit is

determined to be the value of the majority decision of

three values. The three samples are taken at the sam-

ple poin t, a nd twice before with a tim e o f T Q/2 between

each sample.

5.6 Inform ation Processing Time

The Inform ation P roce ssing Time (IPT) i s the time seg-

ment, starting at the sample point, that is reserved for

calculation of the subsequent bit level. The CAN spec-

ification defines this time to be less than or equal to 2

TQ. The MCP2510 defines this time to be 2 TQ. Thus,

phase segment 2 must be at least 2 TQ long.

TQ2* Baud Rate + 1()*TOSC

MCP2510

5.7 Synchronization

To compensate for phase shifts between the oscillator

frequenc ies of ea ch of the nod es on the bu s, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. Synchronization is

the process by which the DPLL function is imple-

mented. When an edge in the transmitted data is

detecte d, the logic will co mpare the location of the edge

to the expected time (Sync Seg). The circuit will then

adjust the values of phase segment 1 and phase seg-

ment 2 as neces sary. There are two mec hanis ms use d

for synchronization.

5.7.1 HARD SYNCHRONIZATION

Hard Synchronization is only done when there is a

recessive to dominant edge during a BUS IDLE condi-

tion, indicating the start of a message. After hard syn-

chronization, the bit time counters are restarted with

Sync Seg. Hard synchronization forces the edge which

has occurred to li e within the synch ronization segment

of the restarted bit time. Due to the rules of synchroni-

zation, if a hard synchronization occurs there will not be

a resynchronization within that bit time.

5.7.2 RESYNCHRONIZATION

As a result of Resynchronization, phase segment 1

may be lengthened or phase segment 2 may be short-

ened. The amount of lengthening or shortening of the

phase buffer segments has an upper bound given by

the Synchronization Jump Width (SJW). The value of

the SJW will be added to phase segment 1 (see

Figure 5-2) or subtracted from phase segment 2 (see

Figure 5-3). The SJW represents the loop filtering of

the DPLL. The SJW is programmable between 1 TQ

and 4 TQ.

Clocking information will only be derived from reces-

sive to dominant transitions. The property that only a

fixed maximum number of successive bits have the

same value ensures resynchronization to the bit stream

during a frame.

The phase error of an edge is given by the position of

the edge relative to Sync Seg, measured in TQ. The

phase error is defined in magnitude of TQ as follows:

• e = 0 if the edge lies within SYNCESEG

• e > 0 if the edge lies before the SAMPLE POINT

• e < 0 if the edge lies after the SAMPLE POINT of

the previous bit

If the m agnitude of the p hase erro r is less than or e qual

to the programmed value of the synchronization jump

width , the effec t of a re sync hron izat ion is t he same as

that of a hard synchronization.

If the magnitude of the phase error is larger than the

synchronization jump width, and if the phase error is

positive, then phase segment 1 is lengthened by an

amount equal to the synchronization jump width.

If the magnitude of the phase error is larger than the

resynchronization jump width, and if the phase error is

negative, then phase segment 2 is shortened by an

amount equal to the synchronization jump width.

5.7.3 SYNCHRONIZATION RULES

• Only one synchronization within one bit time is

allowed

• An edge will be used for synchronization only if

the value detected at the previous sample point

(previously read bus value) differs from the bus

value immediately after the edge

• All other recessive to dominant edges fulfilling

rules 1 and 2 will be used for resynchronization

with th e ex ce pti on that a node tr ans mi tti ng a dom -

inant bit will not perform a resynchronization as a

result of a recessive to dominant edge with a pos-

itive phase error

FIGURE 5-2: LENGTHENING A BIT PERIOD

Input Signal

Sync Prop

Segment Phase

Segment 1 Phase

Segment 2

≤ SJW

Sample Nominal Actual Bit

Length

Bit Length

Point

MCP2510

FIGURE 5-3: SHORTENING A BIT PERIOD

5.8 Programming Time Segments

Some requirements for programming of the time seg-

ments:

• Prop Seg + Phase Seg 1 >= Phase Seg 2

• Prop Seg + Phase Seg 1 >= TDELAY

• Phase Seg 2 > Sync Jump Width

For example, assuming that a 125 kHz CAN baud rate

with FOSC = 20 MHz is desired:

TOSC = 50 nsec, choose BRP<5:0> = 04h, then TQ =

500 nsec. To obtain 125 kHz, the bit time must be 16

TQ.

Typically, the sampling of the bit should take place at

about 60-7 0% of the bit time, depen din g on the sys tem

parameters. Also, typically, the TDELAY is 1- 2 TQ.

Sync Seg = 1 TQ; Prop Seg = 2 TQ; So setting Phase

Seg 1 = 7 TQ w ould place th e sample at 10 TQ after th e

transition. This would leave 6 TQ for Phase Seg 2.

Since Phas e Seg 2 is 6, by the rules, SJW co uld be the

maximum of 4 TQ. However, normally a large SJW is

only n ecessary wh en the cl oc k gen eration of th e d iffer-

ent nodes is inaccurate or unstable, such as using

ceramic resonators. So an SJW of 1 is typically

enough.

5.9 Oscillator Tolerance

The bit timing requirements allow ceramic resonators

to be used in appl icat ions wi th trans mission rates of up

to 125 kbit/sec, as a rule of thumb. For the full bus

speed range of the CAN protocol, a quartz oscillator is

required. A maximum node-to-node oscillator variation

of 1.7% is allowed.

Input Signal

Sync Prop

Segment Phase

Segment 1 Phase

Segment 2 ≤ SJW

Sample Actual Nominal

Bit Length

Point Bit Length

MCP2510

5.10 Bit Timing Configuration

Registers

The configuration registers (CNF1, CNF2, CNF3) con-

trol the bit ti ming for the CAN bus interfac e. These reg-

isters can only be modified when the MCP2510 is in

configuration mode (see Section 9.0).

5.10.1 CNF1

The BRP<5:0> bits control the baud rate prescaler.

These bits set the length of TQ relative to the OSC1

input fre quenc y, with th e min imum le ngt h of TQ bei ng 2

OSC1 clock cycles in length (when BRP<5:0> are set

to 000000). The SJW<1:0> bits select the synchroni-

zation jump width in terms of number of TQ’s.

5.10.2 CNF2

The PRSEG<2:0> bits set the length, in TQ’s, of the

propagation segment. The PHSEG1<2:0> bits set the

length, in TQ’s, of phase segment 1. The SAM bit con-

trols how many times the RXCAN pin is sampled. Set-

ting this bit to a ‘1’ c auses the bus to be s am ple d thre e

times; twic e at T Q/2 bef ore the sampl e poi nt, an d onc e

at the normal sample point (which is at the end of phase

segment 1). The value of the bus is determined to be

the valu e read du ring at l east two o f the sampl es. If the

SAM bit is set to a ‘0’ then the RXCAN pin is sampled

only once at the sample point. The BTLMODE bit con-

trols ho w the leng th of p hase segme nt 2 i s dete rmine d.

If this bit is set to a ‘1’ th en the leng th of phase segme nt

2 is determined by the PHSEG2<2:0> bits of CNF3

(see Section 5.10.3). If the BTLMODE bit is set to a ‘0’

then the length of phase segment 2 is the greater of

phase segment 1 and the information processing time

(which is fixed at 2 TQ for the MCP2510).

5.10.3 CNF3

The PHSEG2<2:0> bits set the length, in TQ’s, of

Phas e Se gme nt 2, i f th e CN F2. BTLM ODE b it is s et t o

a ‘1’. If the BTLMODE bit is set to a ‘0’ then the

PHSEG2<2:0> bits have no effect.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

bit 7 bit 0

bit 7-6 SJW<1:0>: Synchronization Jump Width Length

11 = Length = 4 x TQ

10 = Length = 3 x TQ

01 = Length = 2 x TQ

00 = Length = 1 x TQ

bit 5-0 BRP<5:0>: Baud Rate Prescaler

TQ = 2 x (BRP + 1) / FOSC

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0

bit 7 bit 0

bit 7 BTLMODE: Phase Segment 2 Bit Time Length

1 = Length of Phase Seg 2 determined by PHSEG22:PHSEG20 bits of CNF3

0 = Length of Phase Seg 2 is the greater of Phase Seg 1 and IPT (2TQ)

bit 6 SAM: Sample Point Configuration

1 = Bus line is sampled three times at the sample point

0 = Bus line is sampled once at the sample point

bit 5-3 PHSEG1<2:0>: Phase Segmen t 1 Length

(PHSEG 1 + 1) x TQ

bit 2-0 PRSEG<2:0>: Propagation Segment Length

(PRSEG + 1) x TQ

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— WAKFIL — — — PHSEG22 PHSEG21 PHSEG20

bit 7 bit 0

bit 7 Unimplemented: Reads as '0'

bit 6 WAKFIL: Wake-up Filter

1 = Wake-up filter enabled

0 = Wake-up filter disabled

bit 5-3 Unimplemented: Reads as '0'

bit 2-0 PHSEG2<2:0>: Phase Segment 2 Length

(PHSEG2 + 1) x TQ

Note: Minimum v alid setting for Phase Segment 2 is 2TQ

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

6.0 ERROR DETECTION

The CAN protocol provides sophisticated error detec-

tion me chanisms. The following errors can b e detected.

6.1 CRC Error

With the Cyclic Redundancy Check (CRC), the trans-

mitter c alculat es spec ial che ck bits for the bit sequ ence

from the start of a frame until the end of the data field.

This CRC sequence is transmitted in the CRC Field.

The receiv in g node also calcula tes the C RC se qu enc e

using the same formula and performs a comparison to

the received sequence. If a mismatch is detected, a

CRC error has occurred and an error frame is gener-

ated. The message is repeated.

6.2 Acknowledge Error

In the acknowledge field of a message, the transmitter

checks if the acknowledge slot (which has sent out as

a recess ive b it) cont ain s a domin ant bit. If no t, no oth er

node has received the frame correctly. An acknowl-

edge error has occurred; an error frame is generated;

and the message will have to be repeated.

6.3 Form Error

lf a node detects a dominant bit in one of the four seg-

ments including end of frame, interframe space,

acknowledge delimiter or CRC delimiter; then a form

error has occurred and an error frame is generated.

The message is repeated.

6.4 Bit Error

A Bit Error occurs if a transmitter sends a dominant bit

and de te ct s a re cessive bit or if it sends a recessive bit

and detects a dominant bit when monitoring the actual

bus lev el an d c om p aring it to the ju st transmitted b it. In

the case where the transmitter sends a recessive bit

and a dominant bit is detected during the arbitration

field a nd the ac knowledge s lot, no bi t error is g enerated

because normal arbitration is occurring.

6.5 Stuff Error

lf, between the start of frame an d the CRC delimiter , six

consecutive bits with the same polarity are detected,

the bit stuffing rule has been violated. A stuff error

occurs and an error frame is generated. The message

is repeated.

6.6 Error States

Detected errors are made public to all other nodes via

error frames. The transmission of the erroneous mes-

sage is aborted and the frame is repeated as soon as

possib le. Furthermore, eac h CA N no de is in one of the

three erro r states “error- active”, “error-p assive” or “bus-

off” a ccording to the value of the internal error counters.

The error-active state is the usual state where the bus

node can transmit messages and active error frames

(made of dominant bits) without any restrictions. In the

error-passive state, messages and passive error

frames (made of recessive bits) may be transmitted.

The bus-off state makes it temporarily impossible for

the station to participate in the bus communication.

During this state, messages can neither be received

nor transm itted.

6.7 Error Modes and Error Counters

The MCP2510 contains two error counters: the

Receive Error Counter (REC) (see Register 6-2), and

the Transmit Error Counter (TEC) (see Register 6-1).

The values of both counters can be read by the MCU.

These counters are incremented or decremented in

accor dance with the CAN bus specification.

The MCP2510 is error-active if both error counters are

below the error-passive limit of 128. It is error-passive

if at least one of the error counters equals or exceeds

128. It goes to bus-off if the transmit error counter

equals or exceeds the bus-off limit of 256. The device

remains in this state, until the bus-off recovery

sequence is received. The bus-off recovery sequence

consists of 128 occurrences of 11 consecutive reces-

sive bit s (see Figure 6-1). Note that the MCP2510, after

going bus-off, w ill rec over bac k to error-active, without

any in tervent ion by the MC U, if the bus re mains idl e for

128 X 11 bit times. If this is not desired, the error inter-

rupt service routine should address this. The current

error mode of the MCP2510 can be read by the MCU

via the EFLG register (R egi ste r 6-3).

Additionally, there is an error state warning flag bit,

EFLG: EWA RN, whi ch is set if at least on e of the err or

counters equals or exceeds the error warning limit of

96. EW ARN is reset if both err or counters are less than

the error warning limit.

MCP2510

FIGURE 6-1: ERROR MODES STATE DIAGRAM

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

bit 7 bit 0

bit 7-0 TEC<7:0>: Transmit Error Count

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

bit 7 bit 0

bit 7-0 REC<7:0>: Receive Error Count

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

Bus-Off

Error-Active

Error-Passive

REC > 127 or

TEC > 127

REC < 127 or

TEC < 127

TEC > 255

RESET

128 occurrences of

11 consecutive

“recessive” bits

MCP2510

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

RX1OVR RX0OVR TXBO TXEP RXEP TXWAR RXWAR EWARN

bit 7 bit 0

bit 7 RX1OVR: Receive Buffer 1 Ov erflow Flag

- Set when a valid message is received for RXB1 and CANINTF.RX1IF = 1

- Must be reset by MCU

bit 6 RX0OVR: Receive Buffer 0 Ov erflow Flag

- Set when a valid message is received for RXB0 and CANINTF.RX0IF = 1

- Must be reset by MCU

bit 5 TXBO: Bus-Off Error Flag

- Bit set when TEC reaches 255

- Rese t after a successful bus recovery sequence

bit 4 TXEP: Transmit Error-Passive Flag

- Set when TEC is equal to or greater than 128

- Reset when TEC is less than 128

bit 3 RXEP: Receiv e Error-Passive Flag

- Set when REC is equal to or greater than 128

- Reset when REC is less than 128

bit 2 TXWAR: Transmit Error Warning Flag

- Set when TEC is equal to or greater than 96

- Reset when TEC is less than 96

bit 1 RXWAR: Receive Error Warning Flag

- Set when REC is equal to or greater than 96

- Reset when REC is less than 96

bit 0 EWARN: Error Warning Flag

- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)

- Reset when both REC and TEC are less than 96

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

NOTES:

MCP2510

7.0 INTERRUPTS

The device has eight sources of interrupts. The CAN-

INTE register contains the individual interrupt enable

bits for each interrupt source. The CANINTF register

contains the corresponding interrupt flag bit for each

inte rru pt source . Wh en an inter ru pt oc curs t he IN T pin

is driven low by the MCP2510 and will remain low until

the Interrupt is cleared by the MCU. An Interrupt can

not be cleared if the resp ective co ndition s till prevails.

It is recommended that the bit modify command be

used to reset flag bits in the CANINTF register rather

than normal write operations. This is to prevent unin-

tentionally changing a flag that changes during the

write command, potentially causing an interrupt to be

missed.

It should be noted that the CANINTF flags are read/

write and an Interrupt can be generated by the MCU

setting any of thes e bits , provided t he associat ed CAN-

INTE bit is also set.

7.1 Interrupt Code Bits

The source of a pending interrupt is indicated in the

CANSTAT.ICOD (interrupt code) bits as indicated in

Regis ter 9-2. In the even t that multip le interrupt s occu r ,

the INT will remain low until all interrupts have been

reset by the MCU, and the CANSTAT.ICOD bits will

reflect the code for the highest priority interrupt that is

currently pending. Interrupts are internally prioritized

such t hat the lo wer the ICOD value the high er the int er-

rupt priority. Once the highest priority interrupt condi-

tion has been cleared, the code for the next highest

priority i nte rrupt that is pe nd ing (i f an y) will be re fle cte d

by the I COD bits (s ee Ta ble 7 -1). N ote tha t only th ose

interrupt sources that have their associated CANINTE

enable bit set will be reflected in the ICOD bits.

TABLE 7-1: ICOD<2:0> DECODE

7.2 Transmit Interrupt

When the Transmit Interrupt is enabled (CAN-

INTE.TXNIE = 1) an Interrupt will be generated on the

INT pin when the associated transmit buffer becomes

empty and is ready to be loaded with a new message.

The CANINTF.TXNIF bit will be set to indicate the

source of the interrupt. The interrupt is cleared by the

MCU resetting the TXNIF bit to a ‘0’.

7.3 Receive Interrupt

When the Receive Interrupt is enabled (CAN-

INTE.RXNIE = 1) an in terru pt wil l be gene rated on the

INT pin when a message has been successfully

receive d and load ed into the assoc iated rec eive buf fe r.

This interrupt is activated immediately after receiving

the EOF field. The CANINTF.RXNIF bit will be set to

indicate the source of the interrupt. The interrupt is

cleared by the MCU resetting the RXNIF bit to a ‘0’.

7.4 Message Error Interrupt

When an e rror occurs during tran sm is si on or re ception

of a message the message error flag (CAN-

INTF.MERRF) will be set and, if the CANINTE.MERRE

bit is set, an interrupt will be generated on the INT pin.

This is i ntended to be used to facili tate bau d rate det er-

mination when used in conjunction with listen-only

mode.

7.5 Bus Activity Wakeup Interrupt

When the MCP2510 is in sleep mode and the bus activ-

ity wakeup interrupt is enabled (CANINTE.WAKIE = 1),

an interrupt will be generated on the INT pin, and the

CANINTF.WAKIF bit will be set when activity is

detected on the CAN bus. This interrupt causes the

MCP2510 to exit sleep mode. The interrupt is reset by

the MCU clearing the WAKIF bit.

ICOD<2:0> Boolean Expression

000 ERR•WAK•TX0•TX1•TX2•RX0•RX1

001 ERR

010 ERR•WAK

011 ERR•WAK•TX0

100 ERR•WAK•TX0•TX1

101 ERR•WAK•TX0•TX1•TX2

110 ERR•WAK•TX0•TX1•TX2•RX0

111 ERR•WAK•TX0•TX1•TX2•RX0•RX1

MCP2510

7.6 Error Interrupt

When the error interrupt is enabled (CANINTE.ERRIE

= 1) an inte rrupt is generated on the INT pin if a n ov er-

flow condition occurs or if the error state of transmitter

or receiver has changed. The Error Flag Register

(EFLG) will indicate one of the following conditions.

7.6.1 RECEIVER OVERFLOW

An overflow condition occurs when the MAB has

assembled a valid received message (the message

meets the criteria of the acceptance filters) and the

receive buffer associated with the filter is not available

for loading of a new message. The associated

EFLG.RXNOVR bit will be set to indicate the overflow

condition. This bit must be cleared by the MCU.

7.6.2 RECEIVER WARNING

The receive error counter has reached the MCU warn-

ing limit of 96.

7.6.3 TRANSMITTER WARNING

The trans mit error co unter has r eached the M CU warn-

ing limit of 96.

7.6.4 RECEIVER ERROR-PASSIVE

The recei ve error counte r has exceede d the error- p as-

sive lim it of 127 and th e dev ic e has gon e to err or- p as -

sive state.

7.6.5 TRANSMITTER ERROR-PASSIVE

The transmit error counter has exceeded the error-

passive limit of 127 and the device has gone to error-

passive state.

7.6.6 BUS-OFF

The transmit error counter has exceeded 255 and the

device has gone to bus-off state.

7.7 Interrupt Acknowledge

Interrupts are directly ass oc ia ted with on e or mo re sta-

tus flags in the CANINTF register. Interrupts are pend-

ing as l ong as on e of the flags is set . O nc e an in terru pt

flag is s et by the device, t he flag can not b e reset by the

MCU until the int errupt condition is remov ed.

MCP2510

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE

bit 7 bit 0

bit 7 MERRE: Message Error Interrupt Enable

1 = Interrupt on error during message reception or transmission

0 =Disabled

bit 6 WAKIE: Wakeup Interrupt Enable

1 = Interrupt on CAN bus activity

0 =Disabled

bit 5 ERRIE: Error Interrupt Enable (multiple sources in EFLG register)

1 = Interrupt on EFLG error condition change

0 =Disabled

bit 4 TX2IE: Transm it Buffer 2 Empty Inte rrupt Enable

1 = Interrupt on TXB2 becoming empty

0 =Disabled

bit 3 TX1IE: Transm it Buffer 1 Empty Inte rrupt Enable

1 = Interrupt on TXB1 becoming empty

0 =Disabled

bit 2 TX0IE: Transm it Buffer 0 Empty Inte rrupt Enable

1 = Interrupt on TXB0 becoming empty

0 =Disabled

bit 1 RX1IE: Receive Buffer 1 Full Interrupt Enable

1 = Interrupt when message received in RXB1

0 =Disabled

bit 0 RX0IE: Receive Buffer 0 Full Interrupt Enable

1 = Interrupt when message received in RXB0

0 =Disabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MERRF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF

bit 7 bit 0

bit 7 MERRF: Message Error Interrupt Flag

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

bit 6 WAKIF: Wakeup Interrupt Flag

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

bit 5 ERRIF: Error Interrupt Flag (multiple sources in EFLG register)

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

bit 4 TX2IF: Transmit Buffer 2 Empty Interrupt Flag

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

bit 3 TX1IF: Transmit Buffer 1 Empty Interrupt Flag

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

bit 2 TX0IF: Transmit Buffer 0 Empty Interrupt Flag

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

bit 1 RX1IF: Receive Buffer 1 Full Interrupt Flag

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

bit 0 RX0IF: Receive Buffer 0 Full Interrupt Flag

1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)

0 = No interrupt pending

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

8.0 OSCILLATOR

The MC P2510 is designed to b e operated with a cry stal

or ceramic resonator connected to the OSC1 and

OSC2 pins. The MCP2510 oscillator design requires

the use of a p arallel cut crystal. Use of a series cut crys-

tal may give a frequency out of the crystal manufactur-

ers spe cificatio ns. A typic al oscilla tor circui t is shown i n

Figure 8-1. The MCP2510 may also be driven by an

external clock source connected to the OSC1 pin as

shown in Figure 8-2 and Figure 8-3.

8.1 Oscillator Startup Timer

The MCP25 10 utilizes an oscillator startup timer (OST),

which holds the MCP2510 in reset, to insure that the

oscillator has stabilized before the internal state

machine begins to operate. The OST maintains reset

for the first 128 OSC1 clock cycles after power up,

RESET, or wake up from sleep mode occurs . It should

be noted that no SPI operations should be attempted

until after the OST has expired.

8.2 CLKOUT Pin

The clo ck out pin is provi ded to th e system d esigner f or

use as the main system clock or as a clock input for

other devices in the syste m. The CLKOUT has an inter-

nal prescaler which can divide FOSC by 1, 2, 4 and 8.

The CLKOUT function is enabled and the prescaler is

selected via the CANCNTRL register (see Register 9-

1). The CLKOUT pin will be active upon system reset

and defau lt to th e s low e st speed (divide by 8) so tha t it

can be used as the MCU clock. When sleep mode is

requested, the MCP2510 will drive sixteen additional

clock cycles on the CLKOUT pin before entering sleep

mode. Th e idle s tat e of the CLKOU T pin in sle ep mod e

is low. When the CLKOUT function is disabled (CAN-

CNTRL.CLKEN = ‘0’) the CLKOUT pin is in a high

impedance state.

The CLKOUT function is designed to guarantee that

thCLKOUT and tlCLKOUT timi ngs ar e pre se rved when the

CLKOUT p in func tion i s enabled , di sable d, or the pres-

caler value is changed.

FIGURE 8-1: CRYSTAL/CERAMIC RESONATOR OPERATION

FIGURE 8-2: EXTERNAL CLOCK SOURCE

XTAL

OSC2

RS(1)

OSC1

RF(2) SLEEP

To internal logic

Note 1: A series resistor, RS, may be required for AT strip cut crystals.

Note 2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ.

Clock from

external system OSC1

OSC2

Open

(1)

Note 1: A resistor to ground may be used to reduce system noise. This may increase system current.

Note 2: Duty cycle restrictions must be observed (see Table 12-2).

MCP2510

FIGURE 8-3: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT

330 kΩ

74AS04 74AS04 MCP2510

OSC1

To Other

Devices

XTAL

330 kΩ

74AS04

0.1 mF

Note 1: Duty cycle restric tio ns must be obs erv ed (se e Table 12-2) .

MCP2510

9.0 MODES OF OPERATION

The MCP2510 has five modes of operation. These

modes are:

1. Configuration Mode.

2. Normal Mode.

3. Sleep Mode.

4. List en-O n ly Mo de.

5. Loop bac k Mo de.

The operational mode is selected via the CANCTRL.

REQOP bits (see Register 9-1). When changing

modes, the mode will not actua lly change until all pen d-

ing message transmissions are complete. Because of

this, the user must verify that the device has actually

changed into the requested mode before further oper-

ations are executed. Verification of the current operat-

ing mode is done by reading the CANSTAT. OPMODE

bits (see Register 9-2).

9.1 Configuration Mode

The MCP2510 must be initialized before activation.

This is only possi ble if the dev ice i s in th e confi gur ation

mode. Configuration mode is automatically selected

after powerup or a reset, or can be entered from any

other mode by setting the CANTRL.REQOP bits to

‘100’. When configuration mode is entered all error

counters are cleared. Configuration mode is the only

mode where the following registers are modifiable:

• CNF1, CNF2, CNF3

• TXRTSCTRL

• Acceptance Filter Registers

• Acceptance Mask Registers

Only when the CANSTAT.OPMODE bits read as ‘100’

can the ini tial iz ati on be perform ed , all ow in g the co nfi g-

uration registers, acceptance mask registers, and the

acceptance filter registers to be written. After the con-

figuration is complete, the device can be activated by

programming the CANCTRL.REQOP bits for normal

operation mode (or any other mode).

9.2 Sleep Mode

The MC P251 0 ha s a n in tern al s lee p m ode that is used

to minimize the current consumption of the device. The

SPI interface remains active even when the MCP2510

is in sleep mode, allowing access to all registers.

To enter sleep mode, the mode request bits are set in

the CANCTRL register. The CANSTAT.OPMODE bits

indica te w h eth er th e d ev ic e s uc cess ful ly en tere d s lee p

mode. These bits should be read after sending the

sleep command to the MCP2510. The MCP2510 is

active and has not yet entered sleep mode until these

bits indicate that sleep mode has been entered. When

in internal sleep mode, the wakeup interrupt is still

active (if enabled). This is done so the MCU can also

be placed into a sleep mode and use the MCP2510 to

wake it up upon detecting activity on the bus.

When in sleep mode, the MCP2510 stops its internal

oscillator . The MCP2510 will wake-up when bus activity

occurs or whe n the MCU set s, via the SPI interf ace, the

CANINTF.WAKIF bit to ‘generate’ a wake up attempt

(the CANIN TF.WAKIF bit must also be set i n ord er for

the wakeup interrupt to occur). The TXCAN pin will

remain in the recessive state while the MCP2510 is in

sleep mode. Note that Sleep Mode will be entered

immediately, even if a message is currently being

transmi tted, so it is neces sary to insure th at all TXREQ

bits are clear before setting Sleep Mode.

9.2.1 WAKE-UP FUNCTIONS

The device will monitor the RXCAN pin for activity while

it is in sleep mode. If the CANINTE.WAKIE bit is set,

the device will wake up and generate an interrupt.

Since the internal oscillator is shut down when sleep

mode is entered, it will take some amount of time for the

oscillator to start up and the device to enable itself to

receive messages. The device will ignore the message

that caused the wake-up from sleep mode as well as

any messages that occur while the device is ‘waking

up.’ The device will wake up in listen-only mode. The

MCU must set normal mode before the MCP2510 will

be able to communicate on the bus.

The dev ice c an be p rogramm ed to apply a low -pa ss fi l-

ter function to the RXCAN input line while in internal

sleep mode. This feature can be used to prevent the

device from wakin g up due to short glitches on the CAN

bus lines. The CNF3.WAKFIL bit enables or disables

the filter.

9.3 Listen Only Mode

Listen-only mode provides a means for the MCP2510

to receive all messages including messages with

errors. Th is mo de ca n b e used fo r bus mo nitor a pplic a-

tions or for detecting the baud rate in ‘hot plugging’ sit-

uations. For auto-baud detection it is necessary that

there are at least t wo other nodes, whi ch are co mmuni-

catin g wi t h each o t he r. T h e ba ud r at e ca n be de t ec ted

empirically by testing different values until valid mes-

sages are received. The listen-only mode is a silent

mode, meaning no messages will be transmitted while

in this state, including error flags or acknowledge sig-

nals. The filters and masks can be used to allow only

particular messages to be loaded into the receive reg-

isters, or the filte r masks can be se t to all z eros to all ow

a message with any identifier to pass. The error

Note: Care must be exercised to not enter sleep

mode while the MCP2510 is transmitting a

messa ge. If sleep mode is requested w hile

transmitting, the transmission will stop

withou t completing an d errors wil l occur on

the bus. Also, the message will remain

pending and transmit upon wake up.

MCP2510

counters are reset and deacti vated in th is state . The lis-

ten-only mode is act ivated by se tting th e mod e reques t

bits in th e CANCTRL register.

9.4 Loopback Mode

This mo de will allow internal transmissi on of message s

from the transmit buffers to the receive buffers without

actually transmitting messages on the CAN bus. This

mode can be used in sy stem develo pment an d testin g.

In this mode the ACK bit is ignored and the device will

allow incoming messages from its elf just a s if they w ere

coming from another node. The loopback mode is a

silent mode, meaning no messages will be transmitted

while in th is state, incl uding error flag s o r a ck nowl edg e

signals. The TXCAN pin will be in a reccessive state

while the device is in this mode. The filters and masks

can be used to allow only particular messages to be

loaded into the recei ve registers . The masks ca n be set

to all zeros to provide a mode that accepts all mes-

sages. The loopback mode is activated by setting the

mode request bits in the CANCTRL register.

9.5 Normal Mode

This is the standard operating mode of the MC P2510.

In this mode the device actively monitors all bus mes-

sages and generates acknowledge bits, error frames,

etc. This is also the only mode in which the MCP2510

will transmit messages over the CAN bus.

R/W-1 R/W-1 R/W-1 R/W-0 U-0 R/W-1 R/W-1 R/W-1

REQOP2 REQOP1 REQOP0 ABAT — CLKEN CLKPRE1 CLKPRE0

bit 7 bit 0

bit 7-5 REQOP<2:0>: Request Operation Mode

000 = Set Normal Operation Mode

001 = Set Sleep Mode

010 = Set Loopback Mode

011 = Set Listen Only Mode

100 = Set Configuration Mode

All other values for REQOP bits are invalid and should not be used

Note: On power up, REQOP = b’111’

bit 4 ABAT: Abort All Pending Transmissions

1 = Request abort of all pending transmit buffers

0 = Terminate request to abort all transmissions

bit 3 Unimplemented: Read as '0'

bit 2 CLKEN: CLKOUT Pin Enable

1 = CLKOUT pin enabled

0 = CLKOUT pin disabled (Pin is in high impedance state)

bit 1-0 CLKPRE <1:0>: CLKOUT Pin Prescaler

00 =F

CLKOUT = System Clock/1

01 =F

CLKOUT = System Clock/2

10 =F

CLKOUT = System Clock/4

11 =F

CLKOUT = System Clock/8

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

R-1 R-0 R-0 U-0 R-0 R-0 R-0 U-0

OPMOD2 OPMOD1 OPMOD0 — ICOD2 ICOD1 ICOD0 —

bit 7 bit 0

bit 7-5 OPMOD<2:0>: Operation Mode

000 = Device is in Normal Operation Mode

001 = Device is in Sleep Mode

010 = Device is in Loopback Mode

011 = Device is in Listen Only Mode

100 = Device is in Configuration Mode

bit 4 Unimplemented: Read as '0'

bit 3-1 ICOD<2:0>: Interrupt Flag Code

000 = No Interrupt

001 = Error Interrupt

010 = Wake Up Interrupt

011 = TXB0 Interrupt

100 = TXB1 Interrupt

101 = TXB2 Interrupt

110 = RXB0 Interrupt

111 = RXB1 Interrupt

bit 0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

MCP2510

NOTES:

MCP2510

10.0 REGISTER MAP

The register map for the MCP2510 is shown in

Table 10-1. Address locations for each register are

determined by using the column (higher order 4 bits)

and row (l ower o r de r 4 b it s ) v al ues . Th e r egi ste r s hav e

been arranged to optimize the sequential reading and

writing of data. Some specific control and status regis-

ters allow individual bit modification using the SPI Bit

Modify command. The registers that allow this com-

mand are shown as shaded locations in Table 10-1. A

summa ry of the MCP2 510 co ntrol reg isters is sh own in

Table 10-2.

TABLE 10-1: CAN CONTROLLER REGISTER MAP

TABLE 10-2: CONTROL REGISTER SUMMARY

Lower

Address

Bits

Higher Order Address Bits

x000 xxxx x001 xxxx x010 xxxx x0011 xxxx x100 xxxx x101 xxxx x110 xxxx x111 xxxx

0000 RXF0SIDH RXF3SIDH RXM0SIDH TXB0CTRL TXB1CTRL TXB2CTRL RXB0CTRL RXB1CTRL

0001 RXF0SIDL RXF3SIDL RXM0SIDL TXB0SIDH TXB1SIDH TXB2SIDH RXB0SIDH RXB1SIDH

0010 RXF0EID8 RXF3EID8 RXM0EID8 TXB0SIDL TXB1SIDL TXB2SIDL RXB0SIDL RXB1SIDL

0011 RXF0EID0 RXF3EID0 RXM0EID0 TXB0EID8 TXB1EID8 TXB2EID8 RXB0EID8 RXB1EID8

0100 RXF1SIDH RXF4SIDH RXM1SIDH TXB0EID0 TXB1EID0 TXB2EID0 RXB0EID0 RXB1EID0

0101 RXF1SIDL RXF4SIDL RXM1SIDL TXB0DLC TXB1DLC TXB2DLC RXB0DLC RXB1DLC

0110 RXF1EID8 RXF4EID8 RXM1EID8 TXB0D0 TXB1D0 TXB2D0 RXB0D0 RXB1D0

0111 RXF1EID0 RXF4EID0 RXM1EID0 TXB0D1 TXB1D1 TXB2D1 RXB0D1 RXB1D1

1000 RXF2SIDH RXF5SIDH CNF3 TXB0D2 TXB1D2 TXB2D2 RXB0D2 RXB1D2

1001 RXF2SIDL RXF5SIDL CNF2 TXB0D3 TXB1D3 TXB2D3 RXB0D3 RXB1D3

1010 RXF2EID8 RXF5EID8 CNF1 TXB0D4 TXB1D4 TXB2D4 RXB0D4 RXB1D4

1011 RXF2EID0 RXF5EID0 CANINTE TXB0D5 TXB1D5 TXB2D5 RXB0D5 RXB1D5

1100 BFPCTRL TEC CANINTF TXB0D6 TXB1D6 TXB2D6 RXB0D6 RXB1D6

1101 TXRTSCTRL REC EFLG TXB0D7 TXB1D7 TXB2D7 RXB0D7 RXB1D7

1110 CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT

1111 CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL

Note: Shaded register locations indicate that these allow t he user to manipulate individual bits using the ‘Bit Modify’ Command.

Name Address

(Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/RST

Value

BFPCTRL 0C — — B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM --00 0000

TXRTSCTRL 0D — — B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM --xx x000

CANSTAT xE OPMOD2 OPMOD1 OPMOD0 — ICOD2 ICOD1 ICOD0 — 100- 000-

CANCTRL xF REQOP2 REQOP1 REQOP0 ABAT — CLKEN CLKPRE1 CLKPRE0 1110 -111

TEC 1C Transmit Error Counter 0000 0000

REC 1D Receive Error Counter 0000 0000

CNF3 28 — WAKFIL — — — PHSEG22 PHSEG21 PHSEG20 -0-- -000

CNF2 29 BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 0000 0000

CNF1 2A SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000

CANINTE 2B MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE 0000 0000

CANINTF 2C MERRF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000

EFLG 2D RX1OVR RX0OVR TXBO TXEP RXEP TXWAR RXWAR EWARN 0000 0000

TXB0CTRL 30 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00

TXB1CTRL 40 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00

TXB2CTRL 50 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00

RXB0CTRL 60 — RXM1 RXM0 — RXRTR BUKT BUKT FILHIT0 -00- 0000

RXB1CTRL 70 — RSM1 RXM0 — RXRTR FILHIT2 FILHIT1 FILHIT0 -00- 0000

MCP2510

NOTES:

© 2007 Microchip Technology Inc. DS21291F-page 57
MCP2510
11.0 SPI INTERFACE
11.1 Overview
The MCP2 510 is desig ned to inte rface dire ctly with  the
Serial Perip heral Interface (SPI) port avail able on many
microc ontroll ers an d supp orts  Mode  0,0 an d Mod e 1,1.
Commands and data  are sent to the device via  the SI
pin, with data being clocked in on the rising edge of
SCK. Data is driven out by the MCP2510, on the SO
line, on the falling edge of SCK. The CS pin must be
held l ow while any operation is performed. Table 11-1
shows the instruction by tes for all operations. Refer to
Figure 11-8 and Figure 11-9 for  detailed input and out-
put timing diagrams for both Mode 0,0 and Mode 1,1
operation.
11.2 Read Instruction
The Re ad  Ins truc tio n i s  started by lo w eri ng  the  C S pin.
The read instruction is then sent to the MCP2510 fol-
lowed by the 8-bit address (A7 through A0). After the
read instruction and address are sent, the data stored
in the register at the selected address will be shifted out
on the SO pi n. The interna l address p ointer is autom at-
ically incremented to the next address after each byte
of dat a is shifted  out. Therefore i t is possib le to read the
next  consec utive  regis ter addr ess  by  contin uing t o pr o-
vide clock  pulses. Any number of consecutive register
locations can be read sequentially using this method.
The read operation is terminated by raising the CS pin
(Figure 11-2).
11.3 Write Instruction
The Write Instruction is started by lowering the CS pin.
The write instruction is  then sent to the MCP2510 fol-
lowed  by the address an d at least one  byte of data. It i s
possib le to write to sequential registers by contin uing to
clock  in  da ta bytes, as  long as CS is  he ld  low. Dat a wil l
actually be written to the register on the rising edge of
the SCK line fo r the D0 bit. If the CS lin e is brought hig h
befor e eight bits  are loade d, the write  will be  aborted for
that dat a byte, previous bytes in the command will have
been written. Refer to the timing diagram in
Figure 11-3 for more detailed illustration of the byte
write sequence.
11.4 Request To Send (RTS) Instr uction
The RTS command can be used to initiate message
transmission for one or more of the transmit buffers. 
The part is selected by lowering the CS pin and the
RTS command byte is then sent to the MCP2510. As
shown in Figure 11-4, the last 3 bits of this command
indicate which transmit buffer(s) are enabled to send.
This command will set the TxBnCTRL.TXREQ bit for
the respective buffer(s). Any or all of the last three bits
can be set in a single command. If the RTS command
is sent with nnn = 000, the command will be ignored.
11.5 Read Status Instruction
The Read Status Instruction allows single instruction
access to some of the often used status bits for mes-
sage reception and transmission.
The part is selected by lowering the CS pin and the
read status command byte, shown in Figure 11-6, is
sent to the MCP2510. After the command byte is sent,
the MCP2510 will return eight bits of data that contain
the status. If additional clocks are sent after the first
eight bit s are tra nsmitted, the MC P2510 will co ntinue to
output the status bits as long as the CS pin is held  lo w
and clocks are provided on SCK. Each status bit
returned in this command may also be read by using
the st andard re ad comm and wi th the ap propriate re gis-
ter address.
11.6 Bit Modify Instr uction
The Bit  Mo dif y In stru ct ion provides a m ean s fo r se ttin g
or clearing individual bits in specific status and control
registers. This command is not available for all regis-
ters. See Section 10.0 (register map) to determine
which registers allow the use of this command.
The part is selected by lowering the CS pin and the Bit
Modify command byte is then sent to the MCP2510.
After the command byte is sent, the address for the
register i s s ent f oll ow ed  by th e mask  by te a nd th en the
data byte. The mask byte determines which bits in the
register  will be allowed to change. A  ‘1’ in the mask byte
will allow a bit in the register to change and a ‘0’ will not.
The data byte determines what value the modified bits
in the register will be changed to. A ‘1’ in the data byte
will set the bit and a ‘0’ will clear the bit, provided that
the mask for that bit is set to a ‘1’. (see Figure 11-1)
11.7 Reset Instruction
The Reset Instruction can be used to re-initialize the
internal register s of the MCP2510 and set configuration
mode. This command provides the same functionality,
via the SPI interface, as the RESET pin. The Reset
instruction is a single byte instruction which requires
selecting the device by pulling CS low, sending the
inst ruction byte, an d then raising CS. I t is hi ghly rec om-
mended that the reset command be sent (or the
RESET pin be lowered) as part of the power-on initial-
ization sequence. The MCP2510 will be held in reset
for 128 FOSC cycles.

MCP2510

FIGURE 11-1: BIT MODIFY

TABLE 11-1: SPI INSTRUCTION SET

FIGURE 11-2: READ INSTRUCTION

FIGURE 11-3: BYTE WRITE INSTRUCTION

Mask byt e

Data byte

Contents

Resulting

Contents

001 11100

XX1 100XX

010 11000

011 10000

Instruction Name Instruction Format Description

RESET 1100 0000 Resets internal registers to default state, set configuration mode

READ 0000 0011 Read data from register beginning at selected address

WRITE 0000 0010 Write data to register beginning at selected address

RTS

(Reque st To Send) 1000 0nnn Sets TXBnCTRL.TXREQ bit for one or more transmit buffers

Read Status 1010 0000 Polling command that outputs status bits for transmit/receive functions

Bit Modify 0000 0101 Bit modify selected registers

1000 0nnn

Request to send for TXB0

Request to send for TXB1

Request to send for TXB2

SCK

0 23456789101112131415161718192021221

0100000 1 A7654 1A0

76543210

instruction address byte

data out

high impedance

32 don’t care

SCK

0 23456789101112131415161718192021221

00000 A7654 1A076543210

instruction

high impedance

address byte data byte

MCP2510

FIGURE 11-4: REQUEST TO SEND INSTRUCTION

FIGURE 11-5: BIT MODIFY INSTRUCTION

FIGURE 11-6: READ STATUS INSTRUCTION

SCK

02345671

T2 T000

instruction

high impedance

SCK

0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 221

1100000A7654

1A0 76543210

instruction

high impedance

address byte mask byte

76543210

23 24 25 26 27 28 29 30 31

data byte

Note: Not all registers can be accessed with this command. See the register map in Section 10.0

for a list of the registers that apply.

SCK

0 23456789101112131415161718192021221

00001010

76543210

instruction

data out

high impedance

don’t care

CANINTF.RX0IF

CANINTF.RX1IF

CANINTF.TX0IF

CANINTF.TX1IF

CANINTF.TX2IF

TXB2CNTRL.TXREQ

TXB1CNTRL.TXREQ

TXB0CNTRL.TXREQ

7654321 0

data out

repeat

MCP2510

FIGURE 11-7: RESET INSTRUCTION

FIGURE 11-8: SPI INPUT TIMING

FIGURE 11-9: SPI OUTPUT TIMING

SCK

0 2345671

instruction

high impedance

000

SCK

LSB in

MSB in

high impedance

Mode 1,1

Mode 0,0

SCK

MSB out LSB out

don’t care

Mode 1,1

Mode 0,0

MCP2510

12.0 ELECTRICAL CHARACTERISTICS

12.1 Absolute Maxim um Ratings†

VDD.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VDD +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient tem p. with powe r appli ed................ ..... ................................................... ....................... ...........-65°C to +125°C

Soldering temperature of leads (10 seconds).......................................................................................................+300°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stres s rating only an d funct ional o peratio n of the de vice at those or a ny othe r condit ions ab ove tho se ind icated in

the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

MCP2510

TABLE 12-1: DC CHARACTERISTICS

DC Characteristics Industrial (I): TAMB = -40°C to +85°C VDD = 3. 0V to 5.5V

Extended (E): TAMB = -40°C to +125°C VDD = 4. 5V to 5.5V

Param.

No. Sym Characteristic Min Max Units Conditions

VDD Supply Voltage 3.0 5.5 V

VRET Register Retention Voltage 2.4 — V

High Level Input Voltage Note

VIH RXCAN 2 VDD+1 V

SCK, CS, SI , T X n RTS Pins .7 VDD VDD+1 V

OSC1 .85 VDD VDD V

RESET .85 VDD VDD V

Low Level Input Voltage Note

VIL RXCAN,TXnRTS Pins -0.3 .15 VDD V

SCK, CS, SI -0.3 0.4 V

OSC1 VSS .3 VDD V

RESET VSS .15 VDD V

Low Level Output Vo ltage

VOL TXCAN — 0.6 V IOL = -6.0 mA, VDD = 4.5V

RXnBF Pins — 0.6 V IOL = -8.5 mA, VDD = 4.5V

SO, CLKOUT — 0.6 V I OL = -2.1 mA, VDD = 4.5V

INT —0.6VIOL = -1.6 mA, VDD = 4.5V

High Level Output Voltage V

VOH TXCAN, RXnBF Pins VDD -0.7 — V IOH = 3.0 mA, VDD = 4.5V, I temp

SO, CLKOUT VDD -0.5 — V IOH = 400 µA, VDD = 4.5V

INT VDD -0.7 — V IOH = 1.0 mA, VDD = 4.5V

Input Leakage Current

ILI All I/O except OSC1 and

TXnRTS pins -1 +1 µA CS = RESET = VDD,

VIN = VSS to VDD

OSC1 Pin -5 +5 µA

CINT Internal Capacitance

(All Inputs And Outputs) —7pFTAMB = 25°C, fC = 1.0 MHz,

VDD = 5.0V (Note)

IDD Operating Current — 10 mA VDD = 5.5V, FOSC = 25 MHz,

FCLK = 1 MHz, SO = Open

IDDS Standby Current (Sleep Mode) — 5 µA CS, TXn RT S = VDD, Inputs tied to

VDD or VSS

Note: This parameter is periodically sampled and not 100% tested.

MCP2510

TABLE 12-2: OSCILLATOR TIMING CHARACTERISTICS

TABLE 12-3: CAN INTERFACE AC CHARACTERISTICS

TABLE 12-4: CLKOUT PIN AC/DC CHARACTERISTICS

Oscillator Timing Characteristics Industrial (I): TAMB = -40°C to +85°C VDD = 3.0V to 5.5V

Extended (E): TAMB = -40°C to +125°C VDD = 4. 5V to 5.5V

Param.

No. Sym Characteristic Min Max Units Conditions

FOSC Clock In Frequency 1

125

16 MHz

MHz 4.5V to 5.5V

3.0V to 4.5V

TOSC Clock In Period 40

62.5 1000

1000 ns

ns 4.5V to 5.5V

3.0V to 4.5V

TDUTY Duty Cycle (Exter nal Clock

Input) 0.45 0.55 — TOSH / (TOSH + TOSL)

Note: This parameter is periodically sampled and not 100% tested.

CAN Interface AC Characteristics Industrial (I): TAMB = -40°C to +85°C VDD = 3. 0V to 5.5V

Extended (E): TAMB = -40°C to +125°C VDD = 4. 5V to 5.5V

Param.

No. Sym Characteristic Min Max Units Conditions

TWF Wakeup Noise Filter 50 — ns

TDCLK CLOCKOUT Propagation

Delay —100ns

CLKOUT Pin AC/DC Characteristics Industrial (I): TAMB = -40°C to +85°C VDD = 3. 0V to 5.5V

Extended (E): TAMB = -40°C to +125°C VDD = 4. 5V to 5.5V

Param.

No. Sym Characteristic Min Max Units Conditions

thCLKOUT CLKOUT Pin High Time 15 — ns TOSC = 40 ns (Note)

tlCLKOUT CLK OUT Pin Low Time 15 — ns TOSC = 40 ns (Note)

trCLKOUT CLKOUT Pin Rise Time — 5 ns Measured from 0.3 VDD to 0.7 VDD

(Note)

tfCLKOUT CLK O UT Pin Fall Time — 5 ns Measured from 0.7 VDD to 0.3 VDD

(Note)

tdCLKOUT CLOCKOUT Propagation Delay — 100 ns

Note: CLKOUT prescaler set to divide by one.

MCP2510

TABLE 12-5: SPI INTERFACE AC CHARACTERISTICS

SPI Interface AC Characteristics In d ustr ia l ( I): TAMB = -40°C to +85°C VDD = 3.0V to 5.5V

Extended (E): TAMB = -40°C to +125°C VDD = 4. 5V to 5.5V

Param.

No. Sym Characteristic Min Max Units Conditions

FCLK Clock Frequency —

—

2.5

MHz

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

CSS CS Setup T ime 100 — ns

CSH CS Hold Time 100

115

180

—

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

CSD CS Disable T ime 100

100

280

—

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

SU Data Setup Time 20

—

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

HD Data Hold Tim e 20

—

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

RCLK Rise Time — 2 µs Note

FCLK Fall Ti me — 2 µs Note

HI Clock High Time 90

115

180

—

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

LO Clock Low Time 90

115

180

—

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

10 TCLD Clock Delay Ti me 50 — ns

11 TCLE Clock Enable Ti me 50 — ns

12 TVOutput Valid from Cloc k Low —

—

115

180

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

13 THO Output Hold Time 0 — ns Note

14 TDIS Output Disable Time — 200 ns Note

Note: This parameter is not 100% tested.

MCP2510

13.0 PACKAGING INFORMATION

13.1 Package Marking Information

18-Lead PDIP ( 300 mil)

18-Lead S OIC (300 mil)

20-Lead T SSOP (4.4 mm)

XXXXXXXX

XXXXXNNN

YYWW

XXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXXXXXX

YYWWNNN

Example:

MCP2510

I/STNNN

0728

MCP2510-I/SO

XXXXXXXXXXXX

0737NNN

MCP2510-I/P

XXXXXXXXXXXXXXXXX

0726NNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the ful l Micro chip pa rt num ber cannot be ma rked on o ne line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

MCP2510

18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 18

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .300 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .880 . 900 . 920

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .014

Upper Lead Width b1 .045 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

123

Microchip Technology Drawing C04-007

MCP2510

18-Lead Plastic Small Outline (SO ) – Wide, 7.50 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not ex ceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 18

Pitch e 1.27 BSC

Overall Height A – – 2.65

Molded Package Thickness A2 2.05 – –

Standoff § A1 0.10 – 0.30

Overall Width E 10.30 BSC

Molded Package Width E1 7.50 BSC

Overall Length D 11.55 BSC

Chamfer (optional) h 0. 25 – 0.75

Foot Length L 0.40 – 1. 27

Footprint L1 1.40 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.20 – 0.33

Lead Width b 0.31 – 0. 51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

Microchip Technology Drawing C04-051

MCP2510

20-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for inf orm ation purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 20

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 6.40 6.50 6.60

Foot Length L 0.45 0 .60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-088

MCP2510

APPENDIX A: REVISION HISTORY

Revisi on F (January 200 7)

This revision includes updates to the packaging

diagrams.

NOTES:

© 2007 Microchip Technology Inc. DS21291F-page 71
MCP2510
INDEX
A
Acknowledge Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1
B
BFpctrl - RXnBF Pin Control and Status Register . . . . . . .26
Bit Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
BIT Modify i nstr u ction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Bit Modi fy  In st ruction . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .57
Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Bit Timing Configuration Registers  . . . . . . . . . . . . . . . . . .39
Bit Timing Logic .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Bus Activity Wakeup Interrupt  . . . . . . . . . . . . . . . . . . . . . .45
Bus Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Byte Write instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
C
CAN Buffers and Protocol Engine Block Diagram . . . . . . . .5
CAN controller Register Map . . . . . . . . . . . . . . . . . . . . . . .55
CAN Interface AC characteristics  . . . . . . . . . . . . . . . . . . .63
CAN Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
CAN Protocol Engine Block Diagram  . . . . . . . . . . . . . . . . .6
CANCTRL - CAN Control Register  . . . . . . . . . . . . . . . . . .52
CANINTE - Interrupt Enable Register  . . . . . . . . . . . . . . . .47
CANSTAT - CAN Status Register  . . . . . . . . . . . . . . . . . . .53
CNF1 - Configuration Register1  . . . . . . . . . . . . . . . . . . . .39
CNF2 - Configuration Register2  . . . . . . . . . . . . . . . . . . . .40
CNF3 - Configuration Register3  . . . . . . . . . . . . . . . . . . . .40
Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1
CRC Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Crystal/ceramic resonator operation  . . . . . . . . . . . . . . . . .49
Cyclic Redundancy Check . . . . . . . .  . . . . . . . . . . . . . . . . . .6
D
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Device Functionality . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .5
E
EFLG - Error Flag Register  . . . . . . . . . . . . . . . . . . . . . . . .43
Electrical Characteristics . . . . . . . . .  . . . . . . . . . . . . . . . . .61
Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Error Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7, 13
Error Interrupt  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Error Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Error Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Error Modes and Error Counters . . . . . . . . . . . . . . . . . . . .41
Error States  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Extended Data Frame  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
External Clock (osc1) Timing chara cteristics  . . . . . . . . . . .63
External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 9
External Series Resonant Crystal Oscillator Circuit . . . . . .50
F
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Filter/Mask Truth Table  . . . . . . . . . .  . . . . . . . . . . . . . . . . .29
Form Erro r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Frame Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
H
Hard Synchronization  . . . . . . . . . . .  . . . . . . . . . . . . . . . . .37
I
Information Processing Time . . . . . . . . . . . . . . . . . . . . . . .36
Initiating Message Transmission . . . . . . . . . . . . . . . . . . . .15
Interframe Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Interrupt Acknowledge . . . . . . . . . . .  . . . . . . . . . . . . . . . . .46
Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
L
Lenghtening a Bit Period  . . . . . . . . . . . . . . . . . . . . . . . . .  37
Listen Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51
Loopback Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52
M
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61
Message Acceptance Filter  . . . . . . . . . . . . . . . . . . . . . . .  30
Message Acceptance Filters and Masks  . . . . . . . . . . . . .  29
Message Reception  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
Message Reception Flowchart . . . . . . . . . . . . . . . . . . . . .  23
Modes of Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51
N
Normal Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52
O
Oscillator  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
Oscillator Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38
Overload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3
P
Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
Packaging Information  . . . . . . . . . . . . . . . . . . . . . . . . . . .  65
Phase Buffer Segments . . . . . . . . . . . . . . . . . . . . . . . . . .  36
Programming Time Segments  . . . . . . . . . . . . . . . . . . . . .  38
Propagation Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
Protocol Finite State Machine  . . . . . . . . . . . . . . . . . . . . . .  6
R
Read Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
Read instruction Diagram . . . . . . . . . . . . . . . . . . . . . . . . .  58
Read Status Instruction  . . . . . . . . . . . . . . . . . . . . . . . . . .  57
Read Status instruction  . . . . . . . . . . . . . . . . . . . . . . . . . .  59
REC - Receiver Error Count . . . . . . . . . . . . . . . . . . . . . . .  42
Receive Buffers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
Receive Buffers Diagram . . . . . . . . . . . . . . . . . . . . . . . . .  22
Receive Interrupt  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
Receive Message Buffering . . . . . . . . . . . . . . . . . . . . . . .  21
Receiver Error Passive . . . . . . . . . . . . . . . . . . . . . . . . . . .  46
Receiver Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  46
Receiver Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  46
Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  55
Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
Request To Send (RTS) Instruction  . . . . . . . . . . . . . . 57, 59
Resynchronization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
RXB0BF and RXB1BF Pins . . . . . . . . . . . . . . . . . . . . . . .  21
RXB0CTRL - Receive Buffer 0 Control Register  . . . . . . .  24
RXB1CTRL - Receive Buffer 1 Control Register  . . . . . . .  25
RXBnDLC - Receive Buffer n Data Length Code . . . . . . .  28
RXBnDm - Receive Buffer n Data Field Byte m . . . . . . . .  28
RXBnEID0 - Receive Buffer n Extended Identifier Low  . .  28
RXBnEID8 - Receive Buffer n Extended Identifier Mid  . .  27
RXBnSIDH - Receive Buffer n Standard Identifier High . .  26
RXBnSIDL - Receive Buffer n Standard Identifier Low  . .  27
RXFnEID0 - Acceptance Filter n Extended Identifier Low  32
RXFnEID8 - Acceptance Filter n Extended Identifier Mid  31
RXFnSIDH - Acceptance Filter n Standard Identifier High 30
RXFnSIDL - Acceptance Filter n Standard Identifier Low  31
RXMnEID0 - Accep tance Filter Mask  n Extended Identifier 
Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
RXMnEID8 - Accep tance Filter Mask  n Extended Identifier 
Mid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
RXMnSIDH - Acce ptance  Filter Mask n Standard Identifier 
High  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32

MCP2510
DS21291F-page 72 © 2007 Mic rochip Technology Inc.
RXMnSIDL - Acceptance Filter Mask  n Standard Identifier 
Low  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
S
Sample Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Shortening a Bit Period  . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Sleep Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
SPI Int e r f a ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
SPI Interface Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . .57
SPI Port AC Characterist ics . . . . . . . . . . . . . . . . . . . . . . . .64
Standard Data Frame  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Stuff Error  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Synchronization Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Synchronization Segment  . . . . . . . . . . . . . . . . . . . . . . . . .36
T
TEC - Transmitter Error Count . . . . . . . . . . . . . . . . . . . . . .42
Time Quanta  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Transmit Interrupt  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Transmit Message Aborting . . . . . . . . . . .  . . . . . . . . . . . . .15
Transmit Message Buffering  . . . . . . . . . . . . . . . . . . . . . . .15
Transmit Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . .15
Transmit Message flowchart  . . . . . . . . . . . . . . . . . . . . . . .16
Transmit Message Priority . . . . . . . . . . . . . . . . . . . . . . . . .15
Transmitter Error Passive  . . . . . . . . . . . .  . . . . . . . . . . . . .4 6
Transmitter Warning  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
TXBnCTRL Transmit buffer n Control Register . . . . . . . . .17
TXBnDm - Transmit Buffer n Data Field Byte m  . . . . . . . .20
TXBnEID0 - Transmit Buffer n Extended Identifier Low  . .2 0
TXBnEID8 - Transmit Buffer n Extended Identifier Mid . . .1 9
TXBnEIDH - Transmit Buffer n Extended Identifier High . .19
TXBnSIDH - Transmit Buffer n Standard Identifier High  . .18
TXBnSIDL - Transmit Buffer n Standard Identifier Low . . .1 9
TXnRTS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
TXRTSCTRL - TXBNRTS Pin Contro l and Status Register  .
18
Typical System Implementation . . . . . . . . . . . . . . . . . . . . . .4
W
WAKE-up functions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Write Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
WWW, On-Line Support  . . . . . . . . . . . . .  . . . . . . . . . . . . . .2

MCP2510

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.com . Thi s w eb si te i s us ed as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user ’s guides and hardware support

docume nts , latest softw are releas es and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

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•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listin gs of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical suppo rt is a vailable through the web site

at: http://support.microchip.com

MCP2510

READER RESPONSE

It is ou r intention to pro vi de you with the best documentation possib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subject matter, and w ays in wh ich our d ocument ation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

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DS21291FMCP2510

1. What are t he best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

MCP2510

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTemperature

Range

Device

Device: MCP2510: CAN Controller w/SPI Interface

MCP2510T: CAN Controller w/SPI Interface

(Tape and Reel)

Temperature Range: - = -40°C to +85°C

E = -40°C to +125°C

Package: P = Plastic DIP (300 mil Body), 18-Lead

SO = Plastic SOIC (300 mil Body), 18-Lead

ST = TSSOP, (4.4 mm Body), 20-Lead

Examples:

a) MCP2510-E/P: Extended temperature,

PDIP package.

b) MCP2510-I/P: Industrial temperature,

PDIP package.

c) MCP2510-E/SO: Extended temperature,

SOIC package.

d) MCP2510-I/SO: Industrial temperature,

SOIC package.

e) MCP2510-I/SO: Tape and Reel, Industrial

temperature, SOIC package.

f) MCP2510I/ST: Industrial temperature,

TSSOP package.

g) MCP2510T-I/ST: Tape and Reel, Industrial

temperature, TSSOP package.

MCP2510

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only fo r yo ur c onvenien ce

and may be supers eded by updates. It is y our resp o ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXD EV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC , Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in t heir particular Microchip Data Sheet.

• Microchip believes that its family of products is one of t he most secure famili es of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal m ethods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

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Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11- 4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thail a nd - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhage n

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Sp ain - Mad rid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

12/08/06

MCP2510

Stand-Alone CAN Controller with SPI™ Inte rface 1

1.0 Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.0 Can Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.0 Message Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.0 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.0 Bit Ti m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.0 Erro r Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.0 Inte rr u p t s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.0 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.0 Regi s ter Ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.0 SPI In t e r f a c e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.0 Electr i c a l Char a cteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

13.0 Packag in g In fo rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

On-Line Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Reader Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Prod u c t Id enti fi catio n Sy stem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Worldwide Sa le s and Service........................................................ ..................................................................................................... 76

MCP2510