DataSheeT - enpirion(R) power solutions EP53A8xQI 1A PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor DESCRIPTION The EP53A8xQI is an Intel(R) Enpirion(R) Power System on a Chip (PowerSoC) DC-DC converter. It integrates the inductor, MOSFET switches, small-signal circuits and compensation in an advanced 3mm x 3mm x 1.1mm 16-pin QFN package. FEATURES * Integrated Inductor Technology * -40C to +85C Ambient Temperature Range * 3mm x 3mm x 1.1mm QFN Package * Total Solution Footprint ~ 21mm2 Integrated inductor ensures the complete power solution is fully characterized with the inductor carefully matched to the silicon and compensation network. It enables a tiny solution footprint, low output ripple, low part-count, and high reliability, while maintaining high efficiency. The complete solution can be implemented in as little as 21mm2 and operate from -40C to 85C ambient temperature range. * Low VOUT Ripple for IO Compatibility * High Efficiency, up to 94% * VOUT Range 0.6V to VIN - 0.5V * 1A Continuous Output Current * 5 MHz Switching Frequency * 3-pin VID for Glitch Free Voltage Scaling * Internal soft start circuit The EP53A8xQI uses a 3-pin VID to easily select the output voltage setting. Output voltage settings are available in two optimized ranges providing coverage for typical VOUT settings. * Short Circuit and Over Current Protection * UVLO and Thermal Protection * IC Level Reliability in a PowerSoC Solution The VID pins can be changed on the fly for fast dynamic voltage scaling. EP53A8LQI further has the option to use an external voltage divider. All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible. EP53A8xQI 4.7F 0805 X7R Portable Wireless and RF applications * Wireless Broad Band Data Cards * Solid State Storage Applications * Noise and Space Sensitive Applications VOUT AVIN ENABLE VSENSE VS0 VFB VS1 VS2 PGND AGND 10F 0805 X7R EFFICIENCY (%) 100 * VOUT VIN PVIN APPLICATIONS Efficiency vs. IOUT (VIN = 3.3V) 100 95 90 85 80 75 70 65 60 55 50 45 40 21mm2 CONDITIONS VIN = 3.3V 0 VOUT = 2.5V 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 OUTPUT CURRENT (A) Figure 1: Simplified Applications Circuit Figure 2. Highest Efficiency in Smallest Solution Size Page 1 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI ORDERING INFORMATION Part Number Package Markings TJ Rating Package Description EP53A8LQI AJXX -40C to +125C 16-pin (3mm x 3mm x 1.1mm) QFN EP53A8HQI AMXX -40C to +125C 16-pin (3mm x 3mm x 1.1mm) QFN EVB-EP53A8xQI QFN Evaluation Board Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html NC(SW) 1 2 13 AVIN PGND PGND 3 12 ENABLE VFB 4 11 VSENSE 5 AGND 6 7 8 NC(SW) PVIN 16 15 14 PVIN 2 13 AVIN PGND 3 12 ENABLE VS0 NC 4 11 VS0 10 VS1 VSENSE 5 10 VS1 9 VS2 AGND 9 VS2 Figure 3. EP53A8LQI Pin Out Diagram (Top View) 6 7 8 VOUT 14 NC(SW) 15 VOUT NC(SW) PGND 16 VOUT 1 VOUT NC(SW) NC(SW) PIN FUNCTIONS Figure 4. EP53A8HQI Pin Out Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: White `dot' on top left is pin 1 indicator on top of the device package. Page 2 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI PIN DESCRIPTIONS PIN NAME TYPE FUNCTION 1, 15, 16 NC(SW) - NO CONNECT - These pins are internally connected to the common switching node of the internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage to the device. 2, 3 PGND Ground Power ground. Connect this pin to the ground electrode of the Input and output filter capacitors. 4 VFB/ NC Analog 5 VSENSE Analog Sense pin for preset output voltages. Refer to application section for proper configuration. 6 AGND Power Analog ground. This is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider 7, 8 VOUT Power Regulated Output Voltage. Refer to application section for proper layout and decoupling. EP53A8LQI: Feedback pin for external divider option. EP53A8HQI: No Connect Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11. 9, 10, 11 VS2, VS1, VS0 Analog EP53A8LQI: Selects one of seven preset output voltages or an external resistor divider. EP53A8HQI: Selects one of eight preset output voltages. (Refer to section on output voltage select for more details.) 12 ENABLE Analog Output Enable. Enable = logic high; Disable = logic low 13 AVIN Power Input power supply for the controller circuitry. Connect to PVIN through a 100 Ohm resistor. 14 PVIN Power Input Voltage for the MOSFET switches. ABSOLUTE MAXIMUM RATINGS CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Absolute Maximum Pin Ratings PARAMETER SYMBOL MIN MAX UNITS Input Supply Voltage -0.3 6.0 V ENABLE, VSENSE, VSO - VS2 -0.3 VIN+0.3 V VFB (EP53A8LQI) -0.3 2.7 V Page 3 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI Absolute Maximum Thermal Ratings PARAMETER CONDITION MIN Maximum Operating Junction Temperature Storage Temperature Range Reflow Peak Body Temperature -65 (10 Sec) MSL3 JEDEC J-STD-020A MAX UNITS +150 C +150 C +260 C MAX UNITS Absolute Maximum ESD Ratings PARAMETER CONDITION MIN HBM (Human Body Model) 2000 V RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Input Voltage Range VIN 2.7 5.5 V Operating Ambient Temperature Range TA -40 +85 C Operating Junction Temperature TJ -40 +125 C THERMAL CHARACTERISTICS PARAMETER Thermal Resistance: Junction to Ambient -0 LFM (1) Thermal Overload Trip Point Thermal Overload Trip Point Hysteresis SYMBOL TYPICAL UNITS JA 80 C/W TJ-TP +155 C 25 C (1) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. Page 4 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI ELECTRICAL CHARACTERISTICS NOTE: VIN = 3.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25C. PARAMETER Operating Input Voltage SYMBOL TEST CONDITIONS VIN MIN TYP 2.4 MAX UNITS 5.5 V Under Voltage LockOut - VIN Rising VUVLOR 2.0 V Under Voltage LockOut - VIN Falling VUVLOF 1.9 V/ms Drop Out Resistance RDO Input to Output Resistance Output Voltage Range VOUT EP53A8LQI (VDO = ILOAD X RDO) EP53A8HQI Dynamic Voltage Slew Rate VSLEW EP53A8HQI EP53A8LQI VID Preset VOUT Initial Accuracy 350 0.6 1.8 500 m VIN-VDO 3.3 V 8 4 V/ms TA = 25C, VIN = 3.6V; VOUT ILOAD = 100mA ; -2 +2 % 0.612 V 0.8V VOUT 3.3V VFB Pin Voltage (Load and Temperature) 0A ILOAD 1A VVFB Starting Date Code: X501 or greater 0.588 0.6 Line Regulation VOUT_LINE 2.4V VIN 5.5V; Load = 0A 0.03 %/V Load Regulation VOUT_LOAD 0A ILOAD 1A; VIN = 3.6V 0.6 %/A Temperature Variation VOUT_TEMPL -40C TA +85C 30 ppm/C Output Current Range IOUT Subject to de-rating Shut-down Current ISD Enable = Low OCP Threshold ILIM 2.4V VIN 5.5V 0.6V VOUT 3.3V 0 1.25 1000 mA 0.75 A 1.4 A VS0-VS2, Pin Logic Low VVSLO 0.0 0.3 V VS0-VS2, Pin Logic High VVSHI 1.4 VIN V VS0-VS2, Pin Input Current (2) IVSX <100 nA Page 5 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 0.4 V Enable Pin Logic Low VENLO Enable Pin Logic High VENHI Enable Pin Current (2) IENABLE <100 nA IFB <100 nA Operating Frequency FOSC 5 MHz Soft Start Slew Rate VSS 8 4 V/ms Soft Start Rise Time (3) TSS Feedback Pin Input Current (2) 1.4 EP53A8HQI (VID only) EP53A8LQI (VID only) EP53A8LQI (VFB mode) 170 V 225 280 s (2) Parameter guaranteed by design and characterization. (3) Measured from when VIN VUVLO_R & ENABLE pin crosses its logic High threshold. Page 6 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI Efficiency vs. IOUT (VIN = 3.3V) 100 95 90 85 80 75 70 65 60 55 50 45 40 EFFICIENCY (%) EFFICIENCY (%) TYPICAL PERFORMANCE CURVES VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V CONDITIONS VIN = 3.3V 0 VOUT = 1.2V VOUT = 1.0V 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Efficiency vs. IOUT (VIN = 5.0V) 95 90 85 80 75 70 65 60 55 50 45 40 35 VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V CONDITIONS VIN = 5V 0 1 OUTPUT CURRENT (A) Output Voltage vs. Output Current Output Voltage vs. Output Current 1.220 1.015 VIN = 5.0V 1.010 VIN = 3.3V OUTPUT VOLTAGE (V) 1.020 OUTPUT VOLTAGE (V) VOUT = 1.0V 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1.005 1.000 0.995 0.990 CONDITIONS VOUT = 1.0V 0.985 0.980 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.215 VIN = 5.0V 1.210 VIN = 3.3V 1.205 1.200 1.195 1.190 CONDITIONS VOUT = 1.2V 1.185 1.180 1 0 OUTPUT CURRENT (A) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 OUTPUT CURRENT (A) Output Voltage vs. Output Current Output Voltage vs. Output Current 1.820 1.515 VIN = 5.0V 1.510 VIN = 3.3V OUTPUT VOLTAGE (V) 1.520 OUTPUT VOLTAGE (V) VOUT = 1.2V 1.505 1.500 1.495 1.490 CONDITIONS VOUT = 1.5V 1.485 1.480 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.815 VIN = 5.0V 1.810 VIN = 3.3V 1.805 1.800 1.795 1.790 CONDITIONS VOUT = 1.8V 1.785 1.780 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Page 7 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI TYPICAL PERFORMANCE CURVES (CONTINUED) Output Voltage vs. Output Current Output Voltage vs. Output Current 3.320 2.515 VIN = 5.0V 2.510 VIN = 3.3V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.520 2.505 2.500 2.495 2.490 CONDITIONS VOUT = 2.5V 2.485 2.480 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 3.315 VIN = 5.0V 3.305 3.300 3.295 3.290 3.285 3.280 0 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Output Voltage vs. Input Voltage 1.020 1.220 1.015 1.215 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Output Voltage vs. Input Voltage 1.010 1.005 1.000 0.995 LOAD = 0A 0.985 CONDITIONS VOUT_NOM = 1.0V LOAD = 1A 3 3.5 4 4.5 1.210 1.205 1.200 1.195 1.190 LOAD = 0A 1.185 5 2.5 5.5 3 1.520 1.820 1.515 1.815 1.510 1.505 1.500 1.495 1.485 CONDITIONS VOUT_NOM = 1.5V LOAD = 1A 4 4.5 5 5.5 Output Voltage vs. Input Voltage OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Output Voltage vs. Input Voltage LOAD = 0A 3.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 1.490 CONDITIONS VOUT_NOM = 1.2V LOAD = 1A 1.180 0.980 2.5 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 0.990 CONDITIONS VOUT = 3.3V 3.310 1.810 1.805 1.800 1.795 1.790 LOAD = 0A 1.785 1.480 CONDITIONS VOUT_NOM = 1.8V LOAD = 1A 1.780 2.5 3 3.5 4 4.5 5 5.5 INPUT VOLTAGE (V) 2.5 3 3.5 4 4.5 5 5.5 INPUT VOLTAGE (V) Page 8 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI TYPICAL PERFORMANCE CURVES (CONTINUED) Output Voltage vs. Input Voltage 2.520 3.320 2.515 3.315 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Output Voltage vs. Input Voltage 2.510 2.505 2.500 2.495 2.490 LOAD = 0A 2.485 LOAD = 1A CONDITIONS VOUT_NOM = 2.5V LOAD = 0A 3.305 3.300 3.295 3.290 3.285 2.480 3.280 3 3.5 4 4.5 5 5.5 5 5.1 INPUT VOLTAGE (V) LOAD = 0A OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.020 5.3 5.4 5.5 Output Voltage vs. Temperature 1.030 CONDITIONS VIN = 3.3V VOUT_NOM = 1.0V 5.2 INPUT VOLTAGE (V) Output Voltage vs. Temperature 1.030 LOAD = 1A 1.010 1.000 0.990 CONDITIONS VIN = 5.0V VOUT_NOM = 1.0V 1.020 LOAD = 0A LOAD = 1A 1.010 1.000 0.990 0.980 0.980 -40 -15 10 35 60 -40 85 -15 3.330 MAXIMUM OUTPUT CURRENT (A) CONDITIONS VIN = 5.0V VOUT_NOM = 3.3V 3.340 LOAD = 0A LOAD = 1A 3.320 3.310 3.300 3.290 3.280 -40 -15 10 35 60 35 60 85 Output Current De-rating Output Voltage vs. Temperature 3.350 10 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) OUTPUT VOLTAGE (V) CONDITIONS VOUT_NOM = 3.3V LOAD = 1A 3.310 85 AMBIENT TEMPERATURE (C) 2.0 1.8 VOUT = 1.0V 1.6 VOUT = 1.8V 1.4 VOUT = 2.5V CONDITIONS VIN = 3.3V TJMAX = 125C JA = 80C/W No Air Flow 1.2 1.0 0.8 0.6 0.4 0.2 0.0 55 60 65 70 75 80 85 90 95 100 105 AMBIENT TEMPERATURE (C) Page 9 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI TYPICAL PERFORMANCE CURVES (CONTINUED) MAXIMUM OUTPUT CURRENT (A) Output Current De-rating 2.0 1.8 VOUT = 1.0V 1.6 VOUT = 1.8V 1.4 VOUT = 2.5V CONDITIONS VIN = 5.0V TJMAX = 125C JA = 80C/W No Air Flow VOUT = 3.3V 1.2 1.0 0.8 0.6 0.4 0.2 0.0 55 60 65 70 75 80 85 90 95 100 105 AMBIENT TEMPERATURE (C) Page 10 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI TYPICAL PERFORMANCE CHARACTERISTICS Output Ripple at 20MHz Bandwidth CONDITIONS VIN = 5.0V VOUT = 1.2V IOUT = 1A VOUT (AC Coupled) Output Ripple at 20MHz Bandwidth CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 1A VOUT (AC Coupled) Enable Power Up Output Ripple at 20MHz Bandwidth CONDITIONS VIN = 5V VOUT = 3.3V IOUT = 1A VOUT (AC Coupled) Output Ripple at 20MHz Bandwidth CONDITIONS VIN = 3.3V VOUT = 1.8V IOUT = 1A VOUT (AC Coupled) Enable Power Down ENABLE ENABLE VOUT CONDITIONS VIN = 5.0V VOUT = 3.3V LOAD = 1A CONDITIONS VIN = 5.0V VOUT = 3.3V LOAD = 1A VOUT Page 11 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) Load Transient from 0 to 1A VOUT (AC Coupled) Load Transient from 0 to 1A CONDITIONS VIN = 5V VOUT = 1.2V LOAD VOUT (AC Coupled) CONDITIONS VIN = 5V VOUT = 3.3V LOAD Load Transient from 0 to 1A VOUT (AC Coupled) Load Transient from 0 to 1A CONDITIONS VIN = 3.7V VOUT = 1.2V VOUT (AC Coupled) CONDITIONS VIN = 3.3V VOUT = 1.8V LOAD LOAD Page 12 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI FUNCTIONAL BLOCK DIAGRAM PVIN UVLO Thermal Limit Current Limit ENABLE NC(SW) Soft Start P-Drive (-) Logic VOUT PWM Comp (+) N-Drive PGND VSENSE Sawtooth Generator Compensation Network (-) Switch VFB Error Amp (+) DAC VREF Voltage Select Package Boundry AVIN AGND VS0 VS1 VS2 Figure 5: Functional Block Diagram Page 13 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI FUNCTIONAL DESCRIPTION Synchronous DC-DC Step-Down PowerSoC The EP53A8xQI requires only 2 small MLCC capacitors and an 0201 MLC resistor for a complete DC-DC converter solution. The device integrates MOSFET switches, PWM controller, Gate-drive, compensation, and inductor into a tiny 3mm x 3mm x 1.1mm QFN package. Advanced package design, along with the high level of integration, provides very low output ripple and noise. The EP53A8xQI uses voltage mode control for high noise immunity and load matching to advanced 90nm loads. A 3-pin VID allows the user to choose from one of 8 output voltage settings. The EP53A8xQI comes with two VID output voltage ranges. The EP53A8HQI provides VOUT settings from 1.8V to 3.3V, the EP53A8LQI provides VID settings from 0.8V to 1.5V, and also has an external resistor divider option to program output setting over the 0.6V to VIN-0.5V range. The EP53A8xQI provides the industry's highest power density of any 1A DC-DC converter solution. The key enabler of this revolutionary integration is Altera's proprietary power MOSFET technology. The advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss at high switching frequencies and to allow a high level of integration. The semiconductor process allows seamless integration of all switching, control, and compensation circuitry. The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Altera Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. Protection features include under-voltage lock-out (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection. Integrated Inductor: Low-Noise Low-EMI The EP53A8xQI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly simplifies the power supply design process. The inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. Further, the package layout is optimized to reduce the electrical path length for the high di/dT input AC ripple currents that are a major source of radiated emissions from DC-DC converters. The integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power DCDC converter design. Voltage Mode Control, High Bandwidth The EP53A8xQI utilizes an integrated type III compensation network. Voltage mode control is inherently impedance matched to the sub 90nm process technology that is used in today's advanced ICs. Voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. The very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. Soft Start Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the "ENABLE" pin is asserted "high". Digital control circuitry limits the V OUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The EP53A8HQI has a soft-start slew rate that is twice that of the EP53A8LQI. Page 14 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI When the EP53A8LQI is configured in external resistor divider mode, the device has a fixed VOUT ramp time. Therefore, the ramp rate will vary with the output voltage setting. Output voltage ramp time is given in the Electrical Characteristics Table. Excess bulk capacitance on the output of the device can cause an over-current condition at startup. Assuming no-load at startup, the maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as: EP53A8LQI: COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 250uF EP53A8HQI: COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 125uF EP53A8LQI (in external divider mode): COUT_TOTAL_MAX = 2.25x10-4/VOUT Farads The nominal value for COUT is 10uF. See the applications section for more details. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense P-MOSFET which is compared to a reference current. When this level is exceeded the P-FET is turned off and the N-FET is turned on, pulling VOUT low. This condition is maintained for approximately 0.5mS and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat. Under Voltage Lockout During initial power up, an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. NOTE: The ENABLE pin must not be left floating. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature, the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 25C, the device will go through the normal startup process. Page 15 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI APPLICATION INFORMATION Output Voltage Programming The EP53A8xQI utilizes a 3-pin VID to program the output voltage value. The VID is available in two sets of output VID programming ranges. The VID pins should be connected either to an external control signal, AVIN or to AGND to avoid noise coupling into the device. The "Low" range is optimized for low voltage applications. It comes with preset VID settings ranging from 0.80V and 1.5V. This VID set also has an external divider option. To specify this VID range, order part number EP53A8LQI. The "High" VID set provides output voltage settings ranging from 1.8V to 3.3V. This version does not have an external divider option. To specify this VID range, order part number EP53A8HQI. EP53A8HQI VOUT VIN 100 PVIN VOUT 100 AVIN ENABLE VSENSE VS0 VS1 VS2 PGND AGND 4.7F 0805 X7R EP53A8LQI 10F 0805 X7R Figure 6. EP53A8HQI VID Application Circuit VOUT VIN PVIN VOUT AVIN ENABLE VSENSE VS0 VFB VS1 VS2 PGND AGND 4.7F 0805 X7R 10F 0805 X7R Figure 7. EP53A8LQI VID Application Circuit Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. NOTE: The VID pins must not be left floating. Table 1: EP53A8LQI VID Voltage Select Settings VS2 0 0 0 0 1 1 1 1 VS1 0 0 1 1 0 0 1 1 VS0 0 1 0 1 0 1 0 1 VOUT 1.50 1.45 1.20 1.15 1.10 1.05 0.8 EXT EP53A8L Low VID Range Programming The EP53A8LQI is designed to provide a high degree of flexibility in powering applications that require low VOUT settings and dynamic voltage scaling (DVS). The device employs a 3-pin VID architecture that allows the user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage divider option. The VID pin settings can be changed on the fly to implement glitch-free voltage scaling. Page 16 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI Table 1 shows the VS2-VS0 pin logic states for the EP53A8LQI and the associated output voltage levels. A logic "1" indicates a connection to AVIN or to a "high" logic voltage level. A logic "0" indicates a connection to AGND or to a "low" logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate. EP53A8LQI External Voltage Divider The external divider option is chosen by connecting VID pins VS2-VS0 to VIN or a logic "1" or "high". The EP53A8LQI uses a separatefeedback pin, VFB, when using the external divider. VSENSE must be connected to VOUT as indicated in Figure 8. The output voltage is selected by the following formula: VOUT 0.6V 1 Ra Rb EP53A8LQI VOUT VIN 100 4.7F 0805 X7R PVIN VOUT AVIN VS0 VSENSE VS1 VFB VS2 ENABLE PGND AGND RA 10F 0805 X7R RB Figure 8. EP53A8LQI External VOUT Setting Ra must be chosen as 237K to maintain loop gain. Then Rb is given as: Rb 142 .2 x10 3 VOUT 0.6 VOUT can be programmed over the range of 0.6V to (VIN - 0.5V). NOTE: Dynamic Voltage Scaling is not allowed between internal preset voltages and external divider. EP53A8HQI High VID Range Programming The EP53A8HQI VOUT settings are optimized for higher nominal voltages such as those required to power IO, RF, or IC memory. The preset voltages range from 1.8V to 3.3V. There are eight (8) preset output voltage settings. The EP53A8HQI does not have an external divider option. As with the EP53A8LQI, the VID pin settings can be changed while the device is enabled. Table 2 shows the VS0-VS2 pin logic states for the EP53A8HQI and the associated output voltage levels. A logic "1" indicates a connection to AVIN or to a "high" logic voltage level. A logic "0" indicates a connection to AGND or to a "low" logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate. These pins must not be left floating. Page 17 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI Table 2: EP53A8HQI VID Voltage Select Settings VS2 0 0 0 0 1 1 1 1 VS1 0 0 1 1 0 0 1 1 VS0 0 1 0 1 0 1 0 1 VOUT 3.3 3.0 2.9 2.6 2.5 2.2 2.1 1.8 Input Filter Capacitor The input filter capacitor requirement is a 4.7F 0603 low ESR MLCC capacitor. The input capacitor must use X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input filter applications. Output Filter Capacitor The output filter capacitor requirement is a minimum of 10F 0805 MLCC. Ripple performance can be improved by using 2x10F 0805 MLCC capacitors. The maximum output filter capacitance next to the output pins of the device is 60F low ESR MLCC capacitance. VOUT has to be sensed at the last output filter capacitor next to the EP53A8xQI. Additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient separation between the VOUT Sense point and the bulk capacitance. The separation provides an inductance that isolates the control loop from the bulk capacitance. Excess total capacitance on the output (Output Filter + Bulk) can cause an over-current condition at startup. Refer to the section on Soft-Start for the maximum total capacitance on the output. The output capacitor must use X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-DC converter output filter applications. Power-Up/Down Sequencing During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during power up or power down meets these requirements. Pre-Bias Start-up The EP53A8xQI supports startup into a pre-biased output of up to 1.5V. The output of the EP53A8xQI can be pre-biased with a voltage up to 1.5V when it is first enabled. Page 18 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI THERMAL CONSIDERATIONS Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Enpirion PowerSoC helps alleviate some of those concerns. The Enpirion EP53A8xQI DCDC converter is packaged in a 3x3x1.1mm 16-pin QFN package. The recommended maximum junction temperature for continuous operation is 125C. Continuous operation above 125C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 155C. The following example and calculations illustrate the thermal performance of the EP53A8xQI. Example: VIN = 5V VOUT = 3.3V IOUT = 1A First calculate the output power. POUT = 3.3V x 1A = 3.3W EFFICIENCY (%) Next, determine the input power based on the efficiency () shown in Figure 9. Efficiency vs. IOUT (VIN = 5.0V) 95 90 85 80 75 70 65 60 55 50 45 40 35 86.5% CONDITIONS VIN = 5V 0 0.1 0.2 0.3 0.4 0.5 VOUT = 3.3V 0.6 0.7 0.8 0.9 1 OUTPUT CURRENT (A) Figure 9: Efficiency vs. Output Current For VIN = 5V, VOUT = 3.3V at 1A, 86.5% = POUT / PIN = 86.5% = 0.865 PIN = POUT / PIN 3.3W / 0.865 3.815W Page 19 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output power from the input power. PD = PIN - POUT 3.815W - 3.3W 0.515W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (JA). The JA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EP53A8xQI has a JA value of 80 C/W without airflow. Determine the change in temperature (T) based on PD and JA. T = PD x JA T 0.515W x 80C/W = 41.2C 41C The junction temperature (TJ) of the device is approximately the ambient temperature (T A) plus the change in temperature. We assume the initial ambient temperature to be 25C. TJ = TA + T TJ 25C + 41C 66C The maximum operating junction temperature (TJMAX) of the device is 125C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated. TAMAX = TJMAX - PD x JA 125C - 41C 84C The maximum ambient temperature (before de-rating) the device can reach is 84C given the input and output conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. Page 20 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI LAYOUT RECOMMENDATIONS Figure 10 shows critical components and layer 1 traces of a recommended minimum footprint EP53A8LQI/EP53A8HQI layout with ENABLE tied to VIN. Alternate ENABLE configurations, and other small signal pins need to be connected and routed according to specific customer application. Please see the Gerber files on the Altera website www.altera.com/enpirion for exact dimensions and other layers. Please refer to Figure 10 while reading the layout recommendations in this section. Figure 10: Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View) Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EP53A8xQI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EP53A8xQI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: Input and output grounds are separated until they connect at the PGND pins. The separation shown on Figure 10 between the input and output GND circuits helps minimize noise coupling between the converter input and output switching loops. Recommendation 3: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please see the Gerber files on the Altera website www.altera.com/enpirion. Recommendation 4: Multiple small vias should be used to connect the ground traces under the device to the system ground plane on another layer for heat dissipation. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the +V copper. Please see Figure 10. These vias connect the input/output filter capacitors to the GND plane and help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under CIN and COUT, then put them just outside the capacitors along the GND. Do not use thermal reliefs or spokes to connect these vias to the ground plane. Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 10 this connection is made with RAVIN at the input capacitor close to the VIN connection. Page 21 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI RECOMMENDED PCB FOOTPRIN Figure 11: EP53A8xQI PCB Footprint (Top View) Page 22 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI PACKAGE DIMENSIONS Figure 12: EP53A8LQI Package Dimensions Page 23 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI Figure 13: EP53A8HQI Package Dimensions Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html Page 24 03651 September 20, 2018 Rev H Datasheet | Intel(R) Enpirion(R) Power Solutions: EP53A8xQI REVISION HISTORY Rev I Date Change(s) Sep 2018 Changed datasheet into Intel format. WHERE TO GET MORE INFORMATION For more information about Intel(R) and Enpirion(R) PowerSoCs, visit: www.altera.com/enpirion (c) 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. * Other marks and brands may be claimed as the property of others. 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