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EP53A8xQI 1A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EP53A8xQI is an Intel® Enpirion® Power System
on a Chip (PowerSoC) DC-DC converter. It integrates
the inductor, MOSFET switches, small-signal circuits
and compensation in an advanced 3mm x 3mm x
1.1mm 16-pin QFN package.
Integrated inductor ensures the complete power
solution is fully characterized with the inductor
carefully matched to the silicon and compensation
network. It enables a tiny solution footprint, low
output ripple, low part-count, and high reliability,
while maintaining high efficiency. The complete
solution can be implemented in as little as 21mm2
and operate from -40°C to 85°C ambient temperature
range.
The EP53A8xQI uses a 3-pin VID to easily select the
output voltage setting. Output voltage settings are
available in two optimized ranges providing coverage
for typical VOUT settings.
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP53A8LQI further has the
option to use an external voltage divider.
All Enpirion products are RoHS compliant and lead-
free manufacturing environment compatible.
FEATURES
• Integrated Inductor Technology
• -40°C to +85°C Ambient Temperature Range
• 3mm x 3mm x 1.1mm QFN Package
• Total Solution Footprint ~ 21mm2
• Low VOUT Ripple for IO Compatibility
• High Efficiency, up to 94%
• VOUT Range 0.6V to VIN – 0.5V
• 1A Continuous Output Current
• 5 MHz Switching Frequency
• 3-pin VID for Glitch Free Voltage Scaling
• Internal soft start circuit
• Short Circuit and Over Current Protection
• UVLO and Thermal Protection
• IC Level Reliability in a PowerSoC Solution
APPLICATIONS
• Portable Wireless and RF applications
• Wireless Broad Band Data Cards
• Solid State Storage Applications
• Noise and Space Sensitive Applications
VOUT
VIN
10µF
0805
X7R
4.7µF
0805
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP53A8xQI
100Ω
VFB
VS0
VS1
VS2
ENABLE
Figure 1: Simplified Applications Circuit
Figure 2. Highest Efficiency in Smallest Solution Size
40
45
50
55
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. IOUT (VIN = 3.3V)
VOUT = 2.5V
CONDITIONS
VIN = 3.3V
21mm2
DataSheeT – enpirion® power solutions
03651 September 20, 2018 Rev H
Datasheet | Intel® Enpirion® Power Solutions: EP53A8xQI
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ORDERING INFORMATION
Package Markings
TJ Rating
Package Description
AJXX
-40°C to +125°C
16-pin (3mm x 3mm x 1.1mm) QFN
AMXX
-40°C to +125°C
16-pin (3mm x 3mm x 1.1mm) QFN
QFN Evaluation Board
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
PIN FUNCTIONS
Figure 3. EP53A8LQI Pin Out Diagram (Top View)
Figure 4. EP53A8HQI Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
NC(SW)
PGND
VFB
VSENSE
AGND
1
2
3
4
5
6
PVIN
AVIN
ENABLE
VS0
VS2
14
13
12
11
10
9
NC(SW)
NC(SW)
16 15
PGND
VOUT
VOUT
VS1
78
NC(SW)
PGND
NC
VSENSE
AGND
1
2
3
4
5
6
PVIN
AVIN
ENABLE
VS0
VS2
14
13
12
11
10
9
NC(SW)
NC(SW)
16 15
PGND
VOUT
VOUT
VS1
78
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Datasheet | Intel® Enpirion® Power Solutions: EP53A8xQI
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PIN DESCRIPTIONS
PIN
NAME
TYPE
FUNCTION
1, 15,
16
NC(SW)
-
NO CONNECT – These pins are internally connected to the common
switching node of the internal MOSFETs. NC (SW) pins are not to be
electrically connected to any external signal, ground, or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may
result in part malfunction or damage to the device.
2, 3
PGND
Ground
Power ground. Connect this pin to the ground electrode of the Input and
output filter capacitors.
4
VFB/ NC
Analog
EP53A8LQI: Feedback pin for external divider option.
EP53A8HQI: No Connect
5
VSENSE
Analog
Sense pin for preset output voltages. Refer to application section for
proper configuration.
6
AGND
Power
Analog ground. This is the quiet ground for the internal control circuitry,
and the ground return for external feedback voltage divider
7, 8
VOUT
Power
Regulated Output Voltage. Refer to application section for proper layout
and decoupling.
9, 10,
11
VS2,
VS1, VS0
Analog
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
EP53A8LQI: Selects one of seven preset output voltages or an external
resistor divider.
EP53A8HQI: Selects one of eight preset output voltages.
(Refer to section on output voltage select for more details.)
12
ENABLE
Analog
Output Enable. Enable = logic high; Disable = logic low
13
AVIN
Power
Input power supply for the controller circuitry. Connect to PVIN through
a 100 Ohm resistor.
14
PVIN
Power
Input Voltage for the MOSFET switches.
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Supply Voltage
-0.3
6.0
V
ENABLE, VSENSE, VSO – VS2
-0.3
VIN+0.3
V
VFB (EP53A8LQI)
-0.3
2.7
V
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Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
MIN
MAX
UNITS
Maximum Operating Junction
Temperature
+150
°C
Storage Temperature Range
-65
+150
°C
Reflow Peak Body
Temperature
(10 Sec) MSL3 JEDEC J-STD-020A
+260
°C
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
MAX
UNITS
HBM (Human Body Model)
±2000
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
VIN
2.7
5.5
V
Operating Ambient Temperature Range
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
Thermal Resistance: Junction to Ambient –0 LFM (1)
JA
80
°C/W
Thermal Overload Trip Point
TJ-TP
+155
°C
Thermal Overload Trip Point Hysteresis
25
°C
(1) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high
thermal conductivity boards.
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Datasheet | Intel® Enpirion® Power Solutions: EP53A8xQI
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ELECTRICAL CHARACTERISTICS
NOTE: VIN = 3.6V, Minimum and Maximum values are over operating ambient temperature range unless
otherwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input
Voltage
VIN
2.4
5.5
V
Under Voltage Lock-
Out – VIN Rising
VUVLOR
2.0
V
Under Voltage Lock-
Out – VIN Falling
VUVLOF
1.9
V/ms
Drop Out Resistance
RDO
Input to Output Resistance
350
500
mΩ
Output Voltage Range
VOUT
EP53A8LQI (VDO = ILOAD X
RDO)
EP53A8HQI
0.6
1.8
VIN-VDO
3.3
V
Dynamic Voltage Slew
Rate
VSLEW
EP53A8HQI
EP53A8LQI
8
4
V/ms
VID Preset VOUT Initial
Accuracy
VOUT
TA = 25C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
-2
+2
%
VFB Pin Voltage (Load
and Temperature)
VVFB
0A ≤ ILOAD ≤ 1A
Starting Date Code: X501 or
greater
0.588
0.6
0.612
V
Line Regulation
VOUT_LINE
2.4V ≤ VIN ≤ 5.5V; Load = 0A
0.03
%/V
Load Regulation
VOUT_LOAD
0A ≤ ILOAD ≤ 1A; VIN = 3.6V
0.6
%/A
Temperature Variation
VOUT_TEMPL
-40C ≤ TA ≤ +85C
30
ppm/C
Output Current Range
IOUT
Subject to de-rating
0
1000
mA
Shut-down Current
ISD
Enable = Low
0.75
µA
OCP Threshold
ILIM
2.4V ≤ VIN ≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V
1.25
1.4
A
VS0-VS2, Pin Logic Low
VVSLO
0.0
0.3
V
VS0-VS2, Pin Logic
High
VVSHI
1.4
VIN
V
VS0-VS2, Pin Input
Current (2)
IVSX
<100
nA
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PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Enable Pin Logic Low
VENLO
0.4
V
Enable Pin Logic High
VENHI
1.4
V
Enable Pin Current (2)
IENABLE
<100
nA
Feedback Pin Input
Current (2)
IFB
<100
nA
Operating Frequency
FOSC
5
MHz
Soft Start Slew Rate
VSS
EP53A8HQI (VID only)
EP53A8LQI (VID only)
8
4
V/ms
Soft Start Rise Time (3)
TSS
EP53A8LQI (VFB mode)
170
225
280
s
(2) Parameter guaranteed by design and characterization.
(3) Measured from when VIN ≥ VUVLO_R & ENABLE pin crosses its logic High threshold.
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TYPICAL PERFORMANCE CURVES
40
45
50
55
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. IOUT (VIN = 3.3V)
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
VIN = 3.3V
35
40
45
50
55
60
65
70
75
80
85
90
95
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. IOUT (VIN = 5.0V)
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
VIN = 5V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.0V
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.2V
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.5V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.8V
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TYPICAL PERFORMANCE CURVES (CONTINUED)
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 2.5V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
CONDITIONS
VOUT = 3.3V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
2.5 3 3.5 4 4.5 5 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 1A
CONDITIONS
VOUT_NOM = 1.0V
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
2.5 3 3.5 4 4.5 5 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 1A
CONDITIONS
VOUT_NOM = 1.2V
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
2.5 3 3.5 4 4.5 5 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 1A
CONDITIONS
VOUT_NOM = 1.5V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.5 3 3.5 4 4.5 5 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 1A
CONDITIONS
VOUT_NOM = 1.8V
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TYPICAL PERFORMANCE CURVES (CONTINUED)
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
3 3.5 4 4.5 5 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 1A
CONDITIONS
VOUT_NOM = 2.5V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
5 5.1 5.2 5.3 5.4 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 0A
LOAD = 1A
CONDITIONS
VOUT_NOM = 3.3V
0.980
0.990
1.000
1.010
1.020
1.030
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 0A
LOAD = 1A
CONDITIONS
VIN = 3.3V
VOUT_NOM = 1.0V
0.980
0.990
1.000
1.010
1.020
1.030
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 0A
LOAD = 1A
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.0V
3.280
3.290
3.300
3.310
3.320
3.330
3.340
3.350
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 0A
LOAD = 1A
CONDITIONS
VIN = 5.0V
VOUT_NOM = 3.3V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
55 60 65 70 75 80 85 90 95 100 105
MAXIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
Output Current De-rating
VOUT = 1.0V
VOUT = 1.8V
VOUT = 2.5V
CONDITIONS
VIN = 3.3V
TJMAX = 125°C
θJA = 80°C/W
No Air Flow
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TYPICAL PERFORMANCE CURVES (CONTINUED)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
55 60 65 70 75 80 85 90 95 100 105
MAXIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
Output Current De-rating
VOUT = 1.0V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
VIN = 5.0V
TJMAX = 125°C
θJA = 80°C/W
No Air Flow
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TYPICAL PERFORMANCE CHARACTERISTICS
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5.0V
VOUT = 1.2V
IOUT = 1A
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 3.3V
IOUT = 1A
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1.2V
IOUT = 1A
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
IOUT = 1A
ENABLE
Enable Power Up
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
LOAD = 1A
VOUT
Enable Power Down
ENABLE
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
LOAD = 1A
VOUT
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
VOUT
(AC Coupled)
Load Transient from 0 to 1A
CONDITIONS
VIN = 5V
VOUT = 1.2V
LOAD
VOUT
(AC Coupled)
Load Transient from 0 to 1A
CONDITIONS
VIN = 5V
VOUT = 3.3V
LOAD
VOUT
(AC Coupled)
Load Transient from 0 to 1A
CONDITIONS
VIN = 3.7V
VOUT = 1.2V
LOAD
VOUT
(AC Coupled)
Load Transient from 0 to 1A
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
LOAD
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FUNCTIONAL BLOCK DIAGRAM
DAC
Switch
VREF
(+)
(-)
Error
Amp
VSENSE
VFB
VOUT
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
PVIN
ENABLE
PGND
Logic
Compensation
Network
NC(SW)
Voltage
Select
VS0 VS1
AVIN VS2AGND
Figure 5: Functional Block Diagram
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FUNCTIONAL DESCRIPTION
Synchronous DC-DC Step-Down PowerSoC
The EP53A8xQI requires only 2 small MLCC capacitors and an 0201 MLC resistor for a complete DC-DC
converter solution. The device integrates MOSFET switches, PWM controller, Gate-drive, compensation, and
inductor into a tiny 3mm x 3mm x 1.1mm QFN package. Advanced package design, along with the high level
of integration, provides very low output ripple and noise. The EP53A8xQI uses voltage mode control for high
noise immunity and load matching to advanced ≤90nm loads. A 3-pin VID allows the user to choose from one
of 8 output voltage settings. The EP53A8xQI comes with two VID output voltage ranges. The EP53A8HQI
provides VOUT settings from 1.8V to 3.3V, the EP53A8LQI provides VID settings from 0.8V to 1.5V, and also has
an external resistor divider option to program output setting over the 0.6V to VIN-0.5V range. The EP53A8xQI
provides the industry’s highest power density of any 1A DC-DC converter solution.
The key enabler of this revolutionary integration is Altera’s proprietary power MOSFET technology. The
advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss at
high switching frequencies and to allow a high level of integration. The semiconductor process allows seamless
integration of all switching, control, and compensation circuitry.
The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Altera
Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal
solution with assured performance over the entire operating range.
Protection features include under-voltage lock-out (UVLO), over-current protection (OCP), short circuit
protection, and thermal overload protection.
Integrated Inductor: Low-Noise Low-EMI
The EP53A8xQI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly
simplifies the power supply design process. The inherent shielding and compact construction of the integrated
inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board.
Further, the package layout is optimized to reduce the electrical path length for the high di/dT input AC ripple
currents that are a major source of radiated emissions from DC-DC converters. The integrated inductor
provides the optimal solution to the complexity, output ripple, and noise that plague low power DCDC
converter design.
Voltage Mode Control, High Bandwidth
The EP53A8xQI utilizes an integrated type III compensation network. Voltage mode control is inherently
impedance matched to the sub 90nm process technology that is used in today’s advanced ICs. Voltage mode
control also provides a high degree of noise immunity at light load currents so that low ripple and high
accuracy are maintained over the entire load range. The very high switching frequency allows for a very wide
control loop bandwidth and hence excellent transient performance.
Soft Start
Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when
the “ENABLE” pin is asserted “high”. Digital control circuitry limits the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated inductor.
The EP53A8HQI has a soft-start slew rate that is twice that of the EP53A8LQI.
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When the EP53A8LQI is configured in external resistor divider mode, the device has a fixed VOUT ramp time.
Therefore, the ramp rate will vary with the output voltage setting. Output voltage ramp time is given in the
Electrical Characteristics Table.
Excess bulk capacitance on the output of the device can cause an over-current condition at startup. Assuming
no-load at startup, the maximum total capacitance on the output, including the output filter capacitor and bulk
and decoupling capacitance, at the load, is given as:
EP53A8LQI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 250uF
EP53A8HQI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 125uF
EP53A8LQI (in external divider mode):
COUT_TOTAL_MAX = 2.25x10-4/VOUT Farads
The nominal value for COUT is 10uF. See the applications section for more details.
Over Current/Short Circuit Protection
The current limit function is achieved by sensing the current flowing through a sense P-MOSFET which is
compared to a reference current. When this level is exceeded the P-FET is turned off and the N-FET is turned
on, pulling VOUT low. This condition is maintained for approximately 0.5mS and then a normal soft start is
initiated. If the over current condition still persists, this cycle will repeat.
Under Voltage Lockout
During initial power up, an under voltage lockout circuit will hold-off the switching circuitry until the input
voltage reaches a sufficient level to insure proper operation. If
the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between
states.
Enable
The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will
disable the converter and cause it to shut down. A logic high will enable the converter into normal operation.
NOTE: The ENABLE pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature
exceeds the thermal shutdown temperature, the thermal shutdown circuit turns off the converter output
voltage thus allowing the device to cool. When the junction temperature decreases by 25C°, the device will go
through the normal startup process.
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APPLICATION INFORMATION
Output Voltage Programming
The EP53A8xQI utilizes a 3-pin VID to program the output voltage value. The VID is available in two sets of
output VID programming ranges. The VID pins should be connected either to an external control signal, AVIN
or to AGND to avoid noise coupling into the device.
The “Low” range is optimized for low voltage applications. It comes with preset VID settings ranging from
0.80V and 1.5V. This VID set also has an external divider option.
To specify this VID range, order part number EP53A8LQI.
The “High” VID set provides output voltage settings ranging from 1.8V to 3.3V. This version does not have an
external divider option. To specify this VID range, order part number EP53A8HQI.
VOUT
VIN
10µF
0805
X7R
4.7µF
0805
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP53A8HQI
100Ω
VS0
VS1
VS2
ENABLE
Figure 6. EP53A8HQI VID Application Circuit
VOUT
VIN
10µF
0805
X7R
4.7µF
0805
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP53A8LQI
100Ω
VFB
VS0
VS1
VS2
ENABLE
Figure 7. EP53A8LQI VID Application Circuit
Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is
connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider
with constant loop gain and optimum compensation, independent of the output voltage selected.
NOTE: The VID pins must not be left floating.
Table 1: EP53A8LQI VID Voltage Select Settings
EP53A8L Low VID Range Programming
The EP53A8LQI is designed to provide a high degree of flexibility in powering applications that require low
VOUT settings and dynamic voltage scaling (DVS). The device employs a 3-pin VID architecture that allows the
user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage divider
option. The VID pin settings can be changed on the fly to implement glitch-free voltage scaling.
VS2 VS1 VS0 VOUT
0 0 0 1.50
0 0 1 1.45
0 1 0 1.20
0 1 1 1.15
1 0 0 1.10
1 0 1 1.05
1 1 0 0.8
1 1 1 EXT
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Table 1 shows the VS2-VS0 pin logic states for the EP53A8LQI and the associated output voltage levels. A
logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively
can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level
between the logic high and logic low is indeterminate.
EP53A8LQI External Voltage Divider
The external divider option is chosen by connecting VID pins VS2-VS0 to VIN or a logic “1” or “high”. The
EP53A8LQI uses a separatefeedback pin, VFB, when using the external divider. VSENSE must be connected to
VOUT as indicated in Figure 8.
The output voltage is selected by the following formula:
Rb
Ra
OUT VV 16.0
VOUT
VIN
10µF
0805
X7R
4.7µF
0805
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP53A8LQI
100Ω
VFB
VS0
VS1
VS2
ENABLE
RA
RB
Figure 8. EP53A8LQI External VOUT Setting
Ra must be chosen as 237KΩ to maintain loop gain. Then Rb is given as:
6.0
102.142 3
OUT
bVx
R
VOUT can be programmed over the range of 0.6V to (VIN – 0.5V).
NOTE: Dynamic Voltage Scaling is not allowed between internal preset voltages and external divider.
EP53A8HQI High VID Range Programming
The EP53A8HQI VOUT settings are optimized for higher nominal voltages such as those required to power IO,
RF, or IC memory. The preset voltages range from 1.8V to 3.3V. There are eight (8) preset output voltage
settings. The EP53A8HQI does not have an external divider option. As with the EP53A8LQI, the VID pin
settings can be changed while the device is enabled.
Table 2 shows the VS0-VS2 pin logic states for the EP53A8HQI and the associated output voltage levels. A
logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively
can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level
between the logic high and logic low is indeterminate. These pins must not be left floating.
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Table 2: EP53A8HQI VID Voltage Select Settings
Input Filter Capacitor
The input filter capacitor requirement is a 4.7µF 0603 low ESR MLCC capacitor. The input capacitor must use
X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with
frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input filter
applications.
Output Filter Capacitor
The output filter capacitor requirement is a minimum of 10µF 0805 MLCC. Ripple performance can be
improved by using 2x10µF 0805 MLCC capacitors. The maximum output filter capacitance next to the output
pins of the device is 60µF low ESR MLCC capacitance. VOUT has to be sensed at the last output filter capacitor
next to the EP53A8xQI.
Additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient
separation between the VOUT Sense point and the bulk capacitance. The separation provides an inductance
that isolates the control loop from the bulk capacitance.
Excess total capacitance on the output (Output Filter + Bulk) can cause an over-current condition at startup.
Refer to the section on Soft-Start for the maximum total capacitance on the output.
The output capacitor must use X7R or equivalent dielectric formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-DC
converter output filter applications.
Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted
before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN
should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN,
ENABLE) together during power up or power down meets these requirements.
Pre-Bias Start-up
The EP53A8xQI supports startup into a pre-biased output of up to 1.5V. The output of the EP53A8xQI can be
pre-biased with a voltage up to 1.5V when it is first enabled.
VS2 VS1 VS0 VOUT
0 0 0 3.3
0 0 1 3.0
0 1 0 2.9
0 1 1 2.6
1 0 0 2.5
1 0 1 2.2
1 1 0 2.1
1 1 1 1.8
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THERMAL CONSIDERATIONS
Thermal considerations are important power supply design facts that cannot be avoided in the real world.
Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be
accounted for. The Enpirion PowerSoC helps alleviate some of those concerns. The Enpirion EP53A8xQI DC-
DC converter is packaged in a 3x3x1.1mm 16-pin QFN package. The recommended maximum junction
temperature for continuous operation is 125°C. Continuous operation above 125°C may reduce long-term
reliability. The device has a thermal overload protection circuit designed to turn off the device at an
approximate junction temperature value of 155°C.
The following example and calculations illustrate the thermal performance of the EP53A8xQI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 1A
First calculate the output power.
POUT = 3.3V x 1A = 3.3W
Next, determine the input power based on the efficiency (η) shown in Figure 9.
Figure 9: Efficiency vs. Output Current
For VIN = 5V, VOUT = 3.3V at 1A, η ≈ 86.5%
η = POUT / PIN = 86.5% = 0.865
PIN = POUT / η
PIN ≈ 3.3W / 0.865 ≈ 3.815W
35
40
45
50
55
60
65
70
75
80
85
90
95
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. IOUT (VIN = 5.0V)
VOUT = 3.3V
CONDITIONS
VIN = 5V
86.5%
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The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output
power from the input power.
PD = PIN – POUT
≈ 3.815W – 3.3W ≈ 0.515W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA
value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of
power dissipation. The EP53A8xQI has a θJA value of 80 ºC/W without airflow.
Determine the change in temperature (ΔT) based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.515W x 80°C/W = 41.2°C ≈ 41°C
The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in
temperature. We assume the initial ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 41°C ≈ 66°C
The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a
higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 41°C ≈ 84°C
The maximum ambient temperature (before de-rating) the device can reach is 84°C given the input and output
conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an
estimate.
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LAYOUT RECOMMENDATIONS
Figure 10 shows critical components and layer 1 traces of a recommended minimum footprint
EP53A8LQI/EP53A8HQI layout with ENABLE tied to VIN. Alternate ENABLE configurations, and other small
signal pins need to be connected and routed according to specific customer application. Please see the Gerber
files on the Altera website www.altera.com/enpirion for exact dimensions and other layers. Please refer to
Figure 10 while reading the layout recommendations in this section.
Figure 10: Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View)
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EP53A8xQI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EP53A8xQI should be as close to each other as possible
so that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Input and output grounds are separated until they connect at the PGND pins. The
separation shown on Figure 10 between the input and output GND circuits helps minimize noise coupling
between the converter input and output switching loops.
Recommendation 3: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors. Please see the Gerber files on the Altera website www.altera.com/enpirion.
Recommendation 4: Multiple small vias should be used to connect the ground traces under the device to the
system ground plane on another layer for heat dissipation. The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around
0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. It is preferred to
put these vias under the capacitors along the edge of the GND copper closest to the +V copper. Please see
Figure 10. These vias connect the input/output filter capacitors to the GND plane and help reduce parasitic
inductances in the input and output current loops. If the vias cannot be placed under CIN and COUT, then put
them just outside the capacitors along the GND. Do not use thermal reliefs or spokes to connect these vias to
the ground plane.
Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 10 this connection is made with RAVIN at the input
capacitor close to the VIN connection.
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Datasheet | Intel® Enpirion® Power Solutions: EP53A8xQI
Page 22
RECOMMENDED PCB FOOTPRIN
Figure 11: EP53A8xQI PCB Footprint (Top View)
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Datasheet | Intel® Enpirion® Power Solutions: EP53A8xQI
Page 23
PACKAGE DIMENSIONS
Figure 12: EP53A8LQI Package Dimensions
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Datasheet | Intel® Enpirion® Power Solutions: EP53A8xQI
Page 24
Figure 13: EP53A8HQI Package Dimensions
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
03651 September 20, 2018 Rev H
Datasheet | Intel® Enpirion® Power Solutions: EP53A8xQI
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.altera.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
Page 25
REVISION HISTORY
Rev
Date
Change(s)
I
Sep 2018
Changed datasheet into Intel format.
03651 September 20, 2018 Rev H