1
®X9400
Low Noise/Low Power/SPI Bus
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40Ω typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA max
•System V
CC: 2.7V to 5.5V operation
•Analog V
+/V–: -5V to +5V
•10kΩ, 2.5kΩ end to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
Interface
and
Control
Circuitry
CS
SCK
SO
A0
A1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
Data
8
VW0/RW0
VW1/RW1
R0 R1
R2 R3
Resistor
Array
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Resistor
Array
VH3/RH3
VL3/RL3
VW3/RW3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR) Pot 3
Pot 2
HOLD
Pot 0
VCC
VSS
WP
SI
V+
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Data Sheet FN8189.3July 28, 2006
2FN8189.3
July 28, 2006
Ordering Information
PART NUMBER PART
MARKING VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMPERATURE
RANGE
(°C) PACKAGE PKG. DWG. #
X9400WS24* X9400WS 5 ±10% 10 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400WS24ZT1
(Note) X9400WS Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free)
Tape and Reel M24.3
X9400WS24I* X9400WS I -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400WS24IZ*
(Note) X9400WS ZI -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9400WV24* X9400WV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24I* X9400WV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24IZ*
(Note) X9400WV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400WV24Z*
(Note) X9400WV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400YS24* X9400YS 2.5 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400YS24I* X9400YS I -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400YV24* X9400YV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24I* X9400YV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24IZ*
(Note) X9400YV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400YV24Z*
(Note) X9400YV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400WS24-2.7* X9400WS F 2.7 to 5.5 10 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400WS24I-2.7* X9400WS G -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400WS24IZ-2.7*
(Note) X9400WS ZG -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9400WV24-2.7* X9400WV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24I-2.7* X9400WV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400WV24IZ-2.7*
(Note) X9400WV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400WV24Z-2.7*
(Note) X9400WV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400YS24-2.7* X9400YS F 2.5 0 to +70 24 Ld SOIC (300 mil) M24.3
X9400YS24I-2.7* X9400YS G -40 to +85 24 Ld SOIC (300 mil) M24.3
X9400YV24-2.7* X9400YV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24I-2.7* X9400YV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9400YV24IZ-2.7*
(Note) X9400YV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9400YV24Z-2.7*
(Note) X9400YV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9400
3FN8189.3
July 28, 2006
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9400.
Chip Select (CS)
When CS is HIGH, the X9400 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9400, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A0 - A1)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9400. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 -
VL3/RL3)
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VW/RW (VW0/RW0 - VW3/RW3)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog Supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
VCC
VL0/RL0
VH0/RH0
WP
SI
A1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
V+
VL3/RL3
VH3/RH3
VW3/RW3
A0
SO
HOLD
SCK
VL2/RL2
VH2/RH2
SOIC
X9400
VSS
VW0/RW0
14
13
11
12
CS
VL1/RL1
VH1/RH1
VW1/RW1 VW2/RW2
V-
SI
A1
VH2/RH2
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
CS
VW0/RW0
VCC
V+
VL3/RL3
VH3/RH3
VW3/RW3
TSSOP
X9400
VW2/RW2
14
13
11
12
HOLD
VL1/RL1
VH1/RH1
VW1/RW1
A0
SO
VH0/RH0
V-
SCK
VL2/RL2
VL0/RL0
VSS
X9400
4FN8189.3
July 28, 2006
PIN NAMES
DEVICE DESCRIPTION
The X9400 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a wiper counter
register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9400 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of sixty-four
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register or
global XFR data register instructions (parallel load); it
can be modified one step at a time by the
increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9400 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
Symbol Description
SCK Serial Clock
SI, SO Serial Data
A0 - A1Device Address
VH0/RH0 - VH3/RH3,
VL0/RL0 - VL3/RL3
Potentiometer Pins (terminal
equivalent)
VW0/RW0 - VW1/RW1 Potentiometer Pins (wiper
equivalent)
WP Hardware Write Protection
VCC System Supply Voltage
VSS System Ground
NC No Connection
(MSB) (LSB)
D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV
X9400
5FN8189.3
July 28, 2006
Figure 1. Detailed Potentiometer Block Diagram
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9400 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9400 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9400 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9400 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9400 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
VH/RH
VL/RL
VW/RW
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
8 6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
(One of Four Arrays)
100
0 0 A1 A0
Device Type
Identifier
Device Address
1
X9400
6FN8189.3
July 28, 2006
Figure 3. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P0) selects which one of the four
potentiometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register —
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter Register
—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register
—This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where the
transfer occurs between all potentiometers and one
associated register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figure 7 and Figure 8.
I1I2I3 I0 R1 R0 P1 P0
Pot Select
Register
Select
Instructions
X9400
7FN8189.3
July 28, 2006
Figure 4. Two-Byte Instruction Sequence
Figure 5. Three-Byte Instruction Sequence (Write)
Figure 6. Three-Byte Instruction Sequence (Read)
Figure 7. Increment/Decrement Instruction Sequence
010100A1A0 I3 I2 I1 I0 R1 R0 P1 P0
SCK
SI
CS
0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0
SCK
SI
0 0 D5 D4 D3 D2 D1 D0
CS
00
0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0
SCK
SI
CS
00
S0
0 0 D5 D4 D3 D2 D1 D0
Don’t Care
010100A1A0 I3 I2 I1 I0 0 P1 P0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
X9400
8FN8189.3
July 28, 2006
Figure 8. Increment/Decrement Timing Limits
Table 1. Instruction Set
Instruction
Instruction Set
OperationI3I2I1I0R1R0P1P0
Read Wiper Counter Register 1 0 0 1 0 0 P1P0Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter Register 1 0 1 0 0 0 P1P0Write new value to the Wiper Counter Register
pointed to by P1 - P0
Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register pointed to
by P1 - P0 and R1 - R0
Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed to by
P1 - P0 and R1 - R0
XFR Data Register to Wiper
Counter Register
1101R
1R0P1P0Transfer the contents of the Data Register pointed to
by R1 - R0 to the Wiper Counter Register pointed to by
P1 - P0
XFR Wiper Counter Register
to Data Register
1110R
1R0P1P0Transfer the contents of the Wiper Counter
Register pointed to by P1 - P0 to the Register
pointed to by R1 - R0
Global XFR Data Register to
Wiper Counter Register
0001R
1R00 0 Transfer the contents of the Data Registers pointed
to by R1 - R0 of all four pots to their respective Wiper
Counter Register
Global XFR Wiper Counter
Register to Data Register
1000R
1R00 0 Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1 - R0 of all four pots
Increment/Decrement Wiper
Counter Register
00100 0P
1P0Enable Increment/decrement of the Wiper Counter
Register pointed to by P1 - P0
Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by
checking the WIP bit.
SCK
SI
VW/RW
INC/DEC CMD Issued
tWRID
Voltage Out
X9400
9FN8189.3
July 28, 2006
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9400 on SO) CS
Rising
Edge
010100A
1
A
0100100P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI) CS
Rising
Edge
010100A
1
A
0101000P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
Data Byte
(sent by X9400 on SO) CS
Rising
Edge
010100A
1
A
01011R
1
R
0
P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
Data Byte
(sent by host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1
A
01100R
1
R
0
P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses CS
Rising
Edge
010100A
1
A
01101R
1
R
0
P
1
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1
A
01110R
1
R
0
P
1
P
0
X9400
10 FN8189.3
July 28, 2006
Increment/Decrement Wiper Counter Register (WCR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Read Status
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SDA) CS
Rising
Edge
010100A
1
A
00010XXP
1
P
0
I/
D
I/
D....
I/
D
I/
D
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR
addresses CS
Rising
Edge
010100A
1
A
00001R
1
R
000
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR
addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A
1
A
01000R
1
R
000
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9400 on SO) CS
Rising
Edge
010100A
1
A
0010100010000000
W
I
P
X9400
11 FN8189.3
July 28, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any address
input with respect to VSS......................... -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH....................................................................V+
Any VL......................................................................V-
Lead temperature (soldering, 10 seconds)........ 300°C
IW (10 seconds)................................................±12mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
RTOTAL End to end resistance ±20 %
Power rating 50 mW 25°C, each pot
IW Wiper current ±6 mA
RWWiper resistance 150 250 ΩWiper Current = ± 1mA,
VCC =3V
40 100 ΩWiper Current = ± 1mA,
VCC =5V
Vv+ Voltage on V+ Pin X9400 +4.5 +5.5 V
X9400-2.7 +2.7 +5.5
Vv- Voltage on V- Pin X9400 -5.5 -4.5 V
X9400-2.7 -5.5 -2.7
VTERM Voltage on any VH/RH or VL/RL Pin V- V+ V
Noise -120 dBV Ref: 1kHz
Resolution 1.6 %
Absolute linearity (1) -1 +1 MI(3) Rw(n)(actual) - Rw(n)(expected)
Relative linearity (2) -0.2 +0.2 MI(3) Rw(n + 1) - [Rw(n) + MI]
Temperature coefficient of RTOTAL ±300 ppm/°C
Ratiometric temp. coefficient ±20 ppm/°C
CH/CL/CWPotentiometer capacitances 10/10/25 pF See Spice Macromodel
IAL RH, RL, RW leakage current 0.1 10 µA VIN = VSS to VCC. Device is in
stand-by mode.
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85°C
Device Supply Voltage (VCC) Limits
X9400 5V ± 10%
X9400-2.7 2.7V to 5.5V
X9400
12 FN8189.3
July 28, 2006
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP REQUIREMENTS (Power-up sequencing
can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First
VCC, then the potentiometer pins, RH, RL, and RW.
Voltage should not be applied to the potentiometer
pins before V+ or V- is applied. The VCC ramp rate
specifi-cation should be met, and any glitches or slope
changes in the VCC line should be held to <100mV if
possible. If VCC powers down, it should be held below
0.1V for more than 1 second before powering up again
in order for proper wiper register recall. Also, VCC
should not reverse polarity by more than 0.5V. Recall
of wiper position will not be complete until VCC, V+
and V-reach their final value.
EQUIVALENT A.C. LOAD CIRCUIT
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
ICC1 VCC supply current (Active) 400 µA fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2 VCC supply current (Nonvolatile
Write)
1mAf
SCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB VCC current (standby) 1 µA SCK = SI = VSS, Addr. = VSS
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V
VIL Input LOW voltage -0.5 VCC x 0.1 V
VOL Output LOW voltage 0.4 V IOL = 3mA
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Test Max. Unit Test Conditions
COUT(4) Output capacitance (SO) 8 pF VOUT = 0V
CIN(4) Input capacitance (A0, A1, SI, and SCK) 6 pF VIN = 0V
Symbol Parameter Min. Max. Unit
tPUR(5) Power-up to initiation of read operation 1 ms
tPUW(5) Power-up to initiation of write operation 5 ms
tR VCC(4) VCC Power-up ramp 0.2 50 V/msec
5V
1533Ω
100pF
SDA Output
X9400
13 FN8189.3
July 28, 2006
A.C. TEST CONDITIONS
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) tPUR and tPUW are the delays required from the time the
third (last) power supply (VCC, V+ or V-) is stable until the
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
SPICE Macro Model
SYMBOL TABLE
AC TIMING
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
Symbol Parameter Min. Max. Unit
fSCK SSI/SPI clock frequency 2.0 MHz
tCYC SSI/SPI clock cycle time 500 ns
tWH SSI/SPI clock high time 200 ns
tWL SSI/SPI clock low time 200 ns
tLEAD Lead time 250 ns
tLAG Lag time 250 ns
tSU SI, SCK, HOLD and CS input setup time 50 ns
tHSI, SCK, HOLD and CS input hold time 50 ns
tRI SI, SCK, HOLD and CS input rise time 2 µs
tFI SI, SCK, HOLD and CS input fall time 2 µs
tDIS SO output disable time 0 500 ns
tVSO output valid time 100 ns
tHO SO output hold time 0 ns
tRO SO output rise time 50 ns
tFO SO output fall time 50 ns
tHOLD HOLD time 400 ns
tHSU HOLD setup time 100 ns
tHH HOLD hold time 100 ns
tHZ HOLD low to output in High Z 100 ns
tLZ HOLD high to output in Low Z 100 ns
TINoise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns
tCS CS deselect time 2 µs
tWPASU WP, A0 and A1 setup time 0 ns
tWPAH WP, A0 and A1 hold time 0 ns
X9400
14 FN8189.3
July 28, 2006
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
TIMING DIAGRAMS
Input Timing
Output Timing
Symbol Parameter Typ. Max. Unit
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Unit
tWRPO Wiper response time after the third (last) power supply is stable 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 10 µs
tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns
...
CS
SCK
SI
SO
MSB LSB
High Impedance
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
X9400
15 FN8189.3
July 28, 2006
Hold Timing
XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
...
CS
SCK
SI MSB LSB
VW/RW
tWRL
...
SO High Impedance
...
CS
SCK
SO
SI ADDR
tWRID
High Impedance
VW/RW
...
Inc/Dec Inc/Dec
...
X9400
16 FN8189.3
July 28, 2006
Write Protect and Device Address Pins Timing
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
CS
WP
A0
A1
tWPASU tWPAH
(Any Instruction)
VR
VW/RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysteresis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9400
17 FN8189.3
July 28, 2006
Application Circuits (continued)
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
Attenuator Filter
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
R2
R4All RS = 10kΩ
+
–
VS
R2
R1
R
C
VO
X9400
18 FN8189.3
July 28, 2006
X9400
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
α0° 8° 0° 8° -
Rev. 1 4/06
19
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8189.3
July 28, 2006
X9400
Thin Shrink Small Outline Package Family (TSSOP)
N(N/2)+1
(N/2)
TOP VIEW
AD
0.20 C
2X B A
N/2 LEAD TIPS
B
E1
E
0.25 CAB
M
1
H
PIN #1 I.D.
0.05
e
C
0.10 C
N LEADS SIDE VIEW
0.10 CABM
b
c
SEE DETAIL “X”
END VIEW
DETAIL X
A2
0° - 8°
GAUGE
PLANE
0.25
L
A1
A
L1
SEATING
PLANE
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. E 12/02
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
