ispLSI® 2128/A
In-System Programmable High Density PLD
2128_10 1
USE ispLSI 2128E FOR NEW DESIGNS
Lead-
Free
Package
Options
Available!
Features
• ENHANCEMENTS
— ispLSI 2128A is Fully Form and Function Compatible
to the ispLSI 2128, with Identical Timing
Specifcations and Packaging
— ispLSI 2128A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 128 I/O Pins, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 100 MHz Maximum Operating Frequency
—tpd = 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Functional Block Diagram
Global Routing Pool (GRP)
Output Routing Pool (ORP) Output Routing Pool (ORP)
Output Routing Pool (ORP) Output Routing Pool (ORP)
Output Routing Pool (ORP) Output Routing Pool (ORP)
CLK 0
Output Routing Pool (ORP) Output Routing Pool (ORP)
CLK 1
CLK 2
Logic
Array GLB
DQ
DQ
DQ
DQ
0139(9A)/2128
C7
C6
C5
C4
C3
C2
C1
C0
D3 D2 D1 D0
D7 D6 D5 D4
B4 B5 B6 B7
B0 B1 B2 B3
A0
A1
A2
A3
A4
A5
A6
A7
Description
The ispLSI 2128 and 2128A are High Density Program-
mable Logic Devices. The devices contains128 Registers,
128 Universal I/O pins, eight Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2128 and 2128A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2128 and 2128A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. D7
(Figure 1). There are a total of 32 GLBs in the ispLSI 2128
and 2128A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com August 2006
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
2
USE ispLSI 2128E FOR NEW DESIGNS
Functional Block Diagram
Figure 1. ispLSI 2128/A Functional Block Diagram
Global
Routing
Pool
(GRP)
0139(10A)/2128
Megablock
RESET
Input Bus
D3 D2 D1 D0
D7 D6 D5 D4
Output Routing Pool (ORP) Output Routing Pool (ORP)
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
I/O 122
I/O 121
I/O 120
I/O 119
I/O 118
I/O 117
I/O 116
I/O 115
I/O 114
I/O 113
I/O 112
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
I/O 104
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
I/O 98
I/O 97
I/O 96
SDI/IN 7
C7
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP) Output Routing Pool (ORP)
Input Bus
IN 5
IN 4
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 95
I/O 94
I/O 93
I/O 92
Output Routing Pool (ORP) Output Routing Pool (ORP)
Input Bus
CLK 0
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
Y0
Y1
Y2
IN 2
IN 3
B4 B5 B6 B7
B0 B1 B2 B3
Output Routing Pool (ORP) Output Routing Pool (ORP)
A0
A1
A2
A3
A4
A5
A6
A7
ispEN
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 0
I/O 1
I/O 2
I/O 3
GOE 0
GOE 1
CLK 1
CLK 2
Input Bus
SCLK/IN 0
MODE/IN 1
SDO/IN 6
Generic Logic
Blocks (GLBs)
The device also has 128 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2128 and 2128A device contains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128 and 2128A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
3
USE ispLSI 2128E FOR NEW DESIGNS
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V
Input Voltage Applied........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
Table 2-0006/2128
C
PARAMETER
Clock Capacitance 15
UNITSTYPICAL TEST CONDITIONS
2
C
1
I/O and Dedicated Input Capacitance
pf V = 5.0V, V = 2.0V
CC Y
8 pf V = 5.0V, V = 2.0V
CC I/O, IN
Data Retention Specifications
TA = 0°C to + 70°C
TA = -40°C to + 85°C
SYMBOL
Table 2 - 0005/2128
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
4.75
4.5
2.0
0
5.25
5.5
Vcc+1
0.8
V
V
V
V
Commercial
Industrial
Table 2-0008/2128
PARAMETER
Data Retention
MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles
20
10,000
–
–
Years
Cycles
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
4
USE ispLSI 2128E FOR NEW DESIGNS
Switching Test Conditions
Figure 2. Test Load
+ 5V
R1
R2CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213A
Input Pulse Levels
Table 2 - 0003/2000
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
≤ 3ns 10% to 90%
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from steady-state
active level.
DC Electrical Characteristics
Over Recommended Operating Conditions
TEST CONDITION R1 R2 CL
A 470Ω390Ω35pF
B∞390Ω35pF
470Ω390Ω35pF
Active High
Active Low
C
470Ω390Ω5pF
∞390Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2 - 0004A/2000
Output Load Conditions (see Figure 2)
VOL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at V = 5V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM
to estimate maximum I .
Table 2-0007/2128
1
VOH
IIH
IIL
IIL-isp
PARAMETER
IIL-PU
IOS
2, 4
ICC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
3.5V ≤ V ≤ V
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 5V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN CC
IN
IL
IN IL
CC OUT
CLOCK
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
0.4
–
10
-10
-150
-150
-200
V
V
μA
μA
μA
μA
mA
mA
CC A
OUT
165 325
CC
CC
Commercial
Industrial –mA165 –
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
5
USE ispLSI 2128E FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-100
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/2128-100
1
4
3
1
tsu2 + tco1
( )
-80
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns
t
pd2 A 2 Data Propagation Delay – – ns
f
max A 3 Clock Frequency with Internal Feedback 100 – 81.0 – MHz
f
max (Ext.) – 4 Clock Frequency with External Feedback – – MHz
f
max (Tog.) – 5 Clock Frequency, Max. Toggle – – MHz
t
su1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
t
co1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – – ns
t
h1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
t
su2 – 9 GLB Reg. Setup Time before Clock 8.0 – ns
t
co2 – 10 GLB Reg. Clock to Output Delay – – ns
t
h2 – 11 GLB Reg. Hold Time after Clock 0.0 – ns
t
r1 A 12 Ext. Reset Pin to Output Delay – – ns
t
rw1 – 13 Ext. Reset Pulse Duration 6.5 – ns
t
ptoeen B 14 Product Term OE, Enable – – ns
t
ptoedis C 15 Product Term OE, Disable – – ns
t
goeen B 16 Global OE, Enable – – ns
t
goedis C 17 Global OE, Disable – – ns
t
wh – 18 External Synchronous Clock Pulse Duration, High 5.0 – – ns
t
wl – 19 External Synchronous Clock Pulse Duration, Low 5.0 – – ns
77.0
100
6.5
5.0
–
–
6.0
–
13.5
–
15.0
15.0
9.0
9.0
13.0
57.0
83.0
9.0
0.0
11.0
0.0
10.0
6.0
6.0
18.5
6.5
8.0
17.0
18.0
18.0
12.0
12.0
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
6
USE ispLSI 2128E FOR NEW DESIGNS
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2- 0036C/2128-100
Inputs
UNITS
-100
MIN.
-80
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay – – 1.8 ns
t
din 21 Dedicated Input Delay – – 4.4 ns
t
grp 22 GRP Delay – – 2.6 ns
GLB
t
1ptxor 25 1 Product Term/XOR Path Delay – – 8.0 ns
t
20ptxor 26 20 Product Term/XOR Path Delay – – 8.8 ns
t
xoradj 27 XOR Adjacent Path Delay – – 9.8 ns
t
gbp 28 GLB Register Bypass Delay – – 1.3 ns
t
gsu 29 GLB Register Setup Time befor Clock – 1.4 – ns
t
gh 30 GLB Register Hold Time after Clock – 6.0 – ns
t
gco 31 GLB Register Clock to Output Delay – – 0.4 ns
3
t
gro 32 GLB Register Reset to Output Delay – – 1.6 ns
t
ptre 33 GLB Product Term Reset to Register Delay – – 8.6 ns
t
ptoe 34 GLB Product Term Output Enable to I/O Cell Delay – – 9.0 ns
t
ptck 35 GLB Product Term Clock Delay 5.6 10.2 ns
ORP
t
ob 38 Output Buffer Delay – – 2.0 ns
t
sl 39 Output Slew Limited Delay Adder – – 10.0 ns
0.5
2.2
GRP
1.7
t
4ptbpc 23 4 Product Term Bypass Path Delay – – 8.1 ns
t
4ptbpr 24 4 Product Term Bypass Path Delay – – 6.8 ns
6.8
7.3
8.0
0.5
5.8
5.8
1.2
4.0
0.3
1.3
6.1
8.6
4.1 7.1
t
orp 36 ORP Delay – – 2.0 ns
t
orpbp 37 ORP Bypass Delay – – 0.5 ns
1.4
0.4
Outputs
1.6
10.0
t
oen 40 I/O Cell OE to Output Enabled – – 4.6 ns
t
odis 41 I/O Cell OE to Output Disabled – – 4.6 ns
4.2
4.2
t
goe 42 Global Output Enable – – 7.4 ns
4.8
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.7 3.6 3.6 ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.7 3.6 3.6 ns
Clocks
2.7
2.7
t
gr 45 Global Reset to GLB – – 11.4 ns
Global Reset
9.2
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
7
USE ispLSI 2128E FOR NEW DESIGNS
ispLSI 2128/A Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25 - 27
#33 - 35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29 - 32
#38,
39
GOE0, 1 #42
#40, 41
0491
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
tsu Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.5 + 1.7 + 7.3) + (1.2) + (0.5 + 1.7 + 4.1)
=
=
=
=
th Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.5 + 1.7 + 7.1) + ( 4.0) + (0.5 + 1.7 + 7.3)
=
=
=
=
tco Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.5 + 1.7 + 7.1) + (0.3) + (1.4 + 1.6)
4.4 ns
3.8 ns
12.6 ns
Table 2-0042/2128
Note: Calculations are based upon timing specifications for the ispLSI 2128/A-100L.
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
8
USE ispLSI 2128E FOR NEW DESIGNS
Power Consumption
Power consumption in the ispLSI 2128 and 2128A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
0127B/2128
ICC can be estimated for the ispLSI 2128/A using the following equation:
ICC (mA) = 20 + (# of PTs * 0.48) + (# of nets * Max freq * 0.009)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
100
200
300
0 20 40 60 80 100
fmax (MHz)
ICC (mA)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25° C
ispLSI 2128/A
250
150
Figure 4. Typical Device Power Consumption vs fmax
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
9
USE ispLSI 2128E FOR NEW DESIGNS
Pin Description
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Dedicated Clock inputs. These clock inputs are connected
to one of the clock inputs of all the GLBs on the device.
Active Low (0) Reset pin which resets all of the GLB
registers in the device.
Input - Dedicated in-system programming enable input pin.
This pin is brought low to enable the programming mode.
The MODE, SDI, SDO and SCLK options become active.
Input - This pin performs two functions. When ispEN is logic
low, it functions as an input pin to load programming data
into the device. SDI is also used as one of the two control
pins for the isp state machine. When ispEN is high, it
functions as a dedicated input pin.
Input/Output Pins - These are the general purpose I/O pins
used by the logic array.
NAME
Table 2-0002/2128
PQFP/MQFP
PIN NUMBERS DESCRIPTION
25,
32,
37,
42,
48,
54,
59,
65,
70,
76,
82,
87,
93,
106,
113,
118,
123,
129,
135,
140,
146,
152,
157,
3,
8,
15,
26,
33,
38,
43,
49,
55,
60,
66,
72,
77,
83,
88,
94,
108,
114,
119,
124,
130,
136,
141,
147,
153,
158,
4,
9,
16,
28,
34,
39,
44,
50,
56,
61,
67,
73,
78,
84,
89,
95,
109,
115,
120,
126,
132,
137,
142,
148,
154,
159,
5,
11,
17
I/O 0 - I/O 4
I/O 5 - I/O 9
I/O 10 - I/O 14
I/O 15 - I/O 19
I/O 20 - I/O 24
I/O 25 - I/O 29
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
I/O 105 - I/O 109
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
29,
35,
40,
46,
52,
57,
62,
68,
74,
79,
85,
90,
96,
110,
116,
121,
127,
133,
138,
144,
149,
155,
160,
6,
13,
30,
36,
41,
47,
53,
58,
64,
69,
75,
80,
86,
92,
105,
112,
117,
122,
128,
134,
139,
145,
150,
156,
2,
7,
14,
Global Output Enable input pins.
GOE 0, GOE 1
20RESET
Y0, Y1, Y2
21ispEN
22SDI/IN 7
2
23SCLK/IN 0
2
24MODE/IN 1
2
104SDO/IN 6
2
Output/Input - This pin performs two functions. When ispEN
is logic low, it functions as the pin to read the isp data.
When ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic
low, it functions as pin to control the operation of the isp
state machine. When ispEN is high, it functions as a
dedicated input pin.
Input - This pin performs two functions. When ispEN is logic
low, it functions as a clock pin for the Serial Shift Register.
When ispEN is high, it functions as a dedicated input pin.
Ground (GND)
1,
81,
10,
107,
27,
125,
18, 19, 101
100, 99,
GND 45,
143
97, 98, 102, 103
63,
V (+5V)
12,
111,
31,
131,
51,
151
VCC 71, 91,
TQFP PIN NUMBERS
27,
35,
41,
46,
52,
59,
65,
71,
77,
83,
90,
95,
102,
116,
124,
130,
135,
141,
148,
154,
160,
167,
173,
3,
8,
16,
28,
36,
42,
47,
53,
60,
66,
72,
79,
85,
91,
96,
103,
119,
125,
131,
136,
143,
149,
155,
161,
168,
174,
4,
9,
17,
31,
37,
43,
48,
55,
61,
67,
73,
80,
86,
92,
97,
104,
120,
126,
132,
138,
145,
150,
156,
163,
169,
175,
5,
12,
18
32,
38,
44,
50,
57,
62,
68,
75,
81,
87,
93,
99,
105,
121,
127,
133,
139,
146,
151,
158,
164,
170,
176,
6,
14,
33,
39,
45,
51,
58,
63,
70,
76,
82,
88,
94,
101,
115,
123,
129,
134,
140,
147,
153,
159,
165,
171,
2,
7,
15,
22
23
24
25
26
114
1,
89,
11,
117,
29,
137,
19, 21, 111
110, 109,
49,
157
106, 107, 112, 113
69,
13,
122,
34,
144,
56,
166
78, 100,
CC
No Connect.
NC
1
20,
74,
128,
30,
84,
142,
40,
98,
152,
54,
108,
162,
64,
118
172
Dedicated input pins to the device.
IN 2 - IN 5
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
10
USE ispLSI 2128E FOR NEW DESIGNS
Pin Configuration
ispLSI 2128/A 160-Pin PQFP Pinout Diagram
ispLSI 2128/A
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
GND
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
GND
I/O 122
VCC
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
Y0
Y1
RESET
ispEN
1
SDI/IN 7
1
SCLK/IN 0
1
MODE/IN 1
I/O 0
I/O 1
GND
I/O 2
I/O 3
I/O 4
VCC
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 113
I/O 112
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
VCC
I/O 104
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
I/O 98
GND
I/O 97
I/O 96
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
VCC
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
GND
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
VCC
I/O 68
I/O 67
I/O 66
GND
I/O 65
I/O 64
SDO/IN 6
1
IN 5
IN 4
Y2
GOE 0
GOE 1
IN 3
IN 2
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
VCC
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
GND
I/O 14
I/O 15
I/O 16
I/O 17
GND
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
VCC
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
GND
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
VCC
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
1. Pins have dual function capability.
160-PQFP/2128A
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
11
USE ispLSI 2128E FOR NEW DESIGNS
ispLSI 2128/A
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
GND
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
1
NC
GND
I/O 122
VCC
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
Y0
1
NC
Y1
RESET
ispEN
2
SDI/IN 7
2
SCLK/IN 0
2
MODE/IN 1
I/O 0
I/O 1
GND
1
NC
I/O 2
I/O 3
I/O 4
VCC
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
1
NC
I/O 10
I/O 11
I/O 12
I/O 13
I/O 113
I/O 112
I/O 111
I/O 110
NC
1
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
VCC
I/O 104
I/O 103
I/O 102
NC
1
I/O 101
I/O 100
I/O 99
I/O 98
GND
I/O 97
I/O 96
I/O 95
I/O 94
NC
1
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
VCC
I/O 86
NC
1
I/O 85
I/O 84
I/O 83
I/O 82
GND
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
NC
1
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
VCC
I/O 68
I/O 67
I/O 66
NC
1
GND
I/O 65
I/O 64
SDO/IN 6
2
IN 5
IN 4
Y2
GOE 0
GOE 1
NC
1
IN 3
IN 2
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
VCC
I/O 58
NC
1
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
GND
I/O 14
I/O 15
I/O 16
I/O 17
GND
I/O 18
I/O 19
I/O 20
I/O 21
1
NC
I/O 22
VCC
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
1
NC
I/O 30
I/O 31
I/O 32
I/O 33
GND
I/O 34
I/O 35
I/O 36
I/O 37
1
NC
I/O 38
I/O 39
I/O 40
VCC
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
1
NC
I/O 46
I/O 47
I/O 48
I/O 49
176-TQFP/2128A
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Pin Configuration
ispLSI 2128/A 176-Pin TQFP Pinout Diagram
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
12
USE ispLSI 2128E FOR NEW DESIGNS
Part Number Description
ispLSI 2128/A Ordering Information
Conventional Packaging
Device Number
2128
1
2128A
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
ispLSI XXXXX XXX X X
Grade
Blank = Commercial
I = Industrial
X
Speed
100 = 100 MHz fmax
80 = 81 MHz fmax
Power
L = Low
Package
Q = PQFP
–
Device Family
M = MQFP
T = TQFP
QN = Lead-Free PQFP
TN = Lead-Free TQFP
LAICREMMOC
YLIMAF)zHM(xamF)sn(dpTREBMUNGNIREDROEGAKCAP
ISLpsi
00101PFQPniP-061
00101PFQTniP-671
1851PFQPniP-061
1851
ispLSI 2128A-100LQ160
ispLSI 2128A-100LT176
ispLSI 2128A-80LQ160
ispLSI 2128A-80LT176 PFQTniP-671
00101PFQPniP-061
00101PFQTniP-671
1851PFQPniP-061
1851
ispLSI 2128-100LQ
1
ispLSI 2128-100LT
1
ispLSI 2128-80LQ
1
ispLSI 2128-80LT
1
PFQTniP-671
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
LAIRTSUDNI
YLIMAF)zHM(xamF)sn(dpTREBMUNGNIREDROEGAKCAP
ISLpsi 1851PFQTniP-671
1851PFQTniP-671
ispLSI 2128A-80LT176I
ispLSI 2128-80LTI
1
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
Select devices have been discontinued.
See Ordering Information section for product status.
Specifications ispLSI 2128/A
13
USE ispLSI 2128E FOR NEW DESIGNS
ispLSI 2128/A Ordering Information (Cont.)
Lead-Free Packaging
Revision History
LAICREMMOC
YLIMAF)zHM(xamF)sn(dpTREBMUNGNIREDROEGAKCAP
ISLpsi
00101 Lead-Free 160-Pin PQFP
Lead-Free 176-Pin TQFP
Lead-Free 176-Pin TQFP
Lead-Free 160-Pin PQFP
00101
1851
1851
ispLSI 2128A-100LQN160
ispLSI 2128A-100LTN176
ispLSI 2128A-80LQN160
ispLSI 2128A-80LTN176
LAIRTSUDNI
YLIMAF)zHM(xamF)sn(dpTREBMUNGNIREDROEGAKCAP
ISLpsi 1851ispLSI 2128A-80LTN176I Lead-Free 160-Pin TQFP
Date Version
10
09
August 2006
—
Change Summary
Updated for lead-free package options.
Previous Lattice release.
Select devices have been discontinued.
See Ordering Information section for product status.
