FEATURES
DSAME PINOUT AS ADS7846
D2.2V TO 5.25V OPERATION
D1.5V TO 5.25V DIGITAL I/O
DINTERNAL 2.5V REFERENCE
DDIRECT BAT T ERY ME ASUREM ENT (0V TO 6V)
DON-CHIP TEMPERATURE MEASUREMENT
DTOUCH-PRESSURE MEASUREMENT
DQSPI AND SPI 3-WIRE INTERFACE
DAUTO POWER-DOWN
DAVAILABLE IN TSSOP-16, QFN-16, AND
VFBGA-48 PACKAGES
APPLICATIONS
DPERSONAL DIGITAL ASSISTANTS
DPORTABLE INSTRUMENTS
DPOINT-OF-SALE TERMINALS
DPAGERS
DTOUCH SCREEN MONITORS
DCELLULAR PHONES
US Patent No. 6246394
QSPI and SPI are registered trademarks of Motorola.
DESCRIPTION
The TSC2046 is a next-generation version to the
ADS7846 4-wire touc h sc reen controller which support s
a low-voltage I/O interface from 1.5V to 5.25V. The
TSC2046 is 100% pin-compatible with the existing
ADS7846, and w ill drop i nto the same socket. This allows
for easy upgrade of current applications to the new
version. The TSC2046 also has an on-chip 2.5V
reference that can be used for the auxiliary input, battery
monitor, and temperature measurement modes. The
reference can also be powered down when not used to
conserve power . The internal reference operates down to
2.7V supply voltage, while monitoring the battery voltage
from 0V to 6V.
The low power consumption of < 0.75mW typ at 2.7V
(reference off), high-speed (up to 125kHz sample rate),
and o n-chip d rivers m ake the TSC2046 a n i deal c hoice for
battery-operated systems such as personal digital
assistants (PDAs) with resistive touch screens, pagers,
cellular phones, and other portable equipment. The
TSC2046 is available in TSSOP-16, QFN-16, and
VFBGA-48 pac kages and is specified over the –40°C to
+85°C temper at ure range.
CDAC
Internal 2.5V Reference
SAR
TSC2046
Comparator
6− Channel
MUX Serial
Data
In/Out
Temperature
Sensor
Pen Detect
Battery
Monitor
DOUT
BUSY
CS
DCLK
DIN
VBAT
AUX
VREF
+VCC
IOVDD
X+
X−
Y+
Y−
PENIRQ
TSC2046
SBAS265G − OCTOBER 2002 − REVISED JANUARY 2008
Low-Voltage I/O
TOUCH SCREEN CONTROLLER
         
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Copyright 2002−2008, Texas Instruments Incorporated
All trademarks are the property of their respective owners.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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2
ABSOLUTE MAXIMUM RATINGS(1)
+VCC and IOVDD to GND −0.3V to +6V. . . . . . . . . . . . . . . . . . . . .
Analog Inputs to GND −0.3V to +VCC + 0.3V. . . . . . . . . . . . . . . . .
Digital Inputs to GND −0.3V to IOVDD + 0.3V. . . . . . . . . . . . . . . . .
Power Dissipation 250mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature +150°C. . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range −40 °C to +85°C. . . . . . . . . . . . . . . .
Storage Temperature Range −65 °C to +150°C. . . . . . . . . . . . . . . . .
Lead Temperature (soldering, 10s) +300°C. . . . . . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
NOMINAL
PENIRQ
PULLUP
RESISTOR
VALUES
MAXIMUM
INTEGRAL
LINEARITY
ERROR
(LSB) PACKAGE-
LEAD PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE PACKAGE
MARKING ORDERING
NUMBER TRANSPORT
MEDIA, QUANTITY
TSSOP-16
PW
−40°C to +85°C
TSC2046I
TSC2046IPW Rails, 100
TSSOP-16 PW −40°C to +85°C TSC2046I TSC2046IPWR Tape and Reel, 2500
4x4, 1mm
TSC2046IRGVT Tape and Reel, 250
TSC2046I
50kΩ
±2
4x4, 1mm
QFN-16
RGV −40°C to +85°C TSC2046 TSC2046IRGVR Tape and Reel, 2500
TSC2046I 50kΩ ±2
QFN-16
RGV
−40 C to +85 C
TSC2046
TSC2046IRGVRG4 Tape and Reel, 2500
4x4
GQC −40°C to +85°C AZ2046 TSC2046IGQCR Tape and Reel, 2500
4x4
VFBGA-48
ZQC
−40°C to +85°C
BC2046
TSC2046IZQCT Tape and Reel, 250
VFBGA-48
ZQC −40°C to +85°C BC2046 TSC2046IZQCR Tape and Reel, 2500
TSC2046I(2)
90kΩ
±2
4x4
GQC −40°C to +85°C AZ2046A TSC2046IGQCR-90 Tape and Reel, 2500
TSC2046I
(2)
90kΩ ±2
4x4
VFBGA-48 ZQC −40°C to +85°C BC2046A TSC2046IZQCR-90 Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web
site at www.ti.com.
(2) High-impedance version.
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3
ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V
At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital
inputs = GND or IOVDD, and +VCC must be ≥ IOVDD, unless otherwise noted. TSC2046
PARAMETER CONDITION MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Span Positive Input−Negative Input 0 VREF V
Absolute Input Range Positive Input −0.2 +VCC + 0.2 V
Negative Input −0.2 +0.2 V
Capacitance 25 pF
Leakage Current 0.1 µA
SYSTEM PERFORMANCE
Resolution 12 Bits
No Missing Codes 11 Bits
Integral Linearity Error ±2 LSB(1)
Offset Error ±6 LSB
Gain Error External VREF ±4 LSB
Noise Including Internal VREF 70 µVrms
Power-Supply Rejection 70 dB
SAMPLING DYNAMICS
Conversion Time 12 CLK Cycles
Acquisition Time 3CLK Cycles
Throughput Rate 125 kHz
Multiplexer Settling Time 500 ns
Aperture Delay 30 ns
Aperture Jitter 100 ps
Channel-to-Channel Isolation VIN = 2.5VPP at 50kHz 100 dB
SWITCH DRIVERS
On-Resistance
Y+, X+ 5Ω
Y−, X− 6Ω
Drive Current(2) Duration 100ms 50 mA
REFERENCE OUTPUT
Internal Reference Voltage 2.45 2.50 2.55 V
Internal Reference Drift 15 ppm/°C
Quiescent Current 500 µA
REFERENCE INPUT
Range 1.0 +VCC V
Input Impedance SER/DFR = 0, PD1 = 0 1 GΩ
Internal Reference Off
Internal Reference On 250 Ω
BATTERY MONITOR
Input Voltage Range 0.5 6.0 V
Input Impedance
Sampling Battery 10 kΩ
Battery Monitor Off 1 GΩ
Accuracy VBAT = 0.5V to 5.5V, External VREF = 2.5V −2 +2 %
VBAT = 0.5V to 5.5V, Internal Reference −3 +3 %
TEMPERATURE MEASUREMENT
Temperature Range −40 +85 °C
Resolution Dif ferential Method(3) 1.6 °C
TEMP0(4) 0.3 °C
Accuracy Dif ferential Method(3) ±2°C
TEMP0(4) ±3°C
(1) LSB means Least Significant Bit. With VREF = +2.5V, one LSB is 610µV.
(2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation.
(3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary.
(4) Temperature drift is −2.1mV/°C.
(5) TSC2046 operates down to 2.2V.
(6) IOVDD must be ≤ (+VCC).
(7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0.
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4
ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (continued)
At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital
inputs = GND or IOVDD, and +VCC must be ≥ IOVDD, unless otherwise noted. TSC2046
PARAMETER UNITSMAXTYPMINCONDITION
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Capacitance All Digital Control Input Pins 5 15 pF
VIH | IIH | ≤ +5µAIOVDD • 0.7 IOVDD + 0.3 V
VIL | IIL | ≤ +5µA −0.3 0.3 •IOVDD V
VOH IOH = −250µAIOVDD • 0.8 V
VOL IOL = 250µA 0.4 V
Data Format Straight
Binary
POWER-SUPPLY REQUIREMENTS
+VCC(5) Specified Performance 2.7 3.6 V
Operating Range 2.2 5.25 V
IOVDD(6) 1.5 +VCC V
Quiescent Current(7) Internal Reference Off 280 650 µA
Internal Reference On 780 µA
fSAMPLE = 12.5kHz 220 µA
Power-Down Mode with 3µA
CS = DCLK = DIN = IOVDD
Power Dissipation +VCC = +2.7V 1.8 mW
TEMPERATURE RANGE
Specified Performance −40 +85 °C
(1) LSB means Least Significant Bit. With VREF = +2.5V, one LSB is 610µV.
(2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation.
(3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary.
(4) Temperature drift is −2.1mV/°C.
(5) TSC2046 operates down to 2.2V.
(6) IOVDD must be ≤ (+VCC).
(7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0.
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5
PIN CONFIGURATION
Top V iew
1
2
3
4
5
6
7
8
+VCC
X+
Y+
X−
Y−
GND
VBAT
AUX
DCLK
CS
DIN
BUSY
DOUT
PENIRQ
IOVDD
VREF
16
15
14
13
12
11
10
9
TSC2046
Top View QFN
TSSOP Top View VFBGA
NC
NC
A
B
C
D
E
F
G
21 3 4 5 6 7
DCLK
+VCC
+VCC
X+
Y+
PENIRQ
IOVDD
VREF
AUX
CS DIN BUSY DOUT
X−Y−GND GND VBAT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
NCNC
NC
BUSY
DIN
CS
DCLK
AUX
VBAT
GND
Y−
1
2
3
4
12
11
10
9
TSC2046
DOUT
PENIRQ
IOVDD
VREF
16
15
14
13
+VCC
X+
Y+
X−
5
6
7
8
(1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal
pad separate from the digital ground, if possible.
(Thermal Pad)(1)
PIN DESCRIPTION
TSSOP PIN # VFBGA PIN # QFN PIN # NAME DESCRIPTION
1B1 and C1 5 +VCC Power Supply
2 D1 6 X+ X+ Position Input
3 E1 7 Y+ Y+ Position Input
4 G2 8 X− X− Position Input
5 G3 9 Y− Y− Position Input
6G4 and G5 10 GND Ground
7 G6 11 VBAT Battery Monitor Input
8 E7 12 AUX Auxiliary Input to ADC
9 D7 13 VREF Voltage Reference Input/Output
10 C7 14 IOVDD Digital I/O Power Supply
11 B7 15 PENIRQ Pen Interrupt
12 A6 16 DOUT Serial Data Output. Data are shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
13 A5 1 BUSY Busy Output. This output is high impedance when CS is high.
14 A4 2 DIN Serial Data Input. If CS is low, data are latched on the rising edge of DCLK.
15 A3 3 CS Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
16 A2 4 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial
data I/O.
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6
TYPICAL CHARACTERISTICS
At T A = +25°C, +V CC = +2 . 7 V, IOVDD = +1.8 V, VREF = External +2.5V, 12-bit m ode, PD0 = 0, fSAMPLE = 1 25 kHz, and f CLK = 1 6 • f SAMPLE = 2M Hz,
unless otherwise noted.
+VCC SUPPLY CURRENT vs TEMPERATURE
−40 −200 20406080100
+VCC Supply Current (µA)
400
350
300
250
200
150
100
Temperature (°C)
IOVDD SUPPLY CURRENT vs TEMPERATURE
−40 −20 0 20 40 60 80 100
IOVDD Supply Current (µA)
30
25
20
15
10
5
Temperature (°C)
POWER−DOWN SUPPLY CURRENT vs TEMPERATURE
−40 −20 0 20 40 60 80 100
Supply Current (nA)
140
120
100
80
60
40
Temperature (°C)
+VCC SUPPLY CURRENT vs +VCC
2.02.53.03.54.04.55.0
+VCC (V)
+VCC Supply Current (µA)
450
400
350
300
250
200
150
100
fSAMPLE = 125kHz
fSAMPLE = 12.5kHz
IOVDD SUPPLY CURRENT vs IOVDD
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOVDD (V)
IOVDD Supply Current (µA)
60
50
40
30
20
10
0
+VCC ≥IOVDD
fSAMPLE = 125kHz
fSAMPLE = 12.5kHz
MAXIMUM SAMPLE RATE vs +VCC
2.0 5.02.5 3.0 3.5 4.0 4.5
+VCC (V)
Sample Rate (Hz)
1M
100k
10k
1k
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7
TYPICAL CHARACTERISTICS (continued)
At T A = +25°C, +V CC = +2 . 7 V, IOVDD = +1.8 V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 1 25 kHz, and f CLK = 1 6 • f SAMPLE = 2M Hz,
unless otherwise noted.
CHANGE IN GAIN vs TEMPERATURE
−40 −200 20406080100
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
Temperature (°C)
Delta from +25°C (LSB)
CHANGE IN OFFSET vs TEMPERATURE
−40 −20 0 20 40 60 80 100
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
Temperature (°C)
Delta from +25°C (LSB)
REFERENCE CURRENT vs SAMPLE RATE
0 255075100125
Sample Rate (kHz)
Reference Current (µA)
14
12
10
8
6
4
2
0
Temperature (°C)
REFERENCE CURRENT vs TEMPERATURE
−40 −200 20406080100
Reference Current (µA)
18
16
14
12
10
8
6
SWITCH ON− RESISTANCE vs +VCC
(X+, Y+: +VCC to Pin; X−,Y
−: Pin to GND)
2.0 2.5 3.0 3.5 4.0 4.5 5.0
+VCC (V)
8
7
6
5
4
3
Y−
X−
X+, Y+
RON (Ω)
SWITCH ON−RESISTANCE vs TEMPERATURE
(X+, Y+: +VCC to Pin; X−,Y
−: Pin to GND)
−40 −20 0 20 40 60 80 100
8
7
6
5
4
3
2
1
Y−
X−
X+, Y+
Temperature (°C)
RON (Ω)
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8
TYPICAL CHARACTERISTICS (continued)
At T A = +25°C, +V CC = +2 . 7 V, IOVDD = +1.8 V, VREF = External +2.5V, 12-bit m ode, PD0 = 0, fSAMPLE = 1 25 kHz, and f CLK = 1 6 • f SAMPLE = 2M Hz,
unless otherwise noted.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Max Absolute Delta Error from
RIN =0(LSB)
20 40 60 80 100 120 140 160 180 200
Sampling Rate (kHz)
MAXIMUM SAMPLING RATE vs RIN
INL: RIN = 500Ω
INL: RIN =2k
Ω
DNL: RIN = 500Ω
DNL: RIN =2k
Ω
INTERNAL VREF vs TEMPERATURE
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Internal VREF (V)
2.5080
2.5075
2.5070
2.5065
2.5060
3.5055
2.5050
2.5045
2.5040
2.5035
2.5030
Temperature (°C)
INTERNAL VREF vs +VCC
2.53.03.54.04.55.0
+VCC (V)
Internal VREF (V)
2.510
2.505
2.500
2.495
2.490
2.485
2.480
INTERNAL VREF vs TURN−ON TIME
0 200 400 600 800 1000 1200 1400
Internal VREF (%)
100
80
60
40
20
0
Turn-On Time (µs)
1µF Cap
(124µs)
12-Bit Settling
No Cap
(42µs)
12-Bit Settling
TEMP DIODE VOLTAGE vs TEMPERATURE
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
TEMP Diode Voltage (mV)
850
800
750
700
650
600
550
500
450
90.1mV
135.1mV
TEMP1
TEMP0
Temperature (°C)
TEMP0 DIODE VOLTAGE vs +VCC
2.7 3.0 3.3
+VCC (V)
TEMP0 Diode Voltage (mV)
604
602
600
598
596
594
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9
TYPICAL CHARACTERISTICS (continued)
At T A = +25°C, +V CC = +2 . 7 V, IOVDD = +1.8 V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 1 25 kHz, and f CLK = 1 6 • f SAMPLE = 2M Hz,
unless otherwise noted.
TEMP1 DIODE VOLTAGE vs +VCC
2.7 3.0 3.3
+VCC (V)
TEMP1 Diode Voltage (mV)
720
718
716
714
712
710
THEORY OF OPERATION
The TSC2046 is a classic successive approximation
register (SAR) analog-to-digital converter (ADC). The
architecture is based on capacitive redistribution, which
inherently includes a sample-and-hold function. The
converter is fabricated on a 0.6µm CMOS process.
The basic operation of the TSC2046 is shown in Figure 1.
The device features an internal 2.5V reference and uses
an external clock. Operation is maintained from a single
supply of 2.7V to 5.25V. The internal reference can be
overdriven with an external, low-impedance source
between 1V and +VCC. The value of the reference voltage
directly sets the input range of the converter.
The analog input (X-, Y-, and Z-Position coordinates,
auxiliary input, battery voltage, and chip temperature)
to the converter is provided via a multiplexer. A unique
configuration of low on-resistance touch panel driver
switches allows an unselected ADC input channel to
provide power and the accompanying pin to provide
ground for an external device, such as a touch screen.
By maintaining a differential input to the converter and
a differential reference architecture, it is possible to
negate the error from each touch panel driver switch
on-resistance (if this is a source of error for the
particular measurement).
+VCC
+VCC
X+
Y+
X−
Y−
VBAT
AUX
B1
C1
D1
E1
G2
G3
G6
E7
G4 G5
A2
A3
A4
A5
A6
B7
C7
D7
DCLK
CS
DIN
BUSY
DOUT
PENIRQ
IOVDD
VREF
Serial/Conversion Clock
Chip Select
Serial Data In
Converter Status
Serial Data Out
+
1∝
F
to
10∝
F
(Optional)
+2.7V to +5V TSC2046
Auxiliary Input
To Battery
Voltage
Regulator
Touch
Screen
0.1∝
F
Pen Interrupt
GND GND
NOTE: VFBGA package and pin names shown.
Figure 1. Basic Operation of the TSC2046
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10
ANALOG INPUT
Figure 2 show s a bl ock diagram of the input multiplex er on
the TSC2046, the differential input of the ADC, and the
differential reference of the converter . Table 1 and Table 2
show the relationship between the A2, A1, A0, and
SER/DFR control b its a nd t he c onfiguration o f t he TSC2046.
The c ontrol b its a re provided serially v ia t he D IN p in—see t he
Digital Interface section of this data sheet for more detai ls.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (shown in
Figure 2) is captured on the internal capacitor array. The
input current into the analog inputs depends on the
conversion r ate of the device. During the sample period, t he
source m ust c harge t he i nternal sampling c apacitor (typically
25pF). After the capacitor is fully charged, there is no further
input current. The rate of charge transfer from the analog
source to the converter is a function of conversion rate.
ADC
Logic
Level
Shifter
−REF
+REF
+IN
−IN
VBAT
AUX
Battery
On
GND
2.5V
Reference
Ref On/Off
X+
X−
+VCC
TEMP1
PENIRQ
50kΩ
or
90kΩ
Y+
Y−
VREF
IOVDD
TEMP0
7.5kΩ
2.5kΩ
A2− A0
(Shown 001B)SER/DFR
(Shown Low)
Figure 2. Simplified Diagram of Analog Input
A2 A1 A0 VBAT AUXIN TEMP Y− X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS Y-DRIVERS
0 0 0 +IN ( TEMP0) Off Off
0 0 1 +IN Measure Off On
0 1 0 +IN Off Off
0 1 1 +IN Measure X−, On Y+, On
1 0 0 +IN Measure X−, On Y+, On
1 0 1 +IN Measure On Off
1 1 0 +IN Off Off
1 1 1 +IN (TEMP1) Off Off
Table 1. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high)
A2 A1 A0 +REF −REF Y− X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION DRIVERS
0 0 1 Y+ Y− +IN Measure Y+, Y −
0 1 1 Y+ X− +IN Measure Y+, X−
1 0 0 Y+ X− +IN Measure Y+, X−
1 0 1 X+ X− +IN Measure X+, X−
Table 2. Input Configuration (DIN), Differential Reference Mode (SER/DFR low)
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INTERNAL REFERENCE
The TSC2046 has an internal 2.5V voltage reference that
can b e t urned on or o ff with the control bit, PD1 (see Table 5
and F igure 3) . Typically , t he i nternal r eference v oltage i s o nly
used in the single-ended mode for battery monitoring,
temperature measurement, and for using t he auxiliary input.
Optimal touch screen performance is achieved when using
the differential mode. The internal reference voltage of the
TSC2046 must be commanded to be off to maintain
compatibility with the AD S 7843. Therefore, after pow er-up,
a write of PD1 = 0 is required to insure the reference is off
(see the Typical Characteristics for power-up time of the
reference from power-down).
Buffer
Band
Gap
Reference
Power−Down
To
CDAC Optional
VREF
Figure 3. Simplified Diagram of the Internal
Reference
REFERENCE INPUT
The voltage difference between +REF and –REF (see
Figure 2) sets the analog input range. The TSC2046
operates with a reference in the range of 1V to +VCC. There
are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is
reduced, the analog voltage weight of each digital output
code is also reduced. This is often referred to as the LSB
(least significant bit) size and is equal to the reference
voltage divided by 4096 in 12-bit mode. Any offset or gain
error inherent in the ADC appears to increase, in terms of
LSB size, as the reference voltage is reduced. For
example, if the offset of a given converter is 2LSBs with a
2.5V reference, it is typically 5LSBs with a 1V reference.
In each case, the actual offset of the device is the same,
1.22mV. With a lower reference voltage, more care must
be taken to provide a clean layout including adequate
bypassing, a clean (low-noise, low-ripple) power supply, a
low-noise reference (if an external reference is used), and
a low-noise input signal.
The voltage into the VREF input directly drives the
capacitor digital-to-analog converter (CDAC) portion of the
TSC2046. Therefore, the input current is very low (typically
< 13µA).
There is also a critical item regarding the reference when
making measurements while the switch drivers are ON. For
this discussion, it is useful to consider the basic operation o f
the TSC2046 (see Figure 1). This particular application
shows the device being used to digitize a resistive touch
screen. A measurement of the current Y-Position of the
pointing device is made by connecting the X+ input to the
ADC, turning on the Y+ and Y– drivers, and digitizing the
voltage on X+ (Figure 4 shows a block diagram). For this
measurement, the resistance in the X+ lead does not affect
the conversion (it does affect the settling time, but the
resistance i s u sually small e nough t hat t his is not a c oncern).
Howev er, since the resistanc e between Y+ and Y– is fairly
low, the on-resistance of the Y drivers does make a small
difference. Under the situation outlined so far, it is not
possible t o achieve a 0V input o r a f ull-scale input r egardless
of where the pointing device is on the touch screen b ecause
some voltage i s l ost a cross the i nternal s witches. In addition,
the internal switch resistance is unlikely to track the
resistance of the touch screen, providing an additional
source of error.
Converter
+IN +REF
Y+
+VCC VREF
X+
Y−
GND
−REF
−IN
Figure 4. Simplified Diagram of Single-Ended
Reference (SER/DFR high, Y switches enabled,
X+ is analog input)
This situation can be remedied as shown in Figure 5. By
setting the SER/DFR bit low, the +REF and –REF inputs
are connected directly to Y+ and Y–, respectively, which
makes the analog-to-digital conversion ratiometric. The
result of the conversion is always a percentage of the
external resistance, regardless of how it changes in
relation to the on-resistance of the internal switches. Note
that there is an important consideration regarding power
dissipation when using the ratiometric mode of operation
(see the Power Dissipation section for more details).
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Converter
+IN +REF
Y+
+VCC
X+
Y−
GND
−REF
−IN
Figure 5. Simplified Diagram of Differential
Reference (SER/DFR low, Y switches enabled,
X+ is analog input)
As a final note about the differential reference mode, it
must be used with +VCC as the source of the +REF voltage
and cannot be used with VREF. It is possible to use a
high-precision reference on VREF and single-ended
reference mode for measurements which do not need to
be ratiometric. In some cases, it is possible to power the
converter directly from a precision reference. Most
references can provide enough power for the TSC2046,
but might not be able to supply enough current for the
external load (such as a resistive touch screen).
TOUCH SCREEN SETTLING
In some applications, external capacitors may be required
across the touch screen for filtering noise picked up by the
touch screen (e.g., noise generated by the LCD panel or
backlight circuitry). These capacitors provide a low-pass
filter to reduce the noise, but cause a settling time
requirement when the panel is touched that typically
shows up as a gain error. There are several methods for
minimizing or eliminating this issue. The problem is that
the input and/or reference has not settled to the final
steady-state value prior to the ADC sampling the input(s)
and providing the digital output. Additionally, the reference
voltage may still be changing during the measurement
cycle. Option 1 is to stop or slow down the TSC2046 DCLK
for the required touch screen settling time. This allows the
input and reference to have stable values for the Acquire
period (3 clock cycles of the TSC2046; see Figure 9). This
works for both the single-ended and the dif ferential modes.
Option 2 is to operate the TSC2046 in the differential mode
only for the touch screen measurements and command
the TSC2046 to remain on (touch screen drivers ON) and
not go into power-down (PD0 = 1). Several conversions
are made depending on the settling time required and the
TSC2046 data rate. Once the required number of
conversions have been made, the processor commands
the TSC2046 to go into its power-down state on the last
measurement. This process is required for X-Position,
Y-Position, and Z-Position measurements. Option 3 is to
operate in the 15 Clock-per-Conversion mode, which
overlaps the analog-to-digital conversions and maintains
the touch screen drivers on until commanded to stop by the
processor (see Figure 13).
TEMPERATURE MEASUREMENT
In some applications, such as battery recharging, a
measurement of ambient temperature is required. The
temperature measurement technique used in the
TSC2046 relies on the characteristics of a semiconductor
junction operating at a fixed current level. The forward
diode voltage (VBE) has a well-defined characteristic
versus temperature. The ambient temperature can be
predicted in applications by knowing the +25°C value of
the VBE voltage and then monitoring the delta of that
voltage as the temperature changes. The TSC2046 offers
two modes of operation. The first mode requires
calibration at a known temperature, but only requires a
single reading to predict the ambient temperature. A diode
is used (turned on) during this measurement cycle. The
voltage across the diode is connected through t h e M U X fo r
digitizing the forward bias voltage by the ADC with an
address of A2 = 0, A1 = 0, and A0 = 0 (see Table 1 and
Figure 6 for details). This voltage is typically 600mV at
+25°C with a 20µA current through the diode. The absolute
value of this diode voltage can vary a few millivolts.
However, the TC of this voltage is very consistent at
–2.1mV/°C. During the final test of the end product, the
diode voltage would be stored at a known room
temperature, in memory, for calibration purposes by the
user. The result is an equivalent temperature
measurement resolution of 0.3°C/LSB (in 12-bit mode).
ADC
MUX
TEMP0 TEMP1
+VCC
Figure 6. Functional Block Diagram of
Temperature Measurement
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The second mode does not require a test temperature
calibration, b ut u ses a t wo-measurement m ethod t o e liminate
the need for absolute temperature calibration and for
achieving 2°C accuracy. This mode requires a second
conversion with an addres s of A2 = 1, A1 = 1, and A0 = 1,
with a 91 times larger current. The voltage difference
between the first and second conversion using 91 times t he
bias current is represented by Equation (1) :
DV+kT
q@In(N)
where:
N is the current ratio = 91.
k = Boltzmann’s constant = 1.3807 × 10−23 J/K
(joules/kelvins).
q = the electron charge = 1.6022 × 10–19 C (coulombs).
T = the temperature in kelvins (K).
This method can provide improved absolute temperature
measurement, but at a lower resolution of 1.6°C/LSB. The
resulting equation that solves for T is:
T+q@DV
k@In(N)
where:
∆V = VBE(TEMP1) − VBE(TEMP0) (in mV)
∴ T = 2.573 ⋅ ∆V (in K)
or T = 2.573 ⋅ ∆V – 273 (in °C)
NOTE: The bias current for each diode temperature
measurement is only on for 3 clock cycles (during the
acquisition mode) and, therefore, does not add any
noticeable increase in power, especially if the temperature
measurement only occurs occasionally.
BATTERY MEASUREMENT
An a dded f eatur e o f t he T SC2046 is t he a bility t o m onitor t he
battery voltage on the other side of the voltage regulator
(DC/DC converter), as shown in Figure 7. The battery
voltage can v ar y f ro m 0 V t o 6 V, while m ainta ining t he v o ltage
to the TSC2046 at 2.7V, 3.3V, etc. The input voltage (VBAT)
is divided down by 4 so that a 5.5V battery voltage is
represented as 1.375V to the ADC. This simplifies the
multiplexer and control logic. In order to minimize the power
consumption, the divider is only on during the sampling
period when A2 = 0, A1 = 1, and A0 = 0 (see Table 1 for the
relationship between the control bits and c onfiguration of t he
TSC2046).
+VCC
VBAT
7.5kΩ
2.5kΩ
DC/DC
Converter
Battery
0.5V
to
5.5V
0.125V to 1.375V
2.7V
+
ADC
Figure 7. Battery Measurement Functional Block
Diagram
(1)
(2)
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PRESSURE MEASUREMENT
Measuring touch pressure can also be done with the
TSC2046. To determine pen or finger touch, the pressure
of the touch needs to be determined. Generally, it is not
necessary to have very high performance for this test;
therefore, the 8-bit resolution mode is recommended
(however, calculations will be shown here in the 12-bit
resolution mode). There are several different ways of
performing this measurement. The TSC2046 supports two
methods. The first method requires knowing the X-plate
resistance, measurement of the X-Position, and two
additional cross panel measurements (Z1 and Z2) of the
touch screen, as shown in Figure 8. Using Equation (3)
calculates the touch resistance:
RTOUCH +RX−Plate @X−Position
4096 ǒZ2
Z1*1Ǔ
The second method requires knowing both the X-plate
and Y-plate resistance, measurement of X-Position and
Y-Position, and Z1. Using Equation (4) also calculates
the touch resistance:
RTOUCH +RX−Plate @X−Position
4096 ǒ4096
Z1*1Ǔ
*RY−Plateǒ1*Y−Position
4096 Ǔ
DIGITAL INTERFACE
See Figure 9 for the typical operation of the TSC2046
digital interface. This diagram assumes that the source of
the digital signals is a microcontroller or digital signal
processor with a basic serial interface. Each
communication between the processor and the converter ,
such as SPI, SSI, or Microwiret synchronous serial
interface, consists of eight clock cycles. One complete
conversion can be accomplished with three serial
communications for a total of 24 clock cycles on the DCLK
input.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer and reference inputs appropriately, the
converter enters the acquisition (sample) mode and, if
needed, the touch panel drivers are turned on. After three
more clock cycles, the control byte is complete and the
converter enters the conversion mode. At this point, the
input sample-and-hold goes into the hold mode and the
touch panel drivers turn off (in single-ended mode). The
next 12 clock cycles accomplish the actual analog-
to-digital conversion. If the conversion is ratiometric
(SER/DFR = 0), the drivers are on during the conversion
and a 13th clock cycle is needed for the last bit of the
conversion result. Three more clock cycles are needed to
complete the last byte (DOUT will be low), which are
ignored by the converter.
Microwire is a registered trademark of National Semiconductor.
X−Position
Measure
X−Position
Touch
X+ Y+
X−Y−
Measure
Z1−Po s i ti o n
Z1−Position
Touch
X+ Y+
Y−
X−Measure
Z2−P o s i t i o n
Z2−Po s i ti o n
Touch
X+ Y+
Y−
X−
Figure 8. Pressure Measurement Block Diagrams
(3)
(4)
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15
Control Byte
The control byte (on DIN), as shown in Table 3 , provides the
start conversion, addressing, ADC resolution, configuration,
and power-down of the TSC2046. Figure 9, Table 3 and
Table 4 give detailed information regarding the order and
description of these control bits within the control byte.
Initiate START—The first bit, the S bit, must always be
high and initiates the start of the control byte. The
TSC2046 ignores inputs on the DIN pin until the start bit is
detected.
Addressing—The next three bits (A2, A1, and A0) select
the active input channel(s) of the input multiplexer (see
Table 1, Table 2, and Figure 2), touch screen drivers, and
the reference inputs.
MODE—The mode bit sets the resolution of the ADC. With
this bit low, the next conversion has 12 bits of resolution,
whereas with this bit high, the next conversion has eight
bits of resolution.
SER/DFR—The SER/DFR bit controls the reference
mode, either single-ended (high) or differential (low). The
differential mode is also referred to as the ratiometric
conversion mode and is preferred for X-Position,
Y-Position, and Pressure-Touch measurements for
optimum performance. The reference is derived from the
voltage at the switch drivers, which is almost the same as
the voltage to the touch screen. In this case, a reference
voltage is not needed as the reference voltage to the ADC
is the voltage across the touch screen. In the single-ended
mode, the converter reference voltage is always the
difference between the VREF and GND pins (see Table 1
and Table 2, and Figure 2 through Figure 5, for further
information).
BIT 7
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(LSB)
S A2 A1 A0 MODE SER/DFR PD1 PD0
Table 3. Order of the Control Bits in the Control
Byte
BIT NAME DESCRIPTION
7 S Start bit. Control byte starts with first high bit on DIN.
A new control byte can start every 15th clock cycle
in 12-bit conversion mode or every 11th clock cycle
in 8-bit conversion mode (see Figure 13).
6-4 A2-A0 Channel Select bits. Along with the SER/DFR bit,
these bits control the setting of the multiplexer input,
touch driver switches, and reference inputs (see
Table 1 and Figure 13).
3 MODE 12-Bit/8-Bit Conversion Select bit. This bit controls
the number of bits for the next conversion: 12-bits
(low) or 8-bits (high).
2 SER/DFR Single-Ended/Differential Reference Select bit. Along
with bits A2-A0, this bit controls the setting of the
multiplexer input, touch driver switches, and
reference inputs (see Table 1 and Table 2).
1-0 PD1-PD0 Power-Down Mode Select bits. Refer to Table 5 for
details.
Table 4. Descriptions of the Control Bits within
the Control Byte
p
tACQ
AcquireIdle Conversion Idle
1DCLK
CS
81
11
DOUT
BUSY
Drivers 1 and 2(1)
(SER/DFR High)
Drivers 1 and 2(1, 2)
(SER/DFR Low)
(MSB)
(START)
(LSB)
A2S
On
On
Off Off
Off Off
DIN A1 A0 MODE SER/
DFR PD1 PD0
10987654 3210 ZeroFilled...
81 8
(1) For Y−Position, Driver 1 is on X+ is selected, and Driver 2 is off. For X−Position, Driver 1 is off, Y+ is selected, and Driver 2 is on. Y−will turn on
when power−down mode is entered and PD0 = 0.
(2) Drivers will remain on if PD0 = 1 (no power down) until selected input channel, reference mode, or ower−down mode is changed, or CS is high.
NOTES:
Figure 9. Conversion Timing, 24 Clocks-per-Conversion, 8-Bit Bus Interface.
No DCLK delay required with dedicated serial port
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If X-Position, Y-Position, and Pressure-Touch are
measured in the single-ended mode, an external reference
voltage is needed. The TSC2046 must also be powered
from the external reference. Caution should be observed
when using the single-ended mode such that the input
voltage to the ADC does not exceed the internal reference
voltage, especially if the supply voltage is greater than
2.7V.
NOTE: The differential mode can only be used for
X-Position, Y-Position, and Pressure-Touch
measurements. All other measurements require the
single-ended mode.
PD0 and PD1—Table 5 describes the power-down and
the internal reference voltage configurations. The internal
reference voltage can b e turned on or of f independently of
the ADC. This can allow extra time for the internal
reference voltage to settle to the final value prior to making
a conversion. Make sure to also allow this extra wake-up
time if the internal reference is powered down. The ADC
requires no wake-up time and can be instantaneously
used. Also note that the status of the internal reference
power-down is latched into the part (internally) with BUSY
going high. In order to turn the reference off, an additional
write to the TSC2046 is required after the channel has
been converted.
PD1 PD0 PENIRQ DESCRIPTION
0 0 Enabled Power-Down Between Conversions. When
each conversion is finished, the converter
enters a low-power mode. At the start of the
next conversion, the device instantly powers up
to full power. There is no need for additional
delays to ensure full operation, and the very first
conversion is valid. The Y− switch is on when in
power-down.
0 1 Disabled Reference is off and ADC is on.
1 0 Enabled Reference is on and ADC is off.
1 1 Disabled Device is always powered. Reference is on and
ADC is on.
Table 5. Power-Down and Internal Reference
Selection
PENIRQ OUTPUT
The pen-interrupt output function is shown in Figure 10.
While in power-down mode with PD0 = 0, the Y-driver is on
and connects the Y-plane of the touch screen to GND. The
PENIRQ output is connected to the X+ input through two
transmission gates. When the screen is touched, the X+
input is pulled to ground through the touch screen.
In most of the TSC2046 models, the internal pullup resistor
value is nominally 50kΩ, but this may vary between 36kΩ
and 67kΩ given pr ocess and t emperature v ariations. In o r der
to assure a logic low of 0.35 S (+VCC) is presented to the
PENIRQ circuitry, the total resi stance betw een the X+ and
Y− terminals must be less than 21kΩ.
PENIRQ
+VCC
50kΩ
or
90kΩ
On
Y+ or X+ drivers on,
or TEMP0, TEMP1
measurements activated.
Y+
X+
Y−
TEMP0 TEMP1
TEMP
DIODE
High except
when TEMP0,
TEMP1 activated.
+VCC Level
Shifter
IOVDD
Figure 10. PENIRQ Functional Block Diagram
The −90 version of the TSC2046 uses a nominal 90kΩ
pullup resistor, which allows the total resistance between
the X+ and Y− terminals to be as high as 30kΩ. Note that
the higher pullup resistance will cause a slower response
time of the PENIRQ to a screen touch, so user software
should take this into account.
The P ENI RQ o utput g oes l ow d ue t o t he c urrent p ath through
the touch s creen to g round, which initiates an interrupt to the
processor. During the measurement cycle for X-, Y-, and
Z-Posi tion, the X+ input is disconnec ted from the PEN IRQ
internal pull-up resistor . T his is d one t o e liminate a ny leakage
current from the internal pull-up resistor through the touch
screen, thus causing no errors.
Furthermore, t he PENIRQ output is disabled and low during
the measurement cycle for X-, Y-, and Z-Position. The
PENIRQ output is disabled and high during the
measurement cycle for battery monitor, auxiliary input, and
chip temperature. If the last control byte written to the
TSC2046 c ontains PD0 = 1 , t he pen-interrupt output function
is disabled and is not able to detect when the screen is
touched. In order to re-enable the pen-interrupt output
function under these circumstances, a control byte needs to
be written to the TS C 2046 with PD0 = 0. If the last control
byte written to the TSC2046 contains PD0 = 0, the
pen-interrupt output function is enabled at the end of the
conversion. The end of the conversion occurs on the fallin g
edge o f DCLK after bit 1 o f the c onverted data i s clocked out
of the TSC2046.
It is recommended that the processor mask the interrupt
PENIRQ is ass ociated with whenev er the processor sends
a control byte t o the TSC2046. This prevents false t r iggering
of interrupts when the PENIRQ output is disabled in the
cases discussed in this section.
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16 Clocks-per-Conversion
The control bits for conversion n + 1 can be overlapped
with conversion n to allow for a conversion every 16 clock
cycles, as shown in Figure 11. This figure also shows
possible serial communication occurring with other serial
peripherals between each byte transfer from the processor
to the converter. This is possible, provided that each
conversion completes within 1.6ms of starting. Otherwise,
the signal that is captured on the input sample-and-hold
may droop enough to affect the conversion result. Note
that the TSC2046 is fully powered while other serial
communications are taking place during a conversion.
Digital Timing
Figure 9, Figure 12, and Table 6 provide detailed timing for
the digital interface of the TSC2046.
15 Clocks-per-Conversion
Figure 13 provides the fastest way to clock the TSC2046.
This method does not work with the serial interface of most
microcontrollers and digital signal processors, as they are
generally not capable of providing 15 clock cycles per
serial transfer. However, this method can be used with
field-programmable gate arrays (FPGAs) or application-
specific integrated circuits (ASICs). Note that this
effectively increases the maximum conversion rate of the
converter beyond the values given in the specification
tables, which assume 16 clock cycles per conversion.
1
DCLK
CS
81
11
DOUT
BUSY
SDIN
Control Bits
S
Control Bits
1098765 43210 11 10 9
81 18
Figure 11. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface.
No DCLK delay required with dedicated serial port
PD0
tBDV
tDH
tCH tCL
tDS
tCSS
tDV
tBD tBD
tTR
tBTR
tDO tCSH
DCLK
CS
11DOUT
BUSY
DIN
10
Figure 12. Detailed Timing Diagram
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+VCC S 2.7V, +VCC S IOVDD S 1.5V, CLOAD = 50pF
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tACQ Acquisition Time 1.5 µs
tDS DIN Valid Prior to DCLK Rising 100 ns
tDH DIN Hold After DCLK High 50 ns
tDO DCLK Falling to DOUT Valid 200 ns
tDV CS Falling to DOUT Enabled 200 ns
tTR CS Rising to DOUT Disabled 200 ns
tCSS CS Falling to First DCLK Rising 100 ns
tCSH CS Rising to DCLK Ignored 10 ns
tCH DCLK High 200 ns
tCL DCLK Low 200 ns
tBD DCLK Falling to BUSY Rising/Falling 200 ns
tBDV CS Falling to BUSY Enabled 200 ns
tBTR CS Rising to BUSY Disabled 200 ns
Table 6. Timing Specifications, TA = −405C to +855C
1
DCLK
CS
11DOUT
BUSY
A2SDIN A1 A0 MODE SER/
DFR PD1PD0
109876543210 11 10 9 8 7
A1 A0
15 1 15
Power−Down
1
A2SA1A0
MODE PD1 PD0 A2S
SER/
DFR
Figure 13. Maximum Conversion Rate, 15 Clocks-per-Conversion
Data Format
The TSC2046 output data is in Straight Binary format, as
shown in Figure 14. This figure shows the ideal output
code for the given input voltage and does not include the
effects of offset, gain, or noise.
8-Bit Conversion
The TSC2046 provides an 8-bit conversion mode that can
be used when faster throughput is needed and the digital
result is not as critical. By switching to the 8-bit mode, a
conversion is complete four clock cycles earlier. Not only
does this shorten each conversion by four bits (25% faster
throughput), but each conversion can actually occur at a
faster clock rate. This is because the internal settling time
of the TSC2046 is not as critical—settling to better than 8
bits is all that is needed. The clock rate can be as much as
50% faster. The faster clock rate and fewer clock cycles
combine to provide a 2x increase in conversion rate.
Output Code
0V
FS = Full−Scale Voltage = VREF(1)
1LSB = VREF(1)/4096
FS −1LSB
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
NOTES:
Input Voltage(2) (V)
(1) Reference voltage at converter: +REF −(−REF); see Figure 2.
(2) Input voltage at converter, after multiplexer: +IN −(−IN); see
Figure 2.
Figure 14. Ideal Input Voltages and Output Codes
"#$%&
SBAS265G − OCTOBER 2002 − REVISED JANUARY 2008
www.ti.com
19
POWER DISSIPATION
There are two major power modes for the TSC2046:
full-power (PD0 = 1) and auto power-down (PD0 = 0).
When operating at full speed and 16
clocks-per-conversion (see Figure 11), the TSC2046
spends most of the time acquiring or converting. There is
little time for auto power-down, assuming that this mode is
active. Therefore, the difference between full-power mode
and auto power-down is negligible. If the conversion rate
is decreased by slowing the frequency of the DCLK input,
the two modes remain approximately equal. However, if
the DCLK frequency is kept at the maximum rate during a
conversion but conversions are done less often, the
difference between the two modes is dramatic.
Figure 15 shows the difference between reducing the
DCLK frequency (scaling DCLK to match the conversion
rate) or maintaining DCLK at the highest frequency and
reducing the number of conversions per second. In the
latter case, the converter spends an increasing
percentage of time in power-down mode (assuming the
auto power-down mode is active).
1k 1M10k 100k
fSAMPLE (Hz)
Supply Current (µA)
1000
100
10
1
fCLK =2MHz Supply Current from
+VCC and IOVDD
TA=25¡C
+VCC =2.7V
IOVDD = 1.8V
fCLK = 16 ⋅ fSAMPLE
Figure 15. Supply Current versus Directly Scaling
the Frequency of DCLK with Sample Rate or
Maintaining DCLK at the Maximum Possible
Frequency
Another important consideration for power dissipation is
the reference mode of the converter. In the single-ended
reference mode, the touch panel drivers are ON only when
the analog input voltage is being acquired (see Figure 9
and Table 1). The external device (e.g., a resistive touch
screen), therefore, is only powered during the acquisition
period. In the differential reference mode, the external
device must be powered throughout the acquisition and
conversion periods (see Figure 9). If the conversion rate is
high, this could substantially increase power dissipation.
CS also puts the TSC2046 into power-down mode. When
CS goes high, the TSC2046 immediately goes into
power-down mode and does not complete the current
conversion. The internal reference, however, does not turn
off with CS going high. To turn the reference off, an
additional write is required before CS goes high (PD1 = 0).
When the TSC2046 first powers up, the device draws
about 2 0 µA of current until a control byte is written to it with
PD0 = 0 to put it into power-down mode. This can be
avoided if the TSC2046 is powered up with CS = 0 and
DCLK = IOVDD.
"#$%&
SBAS265G − OCTOBER 2002 − REVISED JANUARY 2008
www.ti.com
20
LAYOUT
The following layout suggestions provide the most
optimum performance from the TSC2046. Many portable
applications, however, have conflicting requirements
concerning power, cost, size, and weight. In general, most
portable devices have fairly clean power and grounds
because most of the internal components are very low
power. This situation means less bypassing for the
converter power and less concern regarding grounding.
Still, each situation is unique and the following
suggestions should be reviewed carefully.
For optimum performance, care should be taken with the
physical layout of the TSC2046 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on
the power supply, reference, ground connections, and
digital inputs that occur just prior to latching the output of
the analog comparator. Therefore, during any single
conversion for an n-bit SAR converter, there are n
‘windows’ in which large external transient voltages can
easily affect the conversion result. Such glitches can
originate from switching power supplies, nearby digital
logic, and high-power devices. The degree of error in the
digital output depends on the reference voltage, layout,
and the exact timing of the external event. The error can
change if the external event changes in time with respect
to the DCLK input.
With this in mind, power to the TSC2046 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor
should be placed as close to the device as possible. A 1µF
to 10µF capacitor may also be needed if the impedance of
the connection between +VCC or IOVDD and the power
supplies is high. Low-leakage capacitors should be used
to minimize power dissipation through the bypass
capacitors when the TSC2046 is in power-down mode.
A bypass capacitor is generally not needed on the VREF
pin because the internal reference is buffered by an
internal op amp. If an external reference voltage originates
from an op amp, make sure that it can drive any bypass
capacitor that is used without oscillation.
The TSC2046 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply appears directly in the digital results.
Whereas high-frequency noise can be filtered out, voltage
variation due to line frequency (50Hz or 60Hz) can be
difficult to remove.
The GND pin must be connected to a clean ground point.
In many cases, this is the analog ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run
a ground trace directly from the converter to the
power-supply entry or battery connection point. The ideal
layout includes an analog ground plane dedicated to the
converter and associated analog circuitry.
In the specific case of use with a resistive touch screen,
care should be taken with the connection between the
converter and the touch screen. Although resistive touch
screens have fairly low resistance, the interconnection
should be as short and robust as possible. Longer
connections are a source of error, much like the
on-resistance of the internal switches. Likewise, loose
connections can be a source of error when the contact
resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of
error in touch screen applications (e.g., applications that
require a backlit LCD panel). This EMI noise can be
coupled through the LCD panel to the touch screen and
cause flickering of the converted data. Several things can
be done to reduce this error, such as using a touch screen
with a bottom-side metal layer connected to ground to
shunt the majority of noise to ground. Additionally, filtering
capacitors from Y+, Y–, X+, and X− pins to ground can also
help. Caution should be observed under these
circumstances for settling time of the touch screen,
especially operating in the single-ended mode and at high
data rates.
"#$%&
SBAS265G − OCTOBER 2002 − REVISED JANUARY 2008
www.ti.com
21
Revision History
DATE REV PAGE SECTION DESCRIPTION
1/08
G
3, 4 Electrical Chartacteristics Fixed typos in conditions header and in Note (6).
1/08
G
13 Temperature Measurement Fixed typos in Equations (1) and (2).
8/07 F 5 Pin Configuration Added note to QFN package.
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TSC2046IGQCR BGA MI
CROSTA
R JUNI
OR
GQC 48 2500 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q1
TSC2046IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TSC2046IRGVR VQFN RGV 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TSC2046IRGVT VQFN RGV 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TSC2046IZQCR BGA MI
CROSTA
R JUNI
OR
ZQC 48 2500 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q1
TSC2046IZQCT BGA MI
CROSTA
R JUNI
OR
ZQC 48 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TSC2046IGQCR BGA MICROSTAR
JUNIOR GQC 48 2500 338.1 338.1 20.6
TSC2046IPWR TSSOP PW 16 2500 367.0 367.0 35.0
TSC2046IRGVR VQFN RGV 16 2500 367.0 367.0 35.0
TSC2046IRGVT VQFN RGV 16 250 210.0 185.0 35.0
TSC2046IZQCR BGA MICROSTAR
JUNIOR ZQC 48 2500 338.1 338.1 20.6
TSC2046IZQCT BGA MICROSTAR
JUNIOR ZQC 48 250 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MPLG008D – APRIL 2000 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GQC (S-PBGA-N48) PLASTIC BALL GRID ARRAY
0,50
M
0,05
0,50
0,08
4200460/E 01/02
4,10
3,90
1,00 MAX
0,25
0,35
A
1
Seating Plane
3,00 TYP
B
C
D
E
F
2 3 4 5 6 7
G
0,77
SQ
0,25
0,15
A1 Corner Bottom View
3,00 TYP
0,71
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
D. Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
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