SST39SF512-70-4C-WH-DM003 - Silicon Storage Technology, Inc.

S71149-03-000 2/02 394

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Multi-Purpose Flash and MPF are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit / 1 Mbit (x8) Multi-Purpose Flash

SST39SF512 / SST39SF010

FEATURES:

• Organized as 64K x8 / 128K x8

• Single 4.5-5.5V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 20 mA (typical)

– Standby Current: 10 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 70 ns

– 90 ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 7 ms (typical)

– Chip-Erase Time: 15 ms (typical)

– Byte-Program Time: 20 µs (typical)

– Chip Rewrite Time:

2 seconds (typical) for SST39SF512

3 seconds (typical) for SST39SF010

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP

PRODUCT DESCRIPTION

The SST39SF512/010 are CMOS Multi-Purpose Flash

(MPF) manufactured with SST’s proprietary, high perfor-

mance CMOS SuperFlash technology. The split-gate cell

design and thick oxide tunneling injector attain better reli-

ability and manufacturability compared with alternate

approaches. The SST39SF512/010 devices write (Pro-

gram or Erase) with a 4.5-5.5V power supply. The

SST39SF512/010 device conforms to JEDEC standard

pinouts for x8 memories.

Featuring high performance Byte-Program, the

SST39SF512/010 devices provide a maximum Byte-Pro-

gram time of 30 µsec. These devices use Toggle Bit or

Data# Polling to indicate the completion of Program opera-

tion. To protect against inadvertent write, they have on-chip

hardware and Software Data Protection schemes.

Designed, manufactured, and tested for a wide spectrum of

applications, these devices are offered with a guaranteed

endurance of 10,000 cycles. Data retention is rated at

greater than 100 years.

The SST39SF512/010 devices are suited for applications

that require convenient and economical updating of pro-

gram, configuration, or data memory. For all system appli-

cations, they significantly improve performance and

reliability, while lowering power consumption. They inher-

ently use less energy during erase and program than alter-

native flash technologies. The total energy consumed is a

function of the applied voltage, current, and time of applica-

tion. Since for any given voltage range, the SuperFlash

technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or

Program operation is less than alternative flash technolo-

gies. These devices also improve flexibility while lowering

the cost for program, data, and configuration storage appli-

cations.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet high density, surface mount requirements, the

SST39SF512/010 are offered in 32-lead PLCC packages,

32-lead TSOP, and a 600 mil, 32-pin PDIP is also available.

See Figures 1, 2, and 3 for pinouts.

SST39SF512 / 0105.0V 512Kb / 1Mb (x8) MPF memories

2
Data Sheet
512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010
©2002 Silicon Storage Technology, Inc. S71149-03-000 2/02 394
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39SF512/010 is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device selec-
tion. When CE# is high, the chip is deselected and only
standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 4).
Byte-Program Operation
The SST39SF512/010 are programmed on a byte-by-byte
basis. Before programming, the sector where the byte
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load byte address and byte data. During the Byte-
Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed, within 30 µs.
See Figures 5 and 6 for WE# and CE# controlled Program
operation timing diagrams and Figure 15 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands written during the internal Program operation
will be ignored. 
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The sector address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H)
is latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The end of Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any commands written during the Sector-
Erase operation will be ignored.
Chip-Erase Operation
The SST39SF512/010 provide Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1s” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. Dur-
ing the Erase operation, the only valid read is Toggle Bit or
Data# Polling. SeeTable 4 for the command sequence, Fig-
ure 10 for timing diagram, and Figure 18 for the flowchart.
Any commands written during the Chip-Erase operation
will be ignored.
Write Operation Status Detection
The SST39SF512/010 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the Program or Erase cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflict with either DQ7 or DQ6. In order to prevent spuri-
ous rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed loca-
tion an additional two (2) times. If both reads are valid,
then the device has completed the Write cycle, otherwise
the rejection is valid.

Data Sheet
512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010
3
©2002 Silicon Storage Technology, Inc. S71149-03-000 2/02 394
Data# Polling (DQ7)
When the SST39SF512/010 are in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
thought DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program Operation. For sector or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling
timing diagram and Figure 16 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. The Toggle Bit will
begin with “1”. When the internal Program or Erase opera-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# (or CE#) pulse for Program oper-
ation. For Sector or Chip-Erase, the Toggle Bit is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Toggle Bit timing diagram and Figure 16 for a flowchart. 
Data Protection
The SST39SF512/010 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39SF512/010 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three byte sequence.
The three-byte load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inadvert-
ent Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte load sequence. The SST39SF512 device is
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode, within TRC.
Product Identification
The Product Identification mode identifies the device as the
SST39SF512 and SST39SF010 and manufacturer as
SST. This mode may be accessed by software operations.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details,
Table 4 for software operation, Figure 11 for the software ID
entry and read timing diagram and Figure 17 for the ID
entry command sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the software reset command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 17 for a flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39SF512 0001H B4H
SST39SF010 0001H B5H
T1.2 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

Y-Decoder

I/O Buffers and Data Latches

394 ILL B1.1

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

SST39SF512SST39SF010

SST39SF512 SST39SF010

SST39SF512SST39SF010

SST39SF512 SST39SF010

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

VDD

WE#

A12

A15

A16

VDD

WE#

32-lead PLCC

Top View

394 ILL F02b.5

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

A11

A13

A14

WE#

VDD

A15

A12

A11

A13

A14

WE#

VDD

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

394 ILL F01.2

Standard Pinout

Top View

Die Up

SST39SF512SST39SF010 SST39SF512 SST39SF010

32-pin

PDIP

Top View

394 ILL F02a.3

A15

A12

DQ0

DQ1

DQ2

VSS

A16

A15

A12

DQ0

DQ1

DQ2

VSS

SST39SF512SST39SF010 SST39SF512 SST39SF010

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses.

During Sector-Erase AMS-A12 address lines will select the sector.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide 4.5-5.5V supply

VSS Ground

NC No Connection Unconnected pins.

T2.4 394

1. AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector address,

XXH for Chip-Erase

Standby VIH XXHigh Z X

Write Inhibit X VIL XHigh Z/ D

OUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.4 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX330H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit6XXH F0H

Software ID Exit65555H AAH 2AAAH 55H 5555H F0H

T4.3 394

1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST39SF512.

Addresses A15-A16 can be VIL or VIH, but no other value, for the Command sequence for

SST39SF010.

2. BA = Program Byte address

3. SAX for Sector-Erase; uses AMS-A12 address lines

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST39SF512 Device ID = B4H, is read with A0 = 1

SST39SF010 Device ID = B5H, is read with A0 = 1

6. Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 90 ns

See Figures 13 and 14

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

VDD=VDD Max

Read 30 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Write 50 mA CE#=WE#=VIL, OE#=VIH

ISB1 Standby VDD Current

(TTL input)

3µACE#=V

IH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input)

50 µA CE#=VDD -0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

T5.4 394

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T6.1 394

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.0 394

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH 1Latch Up 100 + IDD mA JEDEC Standard 78

T8.1 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 4.5-5.5V

Symbol Parameter

SST39SF512/010-70 SST39SF512/010-90

UnitsMinMaxMinMax

TRC Read Cycle Time 70 90 ns

TCE Chip Enable Access Time 70 90 ns

TAA Address Access Time 70 90 ns

TOE Output Enable Access Time 35 45 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 25 30 ns

TOHZ1OE# High to High-Z Output 25 30 ns

TOH1Output Hold from Address Change 0 0 ns

T9.3 394

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Byte-Program Time 30 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 10 ms

TSCE Chip-Erase 20 ms

T10.1 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

394 ILL F03.1

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F04.1

ADDRESS AMS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 7: DATA# POLLING TIMING DIAGRAM

394 ILL F05.1

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F06.1

ADDRESS AMS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ7DD# D# D

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

394 ILL F07.1

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note

Note: Toggle bit output is always high first.

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F08.2

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

FIGURE 11: SOFTWARE ID ENTRY AND READ

394 ILL F17.1

ADDRESS AMS-0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

394 ILL F09.2

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

Three-byte sequence for

Software ID Entry

TWP

TWPH TAA

Device ID

55AA 90

Device ID = B5H for SST39SF010 and B6H for SST39SF020

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 12: SOFTWARE ID EXIT AND RESET

394 ILL F10.0

ADDRESS A14-0

DQ7-0

TIDA

TWP

T WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 14: A TEST LOAD EXAMPLE

394 ILL F11.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for

inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.

Note: VHT - VHIGH Te st

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

394 ILL F12.1

TEST LOAD EXAMPLE

TO TESTER

TO DUT

CLRL LOW

RL HIGH

VDD

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 15: BYTE-PROGRAM ALGORITHM

394 ILL F13.1

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Byte

Address/Byte

Data

Wait for end of

Program (TBP'

Data# Polling

bit or Toggle bit

operation)

Program

Completed

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 16: WAIT OPTIONS

394 ILL F14.0

Wait TBP,

TSCE, or TSE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Write

Completed

Write

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte-Program

Initiated

Byte-Program/

Sector Erase

Initiated

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS

394 ILL F15.1

Load data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 18: ERASE COMMAND SEQUENCE

394 ILL F16.1

Load data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH

Address: 5555H

Wait TSCE

Chip-Erase

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SAX

Load data: AAH

Address: 5555H

Wait TSE

Sector-Erase

to FFH

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

PRODUCT ORDERING INFORMATION

Valid combinations for SST39SF512

SST39SF512-70-4C-NH SST39SF512-70-4C-WH SST39SF512-70-4C-PH

SST39SF512-90-4C-NH SST39SF512-90-4C-WH SST39SF512-90-4C-PH

SST39SF512-70-4I-NH SST39SF512-70-4I-WH

SST39SF512-90-4I-NH SST39SF512-90-4I-WH

Valid combinations for SST39SF010

SST39SF010-70-4C-NH SST39SF010-70-4C-WH SST39SF010-70-4C-PH

SST39SF010-90-4C-NH SST39SF010-90-4C-WH SST39SF010-90-4C-PH

SST39SF010-90-4I-NH SST39SF010-90-4I-WH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Device Speed Suffix1 Suffix2

SST39SFxxx -XX -XX-XX

Package Modifier

H = 32 pins or leads

Package Type

N = PLCC

P = PDIP

W = TSOP (type 1, die up, 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

90 = 90 ns

Device Density

010 = 1 Mbit

512 = 512 Kbit

Voltage

S = 4.5-5.5V

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

PACKAGING DIAGRAMS

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

.040

.030

.021

.013

.530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

TOP VIEW SIDE VIEW BOTTOM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30˚

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0˚- 5˚

DETAIL

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)

SST PACKAGE CODE: PH

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

Seating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7˚

4 PLCS.

.600 BSC

.100 BSC

.150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065

1.655

1.645

.012

.008

0˚

15˚

.625

.600

.550

.530

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036