CSP-6
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
I -LoadCurrent-mA
O
0
15
30
45
60
75
90
105
120
135
150
V =3.6V,
V =1.8V
I
O
Efficiency
PFM/PWMOperation
PowerLoss
PFM/PWMOperation
Efficiency-%
PowerLoss-mW
VIN SW
FB
MODE
EN
GND
VOUT
1.8 V @ 500mA
C
2.2 F
I
m
TPS62671 L
0.47 Hm
C
4.7 F
O
m
VBAT
2.3 V .. 4.8 V
TPS62671, TPS62674, TPS62675, TPS62679
www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
500-mA / 650-mA, 6-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER
IN LOW PROFILE CHIP SCALE PACKAGING (HEIGHT <0.4mm)
Check for Samples: TPS62671,TPS62674,TPS62675,TPS62679
1FEATURES APPLICATIONS
23•92% Efficiency at 6MHz Operation •Cell Phones, Smart-Phones
•17μA Quiescent Current •Camera Module Embedded Power
•Wide VIN Range From 2.3V to 4.8V •Digital TV, WLAN, GPS and Bluetooth™
•6MHz Regulated Frequency Operation Applications
•Spread Spectrum, PWM Frequency Dithering •DC/DC Micro Modules
•Best in Class Load and Line Transient
• ±2% Total DC Voltage Accuracy DESCRIPTION
•Low Ripple Light-Load PFM Mode The TPS6267x device is a high-frequency
synchronous step-down dc-dc converter optimized for
• ≥35dB VIN PSRR (1kHz to 10kHz) battery-powered portable applications. Intended for
•Simple Logic Enable Inputs low-power applications, the TPS6267x supports up to
•Supports External Clock Presence Detect 650-mA load current, and allows the use of low cost
Enable Input chip inductor and capacitors.
•Three Surface-Mount External Components With a wide input voltage range of 2.3V to 4.8V, the
Required (One 0603 MLCC Inductor, Two 0402 device supports applications powered by Li-Ion
Ceramic Capacitors) batteries with extended voltage range. Different fixed
voltage output versions are available from 1.0V to
•Complete Sub 0.33-mm Component Profile 2.3V.
Solution The TPS6267x operates at a regulated 6-MHz
•Total Solution Size <10 mm2switching frequency and enters the power-save mode
•Available in a 6-Pin NanoFree™(CSP) operation at light load currents to maintain high
Ultra-Thin Packaging, 0,4mm Max. Height efficiency over the entire load current range.
The PFM mode extends the battery life by reducing
the quiescent current to 17μA (typ) during light load
operation. For noise-sensitive applications, the device
has PWM spread spectrum capability providing a
lower noise regulated output, as well as low noise at
the input. These features, combined with high PSRR
and AC load regulation performance, make this
device suitable to replace a linear regulator to obtain
better power conversion efficiency.
Figure 1. Efficiency vs. Load Current Figure 2. Smallest Solution Size Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
3Bluetooth is a trademark of Bluetooth SIG, Inc.
UNLESS OTHERWISE NOTED this document contains Copyright ©2010–2011, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PACKAGE
PART OUTPUT DEVICE
TAORDERING(3) MARKING
NUMBER VOLTAGE(2) SPECIFIC FEATURE CHIP CODE
TPS62671 1.8V PWM Spread Spectrum Modulation TPS62671YFD NZ
TPS62672(4) 1.5V PWM Spread Spectrum Modulation TPS62672YFD OA
PWM Spread Spectrum Modulation
TPS62674 1.26V PWM Operation Only TPS62674YFD PN
-40°C to 85°C Output Capacitor Discharge
TPS62675 1.2V PWM Spread Spectrum Modulation TPS62675YFD OB
PWM Spread Spectrum Modulation
TPS62679 1.26V Extended Start-Up Time TPS62679ZYFM -
Output Capacitor Discharge
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Internal tap points are available to facilitate output voltages in 25mV increments.
(3) The YFD package is available in tape and reel. Add a R suffix (e.g. TPS62670YFDR) to order quantities of 3000 parts. Add a T suffix
(e.g. TPS62670YFDT) to order quantities of 250 parts.
(4) Product preview. Contact TI factory for more information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Voltage at VIN(2), SW(3) –0.3 V to 6 V
Input Voltage Voltage at FB(3) –0.3 V to 3.6 V
Voltage at EN, MODE (3) –0.3 V to VI+ 0.3 V
Power dissipation Internally limited
TAOperating temperature range(4) –40°C to 85°C
TJ(max) Maximum operating junction temperature 150°C
Tstg Storage temperature range –65°C to 150°C
Human body model 2 kV
ESD rating (5) Charge device model 1 kV
Machine model 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operation above 4.8V input voltage for extended periods may affect device reliability.
(3) All voltage values are with respect to network ground terminal.
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
(5) The human body model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VIInput voltage range 2.3 4.8(1) V
TPS62671 mA
TPS62672 0 500
TPS62674
IOOutput current range TPS62679
TPS62675 0 650 mA
L Inductance 0.3 1.8 µH
Output capacitance (PFM/PWM operation) 0.8 2.5 10 µF
COOutput capacitance (PWM operation) 0.8 2.5 10 µF
TAAmbient temperature –40 +85 °C
TJOperating junction temperature –40 +125 °C
(1) Operation above 4.8V input voltage for extended periods may affect device reliability.
DISSIPATION RATINGS(1)
POWER RATING DERATING FACTOR
PACKAGE RθJA (2) RθJB (2) TA≤25°C ABOVE TA= 25°C
YFD-6 125°C/W 53°C/W 800mW 8mW/°C
(1) Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD= [TJ(max)–TA] / θJA.
(2) This thermal data is measured with high-K board (4-layer board according to JESD51-7 JEDEC standard).
ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VI= 2.3V to 5.5V, VO= 1.8V, EN = 1.8V, AUTO mode and TA=–40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI= 3.6V, VO= 1.8V, EN =
1.8V, AUTO mode and TA= 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
TPS62671
TPS62672 IO= 0mA. Device not switching 17 40 μA
TPS62675
TPS62679
Operating quiescent
IQcurrent TPS62671 IO= 0mA, PWM mode 5.5 mA
TPS62674 IO= 0mA, PWM mode 5.0 mA
TPS62679
I(SD) Shutdown current EN = GND 0.2 1 μA
UVLO Undervoltage lockout threshold 2.05 2.1 V
ENABLE, MODE
High-level input
VIH 1.0 V
voltage TPS62671
Low-level input
VIL TPS62672 0.4 V
voltage TPS62675
Input leakage
Ilkg Input connected to GND or VIN 0.01 1.5 μA
current
High-level input 1.26 V
voltage (ENABLE)
VIH High-level input TPS62674 1.0 V
voltage (MODE) TPS62679
Low-level input 0.54 V
voltage (ENABLE)
VIL Low-level input TPS62679 0.4 V
voltage (MODE)
Input leakage TPS62674
Ilkg Input connected to GND or VIN 0.01 1.5 μA
current TPS62679
Input capacitance
CIN 5 pF
(ENABLE)
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VI= 2.3V to 5.5V, VO= 1.8V, EN = 1.8V, AUTO mode and TA=–40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI= 3.6V, VO= 1.8V, EN =
1.8V, AUTO mode and TA= 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Clock presence 4 27 MHz
detect frequency TPS62674
EXTCLK TPS62679
Clock presence 40 60 %
detect duty cycle
POWER SWITCH
VI= V(GS) = 3.6V. PWM mode 170 mΩ
rDS(on) P-channel MOSFET on resistance VI= V(GS) = 2.5V. PWM mode 230 mΩ
Ilkg P-channel leakage current, PMOS V(DS) = 5.5V, -40°C≤TJ≤85°C 1 μA
VI= V(GS) = 3.6V. PWM mode 120 mΩ
rDS(on) N-channel MOSFET on resistance VI= V(GS) = 2.5V. PWM mode 180 mΩ
Ilkg N-channel leakage current, NMOS V(DS) = 5.5V, -40°C≤TJ≤85°C 2 μA
Discharge resistor for power-down
rDIS 70 150 Ω
sequence
TPS62671
TPS62672
2.3V ≤VI≤4.8V. Open loop 900 1000 1150 mA
TPS62674
P-MOS current limit TPS62679
2.3V ≤VI≤4.8V. Open loop TPS62675 1000 1100 1250 mA
Input current limit under short-circuit VOshorted to ground 12 mA
conditions
Thermal shutdown 140 °C
Thermal shutdown hysteresis 10 °C
OSCILLATOR
TPS62671
Oscillator center TPS62672 IO= 0mA. PWM operation 5.4 6 6.6 MHz
frequency TPS62675
fSW Oscillator center TPS62674 IO= 0mA. PWM operation 4.9 5.45 6.0 MHz
frequency TPS62679
OUTPUT
2.3V ≤VI≤4.8V, 0mA ≤IO≤500 mA 0.98×VNOM VNOM 1.03×VNOM V
PFM/PWM operation
TPS62671 2.3V ≤VI≤5.5V, 0mA ≤IO≤500 mA
TPS62672 0.98×VNOM VNOM 1.04×VNOM V
PFM/PWM operation
TPS62679 2.3V ≤VI≤5.5V, 0mA ≤IO≤500 mA 0.98×VNOM VNOM 1.02×VNOM V
PWM operation
Regulated DC
output voltage 2.3V ≤VI≤5.5V, 0mA ≤IO≤500 mA
TPS62674 0.98×VNOM VNOM 1.02×VNOM V
VOUT PWM operation
2.3V ≤VI≤4.8V, 0mA ≤IO≤650 mA 0.98×VNOM VNOM 1.03×VNOM V
PFM/PWM operation
TPS62675 2.3V ≤VI≤5.5V, 0mA ≤IO≤650 mA 0.98×VNOM VNOM 1.02×VNOM V
PWM operation
Line regulation VI= VO+ 0.5V (min 2.3V) to 5.5V, IO= 200 mA 0.23 %/V
Load regulation IO= 0mA to 500 mA. PWM operation –0.00045 %/mA
Feedback input resistance 480 kΩ
TPS62671 IO= 1mA, VO= 1.8 V 14 mVPP
Power-save mode
ΔVOTPS62675
ripple voltage IO= 1mA, VO= 1.2 V 16 mVPP
TPS62679
TPS62671 IO= 0mA, Time from active EN to VO130 μs
TPS62674 IO= 0mA, Time from EXTCLK clock active to VO125 μs
Start-up time IO= 0mA, Time from EXTCLK clock active to VO
TPS62679 L = 1μH DCR = 240mΩ0603 (TY CKP1608S1R0) 430 μs
CO= 2.2μF 4V 0402 (TY AMK105BJ225MP)
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Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
GND
A1
B1
C1
A2
B2
C2
FB
SW
MODE VIN
EN
TPS6267x
CSP-6
(TOP VIEW)
MODE
C1
A2
B2
C2
A1
B1
VIN
EN
GND FB
SW
TPS6267x
CSP-6
(BOTTOMVIEW)
TPS62671, TPS62674, TPS62675, TPS62679
www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VI= 2.3V to 5.5V, VO= 1.8V, EN = 1.8V, AUTO mode and TA=–40°C to 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are at VI= 3.6V, VO= 1.8V, EN =
1.8V, AUTO mode and TA= 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO= 0mA, Time from EXTCLK clock inactive to VOdown 1.2 ms
CO= 4.7μF 6.3V 0402 (muRata GRM155R60J475M)
TPS62674
Shutdown time IO= 0mA, Time from EXTCLK clock inactive to VOdown
TPS62679 L = 1μH DCR = 240mΩ0603 (TY CKP1608S1R0) 600 μs
CO= 2.2μF 4V 0402 (TY AMK105BJ225MP)
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
FB C1 I Output feedback sense input. Connect FB to the converter’s output.
VIN A2 I Power supply input.
This is the switch pin of the converter and is connected to the drain of the internal Power
SW B1 I/O MOSFETs.
This is the enable pin of the device. Connecting this pin to ground forces the device into
shutdown mode. Pulling this pin to VIenables the device. If an external clock (4MHz to 27MHz) is
EN B2 I detected the device will automatically power up. This pin must not be left floating and must be
terminated.
This is the mode selection pin of the device. This pin must not be left floating and must be
terminated.
MODE = LOW: The device is operating in regulated frequency pulse width modulation mode
MODE A1 I (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load
currents.
MODE = HIGH: Low-noise mode enabled, regulated frequency PWM operation forced.
GND C2 –Ground pin.
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Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
GateDriver
Anti
Shoot-Through
PowerSaveMode
SwitchingLogic
+
-
Frequency
Control
FB
R1
R2
SW
GND
Soft-Start
EN VIN
CurrentLimit
Detect
Undervoltage
Lockout
BiasSupply
Bandgap
Thermal
Shutdown
NegativeInductor
CurrentDetect
VIN
MODE
V = 0.8 V
REF
VREF
VIN SW
FB
MODE
EN
GND
L
VICI
TPS6267x
CO
VO
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
PARAMETER MEASUREMENT INFORMATION
List of components:
•L = MURATA LQM21PN1R0NGR
•CI= MURATA GRM155R60J225ME15 (2.2μF, 6.3V, 0402, X5R)
•CO= MURATA GRM155R60J475M (4.7μF, 6.3V, 0402, X5R)
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V = 1.2 V
O
V = 2.7 V
PFM/PWM Operation
I
V = 4.2 V
PFM/PWM Operation
I
V = 3.6 V
PFM/PWM Operation
I
V = 3.6 V
Forced PWM
I
0.1 1 10 100 1000
I - Load Current - mA
O
0
10
20
30
40
50
60
70
80
90
100
Efficiency - %
0.1 1 10 100 1000
I - Load Current - mA
O
0
10
20
30
40
50
60
70
80
90
100
Efficiency - %
V = 1.8 V
O
V = 4.2 V
PFM/PWM Operation
I
V = 2.7 V
PFM/PWM Operation
I
V = 3.6 V
PFM/PWM Operation
I
V = 3.6 V
Forced PWM
I
TPS62671, TPS62674, TPS62675, TPS62679
www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Load current 3, 4, 5, 6
ηEfficiency vs Input voltage 7
Peak-to-peak output ripple voltage vs Load current 8, 9
Combined line/load transient 10, 11
response 12, 13, 14, 15, 16,
Load transient response 17, 18, 19, 20, 21
AC load transient response 22, 23
VODC output voltage vs Load current 24, 25, 26
PFM/PWM boundaries vs Input voltage 27, 28
IQQuiescent current vs Input voltage 29
PWM switching frequency vs Input voltage 30, 31
fsPFM switching frequency vs Input voltage 32
PWM operation 33, 34
Power-save mode operation 35
Start-up 36, 37, 38, 40
Shutdown 39, 41
PSRR Power supply rejection ratio vs. Frequency 42
Spurious output noise (PWM mode) vs. Frequency 43, 44, 46
Spurious output noise (PFM mode) vs. Frequency 45
Output spectral noise density vs. Frequency 47
EFFICIENCY EFFICIENCY
vs vs
LOAD CURRENT LOAD CURRENT
Figure 3. Figure 4.
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0
10
20
30
40
50
60
70
80
90
100
Efficiency - %
1 10 100 1000
I - Load Current - mA
O
V = 2.7 V
PWM Operation
I
V = 4.2 V
PWM Operation
I
V = 3.6 V
PWM Operation
I
V = 1.26 V
O
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7
V - Input Voltage - V
I
70
72
74
76
78
80
82
84
86
88
90
Efficiency - %
I = 10 mA
O
I = 300 mA
O
I = 100 mA
O
I = 1 mA
O
V = 1.2 V
PFM/PWM Operation
O
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY EFFICIENCY
vs vs
LOAD CURRENT LOAD CURRENT
Figure 5. Figure 6.
EFFICIENCY PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs vs
INPUT VOLTAGE LOAD CURRENT
Figure 7. Figure 8.
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MODE = Low
3.3V to 3.9V Line Step
30 to 300 mA Load Step
V = 3.6 V,
V = 1.8 V
I
O
0
2
4
6
8
10
12
14
16
18
20
22
V -Peak-to-PeakOutputRippleVoltage-mV
O
0 20 40 60 80 100 120 140 160 180 200
I -LoadCurrent-mA
O
V =1.2V
O
V =3.6V
I
V =4.5V
I
V =2.7V
I
MODE = Low
V = 3.6 V,
V = 1.8 V
I
O
2.7V to 3.3V Line Step
30 to 300 mA Load Step
MODE = Low
V = 3.6 V,
V = 1.2 V
I
O
5 to 150 mA Load Step
TPS62671, TPS62674, TPS62675, TPS62679
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
LOAD CURRENT COMBINED LINE/LOAD TRANSIENT RESPONSE
Figure 9. Figure 10.
LOAD TRANSIENT RESPONSE IN
COMBINED LINE/LOAD TRANSIENT RESPONSE PFM/PWM OPERATION
Figure 11. Figure 12.
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MODE = Low
V = 3.6 V,
V = 1.2 V
I
O50 to 350 mA Load Step
MODE = Low
V = 2.7 V,
V = 1.2 V
I
O50 to 350 mA Load Step
MODE = Low
V = 4.8 V,
V = 1.2 V
I
O50 to 350 mA Load Step
MODE = Low
V = 3.6 V,
V = 1.2 V
I
O150 to 500 mA Load Step
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION PFM/PWM OPERATION
Figure 13. Figure 14.
LOAD TRANSIENT RESPONSE IN LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION PFM/PWM OPERATION
Figure 15. Figure 16.
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Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
MODE = Low
V = 2.7 V,
V = 1.2 V
I
O150 to 500 mA Load Step
MODE = Low
V = 4.8 V,
V = 1.2 V
I
O150 to 500 mA Load Step
MODE = Low
V = 3.6 V,
V = 1.8 V
I
O
5 to 150 mA Load Step
MODE = Low
V = 3.6 V,
V = 1.8 V
I
O50 to 350 mA Load Step
TPS62671, TPS62674, TPS62675, TPS62679
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN LOAD TRANSIENT RESPONSE
PFM/PWM OPERATION IN PFM/PWM OPERATION
Figure 17. Figure 18.
LOAD TRANSIENT RESPONSE IN LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION PFM/PWM OPERATION
Figure 19. Figure 20.
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Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
MODE = Low
V = 3.6 V,
V = 1.8 V
I
O150 to 500 mA Load
MODE = Low
V = 3.6 V,
V = 1.2 V
I
O
5 to 300 mA Load Sweep
MODE = Low
V = 3.6 V,
V = 1.8 V
I
O
5 to 300 mA Load Sweep
1.764
1.782
1.800
1.818
1.836
0.1 1 10 100 1000
I -LoadCurrent-mA
O
V =1.8V
PFM/PWMOperation
O
V =3.6V
I
V =4.5V
I
V =2.7V
I
V -OutputVoltage-V
O
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
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TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION AC LOAD TRANSIENT RESPONSE
Figure 21. Figure 22.
DC OUTPUT VOLTAGE
vs
AC LOAD TRANSIENT RESPONSE LOAD CURRENT
Figure 23. Figure 24.
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1.176
1.188
1.2
1.212
1.224
V -OutputVoltage-V
O
0.1 1 10 100 1000
I -LoadCurrent-mA
O
V =1.2V
PFM/PWMOperation
O
V =3.6V
I
V =4.5V
I
V =2.7V
I
0.1 1 10 100 1000
I -LoadCurrent-mA
O
1.235
1.247
1.260
1.273
1.285
V -OutputVoltage-V
O
V =1.26V
PWMOperation
O
V =2.7V
I
V =4.5V
I
V =3.6V
I
2.7 3 3.3 3.6 3.9 4.2 4.5 4.8
V - Input Voltage - V
I
0
20
40
60
80
100
120
140
160
180
200
I - Load Current - mA
O
V = 1.2 V
O
PFM to PWM
Mode Change
PWM to PFM
Mode Change
Always PWM
Always PFM
The switching mode changes
at these borders
0
10
20
30
40
50
60
70
80
90
100
Always PFM
Always PWM
V = 1.8 V
O
PFM to PWM
Mode Change
PWM to PFM
Mode Change
The switching mode changes
at these borders
2.7 3 3.3 3.6 3.9 4.2 4.5 4.8
V - Input Voltage - V
I
I - Load Current - mA
O
TPS62671, TPS62674, TPS62675, TPS62679
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE DC OUTPUT VOLTAGE
vs vs
LOAD CURRENT LOAD CURRENT
Figure 25. Figure 26.
PFM/PWM BOUNDARIES PFM/PWM BOUNDARIES
Figure 27. Figure 28.
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V - Input Voltage - V
I
f - Switching Frequency - MHz
s
2.5
3
3.5
4
4.5
5
5.5
6
6.5
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
V = 1.8 V
O
I = 500 mA
O
I = 400 mA
O
I = 300 mA
O
I = 150 mA
O
V -InputVoltage-V
I
I -QuiescentCurrent- A
Qm
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
2.7 3 3.3 3.6 3.9 4.2 4.5 4.8
T =85°C
A
T =25°C
A
T =-40°C
A
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
6.1
6.3
6.5
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
V -InputVoltage-V
I
f -SwitchingFrequency-MHz
s
I Rangingfrom0to500mA
O
V =1.2V
O
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0 20 40 60 80 100 120 140 160
V =1.2V
O
V =3.6V
I
V =4.5V
I
V =2.7V
I
I -LoadCurrent-mA
O
f -MeanSwitchingFrequency-MHz
S
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT PWM SWITCHING FREQUENCY
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 29. Figure 30.
PWM SWITCHING FREQUENCY PFM SWITCHING FREQUENCY
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 31. Figure 32.
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MODE = Low
V = 3.6 V,
V = 1.2 V,
I
I
O
O= 150 mA
MODE = Low
V = 3.6 V,
V = 1.2 V,
I
O
I = 200 mA
O
MODE = Low
V = 3.6 V, V = 1.2V, I
I O O = 40 mA
MODE = Low
V = 3.6 V,
V = 1.8 V,
I
O
I = 0 mA
O
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www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)
PWM OPERATION
PWM OPERATION SSFM MODULATION
Figure 33. Figure 34.
POWER-SAVE MODE OPERATION START-UP
Figure 35. Figure 36.
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MODE = Low
V = 3.6 V,
V = 1.2 V,
I
O
I = 0 mA
O
MODE = High
V = 3.6 V,
V = 1.2 V,
I
O
I = 0 mA
O
MODE = High
V = 3.6 V,
V = 1.2 V,
I
O
I = 0 mA,
C = 4.7uF 6.3V X5R (0402)
O
O
V = 3.6 V,
V = 1.26 V,
I
O
I = 0 mA
O
L = TY CKP1608S1R0,
C = TY AMK105BJ225MP
O
MODE = Low
TPS62679
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
START-UP START-UP (RF CLOCK)
Figure 37. Figure 38.
SHUT-DOWN (RF CLOCK) START-UP (RF CLOCK)
Figure 39. Figure 40.
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MODE = Low
V = 3.6 V,
V = 1.26 V,
I
O
I = 0 mA
O
L = TY CKP1608S1R0,
C = TY AMK105BJ225MP
O
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
0.01 0.1 1 10 100 1000
f - Frequency - kHz
PSRR - Power Supply Rejection Ratio - dB
I = 10 mA
PFM Operation
O
I = 400 mA
PWM Operation
O
I = 150 mA
PWM Operation
O
V = 3.6 V,
V = 1.8 V
I
O
0 40
70 m
60 m
50 m
40 m
30 m
20 m
10 m
1 n
Spurious Output Noise (PWM Mode) - V
f - Frequency - MHz
Span = 4 MHz
V = 2.7 V
IV = 3.6 V
I
V = 4.2 V
I
V = 1.2 V
R = 12
O
LΩ
80 m
90 m
100 m
10 m
4.65 7.15
70 m
60 m
50 m
40 m
30 m
20 m
1 n
f - Frequency - MHz
Span = 250 kHz
100 m
90 m
80 m
Spurious Output Noise (PWM Mode) - V
V = 3.6 V
I
V = 1.2 V
R = 12
O
LΩ
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www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTICS (continued)
POWER SUPPLY REJECTION RATIO
vs
SHUT-DOWN (RF CLOCK) FREQUENCY
Figure 41. Figure 42.
SPURIOUS OUTPUT NOISE (PWM MODE) SPURIOUS OUTPUT NOISE (PWM MODE)
vs vs
FREQUENCY FREQUENCY
Figure 43. Figure 44.
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0 10
3.5 m
3 m
2.5 m
2 m
1.5 m
1 m
500 m
40 n
Spurious Output Noise (PFM Mode) - V
f - Frequency - MHz
Span = 1 MHz
V = 1.8 V
R = 150
O
LΩ
V = 3.6 V
I
V = 4.2 V
I
V = 2.7 V
I
4 m
0 100
70 m
60 m
50 m
40 m
30 m
20 m
10 m
1.2 n
Spurious Output Noise (PWM Mode) - V
f - Frequency - MHz
Span = 10 MHz
V = 1.8 V
R = 12
O
LΩ
V = 3.6 V
I
V = 4.2 V
IV = 2.7 V
I
90 m
80 m
110 m
100 m
120 m
0.001
0.01
0.1
1
10
0.1 1 10 100 1000
f - Frequency - kHz
Ö
Output Spectral Noise Density - µV/ Hz
V = 3.6 V,
V = 1.8 V
I
O
I = 1 mA
(PFM Mode)
O
I = 10 mA (PFM Mode)
O
I = 150 mA (PWM Mode)
O
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SPURIOUS OUTPUT NOISE (PFM MODE) SPURIOUS OUTPUT NOISE (PWM MODE)
vs vs
FREQUENCY FREQUENCY
Figure 45. Figure 46.
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Figure 47.
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
DETAILED DESCRIPTION
OPERATION
The TPS6267x is a synchronous step-down converter typically operates at a regulated 6-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6267x converter
operates in power-save mode with pulse frequency modulation (PFM).
The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line
response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of
each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the
output voltage until the main comparator trips, then the control logic turns off the switch.
One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response
to change in VOis essentially instantaneous, which explains the transient response. The absence of a traditional,
high-gain compensated linear loop means that the TPS6267x is inherently stable over a range of L and CO.
Although this type of operation normally results in a switching frequency that varies with input voltage and load
current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of
operating conditions.
Combined with best in class load and line transient response characteristics, the low quiescent current of the
device (ca. 17μA) allows to maintain high efficiency at light load, while preserving fast transient response for
applications requiring tight output regulation.
Using the YFD package allows for a low profile solution size (0.4mm max height, including external components).
The recommended external components are stated within the application information. The maximum output
current is 500mA when these specific low profile external components are used.
SWITCHING FREQUENCY
The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of
50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The
intrinsic maximum operating frequency of the converter is about 10MHz to 12MHz, which is controlled to circa.
6MHz by a frequency locked loop.
When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls
below 6MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather
than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at
low duty cycles.
When the converter is required to operate towards the 6MHz nominal at extreme duty cycles, the application can
be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL).
This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation
delay, hence increasing the switching frequency.
POWER-SAVE MODE
If the load current decreases, the converter will enter Power Save Mode operation automatically (does not apply
for TPS62674). During power-save mode the converter operates in discontinuous current (DCM) single-pulse
PFM mode, which produces low output ripple compared with other PFM architectures.
When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal
voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the
inductor current has returned to a zero steady state. The PFM on-time varies inversely proportional to the input
voltage and proportional to the output voltage giving the regulated switching frequency when in steady-state.
PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode.
As a consequence, the DC output voltage is typically positioned ca. 0.5% above the nominal output voltage and
the transition between PFM and PWM is seamless.
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PFMModeatLightLoad
PFMRipple
PWMModeatHeavyLoad
NominalDCOutputVoltage
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
Figure 48. Operation in PFM Mode and Transfer to PWM Mode
MODE SELECTION
The MODE pin allows to select the operating mode of the device. Connecting this pin to GND enables the
automatic PWM and power-save mode operation. The converter operates in regulated frequency PWM mode at
moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide
load current range.
Pulling the MODE pin high forces the converter to operate in the PWM mode even at light load currents. The
advantage is that the converter modulates its switching frequency according to a spread spectrum PWM
modulation technique allowing simple filtering of the switching harmonics in noise-sensitive applications. In this
mode, the efficiency is lower compared to the power-save mode during light loads. Notice that the TPS62674
device only permits PWM operation and required the MODE input to be tied high.
For additional flexibility, it is possible to switch from power-save mode to PWM mode during operation. This
allows efficient power management by adjusting the operation of the converter to the specific system
requirements.
SPREAD SPECTRUM, PWM FREQUENCY DITHERING
The goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar
to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to
comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in
cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that
is focused on specific frequencies.
Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or regulated, based on the output load. This method of conversion
creates large components of noise at the frequency of operation (fundamental) and multiples of the operating
frequency (harmonics).
The spread spectrum architecture varies the switching frequency by ca. ±10% of the nominal switching frequency
thereby significantly reducing the peak radiated and conducting noise on both the input and output supplies. The
frequency dithering scheme is modulated with a triangle profile and a modulation frequency fm.
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( ) )(212 mcfm ffmfB +D×=+××=
0dBV
0dBVref
F1
FENV,PEAK Dfc Dfc Non-modulatedharmonic
Side-bandharmonics
windowaftermodulation
( )
( )
hmfB
ffmfB
fmh
mcfm
×+××=
+D×=+××=
12
)(212
c
ƒ
m
δ ƒ
m = ƒ
´
c
c
ƒ
=ƒ
D
d
( ) ( )
m c m
B = 2 1 + m = 2 +
¦
´ ¦ ´ ´ D¦ ¦
TPS62671, TPS62674, TPS62675, TPS62679
www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
Figure 49. Spectrum of a Frequency Modulated Figure 50. Spread Bands of Harmonics in
Sin. Wave with Sinusoidal Variation in Time Modulated Square Signals (1)
The above figures show that after modulation the sideband harmonic is attenuated compared to the
non-modulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the
modulation index (mf) the larger the attenuation.
(1)
With:
fcis the carrier frequency
fmis the modulating frequency (approx. 0.008*fc)
δis the modulation ratio (approx 0.1)
(2)
The maximum switching frequency fcis limited by the process and finally the parameter modulation ratio (δ),
together with fm, which is the side-band harmonics bandwidth around the carrier frequency fc. The
bandwidth of a frequency modulated waveform is approximately given by the Carson’s rule and can be
summarized as:
(3)
fm<RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are
added in the input filter and the measured value is higher than expected in theoretical calculations.
fm>RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the
measurements match with the theoretical calculations.
ENABLE
The TPS6267x device starts operation when EN is set high and starts up with the soft start as previously
described. For proper operation, the EN pin must be terminated and must not be left floating.
Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.1μA. In
this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected,
and the entire internal-control circuitry is switched off. The TPS6267x device can actively discharge the output
capacitor when it turns off. The integrated discharge resistor has a typical resistance of 100 Ω. The required time
to discharge the output capacitor at the output node depends on load current and the output capacitance value.
(1) Spectrum illustrations and formulae (Figure 49 and Figure 50) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC
COMPATIBILITY, VOL. 47, NO.3, AUGUST 2005. See REFERENCES section for full citation.
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
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When an external clock signal (EXTCLK), 4MHz to 27MHz is applied to the TPS62674 or TPS62679, the DC/DC
converter powers-up automatically within approx. 120μs (TPS62674) or 450μs (TPS62679). When the external
clock signal is stopped, the DC/DC converter is powered down and the output capacitor is discharged actively.
SOFT START
The TPS6267x has an internal soft-start circuit that limits the inrush current during start-up. This limits input
voltage drops when a battery or a high-impedance power source is connected to the input of the converter.
The soft-start system progressively increases the on-time from a minimum pulse-width of 35ns as a function of
the output voltage. This mode of operation continues for c.a. 100μs after enable. Should the output voltage not
have reached its target value by this time, such as in the case of heavy load, the soft-start transitions to a second
mode of operation.
The converter then operates in a current limit mode, specifically the P-MOS current limit is set to half the nominal
limit, and the N-channel MOSFET remains on until the inductor current has reset. After a further 100 μs, the
device ramps up to the full current limit operation if the output voltage has risen above 0.5V (approximately).
Therefore, the start-up time mainly depends on the output capacitor and load current.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS6267x device
have a UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.1V input voltage.
SHORT-CIRCUIT PROTECTION
The TPS6267x integrates a P-channel MOSFET current limit to protect the device against heavy load or short
circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned
off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-by-cycle
basis.
As soon as the output voltage falls below ca. 0.4V, the converter current limit is reduced to half of the nominal
value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half
of its nominal current limit until the output voltage exceeds approximately 0.5V. This needs to be considered
when a load acting as a current sink is connected to the output of the converter.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature again falls below typically 130°C.
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DIL+VO
VI VI*VO
L ƒsw DIL(MAX) +IO(MAX) )
DIL
2
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www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
APPLICATION INFORMATION
INDUCTOR SELECTION
The TPS6267x series of step-down converters have been optimized to operate with an effective inductance
value in the range of 0.3μH to 1.8μH and with output capacitors in the range of 2.2μF to 4.7μF. The internal
compensation is optimized to operate with an output filter of L = 0.47μH and CO= 2.2μF. Larger or smaller
inductor values can be used to optimize the performance of the device for specific operation conditions. For more
details, see the CHECKING LOOP STABILITY section.
The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIor VO.
with: fSW = switching frequency (6 MHz typical)
L = inductor value
ΔIL= peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current (4)
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e.
quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC) , and the following
frequency-dependent components:
•The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
•Additional losses in the conductor from the skin effect (current displacement at high frequencies)
•Magnetic field losses of the neighboring windings (proximity effect)
•Radiation losses
The following inductor series from different suppliers have been used with the TPS6267x converters.
Table 1. List of Inductors
MANUFACTURER SERIES DIMENSIONS (in mm)
LQM21PN1R0NGR 2.0 x 1.2 x 1.0 max. height
LQM21PNR47MC0 2.0 x 1.2 x 0.55 max. height
MURATA LQM21PN1R0MC0 2.0 x 1.2 x 0.55 max. height
LQM18PN1R5-B35 1.6 x 0.8 x 0.4 max. height
LQM18PN1R5-A62 1.6 x 0.8 x 0.33 max. height
PANASONIC ELGTEAR82NA 2.0 x 1.2 x 1.0 max. height
SEMCO CIG21L1R0MNE 2.0 x 1.2 x 1.0 max. height
BRC1608T1R0M6, BRC1608TR50M6 1.6 x 0.8 x 1.0 max. height
CKP1608L1R5M 1.6 x 0.8 x 0.55 max. height
TAIYO YUDEN CKP1608U1R5M 1.6 x 0.8 x 0.4 max. height
CKP1608S1R0M, CKP1608S1R5M 1.6 x 0.8 x 0.33 max. height
NM2012NR82, NM2012N1R0 2.0 x 1.2 x 1.0 max. height
TDK MLP2012SR82T 2.0 x 1.2 x 0.6 max. height
TOKO MDT2012-CR1R0A 2.0 x 1.2 x 1.0 max. height
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SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
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OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS6267x allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. For best performance, the device should be operated with a minimum effective output
capacitance of 0.8μF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor
impedance.
At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load
transitions. A 2.2μF or 4.7μF ceramic capacitor typically provides sufficient bulk capacitance to stabilize the
output during large load transitions. The typical output voltage ripple is 1% of the nominal output voltage VO.
For best operation (i.e. optimum efficiency over the entire load current range, proper PFM/PWM auto transition),
the TPS6267x requires a minimum output ripple voltage in PFM mode. The typical output voltage ripple is ca. 1%
of the nominal output voltage VO. The PFM pulses are time controlled resulting in a PFM output voltage ripple
and PFM frequency that depends (first order) on the capacitance seen at the converter's output.
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 1 or 2.2-μF capacitor is sufficient. If the application exhibits a
noisy or erratic switching frequency, the remedy will probably be found by experimenting with the value of the
input capacitor.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CIand the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
•Switching node, SW
•Inductor current, IL
•Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VOimmediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of CO.ΔI(LOAD) begins to charge or discharge COgenerating a feedback error
signal used by the regulator to return VOto its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VOcan be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45°of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
24 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
MODE
ENABLE
CI
LVIN
CO
VOUT
GND
TPS62671, TPS62674, TPS62675, TPS62679
www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6267x devices demand careful attention to PCB layout. Care must be taken in board layout to get the
specified performance. If the layout is not carefully done, the regulator could show poor line and/or load
regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low
inductance, impedance ground path. Therefore, use wide and short traces for the main current paths.
The ground pins of the dc/dc converter must be strongly connected to the PCB ground (i.e. reference potential
across the system). These ground pins serve as the return path for both the control circuitry and the synchronous
rectifier. Furthermore, due to its high frequency switching circuitry, it is imperative for the input capacitor to be as
close to the SMPS device as possible, and that there is an unbroken ground plane under the TPS6267x and its
external passives. Additionally, minimizing the area between the SW pin trace and inductor will limit high
frequency radiated energy. The feed-back line should be routed away from noisy components and traces (e.g.
SW line).
The output capacitor carries the inductor ripple current. While not as critical as the input capacitor, an unbroken
ground connection from this capacitor’s ground return to the inductor, input capacitor and SMPS device will
reduce the output voltage ripple and it’s associated ESL step. This is a critical aspect to achieve best loop and
frequency stability.
High frequency currents tend to find their way on the ground plane along a mirror path directly beneath the
incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that
layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back
through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There
should be a group of vias in the surrounding of the dc/dc converter leading directly down to an internal ground
plane. To minimize parasitic inductance, the ground plane should be as close as possible to the top plane of the
PCB (i.e. onto which the components are located).
Figure 51. Suggested Layout (Top)
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
J(MAX) A
D(MAX)
JA
T - T 105 C - 85 C
P = = = 160mW
R 125 C/W
q
° °
°
YMDS
CC
A1
A1
B1
C1
A2
B2
D
E
C2
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•Improving the power dissipation capability of the PCB design
•Improving the thermal coupling of the component to the PCB
•Introducing airflow into the system
The maximum recommended junction temperature (TJ) of the TPS6267x devices is 105°C. The thermal
resistance of the 6-pin CSP package (YFD-6) is RθJA = 125°C/W. Regulator operation is specified to a maximum
steady-state ambient temperature TAof 85°C. Therefore, the maximum power dissipation is about 160 mW.
(5)
PACKAGE SUMMARY
CHIP SCALE PACKAGE CHIP SCALE PACKAGE
(BOTTOM VIEW) (TOP VIEW)
Code:
•YM —Year Month date Code
•D—Day of laser mark
•S—Assembly site code
•CC —Chip code
CHIP SCALE PACKAGE DIMENSIONS
The TPS6267x device is available in an 6-bump chip scale package (YFD, NanoFree™). The package
dimensions are given as:
•D = 1.30 ±0.03 mm
•E = 0.926 ±0.03 mm
26 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
VIN SW
FB
VOUT
1.26 V @ 500 mA
C
1 F
I
m
TPS62674 L
1.5 Hm
C
2.2 F
O
m
VBAT
2.3 V .. 4.8 V
MODE
EXTCLK EN GND
L = muRata LQM18PN1R5-B35
C = muRata GRM153R60G225M
C = muRata GRM153R60J105M
I
O
TPS62671, TPS62674, TPS62675, TPS62679
www.ti.com
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
APPLICATION INFORMATION
Figure 52. 1.26V CMOS Sensor Embedded Power Solution —Featuring Sub 0.4mm Profile
REFERENCES
"EMI Reduction in Switched Power Converters Using Frequency Modulation Techniques", in IEEE
TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 4, NO. 3, AUGUST 2005, pp 569-576 by
Josep Balcells, Alfonso Santolaria, Antonio Orlandi, David González, Javier Gago.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
TPS62671, TPS62674, TPS62675, TPS62679
SLVS952D –APRIL 2010–REVISED SEPTEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Original (April 2010) to Revision A Page
•Changed Figure 3 image in Typical Char. graphs ................................................................................................................ 7
•Changed Figure 40 image in the Typical Char. graphs ...................................................................................................... 16
•Changed Figure 45 image in the Typical Char. graphs. ..................................................................................................... 18
Changes from Revision A (November 2010) to Revision B Page
•Changed device TPS62679 to Production status, and changed TPS62671 to Product Preview status in the Ordering
Info table. .............................................................................................................................................................................. 2
Changes from Revision B (January 2011) to Revision C Page
•Changed devices TPS62671 and TPS62675 to Production status in Ordering Info table. .................................................. 2
•Added copyright attribution for spectrum illustrations ......................................................................................................... 21
Changes from Revision C (April 2011) to Revision D Page
•Changed IOspecification for TPS62675 from "600 mA"MAX to "650 mA "......................................................................... 3
•Changed VOUT specification Condition statement from "600 mA"to "650 mA"for TPS62675 ............................................. 4
28 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS62671 TPS62674 TPS62675 TPS62679
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TPS62671YFDR ACTIVE DSBGA YFD 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 NZ
TPS62671YFDT ACTIVE DSBGA YFD 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 NZ
TPS62672YFDR PREVIEW DSBGA YFD 6 TBD Call TI Call TI -40 to 85
TPS62672YFDT PREVIEW DSBGA YFD 6 TBD Call TI Call TI -40 to 85
TPS62674YFDR ACTIVE DSBGA YFD 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 PN
TPS62674YFDT ACTIVE DSBGA YFD 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 PN
TPS62675YFDR ACTIVE DSBGA YFD 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 OB
TPS62675YFDT ACTIVE DSBGA YFD 6 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 OB
TPS62679ZYFMR ACTIVE DSLGA YFM 6 3000 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 85
TPS62679ZYFMT ACTIVE DSLGA YFM 6 250 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62674YFDR DSBGA YFD 6 3000 180.0 8.4 1.03 1.53 0.56 4.0 8.0 Q1
TPS62674YFDT DSBGA YFD 6 250 180.0 8.4 1.03 1.53 0.56 4.0 8.0 Q1
TPS62679ZYFMR DSLGA YFM 6 3000 180.0 8.4 1.04 1.41 0.21 4.0 8.0 Q1
TPS62679ZYFMT DSLGA YFM 6 250 180.0 8.4 1.04 1.41 0.21 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62674YFDR DSBGA YFD 6 3000 220.0 220.0 34.0
TPS62674YFDT DSBGA YFD 6 250 220.0 220.0 34.0
TPS62679ZYFMR DSLGA YFM 6 3000 210.0 185.0 35.0
TPS62679ZYFMT DSLGA YFM 6 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 2
D: Max =
E: Max =
1.33 mm, Min =
0.956 mm, Min =
1.27 mm
0.896 mm
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