SI4703-D30-GM - Silicon Labs

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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Si4702/03-D30

BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS

Features

Applications

Description

The Si4702/03 integrates the complete tuner function from antenna input

to stereo audio output for FM broadcast radio reception.

Functional Block Diagram

This data sheet applies to

Si4702/03-D Firmware 30 and

greater

Worldwide FM band support

(64–108 MHz)

Digital low-IF receiver

Frequency synthesizer with

integrated VCO

Seek tuning

Automatic frequency control (AFC)

Automatic gain control (AGC)

Excellent overload immunity

Signal strength measuremen t

Programmable de-emphasis

(50/75 µs)

Adaptive noise suppression

Volume control

Line-level analog output

32.768 kHz reference clock

2-wire and 3-wire control

interface

2.7 to 5.5 V supply voltage

Integrated LDO regulator

allows direct connection to

battery

3 x 3 mm 20-pin QFN package

Pb-free/RoHS compliant

RDS/RBDS Processor (Si4703)

Integrated crystal oscillator

Cellular handsets

MP3 players

Portable radios

USB FM radio

PDAs

Notebook PCs

Portable navigation

Consumer ele ctr on ics

VIO

CONTROLLER

ADC

Si4702/03

DSP

FILTER

DEMOD

MPX

AUDIO

SCLK

SDIO

CONTROL

INTERFACE

SEN

DAC

DAC ROUT

LOUT

0 / 90 LOW-IF

RSSI

TUNE

GPIO

AMPLIFIER

GPIO

RST

RFGND LNA

FMIP

AFC

AGC

PGA

RCLK

REG

32.768 kHz

2.7–5.5 V

Headphone

Cable

RDS

(Si4703)

XTAL

OSC

U.S. and International

Patents Pending

Abbreviated U.S. patent list:

7272375, 7127217, 7272373,

7272374, 7321324, 7339503,

7339504, 7355476, 7426376,

7436252, 7471940

Ordering Information:

See page 38.

Pin Assignments

(Top View)

Si4702/03-GM

GND

PAD

GPIO1

RCLK

GND

LOUT

ROUT

RST

GND

SDIO

SCLK

GND

FMIP

RFGND

GPIO2

GPIO3

VIO

SEN

71098 11

17181920 16

Si4702/03-D30

2 Rev. 0.6

Si4702/03-D30

Rev. 0.6 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.3. General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7. Pin Descriptions: Si4702/03-D30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

9.1. Si4702 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

9.2. Si4703 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

10. Package Outline: Si4702/03-D30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

11. PCB Land Pattern: Si4702/03-D30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Si4702/03-D30

4 Rev. 0.6

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Co ndit io n Min Typ Max Unit

Digital Supply Voltage VD 2.7 — 5.5 V

Analog Supply Voltage VA2.7 — 5.5 V

Interface Supply Voltage VIO 1.62 — 3.6 V

Digital Power Supply Power-Up

Rise Time VDRISE 10 — — µs

Analog Power Supply Power-Up

Rise Time VARISE 10 — — µs

Interface Power Supply Power-Up

Rise Time VIORISE 10 — — µs

Ambient Temperature TA–20 25 85 °C

Note: All minimum and maximu m spec ifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at VD = VA = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless

otherwise stated.

Table 2. Absolute Maximum Ratings1,2

Parameter Symbol Value Unit

Digital Supply Voltage VD –0.5 to 5.8 V

Analog Supply Voltage VA–0.5 to 5.8 V

Interface Supply Voltage VIO –0.5 to 3.9 V

Input Current3IIN ±10 mA

Input Voltage3VIN –0.3 to (VIO + 0.3) V

Operating Temperature TOP –40 to 95 °C

Storage Temperature TSTG –55 to 150 °C

RF Input Level40.4 VpK

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functi onal operation

should be restricted to the conditions as specified in th e operational sections of this data sheet. Exposure beyond

recommended operating conditions for exte nded periods may affect device reliability.

2. The Si4702/03-D30 device is a high -performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling

and assembly of this device should only be done at ESD-prote cted workstations.

3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.

4. At RF input pins.

Si4702/03-D30

Rev. 0.6 5

Table 3. DC Characteristics

(VD=V

A = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

FM Receiver to Line Output

VDD Supply Current IFM —15—mA

VDD Supply Current1IFM Low SNR level — 17.7 — mA

VDD RDS Supply Current2IFM —16.7—mA

Supplies and Interface

Interface Supply Current IIO —300—µA

Digital Powerdown Current IDDPD —2.5— µA

Analog Powerdown Current IAPD Enable = 0 — 3.5 — µA

VIO Powerdown Current IIOPD SCLK, RCLK inactive — 2.5 — µA

High Level Input Voltage3VIH 0.7 x VIO —V

IO +0.3 V

Low Level Input Voltage3VIL –0.3 — 0.3 x VIO V

High Level Input Current3IIH VIN =V

IO =3.6V –10 — 10 µA

Low Level Input Current3IIL VIN =0V,

VIO =3.6V –10 — 10 µA

High Level Output Voltage4VOH IOUT =500µA 0.8xV

IO ——V

Low Level Output Voltage4VOL IOUT = –500 µA — — 0.2 x VIO V

Notes:

1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.

2. Guaranteed by characterization.

3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.

4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.

Si4702/03-D30

6 Rev. 0.6

Figure 1. Reset Timing Parameters for Busmode Select Method 1 (GPIO3 = 0)

Table 4. Reset Timing Characteristics (Busmode Select Method 1)1,2,3

Parameter Symbol Test Co ndit io n Min Typ Max Unit

RSTpulse width and GPIO3 Setup

to RSTtGSRST14GPIO3 = 0 100 — — µs

SEN and SDIO Setup to RSTtSRST1 30 — — ns

SEN, SDIO, and GPIO3 Hold from

RSTtHRST1 30 — — ns

Notes:

1. When selecting 2-wire Mode, the user must ensu r e that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

3. When selecting 2-wire mode, the user must ensu r e that SCLK is high during the rising edg e of RST, and stays high

until after the 1st start condition.

4. If GPIO3 is driven low by the user, then minimum tGSRST1 is only 30 ns. If GPIO3 is hi-Z, then minimum tGSRST1 is

100 µs, to provide ti me for an on -ch i p 1 M pulldown device (active whil e RST is low) to discharge the pin.

70%

30%

SEN,

SDIO

70%

30%

GPIO3

70%

30%

tGSRST1

RST

tHRST1

tSRST1

Si4702/03-D30

Rev. 0.6 7

Figure 2. Reset Timing Parameters for Busmode Select Method 2 (GPIO3 = 1)

Table 5. Reset Timing Characteristics (Busmode Select Method 2)1,2,3

Parameter Symbol Test Condition Min Typ Max Unit

GPIO1 and GPIO3 Setup to RSTtSRST2 GPIO3 = 1 30 — — ns

GPIO1 and GPIO3 Hold from RSTtHRST2 30 — — ns

Notes:

1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until

after the 1st start condition.

70%

30%

tSRST2

RST

tHRST2

GPIO3 70%

30%

GPIO1 70%

30%

Si4702/03-D30

8 Rev. 0.6

Figure 3. 3-Wire Control Interface Write Timing Parameters

Table 6. 3-Wire Control Interface Characteristics

(VD=V

A= 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Co ndit io n Min Typ Max Unit

SCLK Frequency fCLK 0—2.5MHz

SCLK High Time tHIGH 25 — — ns

SCLK Low Time tLOW 25 — — ns

SDIO Input, SEN to SCLKSetup tS20 — — ns

SDIO Input to SCLKHold tHSDIO 10 — — ns

SEN Input to SCLKHold tHSEN1 10 — — ns

SEN Input to SCLKHold tHSEN2 10 — — ns

SCLKto SDIO Output Valid tCDV Read 2 — 25 ns

SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns

Note: When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

SCLK 70%

30%

SEN 70%

30%

SDIO A7 A0

70%

30%

tHSDIO tHSEN1

A6-A5,

R/W,

A4-A1

Address In Da ta In

D15 D14-D1 D0

tHIGH tLOW

tHSEN2

Si4702/03-D30

Rev. 0.6 9

Figure 4. 3-Wire Control Interface Read Timing Parameters

½ C ycle Bus

Turnaround

SCLK 70%

30%

SEN 70%

30%

SDIO 80%

20%

tHSDIO tCDV tCDZ

Address In Data Out

A7 A0

A6-A5,

R/W,

A4-A1 D15 D14-D1 D0

tStHSEN1

tHSEN2

Si4702/03-D30

10 Rev. 0.6

Table 7. 2-Wire Control Interface Characteristics1,2,3

(VD=V

A= 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fSCL 0—400kHz

SCLK Low Time tLOW 1.3 — — µs

SCLK High Time tHIGH 0.6 — — µs

SCLK Input to SDIO Setup

(START) tSU:STA 0.6 — — µs

SCLK Input to SDIO Hold (START) tHD:STA 0.6 — — µs

SDIO Input to SCLK Setup tSU:DAT 100 — — ns

SDIO Input to SCLK Hold4,5 tHD:DAT 0—900ns

SCLK input to SDIO Setup (STOP) tSU:STO 0.6 — — µs

STOP to START Time tBUF 1.3 — — µs

SDIO Output Fall Time tf:OUT 20 + 0.1 Cb—250ns

SDIO Input, SCLK Rise/Fall Time tf:IN

tr:IN

20 + 0.1 Cb—300ns

SCLK, SDIO Capacitive Loading Cb——50pF

Input Filter Pulse Suppression tSP — — 50 ns

Notes:

1. When VIO = 0 V, SCLK and SDIO are low impedance.

2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high

until after the 1st start condition.

3. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

4. As a 2-wire transmitter, the Si4702/03 -D30 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to

comply with the 0 ns tHD:DAT specification.

5. The maximum tHD:DAT has only to be met when f SCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be

violated so long as all other timing parameters are met.

Si4702/03-D30

Rev. 0.6 11

Figure 5. 2-Wire Control Interface Read and Write Timing Parameters

Figure 6. 2-Wire Control Interface Read and Write Timing Diagram

SCLK 70%

30%

SDIO 70%

30%

START STARTSTOP

tf:IN

tr:IN

tLOW tHIGH

tHD:STA

tSU:STA tSU:STO

tSP tBUF

tSU:DAT

tr:IN tHD:DAT tf:IN ,

tf:OUT

SCLK

SDIO

START STOPADDRESS + R/W ACK DATA ACK DATA ACK

A6-A0,

R/W D7-D0 D7-D0

Si4702/03-D30

12 Rev. 0.6

Table 8. FM Receiver Characteristics1,2

(VD=V

A= 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C, 76–108 MHz)

Parameter Symbol Test Co ndition Min Typ Max Unit

Input Frequency fRF 64 — 108 MHz

Sensitivity3,4,5,6,7 (S+N)/N = 26 dB — 1.7 3.5 µVEMF

Sensitivity (50  matching

network)3,4,5,6,8 (S+N)/N = 26 dB — 1.1 — µVEMF

RDS Sensitivity8f=2kHz,

RDS BLER < 5% — 15 — µVEMF

LNA Input Resistance8,9 345k

LNA Input Capacitance8,9 456pF

Input IP38,10 103 108 — dBµVEMF

AM Suppression3,4,5,8,9 m = 0.3 40 55 — dB

Adjacent Channel Selectivity ±200 kHz 35 50 — dB

Alternate Channel Selectivity ±400 k Hz 60 70 — dB

Spurious Response Rejection8In-band 35 — — dB

RCLK Frequency8— 32.768 — kHz

RCLK Frequency Tolerance8,11 Frequency S p acing = 100

or 200 kHz –200 — 200 ppm

Frequency

Spacing = 50 kHz –50 — 50

Audio Output Voltage3,4,5,9 72 80 90 mVRMS

Audio Output L/R Imbalance3,4,9,12 —— 1 dB

Audio Frequency Response Low8–3 dB — — 30 Hz

Audio Frequency Response High8–3 dB 15 — — kHz

Notes:

1. Additional testing information is available in "AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure".

Volume = maximum for all tests.

2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN383: Si47xx

Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for

qualified customers.

3. FMOD = 1 kHz, 75 µs de-emphasis

4. MONO = 1, and L = R unless noted otherwise.

5. f = 22.5 kHz.

6. BAF = 300 Hz to 15 kHz, A-weighted.

7. Typical sensitivity with headphone matching network.

8. Guaranteed by characterization.

9. VEMF =1mV.

10. |f2 – f1| > 1 MHz, f0=2xf

1 – f2. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page 23.

11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 23. Seek/Tune

timing is guaranteed for 100 and 200 kHz channel spacing.

12. f = 75 kHz.

13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 23.

14. RDS high-performance mode enabled RDSPRF 06h[9] = 1. Refer to 6. "Register Descriptions" on page 23.

15. At LOUT and ROUT pins.

16. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powe rup

time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is

complete. See "AN230: Si4700/01/02/03 Programming Guide" for more information.

17. Minimum and maximum at room temperature (25 °C).

Si4702/03-D30

Rev. 0.6 13

Audio Stereo Separation3,9,12 25 — — dB

Mono/Stereo Switching Level3,8,12 BLNDADJ = 10

10 dB stereo separation —34—dBµVEMF

Audio Mono S/N3,4,5,6,9 58 63 — dB

Audio Stereo S/N3,5,6,8,14 BLNDADJ = 10 — 58 — dB

Audio THD3,4,9,12 —0.10.5 %

De-emphasis Time Constant8,13 DE = 0 70 75 80 µs

DE = 1 45 50 54 µs

Audio Common Mode Voltage15 ENABLE = 1 0.65 0.8 0.9 V

Audio Common Mode Voltage15 ENABLE = 0

AHIZEN = 1 —0.5xV

IO —V

Audio Output Load Resistance8,15 RLSingle-ended 10 — — k

Audio Output Load Capacitance8,15 CLSingle-ended — — 50 pF

Seek/Tune Tim e 8,11 SPACE[1:0] = 0x, RCLK

tolerance = 200 ppm,

(x = 0 or 1)

——60ms/

channel

Powerup Time8,16 From powerdow n

(Write ENABLE bit to 1) ——110ms

RSSI Offset17 Input levels of 8 and

60 dBµV at RF input –3 — 3 dB

Table 8. FM Receiver Characteristics1,2 (Continued)

(VD=V

A= 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C, 76–108 MHz)

Parameter Symbol Test Co ndition Min Typ Max Unit

Notes:

1. Additional testing information is available in "AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure".

Volume = maximum for all tests.

2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN383: Si47xx

Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for

qualified customers.

3. FMOD = 1 kHz, 75 µs de-emphasis

4. MONO = 1, and L = R unless noted otherwise.

5. f = 22.5 kHz.

6. BAF = 300 Hz to 15 kHz, A-weighted.

7. Typical sensitivity with headphone matching network.

8. Guaranteed by characterization.

9. VEMF =1mV.

10. |f2 – f1| > 1 MHz, f0=2xf

1 – f2. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page 23.

11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 23. Seek/Tune

timing is guaranteed for 100 and 200 kHz channel spacing.

12. f = 75 kHz.

13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 23.

14. RDS high-performance mode enabled RDSPRF 06h[9] = 1. Refer to 6. "Register Descriptions" on page 23.

15. At LOUT and ROUT pins.

16. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powe rup

time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is

complete. See "AN230: Si4700/01/02/03 Programming Guide" for more information.

17. Minimum and maximum at room temperature (25 °C).

Si4702/03-D30

14 Rev. 0.6

2. Typical Application Schematic

Notes:

1. Place C1 close to VD pin.

2. All grounds connect directly to GND plane on PCB.

3. Pins 1 and 20 are no connects, leave floatin g.

4. Important Note: FM Receiver performance should adhere to the design guideli nes described in “AN383: Si47xx

Antenna, Schematic, Layout, and Design Guidelines.” Failure to use these guidelines will negatively affect the

performance of the Si4702/03-D30, particularly in weak signal and noisy environments. Silicon Laboratories will evaluate

schematics and layouts for qualified customers.

5. Pin 2 connects to the antenna interface. Refer to AN383.

6. Place Si4702/03-D30 as close as possible to antenna jack and keep the FMIP trace as short as possible.

7. Refer to Si4702/03 Internal Crystal Oscillator Errata.

8. Refer to "AN299: External 32.768 kHz Crystal Oscillator”

3. Bill of Materials

Component(s) Value/Description Supplier(s)

C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata

U1 Si4702/03-D30 FM Radio Tuner Silicon Laboratories

C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional: for

crystal oscillator option) Venkel

X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson

FMIP

RFGND

GND

RST

GND

LOUT

ROUT

GND

GPIO1

GPIO2

GPIO3

SEN

SCLK

SDIO

RCLK

VIO

SEN

SCLK

SDIO

RST

RCLK

GND

PAD

LOUT

ROUT

VBATTERY

2.7 to 5.5 V

GPIO1

GPIO2

GPIO3

VIO

1.62 to 3.6 V

FMIP

RFGND

C2 C3

X1 RCLK

GPIO3

Optional: for crystal oscillator op ti on

Si4702/03-D30

Rev. 0.6 15

4. Functional Description

Figure 7. Si4702/03-D30 FM Receiver Block Diagram

4.1. Overview

The Si4702/03-D30 extends Silicon Laboratories

Si4700/01 FM tuner family, and further increases the

ease and attractiveness of adding FM radio reception to

mobile devices through small size and board area,

minimum component count, flexible programmability,

and superior, proven performance. Si4702/03-D30

software is backwards compatible to existing Si4700/01

and Si4702/03-B16 FM Tuner designs. The

Si4702/03-D30 benefits from proven digital integration

and 100% CMOS process technology, resulting in a

completely integrated solution. It is the industry's

smallest footprint FM tuner IC requiring only 10 mm2

board space and one ex te rn al by pass capacitor.

The device offers significant programmability, and

caters to the subjective nature of FM listeners and

variable FM broadcast environments world-wide

through a simplified programming interface and mature

functionality.

The Si4703-D30 incorporates a digital processor for the

European R adio Data System (R DS) and the U S Radio

Broadcast Data System (RBDS) including all required

symbol decoding, block synchronization, error

detection, and error correction functions.

RDS enables data such as station identification and

song name to be displaye d to the use r. The Si4703-D30

offers a detailed RDS view and a standard view,

allowing adopters to selectively choose granularity of

RDS status, data, and block errors. Si4703-D30

software is backwards compatible to the proven Si4701,

adopted by leading cell-phone and MP3 manufacturers

world-wide.

The Si4702/03-D30 is based on the superior, proven

performance of Silicon Laboratories' Si4700/01

architecture offering unmatched interference rejection

and leading sensitivity. The device uses the same

programming interface as the Si4701 and supports

multiple bus-modes. Power management is also

simplified with an integrated regulator allowing direct

connection to a 2.7 to 5.5 V battery.

The Si4702/03-D30 device’s high level of integration

and complete FM system production testing increases

quality to manufacturers, improves device yields, and

simplifies device manufacturing and final te sting.

4.2. FM Receiver

The Si4702/03-D30’s patented digital low-IF

architecture reduces external components and

eliminates the nee d for factory ad justment s. The re ceive

(RX) section integrates a low noise amplifier (LNA)

supporting the worldwide FM broadcast band (64 to

108 MHz). An automatic gain control (AGC) circuit

controls the gain of the LNA to optimize sensitivity and

rejection of strong interferers. For testing purposes, the

AGC can be disabled with the AGCD bit. Refer to

Section 6. "Register Descriptions" on page 23 for

additional programming and configuration info rmation.

The Si4702/03-D30 architecture and antenna design

increases system performance. To ensure proper

performance and operation, designers should refer to

the guidelines in "AN383: Si47xx Antenna, Schematic,

VIO

CONTROLLER

ADC

Si4702/03

DSP

FILTER

DEMOD

MPX

AUDIO

SCLK

SDIO

CONTROL

INTERFACE

SEN

DAC

DAC ROUT

LOUT

0 / 90 LOW-IF

RSSI

TUNE

GPIO

AMPLIFIER

GPIO

RST

RFGND LNA

FMIP

AFC

AGC

PGA

RCLK

REG

32.768 kHz

2.7 - 5.5 V

Headphone

Cable

RDS

(Si4703)

XTAL

OSC

Si4702/03-D30

16 Rev. 0.6

Layout, and Design Guidelines". Conformance to these

guidelines will help to ensure excellent performance

even in weak signal or noisy environments.

An image-reject mixer downconverts the RF signal to

low-IF. The quadrature mixer output is amplified,

filtered, and digitized with high resolution

analog-to-digital converters (ADCs). This advanced

architecture achieves superior performance by using

digital signal processing (DSP) to perform channel

selection, FM demodulation, and stereo audio

processing compared to traditional analog

architectures.

4.3. General Purpose I/O Pins

The pins GPIO1–3 can serve multiple functions. GPIO1

and GPIO3 can be used to select between 2-wire and

3-wire modes for the control interface as the device is

brought out of reset. See Section “4.9. Reset, Powerup,

and Powerdown”. After powerup of the device, the

GPIO1–3 pins can be used as general purpose

inputs/outputs, and the GPIO2–3 pins can be used as

interrupt request pins for the seek/tune or RDS ready

functions and as a stereo/mono indicator respectively.

See register 04h, bits [5:0] in Section “6. Register

Descriptions” for information on the control of these

pins. It is recommended that the GPIO2–3 pins not be

used as interrupt request outputs until the powerup time

has completed (see Section “4.9. Reset, Powerup, and

Powerdown”). The GPIO3 pin has an internal, 1 M,

±15% pull-down resistor that is only active while RST is

low. General purpose input/output functionality is

available regardless of the state of the VA and VD

supplies, or the ENABLE and DISABLE bits.

4.4. RDS/RBDS Processor and

Functionality

The Si4703 implements an RDS/RBDS* processor for

symbol decoding, block synchronization, error

detection, and error correction. RDS functionality is

enabled by setting the RDS bit. The device offers two

RDS modes, a standard mode and a verbose mode.

The primary difference is increased visibility to RDS

block-error levels and synchronization status with

verbose mod e.

Setting the RDS mode (RDSM) bit low places the

device in standard RDS mode (default). The device will

set the RDS ready (RDSR) bit for a minimum of 40 ms

when a valid RDS group has been re ceived . Set ting t he

RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 01

will configure GPIO2 to pulse low for a minimum of 5 ms

when a valid RDS group has been received. If an invalid

group is received, RDSR will not be set and GPIO2 will

not pulse low. In standard mode RDS synchronization

(RDSS) and block error rate A, B, C and D (BLERA,

BLERB, BLERC, and BLERD) are unused and will read

0. This mode is backward compatible with earlier

firmware revisions.

Setting the RDS mode bit high places the device in RDS

verbose mode. The device sets RDSS high when

synchronized and low when synchronization is lost. If

the device is synchronized, RDS ready (RDSR) will be

set for a minimum of 40 ms when a RDS group has

been received. Setting the RDS interrupt enable

(RDSIEN) bit and GPIO2[1:0] = 01 will configure GPIO2

to pulse low for a minimum of 5 ms if the device is

synchronized and an RDS group has been received.

BLERA, BLERB, BLERC and BLERD provide

block-error levels for the R DS group. Th e number of b it

errors in each block within the group is encoded as

follows: 00 = no errors, 01 = one to two errors,

10 = three to five errors, 11 = six or more errors. Six or

more errors in a block indicate the block is

uncorrectable and should not be used.

*Note: RDS/RBDS is referred to only as RDS throughout the

remainder of this document.

4.5. Stereo Audio Processing

The output of the FM demodulator is a stereo

multiplexed (MPX) signal. The MPX standard was

developed in 1961 and is used worldwide. Today's MPX

signal format consists of left + right (L+R) audio, left –

right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS

data as shown in Figure 8.

Figure 8. MPX Signal Spectrum

The Si4702/03-D30's integrated stereo decoder

automatically decodes the MPX signal. The 0 to 15 kHz

(L+R) sign al is the mon o output of the FM tune r. Stere o

is generated from the (L+R), (L-R), and a 19 kHz pilot

tone. The pilot tone is used as a reference to recover

the (L-R) signal. Separate left and right channels are

obtained by adding and subtracting the (L+R) and (L-R)

signals, respectively. The Si4703-D30 uses frequency

information from the 19 kHz stereo pilot to recover the

57 kHz RDS/RBDS signal.

Adaptive noise suppression is employed to gradually

0575338231915 Frequency (kHz)

Modula t ion Level

Stereo Audio

Le ft - Rig h t RDS/

RBDS

Mono A ud io

Le ft + Righ t Stereo

Pilot

Si4702/03-D30

Rev. 0.6 17

combine the stereo left and right audio channels to a

mono (L+R) audio signal as the signal quality degrades

to maintain optimum sound fidelity under varying

reception conditions. The signal level range over which

the stereo to mono blending occurs can be adjusted by

setting the BLNDADJ[1:0] register. Stereo/mono status

can be monitored with the ST register bit and mono

operation can be forced with the MONO register bit.

Pre-emphasis and de-emphasis is a technique used by

FM broadcasters to improve the signal-to-noise ratio of

FM receivers by reducing the effects of high frequency

interference and noise. When the FM signal is

transmitted, a pre-emphasis filter is applied to

accentuate the high audio frequencies. All FM receivers

incorporate a de-emphasis filter which attenuates high

frequencies to restore a flat frequency response. Two

time constants, 50 or 75 µs, are used in various regions.

The de-emphasis time constant is programmable with

the DE bit.

High-fidelity stereo digital-to-analog converters (DACs)

drive analog audio signals onto the LOUT and ROUT

pins. The audio output may be muted with the DMUTE

bit. Volume can be adjusted digitally with the

VOLUME[3:0] bits. The volume dynamic range can be

set to either –28 dBFS (default) or –58 d BFS by setting

VOLEXT=1.

The sof t mute feature is available to attenuate the audio

outputs and minimize audible noise in weak signal

conditions. The soft mute atta ck and decay rate can be

adjusted with the SMUTER[1:0] bits where 00 is the

fastest setting. The soft mute attenuation level can be

adjusted with the SMUTEA[1:0] bits where 00 is the

most attenuated. The soft mute disable (DSMUTE) bit

may be set high to disable this feature.

4.6. Tuning

The Si4702/03-D30 uses Silicon Laboratories’ patented

and proven frequency synthesizer technology including

a completely integrated VCO. The VCO frequency is

locked to the reference clock and adjusted with an

automatic frequency control (AFC) servo loop during

reception.

The tuning frequency is defined as:

Channel spacings of 50, 100 or 200 kHz are selected

using bits SPACE[1:0]. The channel is selected with bits

CHAN[9:0]. Band selection for Japan, Japan wideband,

or Europe/U.S./Asia is set with BAND[1:0]. The tuning

operation begins by setting the TUNE bit. After tuning

completes, the seek/tune complete (STC) bit will be set

and the RSSI level is available by reading bits

RSSI[7:0]. The TUNE bit must be set low after the STC

bit is set high in order to complete the tune operation

and clear the STC bit.

Seek tuning searches up or down for a channel with an

RSSI greater than or equal to the seek threshold set

with the SEEKTH[7:0] bits. In addition, optional SNR

and/or impulse noise detector criteria may be used to

qualify valid stations. The SKSNR[3:0] bits set the SNR

threshold require d. The SKCNT[3:0] bit s set the impulse

noise threshold. Using the extra seek qualifiers can

reduce false stops and, in combination with lowering the

RSSI seek threshold, increase the number of found

stations. The SNR and impulse noise detectors are

disabled by default for backwards compatibility.

Two seek modes are available. When the seek mode

(SKMODE) bit is low and a seek is initiated, the device

seeks through the band, wraps from one band edge to

the other, and continues seeking. If the seek operation

is unable to find a valid channel, the seek failure/band

limit (SF/BL) bit is set high and the device returns to the

channel selected before the seek operation began.

When the SKMODE bit is high and a seek is initiated,

the device seeks through the band until the band limit is

reached and the SF/BL bit is set high. A seek operation

is initiated by setting the SEEK and SEEKUP bits. After

the seek operation completes, the STC bit is set, and

the RSSI level and tuned channel are available by

reading bit s RSSI[7:0] and bits READCHAN[9:0]. During

a seek operation READCHAN[9:0] is also updated and

may be read to determine and report seek progress.

The STC bit is set after the seek operation completes.

The channel is valid if the seek operatio n completes and

the SF/BL bit is set low. At other times, such as before a

seek operation or after a seek completes and the SF/BL

bit is set high, the channel is valid if the AFC Rail

(AFCRL) bit is set low and the value of RSSI[7:0] is

greater than or equal to SEEKTH[7:0]. Note that if a

valid channel is found but the AFCRL bit is set, the

audio output is muted as in th e sof tmute case discussed

in Section “4.5. Stereo Audio Processing”. The SEEK bit

must be set low after the STC bit is set high in order to

complete the seek operation. Setting the STC bit low

clears STC status and SF/BL bits. The seek operation

may be aborted by setting the SEEK bit low at any time.

The device can be configured to generate an interrupt

on GPIO2 when a tune or seek operation completes.

Setting the seek/tune complete (STCIEN) bit and

GPIO2[1:0] = 01 will configure GPIO2 for a 5 ms low

interrupt when the STC bit is set by the device.

For additional recommendations on optimizing the seek

function, consult "AN230: Si4700/01/02/03

Programming Guide."

Freq (MHz) Spacing (kHz) Channel Bottom of Band (MHz)+=

Si4702/03-D30

18 Rev. 0.6

4.7. Reference Clock

The Si4702/03-D30 accepts a 32.768 kHz reference

clock to the RCLK pin. The reference clock is required

whenever the ENABLE bit is set high. Refer to Table 3,

“DC Characteristics,” on page 5 for input switching

voltage levels and Table 8, "FM Receiver

Characteristics," on page 12 for frequency tolerance

information.

An onboard crystal oscillator is available to generate the

32.768 kHz reference when an external crystal and load

capacitors are provided. Refer to 2. "Typical Application

Schematic" on page 14. The oscillator must be enabled

or disabled while in po werdown (ENABLE = 0) as shown

in Figure 9, “Initialization Sequence,” on page 21.

while in powerdown. Note that RCLK voltage levels are

not specified. The typical RCLK voltage level, when the

crystal oscillator is used, is 0.3 V

pk-pk

4.7.1. Si4702/03-D30 Internal Crystal Oscillator

Errata

The Si4702/03-D30 seek/tune performance may be

affected by data activity on the SDIO bus when using

the integrated internal oscillator. SDIO activity results

from polling the tuner for status or communicating with

other devices that share the SDIO bus. If there is SDIO

bus activity while the Si4702/03-D30 is performing the

seek/tune function, the cryst al oscil lator ma y experie nce

jitter, which may result in mistunes and/or false stops.

SDIO activity during all other operational states does

not affect performance.

For best seek/tune results, Silicon Laboratories

recommends that all SDIO data traffic be suspended

during Si4702/03-D30 seek and tune operations. This is

achieved by keeping the bus quiet for all other devices

on the bus, and delaying tuner polling until the tune or

seek operation is complete. The STC (seek/tune

complete) interrupt should be used instead of polling to

determine when a seek/tune operation is complete.

Please refer to Sections 4.6. "Tuning" on page 17 and 5.

"Register Summary" on page 22 for specified seek/tune

times and register use guidelines.

The layout guidelines in Si4700/01/02/03 Evaluation

Board User’s Guide, Section 8.3 Si4702/03-D30

Daughter Card should be follo wed to help en sure robust

FM performance.

Please refer to the posted Si4702/03 Internal Crystal

Oscillator Errata for more information.

4.8. Control Interface

Two-wire slave-transceiver and three-wire interfaces

are provided for the controller IC to read and write the

control registers. Refer to “4.9. Reset, Powerup, and

Powerdown” for a description of bus mode selection.

Registers may be written and read when the VIO supply

is applied regardless of the state of the VD or VA

supplies. RCLK is not required for proper register

operation.

4.8.1. 3-Wire Control Interface

For three-wire operation, a transfer begins when the

SEN pin is sampled low by the device on a rising SCLK

edge. The control word is latched internally on rising

SCLK edges and is nine bits in length, comprised of a

four bit chip address A7:A4 = 0110b, a read/write bit

(write = 0 and read = 1), and a four bit register address,

A3:A0. The ordering of the control word is A7:A5, R/W,

A4:A0. Refer to Section 5. "Register Summary" on page

22 for a list of all registers and their addresses.

For write operations, the serial control word is followed

by a 16-bit data word and is latched internally on rising

SCLK edges.

For read operations, a bus turn-around of half a cycle is

followed by a 16-bit data word shifted out on rising

SCLK edges and is clocked into the system controller

on falling SCLK edges. The transfer ends on the rising

SCLK edge after SEN is set high. Note that 26 SCLK

cycles are required for a transfer, however, SCLK may

run continuously.

For details on timing specifications and diagrams, refer

to Table 6, “3-Wire Control Interface Characteristics,” on

page 8, Figure 3, “3-Wire Control Interface Write Timing

Parameters,” on page 8, and Figure 4, “3-Wire Control

Interface Read Timing Parameters,” on page 9.

Si4702/03-D30

Rev. 0.6 19

4.8.2. 2-wire Control Interface

For two-wire operation, the SCLK and SDIO pins

function in open-drain mode (pull-down only) and must

be pulled up by an external device. A transfer begins

with the START condition (falling edge of SDIO while

SCLK is high). The control wo rd is latched internally on

rising SCLK edges and is eight bits in length, comprised

of a seven bit device address equal to 0010000b and a

read/write bit (write = 0 and re ad = 1).

The device acknowledges the address by driving SDIO

low after the next falling SCLK edge, for 1 cycle. For

write operation s, the de vice acknowledge is followed by

an eight bit data word latched internally on rising edges

of SCLK. The device acknowledges each byte of data

written by driving SDIO low after the next falling SCLK

edge, for 1 cycle. An internal address counter

automatically increments to allow continuous data byte

writes, starting with the upper byte of register 02h,

followed by the lower byte of register 02h, and onward

until the lower byte of the last register is reached. The

internal address counter then automatically wraps

around to the upper byte of register 00h and proceeds

from there until continuous writes end. Data transfer

ends with the STOP condition (rising edge of SDIO

while SCLK is high). After every STOP condition, the

internal address counter is reset.

For read operations, the device acknowledge is

followed by an eight bit data word shifted out on falling

SCLK edges. An internal address counter automatically

increments to allow continuous data byte reads, starting

with the upper byte of register 0Ah, followed by the

lower byte of register 0Ah, and onward until the lower

byte of the last register is reached. The internal address

counter then automatically wraps around to the upper

byte of register 00h and proceeds from there until

continuous reads cease. After each byte of dat a is read,

the controller IC must drive an acknowledge (SDIO = 0)

if an additional byte of data will be requested. Data

transfer ends with the STOP condition. After every

STOP condition, the inte rnal address counter is reset.

For details on timing specifications and diagrams, refer

to Table 7, “2-Wire Control Interface

Characteristics1,2,3,” on page 10, Figure 5, “2-Wire

Control Interface Read and Write Timing Parameters,”

on page 11 and Figure 6, “2-Wire Control Interface

Read and Write Timing Diagram,” on page 11.

4.9. Reset, Powerup, and Powerdown

Driving the RST pin low will disable the Si4702/03-D30

and its control bus interface, and reset the registers to

their default settings. Driving the RST pin high will bring

the device out of reset. As the device is brought out of

reset, it will sample the state of several pins to select

between 2-wire and 3-wire control interface operation,

using one of two busmode selection methods.

Busmode selection method 1 requires the use of the

GPIO3, SEN, and SDIO pins. To use this busmode

selection method, the GPIO3 and SDIO pins must be

sampled low by the device on the rising edge of RST.

The user may either drive the GPIO3 pin low externally,

or leave the pin floating. If the pin is not driven by the

user, it will be pulled low by an internal 1 M resistor

which is active only while RST is low. The user must

drive the SEN and SDIO pins externally to the proper

state.

To select 2-wire operation, the SEN pin must be

sampled high by the device on the rising edge of RST.

To select 3-wire operation, the SEN pin must be

sampled low by the device on the rising edge of RST.

Refer to Table 4, “Reset Timing Characteristics

(Busmode Select Method 1)1,2,3,” on page 6 and

Figure 1, “Reset Timing Parameters for Busmode

Select Method 1 (GPIO3 = 0),” on page 6.

Busmode selection method 2 requires only the use of

the GPIO3 and GPIO1 pins. This is the recommended

busmode selection method when not using the internal

crystal oscillator. To use this busmode selection

method, the GPIO3 pin must be sampled high on the

rising edge of RST. The user must drive the GPIO3 pin

high externally, or pull it up with a resistor of 100 k or

less. The user must also drive the GPIO1 pin externally

to the proper state.

To select 2-wire operation, the GPIO1 pin must be

sampled high by the device on the rising edge of RST.

To select 3-wire operation, the GPIO1 pin must be

sampled low by the device on the rising edge of RST.

Refer to Table 5, “Reset Timing Characteristics

(Busmode Select Method 2)1,2,3,” on page 7 and

Figure 2, “Reset Timing Parameters for Busmode

Select Method 2 (GPIO3 = 1),” on page 7.

Table 9 summarizes the two bus selection methods.

Si4702/03-D30

20 Rev. 0.6

When proper voltages are applied to the

Si4702/03-D30, the ENABLE and DISABLE bits in

and powerdow n modes. When voltage is firs t applied to

the device, ENABLE = 0 and DISABLE = 0. Setting

ENABLE = 1 and DISABLE = 0 puts the device in

powerup mode. To power do wn the device, d isable RDS

to prevent any unpredictable behavior (Si4703 only),

then write ENABLE and DISABLE bits to 1.

After being written to 1, both bits will be cleared as part

of the internal device powerdown sequence. To put the

device back into powerup mode, set ENABLE = 1 and

DISABLE = 0 as described above. The ENABLE bit

should never be written to a 0.

4.10. Audio Output Summation

The audio outputs LOUT and ROUT may be

capacitively summed with another device. Setting the

audio high-Z enable (AHIZEN) bit maintains a dc bias of

0.5 x VIO on the LOUT and ROUT pins to prevent the

ESD diodes from clamping to the VIO or GND rail in

response to the output swing of the other device. The

bias point is set with a 370 k resistor to VIO and GND.

written during the powerup sequence and only takes

effect when in powerdown and VIO is supplied. In

powerup the LOUT and ROUT pins are set to the

common mode voltage specified in Table 8, “FM

Receiver Characteristics1,2,” on page 12, regardless of

the state of AHIZEN. Bits 13:0 of register 07h must be

preserved as 0x0100 while in powerdown and as

0x3C04 while in powerup.

4.11. Initialization Sequence

Refer to Figure 9, “Initialization S equence,” on pa ge 21.

To initialize the device:

1. Supply VA and VD.

2. Supply VIO while keeping t he R ST pin low. Note that st eps

1 and 2 may be reversed. Power supplies may be

sequenced in any order.

3. Select 2-wire or 3-wire control interface bus mode

operation as described in Section 4.9. "Reset, Powerup,

and Powerdown" on page 19.

4. Provide RCLK. S teps 3 and 4 may be reversed when using

an external oscillator. Wait 500 ms for oscillator startup

when using internal oscillator.

5. Set the ENABLE bit high and the DISABLE bit low to

powerup the device. Software should wait for the power up

time (as specified by Table 8, “FM Receiver

Characteristics1,2,” on page 12) before continuing with

normal part operation.

To power down the device:

1. (Optional) Set the AHIZEN bit high to maintain a dc bias of

0.5 x VIO volts at the LOUT and ROUT pins while in

powerdown, but preserve the states of the other bits in

pins are set to the common mode voltage specified in

Tabl e 8 on page 12, regardless of the state of AHIZEN.

2. Set the ENABLE bit high and the DISABLE bit high to

place the device in powerdown mode. Note that all register

states are maintained so long as VIO is supplied and the

RST pin is high.

3. (Optional) Remove RCLK.

4. Remove VA and VD supplies as needed.

To power up the device (after power down):

1. Note that VIO is still supplied in this scenario. If VIO is not

supplied, refer to device initialization procedure above.

2. (Optional) Set the AHI ZEN bit lo w to disabl e the dc bia s of

0.5 x VIO volts at the LOUT and ROUT pins, but preserve

the states of the other bits in Register 07h. Note that in

powerup the LOUT and ROUT pins are set to the common

mode voltage specified in Table 8 on page 12, regardless

of the state of AHIZEN.

3. Supply VA and VD.

4. Provide RCLK. Wait 500 ms for oscillator startup when

using internal oscillator.

5. Set the ENABLE bit high and the DISABLE bit low to

powerup the devi ce.

Table 9. Selecting 2-Wire or 3-Wire Control

Interface Busmode Operation1,2,3

Busmode

Select Method SEN SDIO GPIO1 GPIO32Bus

mode

1 0 0 X 043-wire

1 1 0 X 042-wire

Xtal Oscillator 0 0 X 053-wire

Xtal Oscillator 1 0 X 052-wire

2 X X 0 163-wire

2 X X 1 162-wire

Xtal Oscillator NA NA NA NA NA

Notes:

1. All parameters applied on rising edge of RST.

2. When selecting 2-wire mode, the user must ensure that SCLK is hig h

during the rising edge of RST, and stays high until the 1st start

condition.

3. GPIO3 is internally pulled down with a 1 M resistor.

4. GPIO3 should be externally driven low , set to high-Z (10 M or greater

pull-up) or float.

5. GPIO3 should be left floating.

6. GPIO3 should be externally driven high (100 kor smaller pull-up).

Si4702/03-D30

Rev. 0.6 21

Figure 9. Initialization Sequence

4.12. Programming Guide

Refer to "AN230: Si4700/01/02/03 Progr amming Guide"

for control interface programming information.

VA,VD Supp ly

RCLK Pin

ENABLE Bit

12345

RST Pin

VIO Supply

Si4702/03-D30

22 Rev. 0.6

5. Register Summary

Reg1Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

00h DEVICEID PN[3:0] MFGID[11:0]

01h CHIPID REV[5:0] DEV[3:0] FIRMWARE[5:0]

02h POWERCFG DSMUTE DMUTE MONO 0 RDSM2SKMODE SEEKUP SEEK 0 DISABLE 0 0 0 0 0 ENABLE

03h CHANNEL TUNE 0 0 0 0 0 CHAN[9:0]

04h SYSCONFIG1 RDSIEN2STCIEN 0 RDS2DE AGCD 0 0 BLNDADJ[1:0] GPIO3[1:0] GPIO2[1:0] GPIO1[1:0]

05h SYSCONFIG2 SEEKTH[7:0] BAND[1:0] SPACE[1:0] VOLUME[3:0]

06h SYSCONFIG3 SMUTER[1:0] SMUTEA[1:0] 0 0 0 VOLEXT SKSNR[3:0] SKCNT[3:0]

07h TEST1 XOSCEN AHIZEN

08h TEST2

09h BOOTCONFIG

0Ah STATUSRSSI RDSR2STC SF/BL AFCRL RDSS2,3 BLERA[1:0]2,3 ST RSSI[7:0]

0Bh READCHAN BLERB[1:0]2,3 BLERC[1:0]2,3 BLERD[1:0]2,3 READCHAN[9:0]

0Ch RDSA RDSA[15:0]2

0Dh RDSB RDSB[15:0]2

0Eh RDSC RDSC[15:0]2

0Fh RDSD RDSD[15:0]2

Notes:

1. Any register not listed is reserved and should not be written. Writing to reserved registers may result in unpredictable behavior.

2. Si4703 only.

3. Available in RDS verbose mode only.

Si4702/03-D30

Rev. 0.6 23

6. Register Descriptions

Reset value = 0x1242

Si4702-D30 Reset value = 0x1400 before powerup

Si4702-D30 Reset value = 0x145E after powerup

Si4703-D30 Reset value = 0x1600 before powerup

Si4703-D30 Reset value = 0x165E after powerup

BitD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name PN[3:0] MFGID[11:0]

Type RR

Bit Name Function

15:12 PN[3:0] Part Number.

0x01 = Si4702/03

11:0 MFGID[11:0] Manufacturer ID.

0x242

BitD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name REV[5:0] DEV[3:0] FIRMWARE[5:0]

Type RRR

Bit Name Function

15:10 REV[5:0] Chip Version.

0x05 = Rev D

9:6 DEV[3:0] Device.

Si4702:

0000 before powerup

0001 after powerup

Si4703:

1000 before powerup

1001 after powerup

5:0 FIRMWARE[5:0] Firmware Version.

0 before powerup.

Firmware version after powerup = 011110.

Si4702/03-D30

24 Rev. 0.6

Reset value = 0x0000

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Name DSMUTE DMUTE MONO 0 RDSM SKMODE SEEKUP SEEK 0 DISABLE 00000ENABLE

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

15 DSMUTE Softmute Disable.

0 = Softmute enable (default).

1 = Softmute disable.

14 DMUTE Mute Disable.

0 = Mute enable (default).

1 = Mut e disa bl e.

13 MONO Mono Select.

0 = Stereo (default).

1 = Force mono.

12 Reserved Reserved.

Always write to 0.

11 RDSM RDS Mode.

0 = Standard (default).

1 = Verbose.

Refer to “4.4. RDS/RBDS Processor and Functionality”.

10 SKMODE Seek Mode.

0 = Wrap at the upper or lower band limit and continue seeking (default).

1 = Stop seeking at the upper or lower band limit.

9 SEEKUP Seek Direction.

0 = Seek down (default).

1 = Seek up.

8 SEEK Seek.

0 = Disab le (d ef au lt) .

1=Enable.

Notes:

1. Seek begins at the current channel, and goes in the direction specified with the SEEKUP

bit. Seek operation stops when a channel is qualified as valid according to the seek

parameters, the entire band has been searched (SKMODE = 0), or the upper or lower

band limit has been reached (SKMODE = 1).

2. The STC bit is set high when the seek opera tion completes and/or the SF/BL bit is set

high if the seek operation was unable to find a channel qualified as valid according to the

seek parameters. The STC and SF/BL bits must be set low by setting the SEEK bit low

before the next seek or tune may begin.

3. Seek performance for 50 kHz channel spacing varies according to RCLK tolerance.

Silicon Laboratories recommends ±50 ppm RCLK crystal tolerance for 50 kHz seek

performance.

4. A seek operation may be aborted by setting SEEK = 0.

Si4702/03-D30

Rev. 0.6 25

Reset value = 0x0000

7 Reserved Reserved.

Always write to 0.

6 DISABLE Powerup Disable.

Refer to “4.9. Reset, Powerup, and Powerdown”.

Default = 0.

5:1 Reserved Reserved.

Always write to 0.

0 ENABLE Powerup Enable.

Refer to “4.9. Reset, Powerup, and Powerdown”.

Default = 0.

Bit D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name TUNE 0 0 0 0 0 CHAN[9:0]

Type R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

15 TUNE Tune.

0 = Disable (default).

1=Enable.

The tune operation begins when the TUNE bit is set high. The STC bit is set high

when the tune operation completes. The STC bit must be set low by setting the TUNE

bit low before the next tune or seek may begin.

14:10 Reserved Reserved.

Always write to 0.

9:0 CHAN[9:0] Channel Select.

Channel value for tune operation.

If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz.

If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then

Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.

If BAND 05h[7:6] = 11, then freq (MHz) = spacing (MHz) x channel + 64 MHz.

CHAN[9:0] is not updated during a seek operation. READCHAN[9:0] provides the

current tune d ch an nel an d is upd a te d durin g a se ek op e ra tio n an d af te r a see k or

tune operation completes. Channel spacing is set with the bits SPACE 05h[5:4].

Bit Name Function

Si4702/03-D30

26 Rev. 0.6

Reset value = 0x0000

Bit D15 D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name RDSIEN STCIEN 0 RDS DE AGCD 0 0 BLNDADJ[1:0] GPIO3[1:0] GPIO2[1:0] GPIO1[1:0]

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

15 RDSIEN RDS Interrupt Enable.

0 = Disable Interrupt (default).

1 = Enable Interrupt.

Setting RDSIEN = 1 and GPIO2[1:0] = 01 will generate a 5 ms low pulse on GPIO2 when

the RDSR 0Ah[15] bit is set.

14 STCIEN Seek/Tune Complete Interrupt Enable.

0 = Disable Interrupt (default).

1 = Enable Interrupt.

Setting STCIEN = 1 and GPIO2[1:0] = 01 will generate a 5 ms low pulse on GPIO2 when

the STC 0Ah[14] bit is set.

13 Reserved Reserved.

Always write to 0.

12 RDS RDS Enable.

0 = Disable (default).

1 = Enable.

11 DE De-emphasis.

0 = 75 µs. Used in USA (default).

1 = 50 µs. Used in Europe, Australia, Japan.

10 AGCD AGC Disable.

0 = AGC enable (default).

1 = AGC disable.

9:8 Reserved Reserved.

Always write to 0.

6:7 BLNDADJ[1:0] Stereo/Mono Blend Level Adjustment.

Sets the RSSI range for stereo/mono blend.

00 = 31–49 RSSI dBµV (default).

01 = 37–55 RSSI dBµV (+6 dB).

10 = 19–37 RSSI dBµV (–12 dB).

11 = 25–43 RSSI dBµV (–6 dB).

ST bit set for RSSI values greater than low end of range.

5:4 GPIO3[1:0] General Purpose I/O 3.

00 = High impedance (default).

01 = Mono/Stereo indicator (ST). The GPIO3 will output a logic high when the device is in

stereo, otherwise the device will output a logic low for mono.

10 = Low.

11 = High.

Si4702/03-D30

Rev. 0.6 27

3:2 GPIO2[1:0] General Purpose I/O 2.

00 = High impedance (default).

01 = STC/RDS interrupt. A logic high will be output unless an interrupt occurs as

described below.

10 = Low.

11 = High.

Setting STCIEN = 1 will generate a 5 ms low pulse on GPIO2 when the STC 0Ah[14] bit is

set. Setting RDSIEN = 1 will generate a 5 ms low pulse on GPIO2 when the RDSR

0Ah[15] bit is set.

1:0 GPIO1[1:0] General Purpose I/O 1.

00 = High impedance (default).

01 = Reserved.

10 = Low.

11 = High.

Bit Name Function

Si4702/03-D30

28 Rev. 0.6

Reset value = 0x0000

BitD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name SEEKTH[7:0] BAND[1:0] SPACE[1:0] VOLUME[3:0]

Type R/W R/W R/W R/W

Bit Name Function

15:8 SEEKTH[7:0] RSSI Seek Threshold.

0x00 = m in RSSI (d ef au lt) .

0x7F = max RSSI.

SEEKTH presents the logarithmic RSSI threshold for the seek operation. The

Si4702/03-D30 will not validate channels with RSSI below the SEEKTH value.

SEEKTH is one of multiple parameters that can be used to validate channels. For

more information, see "AN230: Si4700/01/02/03 Programming Guide."

7:6 BAND[1:0] Band Select.

00 = 87.5–108 MHz (USA, Europe) (Default).

01 = 76–108 MHz (Japan wide band).

10 = 76–90 MHz (Japan).

11 = 64–108 MHz.

5:4 SPACE[1:0] Channel Spacing.

00 = 200 kHz (USA, Australia) (default).

01 = 100 kHz (Europe, Japan).

10 = 50 kHz.

3:0 VOLUME[3:0] Volume.

Relative value of volume is shifted –30 dBFS with the VOLEXT 06h[8] bit.

VOLEXT = 0 (default).

0000 = mute (default).

0001 = –28 dBFS.

1110 = –2 dBFS.

1111 = 0 dBFS.

VOLEXT = 1.

0000 = mute.

0001 = –58 dBFS.

1110 = –32 dBFS.

1111 = –30 dBFS.

FS = full scale.

Volume scale is logarithmic.

Si4702/03-D30

Rev. 0.6 29

Reset value = 0x0000

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7D6D5D4D3D2D1D0

Name SMUTER[1:0] SMUTEA[1:0] 0 0 0 VOLEXT SKSNR[3:0] SKCNT[3:0]

Type R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

15:14 SMUTER[1:0] Softmute Attack/Recover Rate.

00 = fastest (default).

01 = fast.

10 = slow.

11 = slowest.

13:12 SMUTEA[1:0] Softmute Attenuation.

00 = 16 dB (default).

01 = 14 dB.

10 = 12 dB.

11 = 10 dB.

11:9 Reserved Reserved.

Always write to zero.

8 VOLEXT Extended Volume Range.

0 = disabled (default).

1 = enabled.

This bit attenuates the output by 30 dB. With the bit set to 0, the 15 volume settings

adjust the volume be tween 0 and –28 dBFS. With the bit set to 1, the 15 volu me set -

tings adjust the volume between –30 and –58 dBFS.

Refer to 4.5. "Stereo Audio Processing " on page 16.

7:4 SKSNR[3:0] Seek SNR Threshold.

0000 = disabled (default).

0001 = min (most stops).

0111 = max (fewest stops).

Required channel SNR for a valid seek channel.

3:0 SKCNT[3:0] Seek FM Impulse Detection Threshold.

0000 = disabled (default).

0001 = max (most stops).

1111 = min (fewest stops).

Allowable number of FM impulses for a valid seek channel.

Si4702/03-D30

30 Rev. 0.6

Reset value = 0x0100

Bit D15 D14 D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name XOSCEN AHIZEN Reserved

Type R/W R/W R/W

Bit Name Function

15 XOSCEN Crystal Oscillator Enable.

0 = Disable (default).

1 = Enable.

The internal crystal oscillator requires an external 32.768 kHz crystal as shown in

2. "Typical Application Schematic" on page 14. The oscillator must be enabled before

powerup (ENABLE = 1) as shown in Figure 9, “Initia lization Sequence,” on page 21. It

should only be disabled after powerdown (ENABLE = 0). Bits 13:0 of register 07h

must be preserved as 0x0100 while in po werdown and as 0x3C04 while in powerup.

Refer to Si4702/03 Internal Crystal Oscillator Errata.

14 AHIZEN Audio High-Z Enable.

0 = Disable (default).

1 = Enable.

Setting AHIZEN maintains a dc bias of 0.5 x VIO on the LOUT and ROUT pins to pre-

vent the ESD diodes from clamping to the VIO or GND rail in response to the output

swing of another device. Register 07h containing the AHIZEN bit must not be written

during the powerup sequence and high-Z only takes effect when in powerdown and

VIO is supplied. Bits 13:0 of register 07h must be preserved as 0x0100 while in pow-

erdown and as 0x3C04 while in powerup.

13:0 Reserved Reserved.

If written, these bits should be read first and then written with their pre-existing val-

ues. Do not write during powerup.

Si4702/03-D30

Rev. 0.6 31

Reset value = 0x0000

Bit D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name Reserved

Type R/W

Bit Name Function

15:0 Reserved Reserved.

If written, these bits should be read first and then written with their pre-existing val-

ues. Do not write during powerup.

Bit D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name Reserved

Type R/W

Bit Name Function

15:0 Reserved Reserved.

If written, these bits should be read first and then written with their pre-existing val-

ues. Do not write during powerup.

Si4702/03-D30

32 Rev. 0.6

Reset value = 0x0000

Bit D15D14D13 D12 D11D10D9 D8D7D6D5D4D3D2D1D0

Name RDSR STC SF/BL AFCRL RDSS BLERA[1:0] ST RSSI[7:0]

Type RRR R R R R R

Bit Name Function

15 RDSR RDS Ready.

0 = No RDS group ready (default).

1 = New RDS group ready.

Refer to “4.4. RDS/RBDS Processor and Functionality”.

14 STC Seek/Tune Complete.

0 = Not complete (default).

1 = Complete.

The seek/tune complete flag is set when the seek or tune operation completes. Setting

the SEEK 02h[8] or TUNE 03h[15] bit low will clear STC.

13 SF/BL Seek Fail/Band Limit.

0 = Seek successful.

1 = Seek failure/Band limit reached.

The SF/BL flag is set high when SKMODE 02h[10] = 0 and the seek operation fails to

find a channel qualified as valid according to the seek parameters.

The SF/BL flag is set high whe n SKMODE 02h[1 0] = 1 and the up per or lowe r band limit

has been reach e d.

The SEEK 02h[8] bit must be set low to clear SF/BL.

12 AFCRL AFC Rail.

0 = AFC not railed.

1 = AFC railed, indicating an invalid channel. Audio output is softmuted when set.

AFCRL is updated after a tune or seek operation completes and indicates a valid or

invalid channel. During normal operation, AFCRL is updated to r eflect changin g RF en vi-

ronments.

11 RDSS RDS Synchronized.

0 = RDS decoder not synchronized (default).

1 = RDS decoder synchronized.

Available only in RDS Verbose mode (RDSM 02h[11] = 1).

Refer to “4.4. RDS/RBDS Processor and Functionality”.

10:9 BLERA[1:0] RDS Block A Errors.

00 = 0 errors requiring correction.

01 = 1–2 errors requiring correction.

10 = 3–5 errors requiring correction.

11 = 6+ errors or error in checkword, correction not possible.

Available only in RDS Verbose mode (RDSM 02h[11] = 1).

Refer to “4.4. RDS/RBDS Processor and Functionality”.

Si4702/03-D30

Rev. 0.6 33

8STStereo Indicator.

0 = Mono.

1 = Stereo.

Stereo indication is also available on GPIO3 by setting GPIO3 04h[5:4] = 01.

7:0 RSSI[7:0] RSSI (Received Signal Strength Indicator).

RSSI is measured units of dBµV in 1 dB increments with a maximum of approximately

75 dBµV. Si4702/03-D30 does not report RSSI levels greater than 75 dBuV.

Bit Name Function

Si4702/03-D30

34 Rev. 0.6

Reset value = 0x0000

BitD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name BLERB[1:0] BLERC[1:0] BLERD[1:0] READCHAN[9:0]

Type RRR R

Bit Name Function

15:14 BLERB[1:0] RDS Block B Errors.

00 = 0 errors requiring correction.

01 = 1–2 errors requiring correction.

10 = 3–5 errors requiring correction.

11 = 6+ errors or error in checkwor d, correction not possible.

Available only in RDS Verbose mode (RDSM = 1).

Refer to “4.4. RDS/RBDS Processor and Functionality”.

13:12 BLERC[1:0] RDS Block C Errors.

00 = 0 errors requiring correction.

01 = 1–2 errors requiring correction.

10 = 3–5 errors requiring correction.

11 = 6+ errors or error in checkwor d, correction not possible.

Available only in RDS Verbose mode (RDSM = 1).

Refer to “4.4. RDS/RBDS Processor and Functionality”.

11:10 BLERD[1:0] RDS Block D Errors.

00 = 0 errors requiring correction.

01 = 1–2 errors requiring correction.

10 = 3–5 errors requiring correction.

11 = 6+ errors or error in checkwor d, correction not possible.

Available only in RDS Verbose mode (RDSM = 1).

Refer to “4.4. RDS/RBDS Processor and Functionality”.

9:0 READCHAN[9:0] Read Channel.

If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz.

If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then

Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.

If BAND 05h[7:6] = 11, then freq (MHz) = spacing (MHz) x channel + 64 MHz.

READCHAN[9:0] provides the current tuned channel and is updated dur ing a seek

operation and after a seek o r tune operation completes. Spa cing and channel a re set

with the bits SPACE 05h[5:4] and CHAN 03h[9:0].

Si4702/03-D30

Rev. 0.6 35

Reset value = 0x0000

Bit D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name RDSA[15:0]

Type R

Bit Name Function

15:0 RDSA RDS Block A Data.

Bit D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name RDSB[15:0]

Type R

Bit Name Function

15:0 RDSB RDS Block B Data.

Si4702/03-D30

36 Rev. 0.6

Reset value = 0x0000

Bit D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name RDSC[15:0]

Type R

Bit Name Function

15:0 RDSC RDS Block C Data.

Bit D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

Name RDSD[15:0]

Type R

Bit Name Function

15:0 RDSD RDS Block D Data.

Si4702/03-D30

Rev. 0.6 37

7. Pin Descriptions: Si4702/03-D30

Pin Number(s) Name Description

1, 20 NC No Connect. Leave floating.

2 FMIP FM RF inputs.

3 RFGND RF ground. Connect to ground plane on PCB.

4, 12, 15, PAD GND Ground. Connect to ground plane on PCB.

5RST Device reset input (active low).

6SEN Serial enable input (active low).

7 SCLK S erial cloc k input.

8 S DI O Serial da ta input/ ou tp ut .

9 RCLK E xternal reference oscillator input.

10 VIO I/O supply voltage.

11 VDDigital supply voltage. May be connected directly to battery.

13 ROUT Right audio ou tp ut.

14 LOUT Left audio output.

16 VAAnalog supply voltage. May be connected directly to battery.

17, 18, 19 GP IO3, GPI O2,

GPIO1 General purpose input/output.

Top View

GND

PAD

GPIO1

RCLK

GND

LOUT

ROUT

RST

GND

SDIO

SCLK

GND

FMIP

RFGND

GPIO2

GPIO3

VIO

SEN

7 1098 11

17181920 16

Si4702/03-D30

38 Rev. 0.6

8. Ordering Guide

Part

Number* Description Package

Type Operating

Temperature

Si4702-D30-GM Portable Broadcast Radio Tuner

FM Stereo QFN

Pb-free –20 to 85 °C

Si4703-D30-GM Portable Broadcast Radio Tuner

FM Stereo with RDS QFN

Pb-free –20 to 85 °C

*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.

Si4702/03-D30

Rev. 0.6 39

9. Package Markings (Top Marks)

9.1. Si4702 Top Mark

Figure 10. Si4702 Top Mark

9.2. Si4703 Top Mark

Figure 11. Si4703 Top Mark

9.3. Top Mark Explanation

Mark Method: YAG Laser

Line 1 Marking: Part Number 02 = Si4702

03 = Si4703

Firmware Revision 30 = Firmw are Revision 30

Line 2 Marking: R = Die Revision D = Revision D Die

TTT = Internal Code Internal tracking code.

Line 3 Marking: Circle = 0.5 mm Diameter

(Bottom-Left Justified) Pin 1 Identifier

Y = Year

WW = Workweek Assigned by the Assembly House. Corresponds to the last sig-

nificant digit of the year and workweek of the mold date.

0230

DTTT

YWW

0330

DTTT

YWW

Si4702/03-D30

40 Rev. 0.6

10. Package Outline: Si4702/03-D30

Figure 12 illustrates the package details for the Si4702/03-D30. Table 10 lists the values for the dimensions shown

in the illustration.

Figure 12. 20-Pin Quad Flat No-Lead (QFN)

Table 10. Package Dimensions

Symbol Millimeters Symbol Millimeters

Min Nom Max Min Nom Max

A 0.50 0 .55 0.60 f 2.53 BSC

A1 0.00 0.02 0.05 L 0.35 0.40 0.45

b 0.180.250.30 L1 0.00 — 0.10

c 0.27 0.32 0.37 aaa — — 0.10

D 3.00 BSC bbb — — 0.10

D2 1.65 1.70 1.75 ccc — — 0.08

e 0.50 BSC ddd — — 0.10

E 3.00 BSC eee — — 0.10

E2 1.65 1.70 1.75

Notes:

1. All dimensions are shown in millimeters unless otherwise noted.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

Si4702/03-D30

Rev. 0.6 41

11. PCB Land Pattern: Si4702/03-D30

Figure 13 illustrates the PCB land pattern details for the Si4702/03-D30. Table 11 lists the values for the

dimensions shown in the illustration.

Figure 13. PCB Land Pattern

Si4702/03-D30

42 Rev. 0.6

Table 11. PCB Land Pattern Dimensions

Symbol Millimeters Symbol Millimeters

Min Max Min Max

D 2.71 REF GE 2.10 —

D2 1.60 1.80 W — 0.34

e 0.50 BSC X — 0.28

E 2.71 REF Y 0.61 REF

E2 1.60 1.80 ZE — 3.31

f 2.53 BSC ZD — 3.31

GD 2.10 —

Notes: General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-SM-782 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Notes: Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Notes: Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should

be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides

approximately 70% solder paste coverage on the pad, which is optimum to assu re

correct component stand-off.

Notes: Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.

Si4702/03-D30

Rev. 0.6 43

ADDITIONAL REFERENCE RESOURCES

AN230: Si4700/01/02/0 3 Programming Guide

Si4700/01/02/03 EVB User’s Guide

AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure

AN235: Si4700/01/02/03/08/09 EVB Quick Start Guide

AN243: Using RDS/RBDS with the Si4701/03

AN299: External 32.768 kHz Crystal Oscillator

AN383: Antenna, Schematic, Layout, and Design Guidelines

Si4702/03 Internal Crystal Oscillator Errata

Customer Support Site: http://www.silabs.com

This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA

is required for complete access. To request access, register at http://www.silabs.com and send user’s first and

last name and company name to fminfo@silabs.com.

Si4702/03-D30

44 Rev. 0.6

CONTACT INFORMATION

Silicon Laboratories Inc.

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Tel:1+ (512) 416-8500

Fax:1+ (512) 416-9669

Toll Free:1+ (877) 444-3032

Email: FMinfo@silabs.com

Internet: www. silabs.com

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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-

tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no war-

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