Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. D
05/09/2012
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
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unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
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c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61C1024AL
IS64C1024AL
128K x 8 HIGH-SPEED CMOS STATIC RAM
DESCRIPTION
The ISSI IS61C1024AL/IS64C1024AL is a very high-
speed, low power, 131,072-word by 8-bit CMOS static
RAMs. They are fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation
can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS61C1024AL/IS64C1024AL is available in 32-pin
300-mil SOJ, 32-pin 400-mil SOJ, 32-pin TSOP (Type I,
8x20), and 32-pin sTSOP (Type I, 8 x 13.4) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE1
OE
WE
128K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
FEATURES
• High-speed access time: 12, 15 ns
• Low active power: 160 mW (typical)
• Low standby power: 1000 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
• Commercial, industrial, and automotive tempera-
ture ranges available
• Lead free available
MAY 2012
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
TRUTH TABLE
Mode WE CE1 CE2 OE I/O Operation Vdd Current
Not Selected X H X X High-Z Isb1, Isb2
(Power-down) X X L X High-Z Isb1, Isb2
Output Disabled H L H H High-Z Icc1, Icc2
Read H L H L Dout Icc1, Icc2
Write L L H X DIn Icc1, Icc2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VDD
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
32-Pin SOJ
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
VDD Power
GND Ground
OPERATING RANGE (IS64C1024AL)
Range Ambient Temperature Vdd
Automotive -40°C to +125°C 5V ± 10%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VDD
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN CONFIGURATION
32-Pin TSOP (Type 1) (T) and sTSOP (Type 1) (H)
OPERATING RANGE (IS61C1024AL)
Range Ambient Temperature Vdd
Commercial 0°C to +70°C 5V ± 10%
Industrial -40°C to +85°C 5V ± 10%
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vterm Terminal Voltage with Respect to GND –0.5 to +7.0 V
tstg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.5 W
Iout DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 5 pF
cout Output Capacitance Vout = 0V 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a = 25°c, f = 1 MHz, VDD = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
Voh Output HIGH Voltage VDD = Min., Ioh = –4.0 mA 2.4 — V
Vol Output LOW Voltage VDD = Min., Iol = 8.0 mA — 0.4 V
VIh Input HIGH Voltage 2.2 VDD + 0.5 V
VIl Input LOW Voltage(1) –0.3 0.8 V
IlI Input Leakage GND ≤ VIn ≤ VDD Com. –1 1 µA
Ind. –2 2
Auto. –5 5
Ilo Output Leakage GND ≤ Vout ≤ VDD Com. –1 1 µA
Outputs Disabled Ind. –2 2
Auto. –5 5
Note:
1. VIl = –3.0V for pulse width less than 10 ns.
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
IS61C1024AL/IS64C1024AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-12 ns -15 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
Icc1 VDD Operating VDD = VDD max., CE1 = VIl
Com.
— 35 mA
Supply Current Iout = 0 mA, f = 0
Ind.
— 40
Auto.
— 45
Icc2 VDD Dynamic Operating VDD = VDD max., CE1 = VIl
Com.
— 45 mA
Supply Current Iout = 0 mA, f = fmax
Ind.
— 50
Auto.
— 55
typ.(2) — 32
Isb1 TTL Standby Current VDD = VDD max.,
Com.
— 1 mA
(TTL Inputs) VIn = VIh or VIl
Ind.
— 1.5
CE1 ≥ VIh, f = 0 or
Auto.
— 2
CE2
≤
VIl, f = 0
Isb2 CMOS Standby VDD = VDD max.,
Com.
— 400 µA
Current (CMOS Inputs) CE1 ≥ VDD – 0.2V,
Ind.
— 450
ce2
≤
0.2V
Auto.
— 500
VIn ≥ VDD – 0.2V, or typ.(2) — 200
VIn
≤
0.2V, f = 0
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical Values are measured at VDD = 5V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-12 -15
Symbol Parameter Min. Max. Min. Max. Unit
trc Read Cycle Time 12 — 15 — ns
taa Address Access Time — 12 — 15 ns
toha Output Hold Time 3 — 3 — ns
tace1 CE1 Access Time — 12 — 15 ns
tace2 CE2 Access Time — 12 — 15 ns
tDoe OE Access Time — 6 — 7 ns
tlzoe(2) OE to Low-Z Output 0 — 0 — ns
thzoe(2) OE to High-Z Output 0 6 0 6 ns
tlzce1(2) CE1 to Low-Z Output 2 — 2 — ns
tlzce2(2) CE2 to Low-Z Output 2 — 2 — ns
thzce(2) CE1 or CE2 to High-Z Output 0 7 0 8 ns
tPu(3) CE1 or CE2 to Power-Up 0 — 0 — ns
tPD(3) CE1 or CE2 to Power-Down — 12 — 12 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels
of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
480 Ω
5 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
480 Ω
30 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1
t
ACE2
t
LZCE1
t
LZCE2
t
HZOE
HIGH-Z DATA VALID
ADDRESS
OE
CE1
CE2
D
OUT
t
HZCE1
t
HZCE2
CE2_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIl, CE2 = VIh.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
-12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Unit
twc Write Cycle Time 12 — 15 — ns
tsce1 CE1 to Write End 10 — 12 — ns
tsce2 CE2 to Write End 10 — 12 — ns
taw Address Setup Time to Write End 10 — 12 — ns
tha Address Hold from Write End 0 — 0 — ns
tsa Address Setup Time 0 — 0 — ns
tPwe(3) WE Pulse Width 10 — 12 — ns
tsD Data Setup to Write End 7 — 10 — ns
thD Data Hold from Write End 0 — 0 — ns
thzwe(4) WE LOW to High-Z Output — 7 — 7 ns
tlzwe(4) WE HIGH to Low-Z Output 2 — 2 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with OE HIGH.
4. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
WRITE CYCLE NO. 2
(OE is HIGH During Write Cycle) (1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
HIGH
CE2
CE2_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIh.
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE1 Controlled, OE is HIGH or LOW) (1 )
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
WRITE CYCLE NO. 3
(OE is LOW During Write Cycle) (1)
DATA UNDEFINED
t WC
VALID ADDRESS
LOW
LOW
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA t HZWE
ADDRESS
CE1
WE
D
OUT
DIN
OE
DATAIN VALID
t LZWE
t SD
HIGH
CE2
CE2_WR3.eps
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ.(1) Max. Unit
VDr VDD for Data Retention See Data Retention Waveform 2.0 5.5 V
IDr Data Retention Current VDD = 2.0V, CE1 ≥ VDD – 0.2V Com. — 200 400 µA
or CE2
≤ 0.2V
Ind. — — 450
VIn ≥ VDD – 0.2V, or VIn
≤
Vss + 0.2V
Auto. — — 500
tsDr Data Retention Setup Time See Data Retention Waveform 0 — ns
trDr Recovery Time See Data Retention Waveform trc — ns
Note:
1. Typical Values are measured at VDD = 5V, Ta = 25
o
C and not 100% tested.
DATA RETENTION WAVEFORM (CE1 Controlled)
DATA RETENTION WAVEFORM (CE2 Controlled)
VDD
CE1 ≥ VDD
- 0.2V
t
SDR
t
RDR
V
DR
CE1
GND
4.5V
2.2V
Data Retention Mode
VDD
CE2 ≤ 0.2V
tSDR tRDR
VDR
0.4V
CE2
GND
4.5V
2.2V
Data Retention Mode
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
ORDERING INFORMATION: IS64C1024AL
Automotive Range: –40°C to +125°C
Speed (ns) Order Part No. Package
15 IS64C1024AL-15KA3 400-mil Plastic SOJ
IS64C1024AL-15TA3 TSOP (Type I)
ORDERING INFORMATION: IS61C1024AL
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
12 IS61C1024AL-12T TSOP (Type I)
ORDERING INFORMATION: IS61C1024AL
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
12 IS61C1024AL-12JLI 300-mil Plastic SOJ, Lead-free
IS61C1024AL-12KI 400-mil Plastic SOJ
IS61C1024AL-12KLI 400-mil Plastic SOJ, Lead-free
IS61C1024AL-12HI sTSOP (Type I)
IS61C1024AL-12HLI sTSOP (Type I), Lead-free
IS61C1024AL-12TI TSOP (Type I)
IS61C1024AL-12TLI TSOP (Type I), Lead-free
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
NOTE :
2. Dimension D and E1 do not include mold protrusion .
4. Formed leads shall be planar with respect to one another within 0.1mm
3. Dimension b2 does not include dambar protrusion/intrusion.
at the seating plane after final test.
1. Controlling dimension : mm
5. Reference document : JEDEC SPEC MS-027.
SEATING PLANE
12/19/2007
14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15
Rev. D
05/09/2012
IS61C1024AL, IS64C1024AL