7026L15JG - IDT, Integrated Device Technology Inc

MARCH 2018

DSC 2939/16

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

BUSY

13L

2939 drw 01

I/O

-I/O

15L

I/O

-I/O

SEM

M/S

BUSY

I/O

-I/O

15R

I/O

-I/O

13R

SEM

(1,2) (1,2)

14 14

HIGH-SPEED

16K X 16 DUAL-PORT

STATIC RAM

Features

◆◆

◆True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆◆

◆High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

– Military: 20/25/35/55ns (max.)

◆◆

◆Low-power operation

– IDT7026S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7026L

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆◆

◆Separate upper-byte and lower-byte control for multi-

plexed bus compatibility

◆◆

◆IDT7026 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆◆

◆M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆◆

◆TTL-compatible, single 5V (±10%) power supply

◆◆

◆Available in 84-pin PGA and 84-pin PLCC

◆◆

◆Industrial temperature range (-40°C to +85°C) is available

for selected speeds

◆◆

◆Green parts available, see ordering information

Functional Block Diagram

IDT7026S/L

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Description

The IDT7026 is a high-speed 16K x 16 Dual-Port Static RAM. The

IDT7026 is designed to be used as a stand-alone Dual-Port RAM or as

a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word

systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-

bit or wider memory system applications results in full-speed, error-free

operation without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by CE permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using CMOS high-performance technology, these de-

vices typically operate on only 750mW of power.

The IDT7026 is packaged in a ceramic 84-pin PGA, and a 84-pin

PLCC. Military grade product is manufactured in compliance with MIL-

PRF-38535 QML, making it ideally suited to military temperature appli-

cations demanding the highest level of performance and reliability.

Pin Configurations(1,2,3)

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. Package body is approximately 1.15 in x 1.15 in x .17 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

2939 drw 02

INDEX

11 10 9 8 7 6 5 4 3 2 1 84 83

33 34 35 36 37 38 39 40 41 42 43 44 45

GND

I/O

32 46 47 48 49 50 51 52 53

82 81 80 79 78 77 76 75

GND

BUSY

GND

IDT7026J

J84

(4)

84-Pin PLCC

Top View

(5)

M/S

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

I/O

15L

I/O

BUSY

I/O

R/W

SEM

12L

GND

I/O

11L

10L

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

GND

12R

11R

10R

R/W

SEM

13R

13L

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Configurations(1,2,3) (con't.)

Maximum Operating Temperature

and Supply Voltage(1)

Pin Names

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2 . 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

Capacitance(1) (TA = +25°C, f = 1.0mhz)

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

Left Port Right Port Names

Chip Enab le

R/W

Read /Write Enable

Output Enab le

- A

13L

- A

13R

Address

I/O

- I/O

15L

I/O

- I/O

15R

Data Inp ut/ Outp ut

SEM

Semaphore Enable

Upper Byte Select

Lower Byte Select

BUSY

Busy Flag

M/SMaster or Slave Select

Power

GND Ground

2939 tbl 01

Grade Ambient

Temperature GND Vcc

Military -55

C to +125

C0V 5.0V

10%

Commercial 0

C to +70

C0V 5.0V

10%

Industrial -40

C to +85

C0V 5.0V

10%

2939 tb l 02a

Symbol Parameter Conditions

(2)

Max. Unit

Inp u t Cap ac i tanc e V

= 3dV 9 pF

OUT

Output

Capacitance V

OUT

= 3dV 10 pF

2939 tbl 03

2939 drw 03

I/O

63 61 60 58 55 54 51 48 46 45

1 2 5

14 17 20

28 29

32 31

33 35

IDT7026G

G84

(4)

84-Pin PGA

Top View

(5)

A B C D E F G H J K L

59 56 49 50 40

84 3 4 6 9 15 13 16 18

22 24

19 21

GND

57 53 52

47 44

GND GND

R/W

GND GND SEM

R/W

GND

SEM

BUSY

M/S

12L

Index

I/O

10L

I/O

11L

I/O

13L

I/O

12L

I/O

15L

I/O

14L

I/O

10L

11L

10R

11R

12R

I/O

11R

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

13R

13L

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of

VTERM > Vcc + 10%.

Truth Table I – Non-Contention Read/Write Control

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

NOTE:

1. A0L — A13L ≠ A0R — A13R.

Truth Table II – Semaphore Read/Write Control(1)

Absolute Maximum Ratings(1)

Inputs

(1)

Outputs

Mode

CE R/WOE UB LB SEM I/O

8-15

I/O

0-7

H X X X X H Hig h-Z Hig h-Z De s el ec te d : P o we r-Do wn

X X X H H H High-Z High-Z Both Bytes Deselected

LLXLHHDATA

High-Z Write to Upper Byte Only

LLXHLHHigh-ZDATA

Write to Lo we r By te Only

LLXLLHDATA

DATA

Write to B o th B yte s

LHLLHHDATA

OUT

High-Z Read Upper Byte Only

LHLHLHHigh-ZDATA

OUT

Read Lo we r B yte Only

LHLLLHDATA

OUT

DATA

OUT

Read Bo th Bytes

X X H X X X High-Z High-Z Outputs Disabled

2939 tbl 04

Inputs Outputs

Mode

CE R/WOE UB LB SEM I/O

8-15

I/O

0-7

HHLXXLDATA

OUT

DATA

OUT

Re ad Data in S e map ho re F lag

XHLHHLDATA

OUT

DATA

OUT

Re ad Data in S e map ho re F lag

↑

XXXLDATA

DATA

Write I/O

into Semaphore Flag

↑

XHHLDATA

DATA

Write I/O

into Semaphore Flag

LXXLXL

______ ______

No t Allo we d

LXXXLL

______ ______

No t Allo we d

2939 tbl 05

Symbol Rating Commercial

& Industrial Military Unit

TERM

(2)

Term i nal Vo l tage wi th Res p ec t to G ND -0 .5 to + 7. 0 -0 .5 to + 7. 0 V

BIAS

Te mp erature Unde r Bias -55 to +125 -65 to +135

STG

Sto rage Te mp e rature -55 to +125 -65 to +150

OUT

DC Outp ut Curre nt 50 50 m A

2939 tb l 06a

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Soltage Range (VCC = 5.0V ± 10%)

NOTE:

1. At Vcc = 2.0V, input leakages are undefined.

Recommended DC Operating

Conditions

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

AC Test Conditions

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

Figure 1. AC Output Test Load

Symbol Parameter Min. Typ. Max. Unit

Supply Vo ltage 4.5 5.0 5.5 V

GND Ground 0 0 0 V

Input Hig h Vo l tag e 2. 2

____

6.0(2) V

Inp ut Lo w Vo ltage -0.5(1)

____

0.8 V

2939 tbl 07

Symbol Parameter Test Conditions

7026S 7026L

UnitMin. Max. Min. Max.

| Input Leakage Curre nt

(1)

= 5.5V, V

= 0V to V

___ 10 ___ 5µA

Output Leakage Curre nt CE = V

, V

OUT

= 0V to V

___ 10 ___ 5µA

Output Lo w Voltag e I

= 4mA ___ 0.4 ___ 0.4 V

Output Hig h Vo ltage I

= -4mA 2.4 ___ 2.4 ___ V

2939 t bl 0 8

Input Pulse Levels

Input Rise/Fall Time s

Inp u t Tim ing Re fe re nc e Le v e ls

Output Re fe rence Leve ls

Outp ut Load

GND to 3.0V

3ns

1.5V

Fi gures 1 and 2

2939 tbl 09

2939 drw 05

893Ω

30pF

347Ω

DATA

OUT

BUSY

893Ω

5pF*

347Ω

DATA

OUT

2939 drw 04

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%)

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using

“AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

7026X15

Com'l Onl y 7026X20

Com'l, Ind

& Military.

7026X25

Com'l, Ind

& Military

Symbol Parameter Test Condition Version Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

Dy nam ic Op e rati ng Curre n t

(Bo th Po rts A ctiv e) CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(3)

COM'L S

L190

190 325

285 180

180 315

275 170

170 305

265 mA

MIL &

IND S

___

180

180 355

315 170

170 345

305

SB1

Stand b y Curre nt

(B o th P orts - TTL Le ve l

Inputs)

= CE

= V

SEM

= SEM

= V

f = f

MAX

(3)

COM'L S

L35

35 95

70 30

30 85

60 25

25 85

60 mA

MIL &

IND S

___

30 100

80 25

25 100

SB2

Stand b y Curre nt

(One P o rt - TTL Le ve l Inp uts ) CE

"A"

= V

and CE

"B"

= V

(5)

Active Po rt Outp uts Disabled ,

f=f

MAX

(3)

SEM

= SEM

= V

COM'L S

L125

125 220

190 115

115 210

180 105

105 200

170 mA

MIL &

IND S

___

115

115 245

210 105

105 230

200

SB3

Full Standby Current (Both

Ports - All CMOS Le vel

Inputs)

Both Po rts CE

and

> V

- 0.2V

> V

- 0. 2V o r

< 0. 2 V , f = 0

(4)

SEM

= SEM

> V

- 0.2V

COM'L S

L1.0

0.2 15

51.0

0.2 15

51.0

0.2 15

5mA

MIL &

IND S

___

1.0

0.2 30

10 1.0

0.2 30

SB4

Full Standby Current

(On e Port - Al l CMO S Lev el

Inputs)

"A"

< 0. 2V and

"B"

> V

- 0.2V

(5)

SEM

= SEM

> V

- 0.2V

> V

- 0. 2V or V

< 0. 2V

Active Po rt Outp uts Disabled ,

f=f

MAX(3)

COM'L S

L120

120 195

170 110

110 185

160 100

100 170

145 mA

MIL &

IND S

___

110

110 210

185 100

100 200

175

2939 tbl 10

7026X35

Com'l, Ind

& Military

7026X55

Com'l, Ind

& Mi li tary

Symbol Parameter Test Condition Version Typ.

(2)

Max. Typ.

(2)

Max. Unit

Dynamic Operating

Current

(Bo th P orts Ac tive )

CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(3)

COM'L S

L160

160 295

255 150

150 270

230 mA

MIL &

IND S

L160

160 335

295 150

150 310

270

SB1

Stand b y Current

(Bo th P orts - TTL Le ve l

Inputs)

= CE

= V

SEM

= SEM

= V

f = f

MAX

(3)

COM'L S

L20

20 85

60 13

13 85

60 mA

MIL &

IND S

L20

20 100

80 13

13 100

SB2

Stand b y Current

(One Po rt - TTL Le v el

Inputs)

"A"

= V

and CE

"B"

= V

(5)

Active Port Outputs Disabled,

f=f

MAX

(3)

SEM

= SEM

= V

COM'L S

L95

95 185

155 85

85 165

135 mA

MIL &

IND S

L95

95 215

185 85

85 195

165

SB3

Full Standb y Curre nt

(Bo th Po rts - All CMOS

Leve l Inp uts )

Bo th Po rts CE

and

> V

- 0.2V

> V

- 0.2V o r

< 0.2V, f = 0

(4)

SEM

= SEM

> V

- 0.2V

COM'L S

L1.0

0.2 15

51.0

0.2 15

5mA

MIL &

IND S

L1.0

0.2 30

10 1.0

0.2 30

SB4

Full Standb y Curre nt

(One Po rt - A ll CMOS

Leve l Inp uts )

"A"

< 0. 2V and

"B"

> V

- 0.2V

(5)

SEM

= SEM

> V

- 0.2V

> V

- 0. 2V o r V

< 0.2V

Active Port Outp uts Disabled

f=f

MAX

(3)

COM'L S

L90

90 160

135 80

80 135

110 mA

MIL &

IND S

L90

90 190

165 80

80 175

150

2 939 tb l 11

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part numbers indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

7026X15

Com'l Only 7026X20

Com 'l, I nd

& Mi li tary

7026X25

Com'l, Ind

& Mi li tary

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

RE AD CYCLE

Re ad Cyc le Time 15

____

Address Access Time

____

25 ns

ACE

Chip Enable Access Time

(3)

____

25 ns

ABE

Byte Enable Access Time

(3)

____

25 ns

AOE

Output Enable Access Time

____

13 ns

Output Hold from Address Change 3

____

Output Low-Z Time

(1,2)

____

Outp ut High-Z Time

(1,2)

____

15 ns

Chip Enab le to Po wer Up Time

(2)

____

Chip Di sab le to Po we r Do wn Tim e

(2)

____

25 ns

SOP

Semaphore Flag Update Pulse (OE or SEM)10

____

SAA

Semaphore Address Access Time

____

25 ns

2 939 tb l 12 a

7026X35

Com 'l, I nd

& Mi li tary

7026X 55

Com'l, Ind

& Mi li tary

UnitSymbol Parameter Min.Max.Min.Max.

RE AD CYCLE

Re ad Cyc le Time 35

____

Address Access Time

____

55 ns

ACE

Chip Enable Access Time

(3)

____

55 ns

ABE

Byte Enable Access Time

(3)

____

55 ns

AOE

Output Enable Access Time

____

30 ns

Output Hold from Address Change 3

____

Output Low-Z Time

(1,2)

____

Outp ut High-Z Time

(1,2)

____

25 ns

Chip Enab le to Po wer Up Time

(2)

____

Chip Di sab le to Po we r Do wn Tim e

(2)

____

50 ns

SOP

Semaphore Flag Update Pulse (OE or SEM)15

____

SAA

Semaphore Address Access Time

____

55 ns

2939 tbl 12b

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

WAVEFORM OF READ CYCLES(5)

Timing of Power-Up Power-Down

tRC

R/W

ADDR

tAA

UB,LB

2939 drw 06

(4)

tACE

(4)

tAOE

(4)

tABE

(4)

(1)

tLZ tOH

(2)

tHZ

(3, 4)

tBDD

DATAOUT

BUSYOUT

VALID DATA

(4)

2939 drw 07

50% 50%

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part numbers indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5,6)

Symbol Parameter

7026X15

Com 'l Onl y 7026X20

Com 'l, I nd

& Mi li tary

7026X25

Com'l, Ind

& Mi li tary

UnitMin. Max. Min. Max. Min. Max.

WRI TE CYCLE

Write Cycle Time 15

____

Chip Enab le to End-of-Write

(3)

____

Address Valid to End-of-Write 12

____

Address Set-up Time

(3)

____

Write Pulse Width 12

____

Wri te Re c ov e ry Ti me 0

____

Data Vali d to End -o f-Wri te 10

____

Output Hig h-Z Time

(1,2)

____

15 ns

Data Ho ld Ti me

(4)

____

Write Enable to Output in High-Z

(1,2)

____

15 ns

Ou tp ut Ac tiv e fro m End -o f-Wri te

(1,2,4)

____

SWRD

SEM Flag Write to Read Time 5

____

SPS

SEM Flag Contention Window 5

____

3 199 tbl 13 a

Symbol Parameter

7026X35

Com 'l, I nd

& Mi li tary

7026X55

Com'l, Ind

& Mi li tary

UnitMin. Max. Min. Max.

WRI TE CYCLE

Write Cycle Time 35

____

Chip Enab le to End-of-Write

(3)

____

Address Valid to End-of-Write 30

____

Address Set-up Time

(3)

____

Write Pulse Width 25

____

Wri te Re c ov e ry Ti me 0

____

Data Vali d to End -o f-Wri te 15

____

Output Hig h-Z Time

(1,2)

____

25 ns

Data Ho ld Ti me

(4)

____

Write Enable to Output in High-Z

(1,2)

____

25 ns

Ou tp ut Ac tiv e fro m End -o f-Wri te

(1,2,4)

____

SWRD

SEM Flag Write to Read Time 5

____

SPS

SEM Flag Contention Window 5

____

2939 tb l 13b

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Wa vef orm of Write Cyc le No. 1, R/W Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or UB and LB = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a VIL CE = VIL and R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going VIH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7 . This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

Timing Wa vef orm of Write Cyc le No. 2, CE, UB, LB Controlled Timing(1,5)

R/W

tWC

tHZ

tAW

tWRtAS tWP

DATAOUT

(2)

tWZ

tDW tDH

tOW

ADDRESS

DATAIN

(6)

(4) (4)

(7)

UB or LB

2939 drw 08

(9)

CE or SEM

(9)

(7)

(3)

2939 drw 09

ADDRESS

DATA

R/W

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

Timing Waveform of Semaphore Write Contention(1,3,4)

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

SEM

2939 drw 10

SOP

I/O

VALID ADDRESS

SAA

R/W

ACE

VALID ADDRESS

DATA

VALID DATA

OUT

SWRD

AOE

Read Cycle

Write Cycle

-A

VALID

(2)

NOTES:

1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

SEM"A"

2939 drw 11

tSPS

MATCH

R/W"A"

MATCH

A0"A"-A2"A"

SIDE "A"

(2)

SEM"B"

R/W"B"

A0"B"-A2"B"

SIDE

(2)

"B"

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

7. Industrial temperature: for other speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6,7)

7026X15

Com'l Only 7026X20

Com 'l, I nd

& Mi li tary

7026X25

Com'l, Ind

& Mi li tary

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

BUSY TIMI NG (M/S=V

)

BAA

BUSY Access Time from Address Match

____

20 ns

BDA

BUSY Disable Time from Address Not Matched

____

20 ns

BAC

BUSY Acce ss Time from Chip Enable Low

____

20 ns

BDC

BUSY Acce ss Time from Chip Enable High

____

17 ns

APS

Arb itration Prio rity S et-up Time

(2)

____

BDD

BUSY Disable to Valid Data

____

30 ns

Write Ho ld After BUSY

(5)

____

BUSY TIMI NG (M/S=V

)

BUSY In p ut to Write

(4)

____

Write Ho ld After BUSY

(5)

____

P ORT-T O-P ORT DE LAY T IMI NG

WDD

Write Pulse to Data De lay

(1)

____

50 ns

DDD

Write Data Valid to Read Data Delay

(1)

____

35 ns

2939 tbl 14a

7026X35

Com'l , I nd

& Mi li tary

7026X55

Com'l , I nd

& Mi li tary

UnitSymbol Parameter Min.Max.Min.Max.

BUSY TIMING (M/S=V

)

BAA

BUSY Access Time from Address Match

____

45 ns

BDA

BUSY Disable Time from Address Not Matched

____

40 ns

BAC

BUSY Access Time fro m Chip Enab le Low

____

40 ns

BDC

BUSY Access Time from Chip Enable High

____

35 ns

APS

Arb itratio n Pri o ri ty S e t-up Tim e

(2)

____

BDD

BUSY Disable to Valid Data

(3)

____

40 ns

Write Hold After BUSY

(5)

____

BUSY TIMING (M/S=V

)

BUSY In put to Wri te

(4)

____

Write Hold After BUSY

(5)

____

PORT-TO-P ORT DELAY TIMING

WDD

Write Pulse to Data De lay

(1)

____

80 ns

DDD

Wri te Data Val id to Re ad Data De l ay

(1)

____

65 ns

2939 tbl 14b

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

2939 drw 12

APS

ADDR

"A"

DATA

OUT "B"

MATCH

R/W

"A"

DATA

IN "A"

ADDR

"B"

VALID

(1)

MATCH

BUSY

"B"

BDA

VALID

BDD

DDD

(3)

WDD

BAA

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5 . All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Wa veform of Write with BUSY (M/S = VIL)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the “SLAVE” version.

2939 drw 13

R/W"A"

BUSY"B"

WB(3)

R/W"B"

(2)

(1)

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)

Waveform of BUSY Arbitration Cycle Controlled by

Address Match Timing (M/S = VIH)(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

Truth Table III — Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7026.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.

2939 drw 14

ADDR

"A"

and

"B"

ADDRESSES MATCH

"A"

"B"

BUSY

"B"

APS

BAC

BDC

(2)

2939 drw 15

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

APS

BAA

BDA

(2)

MATCHING ADDRESS "N"

Functions D

- D

Left D

- D

Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Le ft P ort Wri tes "0" to Se map ho re 1 0 No chang e . Le ft po rt has no wri te ac c es s to s e map ho re

Rig ht P o rt Wri tes "1" to Se map ho re 0 1 Le ft p ort o b tains se map ho re to ke n

Le ft P ort Wri tes "1" to Se map ho re 1 1 Se map ho re fre e

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Le ft P ort Wri tes "1" to Se map ho re 1 1 Se map ho re fre e

29 39 t bl 15

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Functional Description

The IDT7026 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location

in memory. The IDT7026 has an automatic power down feature controlled

by CE. The CE controls on-chip power down circuitry that permits the

respective port to go into a standby mode when not selected (CE = VIH).

When a port is enabled, access to the entire memory array is permitted.

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “Busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in slave

mode with the M/S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT 7026 RAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a

master. Both are inputs when configured as a slave. BUSYX outputs on the

IDT7026 are push pull, not open drain outputs. On slaves the BUSYX input

internally inhibits writes.

2. LOW if the inputs to the opposite port were stable prior to the address and enable

inputs of this port. HIGH if the inputs to the opposite port became stable after the

address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR

= LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when BUSYR outputs are driving LOW regardless of actual logic level

on the pin.

array and another master indicating BUSY on one other side of the array.

This would inhibit the write operations from one port for part of a word and

inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration on a master is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enough for a BUSY flag to be output from the master before the actual write

pulse can be initiated with either the R/W signal or the byte enables. Failure

to observe this timing can result in a glitched internal write inhibit signal and

corrupted data in the slave.

Semaphores

The IDT7026 is an extremely fast Dual-Port 16K x 16 CMOS Static

RAM with an additional 8 address locations dedicated to binary semaphore

flags. These flags allow either processor on the left or right side of the Dual-

Port RAM to claim a privilege over the other processor for functions defined

by the system designer’s software. As an example, the semaphore can

be used by one processor to inhibit the other from accessing a portion of

the Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be read from,

or written to, at the same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphore location. Semaphores are protected against such ambiguous

situations and may be used by the system program to avoid any conflicts

Width Expansion with BUSY Logic

Master/Slave Arrays

When expanding an IDT7026 RAM array in width while using BUSY

logic, one master part is used to decide which side of the RAM array will

receive a BUSY indication, and to output that indication. Any number of

slaves to be addressed in the same address range as the master use the

BUSY signal as a write inhibit signal. Thus on the IDT7026 RAM the BUSY

pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY

pin is an input if the part used as a slave (M/S pin = VIL) as shown in

Figure 3.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating BUSY on one side of the

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7026 RAMs.

T ruth T able IV —

Address BUSY Arbitration

Inputs Outputs

Function

-A

13L

-A

13R

BUSY

(1)

BUSY

(1)

XX NO MATCH H H Normal

HX MATCH H H Normal

XH MATCH H H Normal

L L MATCH (2) (2) Wri te Inhi b it

(3)

2939 tbl 16

2939 drw 16

MASTER

Dual Port

RAM

BUSY

MASTER

Dual Port

RAM

BUSY

SLAVE

Dual Port

RAM

BUSY

SLAVE

Dual Port

RAM

BUSY

DECODER

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

in the non-semaphore portion of the Dual-Port RAM. These devices have

an automatic power-down feature controlled by CE, the Dual-Port RAM

enable, and SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into

standby mode when not selected. This is the condition which is shown in

Truth Table I where CE and SEM = VIH.

Systems which can best use the IDT7026 contain multiple proces-

sors or controllers and are typically very high-speed systems which

are software controlled or software intensive. These systems can

benefit from a performance increase offered by the IDT7026's hardware

semaphores, which provide a lockout mechanism without requiring

complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in varying

configurations. The IDT7026 does not use its semaphore flags to control

any resources through hardware, thus allowing the system designer total

flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred in

either processor. This can prove to be a major advantage in very high-

speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent

of the Dual-Port RAM. These latches can be used to pass a flag, or token,

from one port to the other to indicate that a shared resource is in use. The

semaphores provide a hardware assist for a use assignment method

called “Token Passing Allocation.” In this method, the state of a semaphore

latch is used as a token indicating that shared resource is in use. If the left

processor wants to use this resource, it requests the token by setting the

latch. This processor then verifies its success in setting the latch by reading

it. If it was successful, it proceeds to assume control over the shared

resource. If it was not successful in setting the latch, it determines that the

right side processor has set the latch first, has the token and is using the

shared resource. The left processor can then either repeatedly request

that semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of the

token via the set and test sequence. Once the right side has relinquished

the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by writing

a zero into a semaphore latch and is released when the same side writes

a one to that latch.

The eight semaphore flags reside within the IDT7026 in a separate

memory space from the Dual-Port RAM. This address space is ac-

cessed by placing a LOW input on the SEM pin (which acts as a chip select

for the semaphore flags) and using the other control pins (Address, OE,

and R/W) as they would be used in accessing a standard Static RAM.

Each of the flags has a unique address which can be accessed by either

side through address pins A0 – A2. When accessing the semaphores,

none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Table III). That semaphore

can now only be modified by the side showing the zero. When a one is

written into the same location from the same side, the flag will be set to a

one for both sides (unless a semaphore request from the other side is

pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits

so that a flag that is a one reads as a one in all data bits and a flag

containing a zero reads as all zeros. The read value is latched into one

side’s output register when that side's semaphore select (SEM) and output

enable (OE) signals go active. This serves to disallow the semaphore from

changing state in the middle of a read cycle due to a write cycle from the

other side. Because of this latch, a repeated read of a semaphore in a test

loop must cause either signal (SEM or OE) to go inactive or the output will

never change.

A sequence WRITE/READ must be used by the semaphore in order

to guarantee that no system level contention will occur. A processor

requests access to shared resources by attempting to write a zero into a

semaphore location. If the semaphore is already in use, the semaphore

request latch will contain a zero, yet the semaphore flag will appear as one,

a fact which the processor will verify by the subsequent read (see Table

III). As an example, assume a processor writes a zero to the left port at a

free semaphore location. On a subsequent read, the processor will verify

that it has written successfully to that location and will assume control over

the resource in question. Meanwhile, if a processor on the right side

attempts to write a zero to the same semaphore flag it will fail, as will be

verified by the fact that a one will be read from that semaphore on the right

side during subsequent read. Had a sequence of READ/WRITE been

used instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed

by either repeated reads or by writing a one into the same location. The

reason for this is easily understood by looking at the simple logic diagram

of the semaphore flag in Figure 4. Two semaphore request latches feed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphore flag will force its side of the semaphore flag LOW and the other

side HIGH. This condition will continue until a one is written to the same

semaphore request latch. Should the other side’s semaphore request latch

have been written to a zero in the meantime, the semaphore flag will flip

over to the other side as soon as a one is written into the first side’s request

latch. The second side’s flag will now stay LOW until its semaphore request

latch is written to a one. From this it is easy to understand that, if a semaphore

is requested and the processor which requested it no longer needs the

resource, the entire system can hang up until a one is written into that

semaphore request latch.

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If simulta-

neous requests are made, the logic guarantees that only one side receives

the token. If one side is earlier than the other in making the request, the first

side to make the request will receive the token. If both requests arrive at

the same time, the assignment will be arbitrarily made to one port or the

other.

One caution that should be noted when using semaphores is that

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

section by writing, then reading a zero into Semaphore 1. If it succeeded

in gaining control, it would lock out the left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could undo

its semaphore request and perform other tasks until it was able to write, then

read a zero into Semaphore 1. If the right processor performs a similar task

with Semaphore 0, this protocol would allow the two processors to swap

8K blocks of Dual-Port RAM with each other.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the Dual-

Port RAM or other shared resources into eight parts. Semaphores can

even be assigned different meanings on different sides rather than being

given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory during

a transfer and the I/O device cannot tolerate any wait states. With the use

of semaphores, once the two devices has determined which memory area

was “off-limits” to the CPU, both the CPU and the I/O devices could access

their assigned portions of memory continuously without any wait states.

Semaphores are also useful in applications where no memory “WAIT”

state is available on one or both sides. Once a semaphore handshake has

been performed, both processors can access their assigned RAM

segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one processor

may be responsible for building and updating a data structure. The other

processor then reads and interprets that data structure. If the interpreting

processor reads an incomplete data structure, a major error condition may

exist. Therefore, some sort of arbitration must be used between the two

different processors. The building processor arbitrates for the block, locks

it and then is able to go in and update the data structure. When the update

is completed, the data structure block is released. This allows the

interpreting processor to come back and read the complete data structure,

thereby guaranteeing a consistent data structure.

semaphores alone do not guarantee that access to a resource is secure.

As with any powerful programming technique, if semaphores are mis-

used or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled

via the initialization program at power-up. Since any semaphore request

flag which contains a zero must be reset to a one, all semaphores on both

sides should have a one written into them at initialization from both sides

to assure that they will be free when needed.

Using Semaphores—Some Examples

Perhaps the simplest application of semaphores is their application

as resource markers for the IDT7026’s Dual-Port RAM. Say the 16K x

16 RAM was to be divided into two 8K x 16 blocks which were to be

dedicated at any one time to servicing either the left or right port. Semaphore

0 could be used to indicate the side which would control the lower section

of memory, and Semaphore 1 could be defined as the indicator for the

upper section of memory.

To take a resource, in this example the lower 8K of Dual-Port RAM,

the processor on the left port could write and then read a zero in to

Semaphore 0. If this task were successfully completed (a zero was

read back rather than a one), the left processor would assume control

of the lower 8K. Meanwhile the right processor was attempting to gain

control of the resource after the left processor, it would read back a one

in response to the zero it had attempted to write into Semaphore 0. At this

point, the software could choose to try and gain control of the second 8K

Figure 4. IDT7026 Semaphore Logic

2939 drw 17

0DQ

WRITE D

WRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT RPORT

SEMAPHORE

READ SEMAPHORE

READ

6.42

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

01/14/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Pages 2 and 3 Added additional notes to pin configurations

060/3/99: Changed drawing format

Page 1 Corrected DSC number

03/10/00: Added Industrial Temperature Ranges and removed related notes

Replaced IDT logo

Page 1 Fixed format in Features

Changed ±200mV to 0mV in notes

05/22/00: Page 3 Clarified TA parameter

Page 6 DC Electrical parameters–changed wording from "open" to "disabled"

11/20/01: Page 1 & 18 Verified accuracy of Industrial temp information throughout datasheet and updated with registered logo

Page 2 & 3 Added date revision for pin configurations

01/29/09: Page 18 Removed "IDT" from orderable part number

08/05/15: Page 1 In Features: Added text: "Green parts available, see ordering information".

Page 2 In Descriptions: Removed IDT in reference to fabrication

Page 2 &18 The package code J84-1 changed to J84 to match standard package codes

Page 3 &18 The package code G84-1 changed to G84 to match standard package codes

Page 18 Added Green and Tape & Reel indicators to the Ordering Information and updated footnotes

Product Discontinuation Notice - PDN# SP-17-02

Last time buy expires June 15, 2018

Commercial Only

Commercial, Industrial & Military

2939 drw 18

Power

999

Speed

Package

Process/

Temperature

Range

Blank

I(1)

Commercial (0°C to +70°C)

Industrial (-40°C to + 85°C)

Military (-55°C to + 125°C)

Compliant to MIL-PRF-38535 QML

J 84-pin PGA (G84)

84-pin PLCC (J84)

L Standard Power

Low Power

XXXXX

Device

Type

256K (16K x 16) Dual-Port RAM 7026

Speed in nanoseconds

Blank

8Tube or Tray

Tape and Reel

Green

G(2)

NOTES:

1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.

2. Green parts available. For specific speeds, packages and powers contact your local sales office

LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02

03/07/18: