1/49June 2003
M29DW323DT
M29DW323DB
32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block)
3V S upp l y Fla sh Memory
FEATURES SUMM ARY
■SUPPLY VOLTAGE
–V
CC = 2.7V to 3.6V f or Program, Erase and
Read
–V
PP =12V for Fast Program (optional)
■ACCESS TIME: 70, 90ns
■PRO GRAMMING TI ME
– 10µs per Byte/Word typical
– Double Word/ Quadruple Byte Program
■MEMORY BLOCKS
– Dual Bank Memory Array: 8Mbit+24Mbit
– Paramete r Bl o cks (Top or Bottom Location )
■DUAL OPERATIONS
– Read in one bank while Program or Erase in
other
■ERASE SU SPEND and RESUM E MOD ES
– Read and Program another Block during
Erase Su spend
■UNLOCK BYPASS PROGRAM COMMAND
– Fas ter Production/Batc h Prog ramm ing
■VPP/WP PIN fo r FAST PROGRAM and W RITE
PROTECT
■TEMPORARY BLOCK UNPROT ECTION
MODE
■COMMON FLASH INTE RFACE
– 64 bit Security Code
■EXTENDED MEMORY BL OCK
– Extra block used as security block or to store
additional information
■LOW POWER CONSUMPTION
– Standby and Autom atic Standby
■100,000 PROGRAM/E RASE CYCL ES per
BLOCK
■ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29 DW323DT : 225 Eh
– Bottom Device Code M2 9DW323DB: 225Fh
Figure 1. Packages
TSOP48 (N)
12 x 20mm
FBGA
TFBGA63 (ZA)
7 x 11mm
FBGA
TFBGA48 (ZE)
6 x 8mm
M29DW323D T, M29DW323DB
2/49
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Nam es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA63 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. TFBGA48 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Addre ss Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
D ata Inputs/Ou tputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
D ata Input/Output or Address Input (DQ15A– 1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
W rite Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
R eady/Busy Out put (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Byte/W ord Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC Supply Volt age (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
V
SS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disab le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Autom at ic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Ele ctronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect a nd Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect a nd Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Bus Operati ons, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Bus Operati ons, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
R ead/Res et Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
3/49
M29DW323DT, M29DW323DB
Quadruple By te Program Com mand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
D ouble Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Reset Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Erase S uspend Com ma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Exit Extended B lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
Table 5. Comm and s, 16-bit mode, BYT E = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Comm and s, 8-bit mode, B Y TE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Program , Erase Times and Prog ram, Erase Enduranc e Cyc les . . . . . . . . . . . . . . . . . . . . 19
STATUS REGIST ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Toggl e Bit (DQ6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Alternative Tog gle Bit (DQ2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Table 8. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Figure 9. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Operating and AC Measuremen t Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Device Capacitanc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. DC Ch aracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
Figure 12. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5
Figure 13. Write AC Wav eforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. Write AC Characteristics, Ch ip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. Reset/Block T emporary Un protect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PAC KAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
Figure 17. TSOP 48 Lead P last ic Thin Small Outline, 12x20 mm , Bottom Vi ew Package Outline . 29
M29DW323D T, M29DW323DB
4/49
Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package M ec hanical Data . . . . . 29
Figure 18. TFBGA6 3 7x11mm - 6x8 Ball Array, 0.8m m Pitch, Bottom View Package Out line . . . . 30
Table 18. TFBG A 63 7x11mm - 6x8 Ball Array, 0 .8mm Pitch, Package Me chanical Data . . . . . . . . 30
Figure 19. TFBGA4 8 6x8mm - 6x8 Ball Array, 0.8m m Pit ch, Bottom View Package Out line . . . . . 31
Table 19. TFBG A 48 6x8mm - 6x8 Ball Array, 0.8m m Pitch, Package Mecha nical Data. . . . . . . . . 31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX A. BL OCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 21. Top Boot Block Addres ses, M29 DW323DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Bottom Boot Blo ck Addresses, M29DW323DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
APPENDIX B. CO MMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 25. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 26. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 27. Pri mary Algorithm -Spe cific Extende d Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 28. Secu rity Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Factory Loc ked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Customer Lockable Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 29. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX D. BL OCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 30. Prog ramm er Techni que Bu s Operations , BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . 43
Figure 20. Programmer Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 21. Programmer Equ ipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. In-System Equipment G roup Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 23. In-System Equipment Chip Unprote ct Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
REVISIO N HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
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M29DW323DT, M29DW323DB
SUMMARY DESCRIPTION
The M29DW323D is a 32 Mbit (4Mb x8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. T hese operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The device f eatures an asymmet rical block archi-
tecture. The M29DW323D has an array of 8 pa-
rameter and 63 main blocks and is divided into two
Banks, A and B, providing Dual Bank operations.
While programming or erasing in Bank A, read op-
erations are possible in Bank B and vice versa.
Only one bank at a time is allowed to be in pro-
gram or erase mode. The bank architecture is
summarized in Table 2. M29DW323DT locates the
Parameter Blocks at the top of the memory ad-
dress space while the M29DW323DB locates the
Parameter Blocks starting from the bottom.
M29DW323D has an extr a 32 KWord (x16 m ode)
or 64 KByte (x8 mode) block, the Extended Block,
that can be accessed using a dedicated com-
mand. The Extended Block can be protected and
so is useful for storing security information. How-
ever the protection is irreversible, once protected
the protect ion c annot be undone.
Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com-
mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special op-
erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi-
fied. The command set required to control the
memory is consistent wi th JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often wit hout additional logic.
The memory is offered in TSOP48 (12x20mm),
TFBGA63 (7x11mm, 0.8mm pitch) and TFBGA48
(6x8mm, 0.8mm pitch) packages. The memory is
supplied w i t h al l the bi t s erased (set to ’1’).
Figure 2. Logic Diagram Table 1. Signal Names
AI05523
21
A0-A20
W
DQ0-DQ14
VCC
M29DW323DT
M29DW323DB
E
VSS
15
G
RP
DQ15A–1
BYTE
RB
VPP/WP
A0-A20 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
VCC Supply Voltage
VPP/WP VPP/Write Protect
VSS Ground
NC Not Connected Internally
M29DW323D T, M29DW323DB
6/49
Figu re 3. TSOP C onnecti ons
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
A7
DQ7
VPP/WP
NC
AI05524
M29DW323DT
M29DW323DB
12
1
13
24 25
36
37
48
DQ8
A20
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14 VSS
E
A0
RP
VSS
7/49
M29DW323DT, M29DW323DB
Figure 4. TFBGA63 Conn ections (Top view through packa ge)
Note: 1. Ball s are shorted together via the su bstrate but not connecte d to the di e.
654321
VSS
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
VPP
/
WP
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 A20
A16
BYTE
C
B
A
E
D
F
G
H
DQ15
A–1
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
J
K
L
M
87
NC(1)
NC(1)
NC(1)
NC(1)
AI05525B
M29DW323D T, M29DW323DB
8/49
Figure 5. TFBGA48 Connections (Top view through packa ge)
Table 2. Bank Architecture
Bank Bank Size Parameter Blocks Main Blocks
No. of
Blocks Block Size No. of Blocks Block Size
A 8 Mbit 8 8KByte/ 4 KWord 15 64KByte/ 32 KWord
B 24 Mbit - 48 64KByte/ 32 KWord
654321
VSS
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
VPP
/
WP
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 A20
A16
BYTE
C
B
A
E
D
F
G
H
DQ15
A–1
AI08084
9/49
M29DW323DT, M29DW323DB
Figure 6. Block Addresses (x8)
Note: Als o see Appendix A, T ables 2 1 and 22 for a full l isting o f t he Bloc k A ddresses.
AI05556
64 KByte or
32 KWord
000000h
00FFFFh
64 KByte or
32 KWord
3E0000h
3EFFFFh
Top Boot Block (x8)
Address lines A20-A0, DQ15A-1
64 KByte or
32 KWord
2F0000h
2FFFFFh
Total of 48
Main Blocks
64 KByte or
32 KWord
300000h
30FFFFh
8 KByte or
4 KWord
3FE000h
3FFFFFh
8 KByte or
4 KWord
3F0000h
3F1FFFh
Total of 15
Main Blocks
Total of 8
Parameter
Blocks (1)
Bank B
Bank A
8 KByte or
4 KWord
000000h
001FFFh
64 KByte or
32 KWord
0F0000h
0FFFFFh
Bottom Boot Block (x8)
Address lines A20-A0, DQ15A-1
8 KByte or
4 KWord
00E000h
00FFFFh
Total of 8
Parameter
Blocks (1)
64 KByte or
32 KWord
010000h
01FFFFh
64 KByte or
32 KWord
3F0000h
3FFFFFh
64 KByte or
32 KWord
100000h
10FFFFh
Total of 15
Main Blocks
Total of 48
Main Blocks
Bank B
Bank A
Note 1. Used as Extended Block Addresses in Extended Block mode.
M29DW323D T, M29DW323DB
10/49
Figure 7. Block Addresses (x16)
Note: Als o see Appendix A, T ables 2 1 and 22 for a full l isting o f t he Bloc k A ddresses.
AI05555
64 KByte or
32 KWord
000000h
007FFFh
64 KByte or
32 KWord
1F0000h
1F7FFFh
Top Boot Block (x16)
Address lines A20-A0
64 KByte or
32 KWord
178000h
17FFFFh
Total of 48
Main Blocks
64 KByte or
32 KWord
180000h
187FFFh
8 KByte or
4 KWord
1FF000h
1FFFFFh
8 KByte or
4 KWord
1F8000h
1F8FFFh
Total of 15
Main Blocks
Total of 8
Parameter
Blocks (1)
Bank B
Bank A
8 KByte or
4 KWord
000000h
000FFFh
64 KByte or
32 KWord
078000h
07FFFFh
Bottom Boot Block (x16)
Address lines A20-A0
8 KByte or
4 KWord
007000h
007FFFh
Total of 8
Parameter
Blocks (1)
64 KByte or
32 KWord
008000h
00FFFFh
64 KByte or
32 KWord
1F8000h
1FFFFFh
64 KByte or
32 KWord
080000h
087FFFh
Total of 15
Main Blocks
Total of 48
Main Blocks
Bank B
Bank A
Note 1. Used as Extended Block Addresses in Extended Block mode.
11/49
M29DW323DT, M29DW323DB
SIGNA L DESCRIPTIONS
See Figure 2, Logic Diag ram, and T able 1, Sign al
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cell s in the memory arra y to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Output s (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Re ad operation when B YTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols th e Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
ma nd Inte r face.
VPP/Wr ite Protect (VPP/WP). The VPP/Write
Protect
pin provides two functions. The VPP f unc-
tion allows the memory to use an external high
voltag e powe r supp ly t o red uce the ti m e req ui re d
for Program operations. This is achieved by by-
passing the unlock cycles and/or using the Dou-
ble Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.
When V PP/W rite Pro te ct is L ow , VIL, the memo ry
protects the two outermost boot blocks; Program
and Erase operation s i n these blocks are ignored
while V PP/Write Protect is Low, even when RP is
at VID.
When VPP/Write Protect is High, VIH, the memor y
reverts to t he previous protection status of the two
out erm os t bo ot bl ock s . Program and Erase oper-
ations can now modify the data in these blocks un-
less the blocks are protected using Block
Protection.
When VPP/Write Protect i s raised to VPP the mem-
ory automati cally enters the Unlock Bypass mode.
When V PP/Write Protect returns to VIH or VIL nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of th e Unlock B y pass c ommand in the
Command Interface section. The transitions from
VIH to VPP and from VPP to VIH must be slower
than tVHVPP, see Figur e 16.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterm inat e state.
The V PP/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should be connected be-
tween the VPP/Write Protect pin and the VSS
Ground pin to decouple the current surges from
the po wer su pp ly. Th e PCB t ra c k wi dths m u s t be
sufficient to carry the currents required during
Unlock Bypa ss Progra m , IPP.
Reset/Block Temporar y Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily u nprotect al l Block s that have been
protected.
Note th at if V PP/WP is at VIL, then the two outer-
most bo ot blocks will rem ain protected even if RP
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See t he Ready/Busy
Output section, Table 16 and Figure 15, Reset/
Temporary Unprotect AC Characteristi cs for more
details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
M29DW323D T, M29DW323DB
12/49
Ready/Busy is Low, V OL. Ready/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend m ode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes h igh-impeda nc e. See Tabl e 16 and Figure
15, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or m ore, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x 16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, VIH, the memory is in x16 m ode.
VCC Supply Voltage (2.7V to 3.6V). VCC pro-
vides the power supply for all operations (Read,
Program and Eras e).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, I CC3.
VSS Ground. VSS is the reference for all voltage
measuremen ts. The device f eatu res two VSS pins
which must be both connected to the system
ground.
13/49
M29DW323DT, M29DW323DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out-
put Disable, Standby and Automatic Standby.
The Dual Bank architecture of the M29 DW323 al-
lows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a tim e.
See Tables 3 and 4, Bus Operations, for a summa-
ry. Typically glitches o f less t han 5ns o n Chi p E n-
able or Write Enable are ignored by the memory
and do not affect b us operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, appl ying a Low s ig nal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Input s/Ou tputs will output the
value, see Figure 12, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Dat a Input s/Outpu ts a re latched by the Com -
mand Interface on the rising edge of Chip Enab le
or Write Enable, whichever occurs first. Output En-
able must remai n High, VIH, du ring the whole Bus
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 14 and 15, Write AC
Characteristics, for details of the timing require-
ments.
Outp ut Disabl e. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For t he Standby current
level see Table 12, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operat ion com pletes .
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programmi ng eq uip-
ment and are not usually used in applications.
They require VID to be applied to som e pins.
Electronic Sign atur e. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These co des can be re ad by app lying the signals
listed in T able s 3 and 4, Bus Operations.
Block Protect and
Chip Unprotect.
Groups of
blocks can be protected against accidental Pro-
gram or Er ase. T he Pr otec tion G roups are shown
in Appendix A, Tables 21 and 22, B lock Add ress-
es. The whole chip can be unprotected to allow the
data inside the blocks to be changed.
The VPP/Write Protec t pi n can be u sed to pr ot ect
the two outermost boot blocks. When VPP/Write
Protect is at VIL the two outermost boot blocks are
protect ed and remain protec ted regard l ess of t he
Block Protection Status or the Reset/Block Tem-
porary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in Appendix D.
M29DW323D T, M29DW323DB
14/49
Table 3. Bus Operations, BYTE = VIL
No te: X = VIL or VIH.
Table 4. Bus Operations, BYTE = VIH
No te: X = VIL or VIH.
Operation E G W Address Inputs
DQ15A–1, A0-A20 Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z 20h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL,
A9 = VID, Others VIL or VIH Hi-Z 5Eh (M29DW323D T)
5Fh (M29DW323DB)
Extended Memory
Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH Hi-Z 81 h (factor y locked)
01h (not factory locked)
Operation E G W Address Inputs
A0-A20 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH X Hi-Z
Standby VIH X X X Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH 0020h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH 225Eh (M29DW323DT)
225Fh (M29DW323DB)
Extended Memory
Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH 8 1h (factor y locked)
01h (not factory locked)
15/49
M29DW323DT, M29DW323DB
COMMAND INTERFACE
All Bus Write operations t o the memory are in ter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the mem ory is in 16-bit or 8-
bit mode. See e ither Table 5, or 6, depending on
the configuration that is being used, for a summary
of the com m ands .
Read/Reset Comm and
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. If the Read/Reset comm and is issued
during the timeout of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.
Auto Select Co mmand
The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. It can be addressed to either Bank.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select comm and. The f i-
nal Write cycle must be addressed to one of the
Banks. Once the Auto Select command is issued
Bus Read operat ions to t he B an k where the com-
mand was issued output the Auto Select data. Bus
Read operat ions to the other Bank will output t he
contents of the memory array. The memory re-
mains i n Auto Select mode until a Re ad/Reset or
CFI Query command is issued.
In Auto Select mode the Manufacturer Code can
be read using a Bus Read operation with A0 = VIL
and A1 = VIL and A19-A20 = Bank Address. The
other address bits may be set to either VIL or VIH.
The Device Code can b e read using a Bus Read
operation with A0 = VIH and A1 = VIL and A19-A20
= Bank Address. The other address bits may be
set to either VIL or VIH.
The B lock P rot ection S t atus of e ac h bl ock can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, A19-A20 = Ban k Address and A 12-A17
specifying the address of the block inside the
Bank. The ot her a ddres s bit s ma y be set to eit her
VIL or V IH. If the addressed block is protected then
01h is output on Data Inputs/Outputs DQ0-DQ7,
otherwise 00h is output.
Read CFI Query Comman d
The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the de-
vice is in the Read Array mode, or when the device
is in Autos ele c t e d mo de.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequen t Bus Read ope ratio ns read from
the Common Flash Interface Memory Area .
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Autos elect ed mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect -
ed mode.
See Appendix B, Tables 23, 24, 25, 26, 27 and 28
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Progra m Command
The Program command can be used to program a
value to one address in the memory array at a
time. The comm and requires four Bus Write oper-
ations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. T he Status Register is never read and
no error condition is given.
During the program o peration the memory will ig-
nore all co mmands. I t is not pos sible to iss ue any
command to abort or pause the operation. After
programming has started, Bus Read operations in
the Bank being programmed output the Status
Register content, while Bus Read operations to
the other Bank output the conten ts of the memory
array. See the section on the Status Register for
more details. Typical program times are given in
Table 7.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return t o Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
M29DW323D T, M29DW323DB
16/49
Fast Program Commands
There are two Fast P rogram com man ds availab le
to improve the programming throughput, by writing
several adjacent words or bytes in parallel. The
Quadruple Byte Program command is available for
x8 operations, while the Double Word Program
command is availab le for x16 operations.
Quadr uple Byte Progr am Command. The Qua-
druple Byte Program command is used to write a
page of four adjacent Bytes in parallel. The four
bytes must differ only for addresses A0, DQ15A-1.
Five bus write cycles are necessary to issue the
Quadru ple Byte Progra m command .
■The first bus cycle sets up the Q uadrupl e Byte
Program Command.
■The second bus cycle latches the Address and
the Data of the first byte to be written .
■The third bus cycle latches the Address and the
Data of th e second byte to be written.
■The fourth bus cycle lat ches the Address and
the Data of the third byte to be written.
■The f if th b us cycl e latches th e Ad dr es s and th e
Data of th e fourth byte to be written and sta rts
the Program/Erase Controlle r.
Double Word Prog r am Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must dif fer only for the address A0.
Three bus write cycles are n eces sary to issue the
Double Word Program command.
■The first bus cycle sets up the Double Word
Program Command.
■The second bus cycle latches the Address and
the Data of the first word to be wri tten.
■The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controlle r.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Programming should not be attempted when VPP
is not at VPPH.
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read opera-
tions to t he other B ank o utpu t the cont ents of t he
mem o ry ar ra y.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return t o Read mode.
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the w hole m emo ry from ’0’ to ’1’.
Typical Program times are given in Tab le 7, Pro-
gram, Erase Times and Program/Erase Endur-
ance Cycles.
Unlock Bypass Comma nd
The Unlock Bypas s com mand is used in co njunc-
tion wit h the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long (as with some EPROM program-
mers) considerable time saving can be made by
using these commands. Three Bus Write opera-
tions are required to issue the Unlock Bypass
command.
Once the Unlock Bypass command has been is-
sued the bank enters Unlock Bypass mode. The
Unlock Bypass Program command can then be is-
sued to program addresses within the bank, or the
Unlock Bypass Reset command can be issued to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin
the memory automatically enters the Unlock By-
pass mode and the Unlock Bypass Program com-
mand can be issued immediately.
Unlock Bypass Prog ram Comm an d
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. The
operation cannot be aborted, a Bus Read opera-
tion to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Comman d
The Unlock B ypass R ese t comm and c an b e us ed
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
Chip Erase Command
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are re-
quired to issue the Chip Erase Command and start
the Program/Erase Controller.
If an y blocks are protected then these are ignored
and all the other blocks are erased. If all of the
17/49
M29DW323DT, M29DW323DB
blocks a re p rote cted the Chip Erase op erat i on ap-
pears to start but will terminate within about 100µs,
leaving the data unchange d. No error co ndition is
given when protected blocks are ignored.
During the erase operation the memory wil l ignore
all commands , including the E rase Suspen d com-
mand. It is no t possible to i ssue any c ommand t o
abort the operation. Typical chip erase times are
given in Table 7. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
After the Chip Erase operation has com pleted the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set th e error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command
The B lock Erase com mand can be used to erase
a list of one or more blocks in a Bank. It sets all of
the bits in the unprotected selected blocks to ’1’.
All previous data in the selected blocks is lost.
Six Bus Wr it e operations are required to select the
first block in the list. Each additional block in the
list can be selected by repeating the sixth Bus
Write operation using the address of the additional
block. All blocks must belon g to the same Bank; if
a block belon ging to the ot her B ank is gi ven it wi ll
not be erased. The Block Erase operation starts
the Program /Erase Controller after a t ime-out pe-
riod of 50µs after the last Bus Write operation.
Onc e the Program /Erase Controller starts it is not
possible to select any more blocks. Each addition-
al block must therefore be sel ec ted within 50µs of
the last block. The 50µs timer restarts when an ad-
ditional block is selected. After the sixth Bus Write
operation a Bus Read operation within the same
Ban k w ill output the S tatus R eg i s ter . See th e Sta -
tus Register section for det ails on how t o identify i f
the Program/Erase Controller has started the
Block Erase operation .
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condit ion is given when protect-
ed blocks are igno red.
During the Blo ck Erase ope ra tion the me mory will
ignore all commands except the Erase Suspend
command and the Read/Reset command which is
only accepted during the 50µs time-out period.
Typical block erase times are given in Table 7.
After the Erase operati on has started all Bus Read
operations to the Bank being erased will output the
Status Register on the Data Inputs/Outputs. See
the section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return t o Read mode.
Erase Suspend Comm and
The Erase Suspend Command may be used to
temporarily sus pend a Block E rase operation and
return the m emory to Read mode. T he comm and
requires one Bus Write operation.
The Program/Er ase Cont roller will sus pend within
the Erase Suspend Latency time of the Erase Sus-
pend Comman d being issued. Onc e the Program/
Erase Controller has stopped the memory will be
set to Read m ode and the E rase wi ll be suspend-
ed. If the Erase Sus pen d c ommand is issued dur-
ing the period when the memory is waiting for an
additional block (before the Program/Erase Con-
troller starts) then the Erase is suspended immedi-
ately and will start immediately when the Erase
Resume Com mand is issued. It is not poss ible to
select any further blocks to erase after the Erase
Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protec ted bl ock or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Regis ter
is not read and no error condi tio n is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
During Erase Suspend a Bus Read operation to
the Extended Block will output the Extended Block
data.
Erase Resum e Command
The Erase Resume command must be used t o re-
start the Program/Erase Co ntroller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be s uspended and res um ed mo re t han
once.
M29DW323D T, M29DW323DB
18/49
Enter Extended Block Comman d
The M29DW323D has an extra 64KByte block
(Extended Block) that can only be accessed using
the Enter Extended Block command. Three Bus
write cycles are required to issue the Extended
Block command. Once the command has been is-
sued the device enters Extended Block mode
where all Bus Read or Program operations to the
Boot Block addresses access the Extended Block.
The Extended Block (with the same address as
the boot block) cannot be erased, and can be
treated as one-time prog rammabl e (OTP) m emo-
ry. In Extended Block mode the Boot Blocks are
not accessible. In Extended Block mode dual op-
erations are possible, with the Extended Block
mapped in Bank A. When in Extended Block
mode, Erase Commands in Bank A are not al-
lowed.
To exit from the Extended Block mode the Exit Ex-
tended Block command must be issued.
The Extended Block can be protected, however
once protected the protection cannot be undone.
Exit Extended B lo ck Com m a n d
The Exit Extended B lock comm and is us ed to exit
from the Extended Block mod e and ret urn t he de-
vice to Read mode. Four Bus Write operations are
required to issue the command.
Block Protect and Chip Unprotect Commands
Groups of blocks can be protected against acci-
dental Program or Erase. The Protection Groups
are shown in Appendix A, Tables 21 and 22, Block
Addresses. The who le chip can be unprot ected to
allow the data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix D.
Table 5. Command s, 16-bit mode, BYTE = VIH
Note: X Don’t Ca r e, PA Pr ogr am Add re ss , PD Pro g ram Data , BA Any add ress in the Blo ck, BKA Ban k Ad d ress . Al l va l u es i n the ta b l e ar e in
hexadecimal.
Th e Com ma nd In terf ace o nl y us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he com man ds; A1 1-A 20, DQ 8-DQ1 4 a nd DQ 15 ar e Don’ t
Care. DQ15A–1 i s A–1 when B Y T E is VIL or DQ15 when BYTE is VIH.
Command
Length
Bus Write Operation s
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 (BKA)
555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Double Word Program 3 555 50 PA0 PD0 PA1 PD1
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 BKA B0
Erase Resume 1 BKA 30
Read CFI Query 1 55 98
Enter Extended Block 3 555 AA 2AA 55 555 88
Exit Extended Block 4 555 AA 2AA 55 555 90 X 00
19/49
M29DW323DT, M29DW323DB
Table 6. Commands, 8-bit mode, BYTE = VIL
Note: X Don’t Care, PA Prog ram Add ress, P D P rogr a m Data, B A Any addre ss i n the Blo ck. All values i n the tabl e are in hexa decim al .
Th e Com ma nd Inte rfac e onl y us es A – 1, A0-A 1 0 and DQ 0-D Q7 to v erify the co mman ds ; A1 1-A2 0, D Q8- DQ14 and DQ 15 are D on’t
Care. DQ15A–1 i s A–1 when B Y T E is VIL or DQ15 when BYTE is VIH.
Table 7. Program , Erase Times and Progra m , Erase Endu ran ce Cycles
No te : 1. T ypica l v al ues measu red at room tem pera ture and nomi nal volt ages.
2. Sampled, but not 100% tested.
3. Max imum va lu e m easu red at worst cas e cond i tions for both tem pera ture and VCC after 100 ,0 0 progr am /er ase cycles.
4. Max imum va lu e m easu red at worst cas e cond i tions for both tem pera ture and VCC.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 (BKA)
AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Quadruple Byte Program 5 AAA 55 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 BKA B0
Erase Resume 1 BKA 30
Read CFI Query 1 AA 98
Enter Extended Block 3 AAA AA 555 55 AAA 88
Exit Extended Block 4 AAA AA 555 55 AAA 90 X 00
Parameter Min Typ (1, 2) Max(2) Unit
Chip Erase 40 200(3) s
Block Erase (64 KBytes) 0.8 6(3) s
Erase Suspend Latency Time 50(4) µs
Program (Byte or Word) 10 200(4) µs
Double Word Program (Byte or Word) 10 200(3) µs
Chip Program (Byte by Byte) 40 200(3) s
Chip Program (Word by Word) 20 100(3) s
Chip Program (Quadruple Byte or Double Word) 10 100(3) s
Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years
M29DW323D T, M29DW323DB
20/49
STATUS REGISTER
The M29DW323D has two Status Registers, one
for each bank. The Status Registers provide infor-
mation on the current or previous Program or
Erase operations executed in each bank. The var-
ious bits convey information and errors on the op-
eration. Bus Read operations from any address
within the Bank, always read the Status Register
during Program and Erase operations. It is also
read during Erase Suspend when an address with-
in a block being erased is accessed.
The bits in the Status Register are s um marized in
Table 8, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is re ad.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operatio ns the Data Polling Bi t ou t-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to R ead Mod e.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has sus pe nded the Erase operat ion.
Figure 8, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A V alid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Togg le Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspen d. The To ggle Bit is
output on DQ6 when the Status Register is re ad.
During Program and Erase operations the Toggle
Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will s top toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 9 , Data Toggle Flowchart, g ives an exam-
ple of how to u se the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Rea d/Re se t comm and must be issued
before other command s are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dres s w ill s how th e bit is s ti ll ‘0’. One of the E r as e
commands must be used to set all the bits in a
block or in the w hole m emo ry from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the E rase Ti mer Bit is set to ’1’ . Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional block s to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative T oggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is re ad.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Re ad operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased wi ll output
the memory cell data as i f in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Altern ative Toggle Bit ch anges from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Togg le Bit does
not change if the addressed block has erased cor-
rectly.
21/49
M29DW323DT, M29DW323DB
Table 8. Status Regi ster Bits
No te : Unspeci fied data bi ts should be ig nore d.
Figu re 8. Da ta Po lli ng Fl owchart Figu r e 9. Da ta To ggle F l owchart
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Bank Address DQ7 Toggle 0 ––0
Program During Erase
Suspend Bank Address DQ7 Toggle 0 – – 0
Program Error Bank Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1
Non-Erasing Block Data read as normal 1
Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI90194
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
READ DQ6
START
READ DQ6
TWICE
FAIL PASS
AI90195B
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
M29DW323D T, M29DW323DB
22/49
MAX I MUM R A T I N G
Stressing the device above the rating l isted in t he
Absolute Maxi mum Ratings table m ay cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indic at-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 9. Absolute Maximum Ratings
Note: 1. M in i m um volta ge may undershoo t t o –2V during transition and for les s t han 20ns during transitions.
2. Max imum vo ltage may oversho ot to VCC +2V duri ng tra nsitio n and fo r l ess than 20ns during transitions.
3. VPP must not remai n at 12V f or m ore than a total of 80 hrs.
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V
VCC Supply Voltage –0.6 4 V
VID Identification Voltage –0.6 13.5 V
VPP(3) Program Voltage –0.6 13.5 V
23/49
M29DW323DT, M29DW323DB
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, a nd the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 10, Operating
and AC Measurement Conditions. Designers
should check that the operati ng conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 10. Operating and AC Measurem en t Conditions
Figu re 10 . AC Meas ureme nt I/ O Wa veform Figu re 11 . AC Meas ureme nt Load C ir cui t
Table 11. Device Capacitance
No te : Sam pled only, not 100% test ed.
Parameter
M29DW323D
Unit70 90
Min Max Min Max
VCC Supply Voltage 3.0 3.6 2.7 3.6 V
Ambient Operati ng Tem peratur e –40 85 –40 85 °C
Load Capacitance (CL)30 30 pF
Input Rise and Fall Times 10 10 ns
Input Pulse Voltages 0 to VCC 0 to VCC V
Input and Output Timing Ref. Voltages VCC/2 VCC/2 V
AI05557
VCC
0V
VCC/2
AI05558
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25kΩ
VCC
25kΩ
VCC
0.1µF
VPP
0.1µF
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6pF
C
OUT Output Capacitance VOUT = 0V 12 pF
M29DW323D T, M29DW323DB
24/49
Table 12. DC Characteristics
Note: 1. Sampled only, not 100% tested.
2. In Dual operations th e Supply Current will be the sum of ICC1(rea d) and ICC3 (program/erase).
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA
ICC1(2) Supply Current (Read) E = VIL, G = VIH,
f = 6MHz 10 mA
ICC2 Supply Current (Standby) E = VCC ±0.2V,
RP = VCC ±0.2V 100 µA
ICC3 (1,2) Supply Current (Program/
Erase) Program/Erase
Controller active
VPP/WP =
VIL or VIH 20 mA
VPP/WP = VPP 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC +0.3 V
VPP Voltage for VPP/WP Program
Acceleration VCC = 3.0V ±10% 11.5 12.5 V
IPP Current for VPP/WP Program
Acceleration VCC = 3.0V ±10% 15 mA
VOL Output Low Voltage IOL = 1.8mA 0.45 V
VOH Output High Voltage IOH = –100µAVCC –0.4 V
VID Identification Voltage 11.5 12.5 V
VLKO Prog ram/Erase Loc kout Supply
Voltage 1.8 2.3 V
25/49
M29DW323DT, M29DW323DB
Figure 12. Read Mode AC Waveforms
Table 13. Read AC Characteristics
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter Test Condition M29DW323D Unit
70 90
tAVAV tRC Address Valid to Next Address Valid E = VIL,
G = VIL Min 70 90 ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G = VIL Max 70 90 ns
tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns
tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 ns
tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns
tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 ns
tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 30 ns
tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 30 ns
tEHQX
tGHQX
tAXQX tOH Chip Enable, Output Enable or Address
Transition to Output Transition Min 0 0 ns
tELBL
tELBH tELFL
tELFH Chip Enable to BYTE Low or High Max 5 5 ns
tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns
tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns
AI05559
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A20/
A–1
G
DQ0-DQ7/
DQ8-DQ15
E
tELQV tEHQX
tGHQZ
VALID
tBHQV
tELBL/tELBH tBLQZ
BYTE
M29DW323D T, M29DW323DB
26/49
Figure 13. Write AC Waveforms, Wr ite Enable Controlled
Table 14. Write AC Characteristics, Write Enable Controlle d
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29DW323D Unit
70 90
tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 45 50 ns
tDVWH tDS Input Valid to Write Enable High Min 45 50 ns
tWHDX tDH Write Enable High to Input Transition Min 0 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns
tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns
tWLAX tAH Write Enable Low to Address Transition Min 45 50 ns
tGHWL Output Enable High to Write Enable Low Min 0 0 ns
tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns
tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns
tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs
AI05560
E
G
W
A0-A20/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
27/49
M29DW323DT, M29DW323DB
Figure 14. Write AC Waveforms, Chip Enable Control led
Table 15. W rite AC Characteristics, Chip Enable Controlled
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29DW323D Unit
70 90
tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 45 50 ns
tDVEH tDS Input Valid to Chip Enable High Min 45 50 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 ns
tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns
tELAX tAH Chip Enable Low to Address Transition Min 45 50 ns
tGHEL Output Enable High Chip Enable Low Min 0 0 ns
tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns
tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns
tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs
AI05561
E
G
W
A0-A20/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
M29DW323D T, M29DW323DB
28/49
Figure 15. Reset/Block Tem porary Unp rotec t AC Wavefo rms
Table 16. Reset/Block Temporary Unprotect AC Characteristics
Note: 1. Sampled only, not 100% tested.
Figure 16. Accelera ted Progr am Timing Wavefo rm s
Symbol Alt Parameter M29DW323D Unit
70 90
tPHWL (1)
tPHEL
tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 50 50 ns
tRHWL (1)
tRHEL (1)
tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 0 0 ns
tPLPX tRP RP Pulse Width Min 500 500 ns
tPLYH tREADY RP Low to Read Mode Max 50 50 µs
tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns
tVHVPP (1) VPP Rise and Fall Time Min 250 250 ns
AI02931B
RB
W,
RP tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
tRHWL, tRHEL, tRHGL
AI05563
VPP/WP
VPP
VIL or VIH tVHVPP tVHVPP
29/49
M29DW323DT, M29DW323DB
PACKAGE MECHANICAL
Figure 17. TS O P4 8 Lead Plastic Thin Smal l Outline , 12x20 mm, Bottom View P ackag e Outlin e
Note: Drawing not to scale.
Table 17. TS OP 48 Lea d Plastic Thin Sm all Outline, 12x20 mm , Packag e Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.080 0.0031
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
L1 0.800 0.0315
α305305
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
M29DW323D T, M29DW323DB
30/49
Figure 18. TF BGA6 3 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Packa ge Outline
Note: Drawing not to scale.
Table 18. TFBG A63 7x11mm - 6x8 Ball Array, 0.8mm P itch, Package Mech an ical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.250 0.0098
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 7.000 6.900 7.100 0.2756 0.2717 0.2795
D1 5.600 – – 0.2205 – –
ddd – – 0.100 – – 0.0039
E 11.000 10.900 11.100 0.4331 0.4291 0.4370
E1 8.800 – – 0.3465 – –
e 0.800 – – 0.0315 – –
FD 0.700 – – 0.0276 – –
FE 1.100 – – 0.0433 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
E
D
eb
SD
SE
A2
A1
A
BGA-Z33
ddd
FD
D1
E1
e
FE
BALL "A1"
31/49
M29DW323DT, M29DW323DB
Figure 19. TF BGA4 8 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Packag e Outline
Note: Drawing not to scale.
Table 19. TFBG A48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Packag e Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 4.000 – – 0.1575 – –
ddd 0.100 0.0039
E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.600 – – 0.2205 – –
e 0.800 – – 0.0315 – –
FD 1.000 – – 0.0394 – –
FE 1.200 – – 0.0472 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
E1E
D1
D
eb
A2
A1
A
BGA-Z32
ddd
FD
FE SD
SE
e
BALL "A1"
M29DW323D T, M29DW323DB
32/49
PAR T NUMBERING
Table 20. Ordering Information Scheme
Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest ST sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a l ist of a vailable opt ions (Speed, P ackage, et c...) or for further information on any as pe ct of t his de-
vice, please contact the ST Sales Office nearest to you.
Example: M29DW323DB 70 N 1 T
Device Type
M29
Architecture
D = Dual Bank
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
323D = 32 Mbit (x8/x16), Boot Block, 1/4-3/4 partitioning
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
ZA = TFBGA63: 7 x 11mm, 0.80 mm pitch
ZE = TFBGA48: 6 x 8mm, 0.8mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
33/49
M29DW323DT, M29DW323DB
APPENDIX A. BL OCK ADDRESSES
Table 21. T op Boot Block Addresse s, M29DW32 3DT
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
Bank B
0 64/32 Protection Group 000000h–00FFFFh 000000h–07FFFh
1 64/32
Protection Group
010000h–01FFFFh 008000h–0FFFFh
2 64/32 020000h–02FFFFh 010000h–17FFFh
3 64/32 030000h–03FFFFh 018000h–01FFFFh
4 64/32
Protection Group
040000h–04FFFFh 020000h–027FFFh
5 64/32 050000h–05FFFFh 028000h–02FFFFh
6 64/32 060000h–06FFFFh 030000h–037FFFh
7 64/32 070000h–07FFFFh 038000h–03FFFFh
8 64/32
Protection Group
080000h–08FFFFh 040000h–047FFFh
9 64/32 090000h–09FFFFh 048000h–04FFFFh
10 64/32 0A0000h–0AFFFFh 050000h–057FFFh
11 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
12 64/32
Protection Group
0C0000h–0CFFFFh 060000h–067FFFh
13 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
14 64/32 0E0000h–0EFFFFh 070000h–077FFFh
15 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
16 64/32
Protection Group
100000h–10FFFFh 080000h–087FFFh
17 64/32 110000h–11FFFFh 088000h–08FFFFh
18 64/32 120000h–12FFFFh 090000h–097FFFh
19 64/32 130000h–13FFFFh 098000h–09FFFFh
20 64/32
Protection Group
140000h–14FFFFh 0A0000h–0A7FFFh
21 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
22 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
23 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
24 64/32
Protection Group
180000h–18FFFFh 0C0000h–0C7FFFh
25 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
26 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
27 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh
28 64/32
Protection Group
1C0000h–1CFFFFh 0E0000h–0E7FFFh
29 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
30 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh
31 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
M29DW323D T, M29DW323DB
34/49
Bank B
32 64/32
Protection Group
200000h–20FFFFh 100000h–107FFFh
33 64/32 210000h–21FFFFh 108000h–10FFFFh
34 64/32 220000h–22FFFFh 110000h–117FFFh
35 64/32 230000h–23FFFFh 118000h–11FFFFh
36 64/32
Protection Group
240000h–24FFFFh 120000h–127FFFh
37 64/32 250000h–25FFFFh 128000h–12FFFFh
38 64/32 260000h–26FFFFh 130000h–137FFFh
39 64/32 270000h–27FFFFh 138000h–13FFFFh
40 64/32
Protection Group
280000h–28FFFFh 140000h–147FFFh
41 64/32 290000h–29FFFFh 148000h–14FFFFh
42 64/32 2A0000h–2AFFFFh 150000h–157FFFh
43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
44 64/32
Protection Group
2C0000h–2CFFFFh 160000h–167FFFh
45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
46 64/32 2E0000h–2EFFFFh 170000h–177FFFh
47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
Bank A
48 64/32
Protection Group
300000h–30FFFFh 180000h–187FFFh
49 64/32 310000h–31FFFFh 188000h–18FFFFh
50 64/32 320000h–32FFFFh 190000h–197FFFh
51 64/32 330000h–33FFFFh 198000h–19FFFFh
52 64/32
Protection Group
340000h–34FFFFh 1A0000h–1A7FFFh
53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
56 64/32
Protection Group
380000h–38FFFFh 1C0000h–1C7FFFh
57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
60 64/32
Protection Group
3C0000h–3CFFFFh 1E0000h–1E7FFFh
61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
35/49
M29DW323DT, M29DW323DB
Note: 1. Used as the Extended Blo ck Ad dres ses in Ext ended Block mode.
Bank A
63 8/4 Protection Group 3F0000h–3F1FFFh(1) 1F8000h–1F8FFFh(1)
64 8/4 Protection Group 3F2000h–3F3FFFh(1) 1F9000h–1F9FFFh(1)
65 8/4 Protection Group 3F4000h–3F5FFFh(1) 1FA000h–1FAFFFh(1)
66 8/4 Protection Group 3F6000h–3F7FFFh(1) 1FB000h–1FBFFFh(1)
67 8/4 Protection Group 3F8000h–3F9FFFh(1) 1FC000h–1FCFFFh(1)
68 8/4 Protection Group 3FA000h–3FBFFFh(1) 1FD000h–1FDFFFh(1)
69 8/4 Protection Group 3FC000h–3FDFFFh(1) 1FE000h–1FEFFFh(1)
70 8/4 Protection Group 3FE000h–3FFFFFh(1) 1FF000h–1FFFFFh(1)
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
M29DW323D T, M29DW323DB
36/49
Table 22. Bottom Boot Block Addresses, M29DW323DB
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
Bank A
0 8/4 Protection Group 000000h-001FFFh(1) 000000h–000FFFh(1)
1 8/4 Protection Group 002000h-003FFFh(1) 001000h–001FFFh(1)
2 8/4 Protection Group 004000h-005FFFh(1) 002000h–002FFFh(1)
3 8/4 Protection Group 006000h-007FFFh(1) 003000h–003FFFh(1)
4 8/4 Protection Group 008000h-009FFFh(1) 004000h–004FFFh(1)
5 8/4 Protection Group 00A000h-00BFFFh(1) 005000h–005FFFh(1)
6 8/4 Protection Group 00C000h-00DFFFh(1) 006000h–006FFFh(1)
7 8/4 Protection Group 00E000h-00FFFFh(1) 007000h–007FFFh(1)
8 64/32
Protection Group
010000h-01FFFFh 008000h–00FFFFh
9 64/32 020000h-02FFFFh 010000h–017FFFh
10 64/32 030000h-03FFFFh 018000h–01FFFFh
11 64/32
Protection Group
040000h-04FFFFh 020000h–027FFFh
12 64/32 050000h-05FFFFh 028000h–02FFFFh
13 64/32 060000h-06FFFFh 030000h–037FFFh
14 64/32 070000h-07FFFFh 038000h–03FFFFh
15 64/32
Protection Group
080000h-08FFFFh 040000h–047FFFh
16 64/32 090000h-09FFFFh 048000h–04FFFFh
17 64/32 0A0000h-0AFFFFh 050000h–057FFFh
18 64/32 0B0000h-0BFFFFh 058000h–05FFFFh
19 64/32
Protection Group
0C0000h-0CFFFFh 060000h–067FFFh
20 64/32 0D0000h-0DFFFFh 068000h–06FFFFh
21 64/32 0E0000h-0EFFFFh 070000h–077FFFh
22 64/32 0F0000h-0FFFFFh 078000h–07FFFFh
Bank B
23 64/32
Protection Group
100000h-10FFFFh 080000h–087FFFh
24 64/32 110000h-11FFFFh 088000h–08FFFFh
25 64/32 120000h-12FFFFh 090000h–097FFFh
26 64/32 130000h-13FFFFh 098000h–09FFFFh
27 64/32
Protection Group
140000h-14FFFFh 0A0000h–0A7FFFh
28 64/32 150000h-15FFFFh 0A8000h–0AFFFFh
29 64/32 160000h-16FFFFh 0B0000h–0B7FFFh
30 64/32 170000h-17FFFFh 0B8000h–0BFFFFh
37/49
M29DW323DT, M29DW323DB
Bank B
31 64/32
Protection Group
180000h-18FFFFh 0C0000h–0C7FFFh
32 64/32 190000h-19FFFFh 0C8000h–0CFFFFh
33 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh
34 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh
35 64/32
Protection Group
1C0000h-1CFFFFh 0E0000h–0E7FFFh
36 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh
37 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh
38 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh
39 64/32
Protection Group
200000h-20FFFFh 100000h–107FFFh
40 64/32 210000h-21FFFFh 108000h–10FFFFh
41 64/32 220000h-22FFFFh 110000h–117FFFh
42 64/32 230000h-23FFFFh 118000h–11FFFFh
43 64/32
Protection Group
240000h-24FFFFh 120000h–127FFFh
44 64/32 250000h-25FFFFh 128000h–12FFFFh
45 64/32 260000h-26FFFFh 130000h–137FFFh
46 64/32 270000h-27FFFFh 138000h–13FFFFh
47 64/32
Protection Group
280000h-28FFFFh 140000h–147FFFh
48 64/32 290000h-29FFFFh 148000h–14FFFFh
49 64/32 2A0000h-2AFFFFh 150000h–157FFFh
50 64/32 2B0000h-2BFFFFh 158000h–15FFFFh
51 64/32
Protection Group
2C0000h-2CFFFFh 160000h–167FFFh
52 64/32 2D0000h-2DFFFFh 168000h–16FFFFh
53 64/32 2E0000h-2EFFFFh 170000h–177FFFh
54 64/32 2F0000h-2FFFFFh 178000h–17FFFFh
55 64/32
Protection Group
300000h-30FFFFh 180000h–187FFFh
56 64/32 310000h-31FFFFh 188000h–18FFFFh
57 64/32 320000h-32FFFFh 190000h–197FFFh
58 64/32 330000h-33FFFFh 198000h–19FFFFh
59 64/32
Protection Group
340000h-34FFFFh 1A0000h–1A7FFFh
60 64/32 350000h-35FFFFh 1A8000h–1AFFFFh
61 64/32 360000h-36FFFFh 1B0000h–1B7FFFh
62 64/32 370000h-37FFFFh 1B8000h–1BFFFFh
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
M29DW323D T, M29DW323DB
38/49
Note: 1. Used as the Extended Blo ck Ad dres ses in Ext ended Block mode.
Bank B
63 64/32
Protection Group
380000h-38FFFFh 1C0000h–1C7FFFh
64 64/32 390000h-39FFFFh 1C8000h–1CFFFFh
65 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh
66 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh
67 64/32
Protection Group
3C0000h-3CFFFFh 1E0000h–1E7FFFh
68 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh
69 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh
70 64/32 Protection Group 3F0000h-3FFFFFh 1F8000h–1FFFFFh
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
39/49
M29DW323DT, M29DW323DB
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system sof tware t o query the de vice t o det ermine
various electrical and timing parameters, density
information and functions supported by t he mem-
ory. The system can interface easily with the de-
vice, enabling the s oftware to upgrad e itse lf when
necessary.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
is read from the memory. Tables 23, 24, 25, 26, 27
and 28 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique securit y number is writ-
ten (see Table 28, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impos sible to change t he secu ri ty num-
ber after it has been written by ST.
Table 23. Query Structure Overview
Note: Query data are always presented on the lowest order data outputs.
Table 24. CFI Query Identification String
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Address Sub-section Name Description
x16 x8
10h 20h CFI Query Identification String Command set ID and algorithm data offset
1Bh 36h System Interface Information Device timing & voltage information
27h 4Eh Device Geometry Definition Flash device layout
40h 80h Primary Algorithm-specific Extended
Query table Additional information specific to the Primary
Algorithm (optional)
61h C2h Security Code Area 64 bit unique device number
Address Data Description Value
x16 x8
10h 20h 0051h “Q”
11h 22h 0052h Query Unique ASCII String "QRY" "R"
12h 24h 0059h "Y"
13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algori thm AMD
Compatible
14h 28h 0000h
15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 27) P = 40h
16h 2Ch 0000h
17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported NA
18h 30h 0000h
19h 32h 0000h Address for Alternate Algorithm extended Query table NA
1Ah 34h 0000h
M29DW323D T, M29DW323DB
40/49
Table 25. CFI Query System In terface Information
Table 26. Device Geometry Definition
Note: The region information contained in addresses 2Dh to 34h (or 5Ah to 68h) is correct for the M29DW323DB. For the M29DW323DT the
regi ons mu st be reve rsed.
Address Data Description Value
x16 x8
1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV 2.7V
1Ch 38h 0036h VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV 3.6V
1Dh 3Ah 00B5h VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV 11.5V
1Eh 3Ch 00C5h VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV 12.5V
1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs
20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA
21h 42h 000Ah Typical timeout per individual block erase = 2n ms 1s
22h 44h 0000h Typical timeout for full chip erase = 2n ms NA
23h 46h 0004h Maximum timeout for byte/word program = 2n times typical 256 µs
24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA
25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 8s
26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical NA
Address Data Description Value
x16 x8
27h 4Eh 0016h Device Size = 2n in number of bytes 4 MByte
28h
29h 50h
52h 0002h
0000h Flash Device Interface Code description x8, x16
Async.
2Ah
2Bh 54h
56h 0000h
0000h Maximum number of bytes in multi-byte program or page = 2n NA
2Ch 58h 0002h Number of Erase Block Regions. It specifies the number of
regions containing contiguous Erase Blocks of the same size. 2
2Dh
2Eh 5Ah
5Ch 0007h
0000h Region 1 Information
Number of identical size erase block = 0007h+1 8
2Fh
30h 5Eh
60h 0020h
0000h Region 1 Information
Block size in Region 1 = 0020h * 256 byte 8Kbyte
31h
32h 62h
64h 003Eh
0000h Region 2 Information
Number of identical size erase block = 003Eh+1 63
33h
34h 66h
68h 0000h
0001h Region 2 Information
Block size in Region 2 = 0100h * 256 byte 64Kbyte
41/49
M29DW323DT, M29DW323DB
Table 27. Primary Algorithm- Speci fic Extended Qu ery Ta ble
Table 28. Security Code Area
Address Data Description Value
x16 x8
40h 80h 0050h
Primary Algorithm extended Query table unique ASCII string “PRI”
"P"
41h 82h 0052h "R"
42h 84h 0049h "I"
43h 86h 0031h Major version number, ASCII "1"
44h 88h 0030h Minor version number, ASCII "0"
45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h 8Ch 0002h Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write 2
47h 8Eh 0001h Block Protection
00 = not supported, x = number of blocks in per group 1
48h 90h 0001h Temporary Block Unprotect
00 = not supported, 01 = supported Yes
49h 92h 0004h Block Protect /Unprotect
04 = M29W400B 4
4Ah 94h 0030h Simultaneous Operations,
x = number of blocks in Bank B 48
4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No
4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No
4Dh 9Ah 00B5h VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5V
4Eh 9Ch 00C5h VPP Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5V
4Fh 9Eh 000xh Top/Bottom Boot Block Flag
02h = Bottom Boot device, 03h = Top Boot device –
Address Data Description
x16 x8
61h C3h, C2h XXXX
64 bit: unique device number
62h C5h, C4h XXXX
63h C7h, C6h XXXX
64h C9h, C8h XXXX
M29DW323D T, M29DW323DB
42/49
APPENDIX C. EXTENDED MEMORY BLOCK
The M29DW323D has an extra block, the Extend-
ed Block, that can be acces sed using a dedicat ed
command.
This Extended Block is 32 KWords in x16 mode
and 64 KBytes in x8 mode. It is used as a security
block (to provide a permanent security identifica-
tion n umb er) or to store add itional information.
The Extended Block is either Factory Locked or
Customer Lockable, its status is indicated by bit
DQ7. Th is bit is pe rmanently set to either ‘ 1’ or ‘ 0’
at the factory and cannot be changed. When set to
‘1’, it indicates that the device is factory locked and
the Extended Block is protected. When set to ‘0’, it
indicates that the device i s customer lockable and
the Extended Block is unprotected. Bi t DQ7 being
permanently locked to either ‘1’ or ‘0’ is another
security feature which ensures that a customer
lockable device cannot be used instead of a facto-
ry lock ed one.
Bit DQ7 is the most significant bit in the E xten ded
Block Verify Code and a specific procedure must
be followed to read it. See “Extended Memory
Block Ve rify Code ” in T ables 3 a nd 4, Bus Opera-
tions, BYTE = VIL and Bus Operations, BYTE =
VIH, respectively, for details of how to read bit
DQ7.
The Extended Block can only be accessed when
the device i s in Extended B lock m ode. Fo r det ails
of how the Extended Block mode is entered and
exited, refer to the Enter Extended Block Com-
mand and Exit Extended Block Command para-
graphs, and to Tables 5 and 6, “Commands, 16-bit
mod e , B YT E = V IH” and “Com m ands , 8-bit m ode,
BYTE = VIL”, respec tivel y.
Factory Locked Extend ed Block
In devices where the Extended Block is factory
locked, the Security Identification Number is writ-
ten to the Ex tended Block address space (see Ta-
ble 29, Extended Block Address and Data) in the
factory. The DQ7 bit is set to ‘1’ and the Exte nded
Block cannot be unprotec ted.
Customer Loc kable Extend ed Block
A device where the Extended Block is customer
lockable is delivered with the DQ7 bit set to ‘0’ and
the Extended Block unprotected. It is up to the
customer to program and protect the Extended
Block but care must be taken because the protec-
tion o f the Extended Block is not reversible.
There are two ways of protecting the Extended
Block:
■Issue the Enter Extended Block comm and to
place the device in Extended Block mode, then
use the In-System Technique (refer to Appendix
D, In-System Technique and to the
corresponding flowcharts, Figures 22 and 23,
for a detailed explanation of the technique).
■Issue the Enter Extended Block comm and to
place the device in Extended Block mode, then
use the Programmer Technique (refer to
Appendix D, Progr ammer Technique and to the
corresponding flowcharts, Figures 20 and 21,
for a detailed explanation of the technique).
Once the Extended Block is programmed and pro-
tected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return
the device to Read mode.
Table 29. Exten ded B lock Address and Data
Note: 1. See Tables 21 and 22, Top and Bottom Boot Block Addresses.
Device Address(1) Data
x8 x16 Factory Locked Customer Lockable
M29DW323DT 3F0000h-3F000Fh 1F8000h-1F8007h Security Identification
Number Determined by
Customer
3F0010h-3FFFFFh 1F8008h-1FFFFFh Unavailable
M29DW323DB 000000h-00000Fh 000000h-000007h Security Identification
Number Determined by
Customer
000010h-00FFFFh 000008h-007FFFh Unavailable
43/49
M29DW323DT, M29DW323DB
APPENDIX D. BLOCK PROTECTION
Block protection ca n be used to prevent any oper-
ation from modifying the data stored in the memo-
ry. The blocks are protected in groups, refer to
Appendix A, Tables 21 and 22 for details of the
Protection G roups. Once p rotected, P ro gram and
Erase operations within the protected group fail to
change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In- System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is des cribed in the S ign al De-
scri pt i ons sect ion.
Prog ram m er Techni q ue
The Programmer technique uses high (VID) volt-
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a group of blocks follow the flowchart in
Figure 20, Programmer Equipment Block Protect
Flowchart. To unprotect t he whole chip it is neces-
sary to protect all of the groups first, then all
groups can be unprotected at the same time. To
unprotect the chip follow Figure 21, Programmer
Equipment Chip Unprotect Flowchart. Table 30,
Programmer Technique Bus Operations, gives a
summary of each operation.
The timing on these flowcharts is critical. Care
should be taken t o ensure that, where a pau se is
specified, it is followed as cl osely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this tec hniqu e is suitable
for use after the memory has been fitted to the sys-
tem.
To protect a group of blocks follow the flowchart in
Figure 22, I n-S ystem Block Protect F lowchart . T o
unprotect the who le chip it is nece ssary to prot ect
all of the groups first, then all the groups can be
unprotected at the same time. To unprotect the
chip follow Figure 23, In-System Chip Unprotect
Flowchart.
The timing on these flowcharts is critical. Care
should be taken t o ensure that, where a pau se is
specified, it is followed as cl osely as possible. Do
not allow the m icroprocessor t o service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Table 30. Program mer Tech niqu e Bus Op erati ons, BYTE = VIH or VIL
Note: 1. Block Protec tion Groups are shown in A ppendix A, Tables 21 and 22.
Operation E G W Address Inputs
A0-A20 Data Input s/Out puts
DQ15 A–1, DQ14 -DQ0
Block (Group)
Protect(1) VIL VID VIL Pulse A9 = VID, A12-A20 Block Address
Others = X X
Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH
Others = X X
Block (Group)
Protection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9=V
ID,
A12-A20 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block (Group)
Unprotection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,
A12-A20 Block Address
Others = X
Retry = XX01h
Pass = XX00h
M29DW323D T, M29DW323DB
44/49
Figure 20. Programmer Equipment Group Protect Flowchart
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
ADDRESS = GROUP ADDRESS
AI05574
G, A9 = VID,
E = VIL
n = 0
Wait 4µs
Wait 100µs
W = VIL
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
A9 = VIH
E, G = VIH
++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
W = VIH
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
Verify Protect Set-upEnd
A9 = VIH
E, G = VIH
45/49
M29DW323DT, M29DW323DB
Fi gure 21. Pr ogrammer Equi pm ent Chip Unp rotect Flowc hart
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
PROTECT ALL GROUPS
AI05575
A6, A12, A15 = VIH(1)
E, G, A9 = VID
DATA
W = VIH
E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1, A6 = VIH
Wait 10ms
=
00h
INCREMENT
CURRENT GROUP
n = 0
CURRENT GROUP = 0
Wait 4µs
W = VIL
++n
= 1000
START
YES
YESNO
NO LAST
GROUP
YES
NO
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
FAIL PASS
Verify Unprotect Set-upEnd
A9 = VIH
E, G = VIH A9 = VIH
E, G = VIH
M29DW323D T, M29DW323DB
46/49
Figu re 22 . In- S ys te m Eq ui pm ent Group Pr ote ct Fl owchart
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
AI05576
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
n = 0
Wait 100µs
WRITE 40h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VIH ++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
RP = VIH
Wait 4µs
Verify Protect Set-upEnd
READ DATA
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
47/49
M29DW323DT, M29DW323DB
Figure 23. In-System Equipment Chip Unprotect Flowchart
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
AI05577
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
n = 0
CURRENT GROUP = 0
Wait 10ms
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VIH
++n
= 1000
START
FAIL PASS
YES
NO
DATA
=
00h
YESNO
RP = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PROTECT ALL GROUPS
INCREMENT
CURRENT GROUP
LAST
GROUP
YES
NO
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Verify Unprotect Set-upEnd
M29DW323D T, M29DW323DB
48/49
RE VISION HIST ORY
Table 31. D ocum ent Revision History
Date Version Revision Details
20-Sep-2001 -01 First Issue (Target Specification)
26-Oct-2001 -02 Document expanded to full Product Preview
16-Jan-2002 -03 Corrections made in “Primary Algorithm-Specific Extended Query” Table in Appendix-B
19-Apr-2002 -04
Description of Ready/Busy signal clarified (and Figure 15 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
tPLYH (time to reset device) re-specified.
24-Apr-2002 -05 Values for addresses 23h and 25h corrected in CFI Query System Interface Information
table in Appendix B
19-Jul-2002 -06 When in Extended Block mode, the block at the boot block address can be used as OTP.
Data Toggle Flow chart corrected. Document promoted from “Product Preview” to
“Preliminary Data”.
08-Apr-2003 6.1
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 06 equals 6.0).
Revision History moved to end of document.
TFBGA48, 6 x 8mm, 0.80mm pitch package added. Identification Current IID removed
from Table 12, DC Characteristics. Erase Suspend Latency time and Data Retention
parameters and notes added to Table 7, Program, Erase Times and Program, Erase
Endurance Cycles.
Appendix C, EXTENDED MEMORY BLOCK, added. Auto Select Command sued to read
the Extended Memory Block. Extended Memory Block V erify Code row added to Tables 3
and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH. Bank Address
modified in Auto Select Command. Chip Erase Address modified in Table 8, Status
Register Bits. VSS pin connection to ground clarified. Note added to Table 20, Ordering
Information Scheme.
07-May-2003 6.2 Table 17, TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical
Data and Figure 17, TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View
Package Outline, co rrecte d.
25-Jun-2003 7.0 Document promoted from Preliminary Data to full Datasheet status. P acking option added
to Table 20, Ordering Information Scheme.
49/49
M29DW323DT, M29DW323DB
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