1
File Number 4143.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 407-727-9207 |Copyright © Intersil Corporation 1999.
RF1K49154
2A, 60V, 0.130 Ohm, Dual N-Channel,
LittleFET™ Power MOSFET
This Dual N-Channel power MOSFET is manufactured using
the latest manufacturing process technology. This process,
which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. These devices can be operated directly from
integrated circuits.
Formerly developmental type TA49154.
Features
• 2A, 60V
•r
DS(ON) = 0.130Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC MS-012AA
Ordering Information
PART NUMBER PACKAGE BRAND
RF1K49154 MS-012AA RF1K49154
NO TE: When ordering, use the entire part number . For ordering in
tape and reel, add the suffix 96 to the part number, i.e., RF1K4915496. G1(2)
D1(8)
S1(1)
D1(7)
D2(6)
D2(5)
S2(3)
G2(4)
BRANDING DASH
1234
5
Data Sheet October 1999
2
Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified RF1K49154 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 60 V
Drain to Gate Voltage (RGS = 20kΩ, Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Drain Current Continuous (Pulse width = 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 2
Refer to Peak Current Curve A
Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
0.016 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 12) 60 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, (Figure 11) 2 - 4 V
Zero Gate Voltage Drain Current IDSS VDS = 55V, VGS = 0V - - 1 µA
VDS = 50V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±10 µA
Drain to Source On Resistance rDS(ON) ID = 2A, VGS = 10V, (Figures 9, 10) - - 0.130 Ω
Turn-On Time tON VDD = 30V, ID≈ 2A,
RL = 15Ω, VGS = 10V,
RGS = 25Ω
(Figure 14)
- - 50 ns
Turn-On Delay Time td(ON) -10-ns
Rise Time tr-25-ns
Turn-Off Delay Time td(OFF) -70-ns
Fall Time tf-35-ns
Turn-Off Time tOFF - - 155 ns
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 48V,
ID = 2A,
RL = 24Ω
(Figure 14)
-2632nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 14 17 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 0.8 1.0 nC
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz (Figure 13) - 340 - pF
Output Capacitance COSS - 140 - pF
Reverse Transfer Capacitance CRSS -40-pF
Thermal Resistance Junction to Ambient RθJA Pulse Width = 1s
Device Mounted on FR-4 Material - - 62.5 oC/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 2A - - 1.5 V
Reverse Recovery Time trr ISD = 2A, dISD/dt = 100A/µs--62ns
RF1K49154
3
Typical Performance Curves TA = 25oC, Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
1
0.5
025 50 75 100 125 150
2
1.5
ID, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
2.5
t, RECTANGULAR PULSE DURATION (s)
10-4 10-2 10-1 100101
0.01
0.1
10-3 102
PDM
t1t2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE
10-5 103
0.001
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
1
5DUTY CYCLE
0.5
0.2
0.1
0.05
0.01
0.02
DESCENDING ORDER
VDS, DRAIN TO SOURCE VOLTAGE (V)
1 10 200
0.1
10
20
0.1
1
ID, DRAIN CURRENT (A)
VDSS (MAX) = 60V
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
10ms
5ms
100
TJ = MAX RATED
TA = 25oC
t, PULSE WIDTH (s)
100
10
110-5 10-4 10-3 10-2 10-1 100101
IDM, PEAK CURRENT CAPABILITY (A)
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
VGS = 20V TA = 25oC
I = I25 150 - TA
125
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
RF1K49154
4
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
1 10 100
5
0.1
10
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0
5
10
0 1.5 3.0 4.5 6.0 7.5
15
20
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 8V
VGS = 10V
VGS = 9V
VGS = 20V VGS = 7V
VGS = 5V
VGS = 6V
PULSE DURATION = 80µs
TA = 25oC
DUTY CYCLE = 0.5% MAX
0468102
0
4
8
12
16
20
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX 150oC
-55oC25oC
VDD = 15V
100
200
300
400
500
04
V
GS
, GATE TO SOURCE VOLTAGE (V)
r
DS(ON)
, ON-STATE RESISTANCE (mΩ)
26810
I
D
= 0.5A
I
D
= 4A
I
D
= 2A
I
D
= 1A
V
DD
= 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0.5
1
1.5
2
-80 -40 0 40 80 120 160
NORMALIZED ON RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
PULSE DURATION = 80µs
VGS = 10V, ID = 2A
DUTY CYCLE = 0.5% MAX
-80 -40 0 40 80 120 160
0.5
0.75
1
1.25
1.5
NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS,ID = 250µA
RF1K49154
5
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
1.5
1.25
1
0.75
0.5-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA500
400
200
00 5 10 15 20 25
C, CAPACITANCE (pF)
CRSS
300
CISS
COSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
60
45
30
15
0
20IGREF()
IG ACT()
----------------------t, TIME (µs) 80IGREF()
IG ACT()
----------------------
10
7.5
5
2.5
0
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = BVDSS
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
RL = 30Ω
IG(REF) = 0.26mA
VGS = 10V
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RF1K49154
6
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10) OR Qg(5)
VGS = 5V FOR
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
VGS = 1V FOR
L2 DEVICES
L2 DEVICES
VGS = 10V
VGS = 10V FOR
L2 DEVICES
RF1K49154
7
PSPICE Electrical Model
SUBCKT RF1K49154 2 1 3 ; rev 2/2/96
CA 12 8 3.5e-10
CB 15 14 3.7e-10
CIN 6 8 2.26e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 63
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 1.4e-9
LSOURCE 3 7 3.1e-10
K1 LGATE LSOURCE 0.131
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 1.9
RLDRAIN 2 5 10
RLGATE 1 9 14
RLSOURCE 3 7 3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.6e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))}
.MODEL DBODYMOD D (IS = 2.6e-13 RS = 2.34e-2 IKF = 5.5 N = 0.995 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46
+ XTI = 5.5)
.MODEL DBREAKMOD D (RS = 0.5 IKF = 0.1 N = 1 TRS1 = 3e-3 TRS2 = -5e-5)
.MODEL DPLCAPMOD D (CJO = 5.6e-10 IS = 1e-30 N = 10 M = 0.92)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9)
.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = 5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4)
.MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 2.2e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.1 VOFF= -4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -7.1)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.01 VOFF= 1.9)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.9 VOFF= 0.01)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RF1K49154
8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
RF1K49154
