HLX6228TVR - Honeywell - Microelectronics & Precision Sensors

OTHER

• Read/Write Cycle Times

≤ 30 ns (-55 to 125°C)

• Typical Operating Power <9 mW/MHz

• JEDEC Standard Low Voltage

CMOS Compatible I/O

• Single 3.3 V ± 0.3 V Power Supply

• Asynchronous Operation

• Packaging Options

– 32-Lead CFP (0.820 in. x 0.600 in.)

– 40-Lead CFP (0.775 in. x 0.710 in.)

128K x 8 STATIC RAM—Low Power SOI

Military & Space Products

RADIATION

• Fabricated with RICMOS™ IV Silicon on Insulator

(SOI) 0.7 µm Low Power Process (Leff = 0.55 µm)

• Total Dose Hardness through 1x106 rad(SiO2)

• Neutron Hardness through 1x1014 cm-2

• Dynamic and Static Transient Upset Hardness

through 1x109 rad(Si)/s

• Dose Rate Survivability through 1x1011 rad(Si)/s

• Soft Error Rate of <1x10-10 Upsets/bit-day in Geosyn-

chronous Orbit

• No Latchup

Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com

FEATURES

GENERAL DESCRIPTION

The 128K x 8 Radiation Hardened Static RAM is a high

performance 131,072 word x 8-bit static random access

memory with industry-standard functionality. It is fabricated

with Honeywell’s radiation hardened technology, and is

designed for use in low voltage systems operating in radiation

environments. The RAM operates over the full military

temperature range and requires only a single 3.3 V ± 0.3V

power supply. The RAM is compatible with JEDEC standard

low voltage CMOS I/O. Power consumption is typically less

than 9 mW/MHz in operation, and less than 2 mW when de-

selected. The RAM read operation is fully asynchronous, with

an associated typical access time of 30 ns at 3.3 V.

Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensi-

tive CMOS) technology is radiation hardened through the use

of advanced and proprietary design, layout and process

hardening techniques. The RICMOS™ IV low power process is

a SIMOX CMOS technology with a 150 Å gate oxide and a

minimum drawn feature size of 0.7 µm (0.55 µm effective gate

length—Leff). Additional features include tungsten via plugs,

Honeywell’s proprietary SHARP planarization process and a

lightly doped drain (LDD) structure for improved short channel

reliability. A 7 transistor (7T) memory cell is used for superior

single event upset hardening, while three layer metal power

bussing and the low collection volume SIMOX substrate

provide improved dose rate hardening.

HLX6228

SIGNAL DEFINITIONS

A: 0-16 Address input pins which select a particular eight-bit word within the memory array.

DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write

operation.

NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS

forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and

disables all input buffers except CE. If this signal is not used it must be connected to VSS.

NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in

a high impedance state. When at a high level NWE allows normal read operation.

NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When

at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must

be connected to VSS.

CE Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a

precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers

except the NCS input buffer. If this signal is not used it must be connected to VDD.

NCS CE NWE NOE MODE DQ

L H H L Read Data Out

L H L X Write Data In

H X XX XX Deselected High Z

X L XX XX Disabled High Z

TRUTH TABLE

FUNCTIONAL DIAGRAM

Notes:

X: VI=VIH or VIL

XX: VSS≤VI≤VDD

NOE=H: High Z output state maintained

for NCS=X, CE=X, NWE=X

NCS

A:3-7,12,14-16

NWE

NOE

WE • CS • CE

NWE • CS • CE • OE

Column Decoder

Data Input/Output

Row

Decoder

131,072 x 8

Memory

Array

A:0-2, 8-11, 13

Signal

All controls must be

enabled for a signal to

pass. (#: number of

buffers, default = 1)

1 = enabled

Signal

DQ:0-7

(0 = high Z)

•

• • •

HLX6228

Total Dose ≥1x106rad(SiO2)

Transient Dose Rate Upset ≥1x109rad(Si)/s

Transient Dose Rate Survivability ≥1x1011 rad(Si)/s

Soft Error Rate <1x10-10 upsets/bit-day

Neutron Fluence ≥1x1014 N/cm2

Parameter Limits (2) Test Conditions

RADIATION HARDNESS RATINGS (1)

Units

TA=25°C

Total Ionizing Radiation Dose

The SRAM will meet all stated functional and electrical

specifications over the entire operating temperature range

after the specified total ionizing radiation dose. All electri-

cal and timing performance parameters will remain within

specifications after rebound at VDD = 3.6 V and T =125°C

extrapolated to ten years of operation. Total dose hard-

ness is assured by wafer level testing of process monitor

transistors and RAM product using 10 KeV X-ray and Co60

radiation sources. Transistor gate threshold shift correla-

tions have been made between 10 KeV X-rays applied at

a dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma

rays (Cobalt 60 source) to ensure that wafer level X-ray

testing is consistent with standard military radiation test

environments.

Transient Pulse Ionizing Radiation

The SRAM is capable of writing, reading, and retaining

stored data during and after exposure to a transient

ionizing radiation pulse, up to the specified transient

dose rate upset specification, when applied under rec-

ommended operating conditions. To ensure validity of all

specified performance parameters before, during, and

after radiation (timing degradation during transient pulse

radiation (timing degradation during transient pulse ra-

diation is ≤10%), it is suggested that stiffening capaci-

tance be placed on or near the package VDD and VSS,

with a maximum inductance between the package (chip)

and stiffening capacitance of 0.7 nH per part. If there are

no operate-through or valid stored data requirements,

typical circuit board mounted de-coupling capacitors are

recommended.

(1) Device will not latch up due to any of the specified radiation exposure conditions.

(2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.

1 MeV equivalent energy,

Unbiased, TA=25°C

TA=125°C, Adams 90%

worst case environment

Pulse width ≤50 ns, X-ray,

VDD=4.0 V, TA=25°C

Pulse width ≤1 µs

RADIATION CHARACTERISTICS

The SRAM will meet any functional or electrical specifica-

tion after exposure to a radiation pulse up to the transient

dose rate survivability specification, when applied under

recommended operating conditions. Note that the current

conducted during the pulse by the RAM inputs, outputs,

and power supply may significantly exceed the normal

operating levels. The application design must accommo-

date these effects.

Neutron Radiation

The SRAM will meet any functional or timing specification

after exposure to the specified neutron fluence under

recommended operating or storage conditions. This as-

sumes an equivalent neutron energy of 1 MeV.

Soft Error Rate

The SRAM is capable of meeting the specified Soft Error

Rate (SER), under recommended operating conditions.

This hardness level is defined by the Adams 90% worst

case cosmic ray environment for geosynchronous orbits.

Latchup

The SRAM will not latch up due to any of the above

radiation exposure conditions when applied under recom-

mended operating conditions. Fabrication with the

SIMOX substrate material provides oxide isolation be-

tween adjacent PMOS and NMOS transistors and elimi-

nates any potential SCR latchup structures. Sufficient

transistor body tie connections to the p- and n-channel

substrates are made to ensure no source/drain snapback

occurs.

HLX6228

Parameter Max

Symbol Test Conditions

Worst Case Units

CAPACITANCE (1)

Symbol Test Conditions

Min Max

Typical

(1) Units

VDR Data Retention Voltage 2.5 V

IDR Data Retention Current 700 mA

(1) This parameter is tested during initial design characterization only.

RECOMMENDED OPERATING CONDITIONS

Symbol MaxTyp

Description

Parameter Min

Worst Case

(2)

Units

VDD Supply Voltage (referenced to VSS) 3.0 3.3 3.6 V

TA Ambient Temperature -55 25 125 °C

VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V

Min

Typical

(1)

CI Input Capacitance 7 pF VI=VDD or VSS, f=1 MHz

CO Output Capacitance 9 pF VIO=VDD or VSS, f=1 MHz

(1) Typical operating conditions: TA= 25°C, pre-radiation.

(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.

DATA RETENTION CHARACTERISTICS

Parameter

(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not

implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.

(2) Voltage referenced to VSS.

(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.

(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.

ABSOLUTE MAXIMUM RATINGS (1)

NCS=VDD=VDR

VI=VDR or VSS

NCS=VDR

VI=VDR or VSS

VDD Supply Voltage Range (2) -0.5 6.0 V

VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V

TSTORE Storage Temperature (Zero Bias) -65 150 °C

TSOLDER Soldering Temperature (5 Seconds) 270 °C

PD Maximum Power Dissipation (3) 2 W

IOUT DC or Average Output Current 25 mA

VPROT ESD Input Protection Voltage (4) 2000 V

32 FP 2

40 FP 2

TJ Junction Temperature 175 °C

Parameter

Symbol

ΘJC Thermal Resistance (Jct-to-Case) °C/W

Units

Rating

Min Max

HLX6228

Symbol Parameter Typ (1)

Worst Case (2)

Units Test Conditions

Min Max

IDDSB1 Static Supply Current 700 µAVIH=VDD IO=0

VIL=VSS Inputs Stable

IDDSBMF Standby Supply Current – Deselected/Disabled 700 µANCS=VDD, CE=VSS, IO=0,

f=40 MHz

IDDOPW Dynamic Supply Current, Selected (Write) 3.2 mA f=1 MHz, IO=0, CE=VIH=VDD

NCS=VIL=VSS (3)

IDDOPR Dynamic Supply Current, Selected (Read) 2.2 mA f=1 MHz, IO=0, CE=VIH=VDD

NCS=VIL=VSS (3)

II Input Leakage Current -5 5 µAVSS VI VDD

IOZ Output Leakage Current -10 10 µAVSS VIO VDD, Output=High Z

VIL Low-Level Input Voltage 0.3xVDD VMarch Pattern VDD = 3.0V

VIH High-Level Input Voltage 0.7xVDD VMarch Pattern VDD= 3.6V

VOL Low-Level Output Voltage 0.4 V VDD = 3.0V, IOL = 8 mA

VOH High-Level Output Voltage 2.7 V VDD = 3.0V, IOH = -4 mA

DC ELECTRICAL CHARACTERISTICS

(1) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55°C to +125°C, post total dose at 25°C.

(3) All inputs switching. DC average current.

DUT

output

Valid low

output

Vref1

CL >50 pF*

249Ω

Tester Equivalent Load Circuit

2.2 V Valid high

output

Vref2

*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ

HLX6228

TAVAVR Address Read Cycle Time 30 ns

TAVQV Address Access Time 30 ns

TAXQX Address Change to Output Invalid Time 3 ns

TSLQV Chip Select Access Time 30 ns

TSLQX Chip Select Output Enable Time 5 ns

TEHQV Chip Enable Access Time 30 ns

TEHQX Chip Enable Output Enable Time 5 ns

TELQZ Chip Enable Output Disable Time 10 ns

TGLQV Output Enable Access Time 7 ns

TGLQX Output Enable Output Enable Time 0 ns

TGHQZ Output Enable Output Disable Time 9 ns

READ CYCLE AC TIMING CHARACTERISTICS (1)

Worst Case (3)

Symbol Parameter Typical -55 to 125°C Units

(2) Min Max

(1) Test conditions: input switching levels,VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the

Tester AC Timing Characteristics table, capacitive output loading CL>50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ, TELQZ

TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).

(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA= -55°C to 125°C, post total dose at 25°C.

HIGH

IMPEDANCE

NCS

NOE

DATA VALID

TAVAVR

TAVQV TAXQX

TSLQV

TSLQX TSHQZ

TEHQX

TEHQV

TGLQX

TGLQV TGHQZ

TELQZ

ADDRESS

(NWE = high)

DATA OUT

HLX6228

WRITE CYCLE AC TIMING CHARACTERISTICS (1)

(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the

Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ.

(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.

(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125°C, post total dose at 25°C.

(4) TAVAVW = TWLWH + TWHWL

(5) Guaranteed but not tested.

Symbol Parameter Typical -55 to 125°C Units

(2) Min

Worst Case (3)

TAVAVW Write Cycle Time (4) 25

TWLWH Write Enable Write Pulse Width ns

TSLWH Chip Select to End of Write Time ns

TDVWH Data Valid to End of Write Time ns

TAVWH Address Valid to End of Write Time ns

TWHDX Data Hold Time after End of Write Time ns

TAVWL Address Valid Setup to Start of Write Time ns

TWHAX Address Valid Hold after End of Write Time ns

TWLQZ Write Enable to Output Disable Time ns

TWHQX Write Disable to Output Enable Time ns

TWHWL Write Disable to Write Enable Pulse Width (5) ns

TEHWH Chip Enable to End of Write Time ns

Max

ADDRESS

HIGH

IMPEDANCE

DATA OUT

NWE

DATA IN

DATA VALID

TAVAVW

NCS

TAVWH

TWLWH

TAVWL

TWLQZ

TDVWH

TWHQX

TWHDX

TSLWH

TEHWH

TWHAX

TWHWL

HLX6228

DYNAMIC ELECTRICAL CHARACTERISTICS

Read Cycle

The RAM is asynchronous in operation, allowing the read

cycle to be controlled by address, chip select (NCS), or chip

enable (CE) (refer to Read Cycle timing diagram). To

perform a valid read operation, both chip select and output

enable (NOE) must be low and chip enable and write enable

(NWE) must be high. The output drivers can be controlled

independently by the NOE signal. Consecutive read cycles

can be executed with NCS held continuously low, and with

CE held continuously high, and toggling the addresses.

For an address activated read cycle, NCS and CE must be

valid prior to or coincident with the activating address edge

transition(s). Any amount of toggling or skew between ad-

dress edge transitions is permissible; however, data outputs

will become valid TAVQV time following the latest occurring

address edge transition. The minimum address activated

read cycle time is TAVAV. When the RAM is operated at the

minimum address activated read cycle time, the data outputs

will remain valid on the RAM I/O until TAXQX time following

the next sequential address transition.

To control a read cycle with NCS, all addresses and CE

must be valid prior to or coincident with the enabling NCS

edge transition. Address or CE edge transitions can occur

later than the specified setup times to NCS; however, the

valid data access time will be delayed. Any address edge

transition, which occurs during the time when NCS is low,

will initiate a new read access, and data outputs will not

become valid until TAVQV time following the address edge

transition. Data outputs will enter a high impedance state

TSHQZ time following a disabling NCS edge transition.

To control a read cycle with CE, all addresses and NCS

must be valid prior to or coincident with the enabling CE

edge transition. Address or NCS edge transitions can

occur later than the specified setup times to CE; however,

the valid data access time will be delayed. Any address

edge transition which occurs during the time when CE is

high will initiate a new read access, and data outputs will

not become valid until TAVQV time following the address

edge transition. Data outputs will enter a high impedance

state TELQZ time following a disabling CE edge transition.

Write Cycle

The write operation is synchronous with respect to the

address bits, and control is governed by write enable

(NWE), chip select (NCS), or chip enable (CE) edge

transitions (refer to Write Cycle timing diagrams). To per-

form a write operation, both NWE and NCS must be low,

and CE must be high. Consecutive write cycles can be

performed with NWE or NCS held continuously low, or CE

held continuously high. At least one of the control signals

must transition to the opposite state between consecutive

write operations.

The write mode can be controlled via three different control

signals: NWE, NCS, and CE. All three modes of control are

similar, except the NCS and CE controlled modes actually

disable the RAM during the write recovery pulse. Both CE

and NCS fully disable the RAM decode logic and input

buffers for power savings. Only the NWE controlled mode

is shown in the table and diagram on the previous page for

simplicity; however, each mode of control provides the

same write cycle timing characteristics. Thus, some of the

parameter names referenced below are not shown in the

write cycle table or diagram, but indicate which control pin

is in control as it switches high or low.

To write data into the RAM, NWE and NCS must be held low

and CE must be held high for at least TWLWH/TSLSH/

TEHEL time. Any amount of edge skew between the

signals can be tolerated, and any one of the control signals

can initiate or terminate the write operation. For consecu-

tive write operations, write pulses must be separated by the

minimum specified TWHWL/TSHSL/TELEH time. Address

inputs must be valid at least TAVWL/TAVSL/TAVEH time

before the enabling NWE/NCS/CE edge transition, and

must remain valid during the entire write time. A valid data

overlap of write pulse width time of TDVWH/TDVSH/TDVEL,

and an address valid to end of write time of TAVWH/

TAVSH/TAVEL also must be provided for during the write

operation. Hold times for address inputs and data inputs

with respect to the disabling NWE/NCS/CE edge transition

must be a minimum of TWHAX/TSHAX/TELAX time and

TWHDX/TSHDX/TELDX time, respectively. The minimum

write cycle time is TAVAV.

HLX6228

TESTER AC TIMING CHARACTERISTICS

ing the need to create detailed specifications and offer

benefits of improved quality and cost savings through

standardization.

RELIABILITY

Honeywell understands the stringent reliability requirements

for space and defense systems and has extensive experi-

ence in reliability testing on programs of this nature. This

experience is derived from comprehensive testing of VLSI

processes. Reliability attributes of the RICMOS

process

were characterized by testing specially designed irradiated

and non-irradiated test structures from which specific failure

mechanisms were evaluated. These specific mechanisms

included, but were not limited to, hot carriers, electromigra-

tion and time dependent dielectric breakdown. This data

was then used to make changes to the design models and

process to ensure more reliable products.

In addition, the reliability of the RICMOSTM process and

product in a military environment was monitored by testing

irradiated and non-irradiated circuits in accelerated dy-

namic life test conditions. Packages are qualified for prod-

uct use after undergoing Groups B & D testing as outlined

in MIL-STD-883, TM 5005, Class S. The product is quali-

fied by following a screening and testing flow to meet the

customer’s requirements. Quality conformance testing is

performed as an option on all production lots to ensure the

ongoing reliability of the product.

QUALITY AND RADIATION HARDNESS

ASSURANCE

Honeywell maintains a high level of product integrity through

process control, utilizing statistical process control, a com-

plete “Total Quality Assurance System,” a computer data

base process performance tracking system and a radia-

tion-hardness assurance strategy.

The radiation hardness assurance strategy starts with a

technology that is resistant to the effects of radiation.

Radiation hardness is assured on every wafer by irradiating

test structures as well as SRAM product, and then monitor-

ing key parameters which are sensitive to ionizing radia-

tion. Conventional MIL-STD-883 TM 5005 Group E testing,

which includes total dose exposure with Cobalt 60, may

also be performed as required. This Total Quality approach

ensures our customers of a reliable product by engineering

in reliability, starting with process development and con-

tinuing through product qualification and screening.

SCREENING LEVELS

Honeywell offers several levels of device screening to meet

your system needs. “Engineering Devices” are available

with limited performance and screening for breadboarding

and/or evaluation testing. Hi-Rel Level B and S devices

undergo additional screening per the requirements of MIL-

STD-883. As a QML supplier, Honeywell also offers QML

Class Q and V devices per MIL-PRF-38535 and are avail-

able per the applicable Standard Microcircuit Drawing

(SMD).

QML devices offer ease of procurement by eliminat-

AAAA

AAA

3 V

0 V

VDD/2

0.4 V

High Z

2.7 V

1.7 V

High Z

Input

Levels*

Output

Sense

Levels

High Z = 2.2V

* Input rise and fall times <1 ns/V

VDD-0.4V

HLX6228

The 128K x 8 SRAM is offered in a custom 32-lead or 40-

lead flat pack (FP). The packages are constructed of

multilayer ceramic (Al2O3) and feature internal power and

ground planes. Ceramic chip capacitors can be mounted to

the package by the user to maximize supply noise

decoupling and increase board packing density. These

PACKAGING

32-LEAD FLAT PACK (22018533-001)

[1] BSC - Basic lead spacing between centers

[2] Where lead is brazed to package

[3] Parts delivered with leads unformed

[4] Lid connected to VSS

0.135 ± 0.015

0.017 ± 0.002

0.004 to 0.009

0.820 ± 0.008

0.050 ± 0.005 [1]

0.600 ± 0.008

0.500 ± 0.008

0.040 ref

0.750 ± 0.005 [2]

0.295 min [3]

0.026 to 0.045

0.035 ± 0.010

0.080 ref

0.380 ref

0.050 ref

0.075 ref

0.010 ref

0.135 ref

All dimensions in inches

22018533-001

(width)

(pitch)

TOP

VIEW

Lead

Alloy 42

Ceramic

Body

Cutout

Area

Kovar

Lid [4]

Optional capacitors

in cutout

VSSVDD VDD

BOTTOM

VIEW

32-LEAD FLAT PACK PINOUT

VDD

A15

NWE

A13

A11

NOE

A10

NCS

DQ7

DQ6

DQ5

DQ4

DQ3

A16

A14

A12

DQ0

DQ1

DQ2

VSS

Top

View

capacitors attach directly to the internal package power

and ground planes. This design minimizes resistance and

inductance of the bond wire and package. All NC (no

connect) pins must be connected to either VDD, VSS or an

active driver to prevent charge build up in the radiation

environment.

A15

VSS

VDD

NWE

A13

A11

NOE

A10

NCS

DQ7

DQ6

DQ5

DQ4

DQ3

VDD

VSS

A16

VSS

VDD

A14

A12

DQ0

DQ1

DQ2

VDD

VSS

Top

View

40-LEAD FLAT PACK PINOUT

HLX6228

40-LEAD FLAT PACK (22019370-001)

Capacitor Pads

Kovar Lid [3]

Ceramic Body

(Pedestal)

D(width)

(pitch)

Top

View

22019370-001

[1] Parts delivered with leads unformed

[2] At tie bar

[3] Lid tied to VSS

0.131 ± .015

0.008 ± 0.002

0.006 ± 0.0015

0.710 ± 0.010

0.775 ± 0.007

0.025 ± 0.004

0.475 ± 0.005

0.760 ± 0.008

0.135 ± 0.005

0.030 ± 0.005

0.285 ± 0.015

0.050 ± 0.004

0.1175 ref

0.064 ref

0.006 ref

0.028 ref

0.125 ref

0.500 ± 0.005

0.140 ref

All dimensions are in inches

Non-Conductive

Tie-Bar

Bottom

View

HLX6228

ORDERING INFORMATION (1)

Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability

arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

900161, Rev. B

6/00

To learn more about Honeywell Solid State Electronics Center,

visit our web site at http://www.ssec.honeywell.com

(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.

(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, IDDSB = 10mA, no radiation guaranteed.

Contact Factory with other needs.

VDD = 3.7V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS

Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave

Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.

VDD = 3.6V, R ≤ 10 KΩ

Ambient Temperature ≥ 125 °C

DYNAMIC BURN-IN DIAGRAM* STATIC BURN-IN DIAGRAM*

A16

A14

A12

DQ0

DQ1

DQ2

VSS

VDD

A15

NWE

A13

A11

NOE

A10

NCS

DQ7

DQ6

DQ5

DQ4

DQ3

128K x 8 SRAM

F18

F19

F15

F12

F11

F10

F19

F17

F16

F13

F14

VDD

A16

A14

A12

DQ0

DQ1

DQ2

VSS

VDD

A15

NWE

A13

A11

NOE

A10

NCS

DQ7

DQ6

DQ5

DQ4

DQ3

128K x 8 SRAM

VDD

*40-Lead FP Burn-in diagram has similar connections and is available on request.

SOURCE

H=HONEYWELL

PROCESS

LX=Low Power SOI

PART NUMBER

6228 T

PACKAGE DESIGNATION

T=32-Lead FP

A=40-Lead FP

K=Known Good Die

- = Bare die (No Package)

TOTAL DOSE

HARDNESS

R=1x105 rad(SiO2)

F=3x105 rad(SiO2)

H=1x106 rad(SiO2)

N=No Level Guaranteed

SCREEN LEVEL

V=QML Class V

Q=QML Class Q

S=Class S

B=Class B

E=Engineering Device (2)