S29PL127J70BAW020 - Advanced Micro Devices

Publication Number 31107 Revision AAmendment 6Issue Date May 24, 2004

PRELIMINARY

S29PL127J/S29PL129J/S29PL064J/S29PL032J

128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory with Enhanced VersatileIOTM Control

Distinctive Characteristics

ARCHITECTURAL ADVANTAGES

128/128/64/32 Mbit Page Mode devices

— Page size of 8 words: Fast page read access from

random locations within the page

Single power supply operation

— Full Voltage range: 2.7 to 3.6 volt read, erase, and

program operations for battery-powered applications

Dual Chip Enable inputs (only in PL129J)

— Two CE# inputs control selection of each half of the

memory space

Simultaneous Read/Write Operation

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Zero latency switching from write to read operations

FlexBank Architecture (PL127J/PL064J/PL032J)

— 4 separate banks, with up to two simultaneous

operations per device

—Bank A:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

—Bank B:

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

—Bank C:

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

—Bank D:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

FlexBank Architecture (PL129J)

— 4 separate banks, with up to two simultaneous

operations per device

— CE#1 controlled banks:

Bank 1A:

PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)

Bank 1B:

PL129J - 48Mbit (32Kw x 96)

— CE#2 controlled banks:

Bank 2A:

PL129J - 48 Mbit (32Kw x 96)

Bank 2B:

PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)

Enhanced VersatileI/OTM (VIO) Control

— Output voltage generated and input voltages

tolerated on all control inputs and I/Os is determined

by the voltage on the VIO pin

—V

IO options at 1.8 V and 3 V I/O for PL127J and

PL129J devices

—3V V

IO for PL064J and PL032J devices

SecSiTM (Secured Silicon) Sector region

— Up to 128 words accessible through a command

sequence

— Up to 64 factory-locked words

— Up to 64 customer-lockable words

Both top and bottom boot blocks in one device

Manufactured on 110 nm process technology

Data Retention: 20 years typical

Cycling Endurance: 1 million cycles per sector

typical

PERFORMANCE CHARACTERISTICS

High Performance

— Page access times as fast as 20 ns

— Random access times as fast as 55 ns

Power consumption (typical values at 10 MHz)

— 45 mA active read current

— 17 mA program/erase current

— 0.2 µA typical standby mode current

SOFTWARE FEATURES

Software command-set compatible with JEDEC

42.4 standard

— Backward compatible with Am29F, Am29LV,

Am29DL, and AM29PDL families and MBM29QM/RM,

MBM29LV, MBM29DL, MBM29PDL families

CFI (Common Flash Interface) compliant

— Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

Erase Suspend / Erase Resume

— Suspends an erase operation to allow read or

program operations in other sectors of same bank

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

2 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

HARDWARE FEATURES

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or

erase cycle completion

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

WP#/ ACC (Write Protect/Acceleration) input

—At V

IL, hardware level protection for the first and

last two 4K word sectors.

—At V

IH, allows removal of sector protection

—At V

HH, provides accelerated programming in a

factory setting

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector

— Sectors can be locked and unlocked in-system at VCC

level

Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

Package options

— Standard discrete pinouts

11 x 8 mm, 80-ball Fine-pitch BGA (PL127J/PL129J

(VBG080)

8.15 x 6.15 mm, 48-ball Fine pitch BGA

(PL064J/PL032J)

(VBK048)

— MCP-compatible pinout

8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J and

PL129J)

7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and

PL032J)

Compatible with MCP pinout, allowing easy

integration of RAM into existing designs

— 20 x 14 mm, 56-pin TSOP (PL127J) (TS056)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 3

PRELIMINARY

General Description

The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page

Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2

Mwords. The devices are offered in the following packages:

11mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J and PL129J)

8mm x 11.6mm, 64-ball Fine-pitch BGA multi-chip compatible

(PL127J/PL129J)

8.15mm x 6.15mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)

7mm x 9mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and

PL032J)

20mm x 14mm, 56-pin TSOP (PL127J)

The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-

grammed in-system or in standard EPROM programmers. A 12.0 V VPP is not

required for write or erase operations.

The device offers fast page access times of 20 to 30 ns, with corresponding ran-

dom access times of 55 to 70 ns, respectively, allowing high speed

microprocessors to operate without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable (WE#) and output enable

(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).

Simultaneous Read/Write Operation with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation

by dividing the memory space into 4 banks, which can be considered to be four

separate memory arrays as far as certain operations are concerned. The device

can improve overall system performance by allowing a host system to program

or erase in one bank, then immediately and simultaneously read from another

bank with zero latency (with two simultaneous operations operating at any one

time). This releases the system from waiting for the completion of a program or

erase operation, greatly improving system performance.

The device can be organized in both top and bottom sector configurations. The

banks are organized as follows:

Bank PL127J Sectors PL064J Sectors PL032J Sectors

A 16 Mbit (4 Kw x 8 and 32 Kw x 31) 8 Mbit (4 Kw x 8 and 32 Kw x 15) 4 Mbit (4 Kw x 8 and 32 Kw x 7)

B 48 Mbit (32 Kw x 96) 24 Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24)

C 48 Mbit (32 Kw x 96) 24 Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24)

D 16 Mbit (4 Kw x 8 and 32 Kw x 31) 8 Mbit (4 Kw x 8 and 32 Kw x 15) 4 Mbit (4 Kw x 8 and 32 Kw x 7)

Bank PL129J Sectors CE# Control

1A 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE1#

1B 48 Mbit (32 Kw x 96) CE1#

2A 48 Mbit (32 Kw x 96) CE2#

2B 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE2#

4 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Page Mode Features

The page size is 8 words. After initial page access is accomplished, the page mode

operation provides fast read access speed of random locations within that page.

Standard Flash Memory Features

The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both

read and write functions. Internally generated and regulated voltages are pro-

vided for the program and erase operations.

The device is entirely command set compatible with the JEDEC 42.4 sin-

gle-power-supply Flash standard. Commands are written to the command

inputs to an internal state-machine that controls the erase and programming cir-

cuitry. Write cycles also internally latch addresses and data needed for the

programming and erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. The

Unlock Bypass mode facilitates faster programming times by requiring only two

write cycles to program data instead of four. Device erasure occurs by executing

the erase command sequence.

The host system can detect whether a program or erase operation is complete by

reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready to read array data or ac-

cept another command.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automat-

ically inhibits write operations during power transitions. The hardware sector

protection feature disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on

hold for any period of time to read data from, or program data to, any sector that

is not selected for erasure. True background erase can thus be achieved. If a read

is needed from the SecSi Sector area (One Time Program area) after an erase

suspend, then the user must use the proper command sequence to enter and exit

this region.

The device offers two power-saving features. When addresses have been stable

for a specified amount of time, the device enters the automatic sleep mode.

The system can also place the device into the standby mode. Power consumption

is greatly reduced in both these modes.

The device electrically erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 5

PRELIMINARY

TABLE OF CONTENTS

Simultaneous Read/Write Operation with Zero Latency ........................3

Page Mode Features .............................................................................................4

Standard Flash Memory Features .....................................................................4

TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . .5

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .7

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 11

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Simultaneous Read/Write Block Diagram . . . . . 12

Simultaneous Read/Write Block Diagram (PL129J)

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 14

80-Ball Fine-pitch BGA ...................................................................................... 14

Special Package Handling Instructions ...................................................... 14

64-Ball Fine-pitch BGA—MCP Compatible .................................................15

Special Package Handling Instructions .......................................................15

48-Ball Fine-pitch BGA ...................................................................................... 16

Connection Diagram (PL064J and PL032J) . . . . . . 17

56-pin TSOP 20 x 14 mm Configuration (PL127J) ...................................... 18

Special Package Handling Instructions ...................................................... 18

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .20

Table 1. PL127J Device Bus Operations ................................ 20

Table 2. PL129J Device Bus Operations ................................ 20

Requirements for Reading Array Data ......................................................... 21

Random Read (Non-Page Read) ................................................................ 21

Page Mode Read .............................................................................................. 21

Table 3. Page Select .......................................................... 21

Simultaneous Read/Write Operation .......................................................... 22

Table 4. Bank Select .......................................................... 22

Writing Commands/Command Sequences ................................................ 22

Accelerated Program Operation ...............................................................23

Autoselect Functions .....................................................................................23

Automatic Sleep Mode ......................................................................................23

RESET#: Hardware Reset Pin ........................................................................ 24

Output Disable Mode ....................................................................................... 24

Table 5. PL127J Sector Architecture ..................................... 25

Table 6. PL064J Sector Architecture ..................................... 32

Table 7. PL032J Sector Architecture ..................................... 35

Table 8. S29PL129J Sector Architecture ............................... 37

Table 9. SecSiTM Sector Addresses ...................................... 43

Autoselect Mode .................................................................................................43

Table 10. Autoselect Codes (High Voltage Method) ................ 44

Table 11. Autoselect Codes for PL129J ................................. 44

Table 12. PL127J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 45

Table 13. PL129J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 46

Table 14. PL064J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 47

Table 15. PL032J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 48

Selecting a Sector Protection Mode ............................................................. 48

Table 16. Sector Protection Schemes ................................... 49

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 49

Persistent Sector Protection .......................................................................... 49

Password Sector Protection ........................................................................... 49

WP# Hardware Protection ............................................................................ 49

Selecting a Sector Protection Mode ............................................................. 49

Persistent Sector Protection . . . . . . . . . . . . . . . . 50

Persistent Protection Bit (PPB) ......................................................................50

Persistent Protection Bit Lock (PPB Lock) .................................................50

Dynamic Protection Bit (DYB) .......................................................................50

Persistent Sector Protection Mode Locking Bit ....................................... 52

Password Protection Mode . . . . . . . . . . . . . . . . . 52

Password and Password Mode Locking Bit ................................................ 52

64-bit Password .................................................................................................. 53

Write Protect (WP#) ....................................................................................... 53

Persistent Protection Bit Lock ................................................................... 53

High Voltage Sector Protection ..................................................................... 54

Figure 1. In-System Sector Protection/Sector Unprotection Algo-

rithms .............................................................................. 55

Temporary Sector Unprotect ........................................................................ 56

Figure 2. Temporary Sector Unprotect Operation ................... 56

SecSi™ (Secured Silicon) Sector Flash Memory Region .......................... 56

Factory-Locked Area (64 words) .............................................................. 56

Customer-Lockable Area (64 words) ...................................................... 57

SecSi Sector Protection Bits ....................................................................... 57

Figure 3. SecSi Sector Protect Verify .................................... 58

Hardware Data Protection .............................................................................58

Low VCC Write Inhibit ................................................................................ 58

Write Pulse “Glitch” Protection ...............................................................58

Logical Inhibit ................................................................................................... 58

Power-Up Write Inhibit ...............................................................................58

Common Flash Memory Interface (CFI) . . . . . . 59

Table 17. CFI Query Identification String .............................. 59

Table 18. System Interface String ........................................ 60

Table 19. Device Geometry Definition ................................... 60

Table 20. Primary Vendor-Specific Extended Query ................ 61

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 63

Reading Array Data ........................................................................................... 63

Reset Command ................................................................................................. 63

Autoselect Command Sequence .................................................................... 64

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................64

Word Program Command Sequence ...........................................................64

Unlock Bypass Command Sequence ........................................................ 65

Figure 4. Program Operation ............................................... 66

Chip Erase Command Sequence ................................................................... 66

Sector Erase Command Sequence ................................................................ 67

Figure 5. Erase Operation ................................................... 68

Erase Suspend/Erase Resume Commands ..................................................68

Command Definitions Tables .........................................................................70

Table 21. Memory Array Command Definitions ...................... 70

Table 22. Sector Protection Command Definitions .................. 72

Write Operation Status . . . . . . . . . . . . . . . . . . . . 73

DQ7: Data# Polling ............................................................................................ 73

Figure 6. Data# Polling Algorithm ........................................ 74

DQ6: Toggle Bit I ............................................................................................... 75

Figure 7. Toggle Bit Algorithm ............................................. 76

DQ2: Toggle Bit II .............................................................................................. 76

Reading Toggle Bits DQ6/DQ2 ..................................................................... 76

DQ5: Exceeded Timing Limits ........................................................................ 77

DQ3: Sector Erase Timer ................................................................................ 77

Table 23. Write Operation Status ......................................... 78

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 79

Figure 8. Maximum Overshoot Waveforms ............................ 79

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .80

Industrial (I) Devices ..........................................................................................80

6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Extended (E) Devices ........................................................................................ 80

Supply Voltages ................................................................................................... 80

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 24. CMOS Compatible ................................................ 81

AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .82

Test Conditions .................................................................................................. 82

Figure 9. Test Setups......................................................... 82

Table 25. Test Specifications ............................................... 82

SWITCHING WAVEFORMS ..........................................................................83

Table 26. KEY TO SWITCHING WAVEFORMS ......................... 83

Figure 10. Input Waveforms and Measurement Levels............. 83

VCC RampRate ...................................................................................................83

Read Operations ................................................................................................ 84

Table 27. Read-Only Operations .......................................... 84

Figure 11. Read Operation Timings ....................................... 85

Figure 12. Page Read Operation Timings ............................... 85

Reset ...................................................................................................................... 86

Table 28. Hardware Reset (RESET#) .................................... 86

Figure 13. Reset Timings ..................................................... 86

Erase/Program Operations ............................................................................. 87

Table 29. Erase and Program Operations .............................. 87

Timing Diagrams ................................................................................................. 88

Figure 14. Program Operation Timings .................................. 88

Figure 15. Accelerated Program Timing Diagram .................... 88

Figure 16. Chip/Sector Erase Operation Timings ..................... 89

Figure 17. Back-to-back Read/Write Cycle Timings ................. 89

Figure 18. Data# Polling Timings (During Embedded Algorithms) .

Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 90

Figure 20. DQ2 vs. DQ6 ..................................................... 91

Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 30. Temporary Sector Unprotect ................................. 91

Figure 21. Temporary Sector Unprotect Timing Diagram ......... 91

Figure 22. Sector/Sector Block Protect and Unprotect Timing

Diagram ........................................................................... 92

Controlled Erase Operations ......................................................................... 93

Table 31. Alternate CE# Controlled Erase and Program Operations

Table 32. Alternate CE# Controlled Write (Erase/Program) Opera-

tion Timings ...................................................................... 94

Table 33. CE1#/CE2# Timing (S29PL129J only) .................... 94

Figure 23. Timing Diagram for Alternating Between CE1# and CE2#

Control............................................................................. 95

Table 34. Erase And Programming Performance ..................... 95

BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 95

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .96

VBG080—80-Ball Fine-pitch Ball Grid Array 8 x 11 mm Package (PL127J

and PL129J) ............................................................................................................96

VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm package

(PL127J) ................................................................................................................. 97

VBK048—48-Ball Fine-pitch Ball Grid Array 8.15 x 6.15 mm package

(PL127J) .................................................................................................................98

TLC056—56-Ball Fine-pitch BGA 7 x 9mm package (PL064J and PL032J)

TS056—20 x 14 mm, 56-pin TSOP (PL127J) ............................................ 100

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 101

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 7

PRELIMINARY

Ordering Information

The order number (Valid Combination) is formed by the following:

Valid Combinations

Valid Combination configuration planned to be supported for this device.

S29PL127J 55 BA W 00 0

PACKING TYPE

0=Tray

1=Tube

2 = 7” Tape and Reel

3 = 13” Tape and Reel

MODEL NUMBER (ADDITIONAL ORDERING OPTIONS)

00 = 3.0V V

, 80-ball 11 x 8 mm FBGA (VBG080)

01 = 1.8V V

, 80-ball 11 x 8 mm FBGA (VBG080)

02 = 3.0V V

, 64-ball 8 x 11.6 mm FBGA (VBH064)

12 = 3.0V V

, 48-ball 8 x 6 mm FBGA (VBK048)

13 = 3.0V V

, 56-ball 20 x 14 mm TSOP (TS056)

15 = 3.0V V

, 56-ball 7 x 9 mm FBGA (TLC056)

TEMPERATURE RANGE

W = Wireless (–25

C to +85

I = Industrial (–40

C to +85

PACKAGE TYPE

BA = Fine-Pitch Grid Array (FBGA)

Lead (Pb)- free compliant

BF = Fine-Pitch Grid Array (FBGA)

Lead (Pb)- free

TA = Thin Small Outline Package (TSOP) Standard Pinout

Lead (Pb)- free compliant

TF = Thin Small Outline Package (TSOP) Standard Pinout

Lead (Pb)- free

CLOCK SPEED

55 = 55 ns (Contact factory for availability)

60 = 60 ns

65 = 65 ns

70 = 70 ns

DEVICE NUMBER/DESCRIPTION

128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit), 32 Megabit (2 M x 16-Bit) CMOS Flash

Memory,

Simultaneous Read/Write, Page Mode Flash Memory, 3.0 Volt-only Read, Program, and Erase

8 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

128 Mb Products Based on 110 nm Floating Gate Technology

Valid FBGA Package

Combinations Package Marking Temperature Speed V

CE#

Configuration Package Type

S29PL129J55BAI00 PL129J55BAI00 (-40 - +85 º C) 55 ns

(Note)

3.0 V

Dual CE#

11 x 8 mm

80 ball FBGA

Standalone Package

VBG080

S29PL129J55BAW00 PL129J55BAW00 (-25 - +85 º C)

S29PL129J60BAI00 PL129J60BAI00 (-40 - +85 º C)

60 ns

S29PL129J60BAW00 PL129J60BAW00 (-25 - +85 º C)

S29PL129J70BAI00 PL129J70BAI00 (-40 - +85 º C)

70 ns

S29PL129J70BAW00 PL129J70BAW00 (-25 - +85 º C)

S29PL129J65BAI01 PL129J60BAI01 (-40 - +85 º C)

65 ns

1.8 V

S29PL129J65BAW01 PL129J60BAW01 (-25 - +85 º C)

S29PL129J70BAI01 PL129J70BAI01 (-40 - +85 º C)

70 ns

S29PL129J70BAW01 PL129J70BAW01 (-25 - +85 º C)

S29PL127J55BAI00 PL127J55BAI00 (-40 - +85 º C) 55 ns

(Note)

3.0 V

Single CE#

S29PL127J55BAW00 PL127J55BAW00 (-25 - +85 º C)

S29PL127J60BAI00 PL127J60BAI00 (-40 - +85 º C)

60 ns

S29PL127J60BAW00 PL127J60BAW00 (-25 - +85 º C)

S29PL127J70BAI00 PL127J70BAI00 (-40 - +85 º C)

70 ns

S29PL127J70BAW00 PL127J70BAW00 (-25 - +85 º C)

S29PL127J65BAI01 PL127J60BAI01 (-40 - +85 º C)

65 ns

1.8 V

S29PL127J65BAW01 PL127J60BAW01 (-25 - +85 º C)

S29PL127J70BAI01 PL127J70BAI01 (-40 - +85 º C)

70 ns

S29PL127J70BAW01 PL127J70BAW01 (-25 - +85 º C)

S29PL127J55BAI02 PL127J55BAI02 (-40 - +85 º C) 55 ns

(Note)

3.0 V

8 x 11.6 mm

64 ball FBGA

MCP-Compatible

VBH064

S29PL127J55BAW02 PL127J55BAW02 (-25 - +85 º C)

S29PL127J60BAI02 PL127J60BAI02 (-40 - +85 º C)

60 ns

S29PL127J60BAW02 PL127J60BAW02 (-25 - +85 º C)

S29PL127J70BAI02 PL127J70BAI02 (-40 - +85 º C)

70 ns

S29PL127J70BAW02 PL127J70BAW02 (-25 - +85 º C)

S29PL127J55TAI13 PL127J55TAI13 (-40 - +85 º C) 55

(Note)

20 x 14 mm

56-pin TSOP

TS056

S29PL127J55TAW13 PL127J55TAW13 (-25 - +85 º C)

S29PL127J60TAI13 PL127J60TAI13 (-40 - +85 º C)

S29PL127J60TAW13 PL127J60TAW13 (-25 - +85 º C)

S29PL127J70TAI13 PL127J70TAI13 (-40 - +85 º C)

S29PL127J70TAW13 PL127J70TAW13 (-25 - +85 º C)

S29PL127J55TFI13 PL127J55TFI13 (-40 - +85 º C) 55

(Note)

S29PL127J55TFW13 PL127J55TFW13 (-25 - +85 º C)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 9

PRELIMINARY

S29PL127J60TFI13 S29PL127J60TFI13 (-40 - +85 º C)

3.0 V Single CE#

20 x 14 mm

56-pin TSOP

TS056

S29PL127J60TFW13 PL127J60TFW13 (-25 - +85 º C)

S29PL127J70TFI13 PL127J70TFI13 (-40 - +85 º C)

S29PL127J70TFW13 PL127J70TFW13 (-25 - +85 º C)

64 Mb Products Based on 110 nm Floating Gate Technology

Valid Combinations

BGA Packages Package Marking Temperature Speed VIO Package Type

S29PL064J55BAI12 PL064J55BAI12 (-40 - +85 º C) 55 ns

(Note)

3.0 V

8 x 6 mm

48-ball

Standalone Package

VBK048

S29PL064J55BAW12 PL064J55BAW12 (-25 - +85 º C)

S29PL064J60BAI12 PL064J60BAI12 (-40 - +85 º C)

60 ns

S29PL064J60BAW12 PL064J60BAW12 (-25 - +85 º C)

S29PL064J70BAI12 PL064J70BAI12 (-40 - +85 º C)

70 ns

S29PL064J70BAW12 PL064J70BAW12 (-25 - +85 º C)

S29PL064J55BAI15 PL064J55BAI15 (-40 - +85 º C) 55 ns

(Note)

3.0 V

7 x 9 mm

56-ball

MCP-Compatible

TLC056

S29PL064J55BAW15 PL064J55BAW15 (-25 - +85 º C)

S29PL064J60BAI15 PL064J60BAI15 (-40 - +85 º C)

60 ns

S29PL064J60BAW15 PL064J60BAW15 (-25 - +85 º C)

S29PL064J70BAI15 PL064J70BAI15 (-40 - +85 º C)

70 ns

S29PL064J70BAW15 PL064J70BAW15 (-25 - +85 º C)

32 Mb Products Based on 110 nm Floating Gate Technology

Valid Combinations

GA Packages Package Marking Temperature Speed VIO Package Type

S29PL032J55BAI12 PL032J55BAI12 (-40 - +85 º C) 55 ns

(Note)

3.0 V

8 x 6 mm

48-ball

Standalone Package

VBK048

S29PL032J55BAW12 PL032J55BAW12 (-25 - +85 º C)

S29PL032J60BAI12 PL032J60BAI12 (-40 - +85 º C)

60 ns

S29PL032J60BAW12 PL032J60BAW12 (-25 - +85 º C)

S29PL032J70BAI12 PL032J70BAI12 (-40 - +85 º C)

70 ns

S29PL032J70BAW12 PL032J70BAW12 (-25 - +85 º C)

128 Mb Products Based on 110 nm Floating Gate Technology

Valid FBGA Package

Combinations Package Marking Temperature Speed V

CE#

Configuration Package Type

10 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Note: Please contact the factory for availability.

S29PL032J55BAI15 PL032J55BAI15 (-40 - +85 º C) 55 ns

(Note)

3.0 V

7 x 9 mm

56-ball

MCP-Compatible

TLC056

S29PL032J55BAW15 PL032J55BAW15 (-25 - +85 º C)

S29PL032J60BAI15 PL032J60BAI15 (-40 - +85 º C)

60 ns

S29PL032J60BAW15 PL032J60BAW15 (-25 - +85 º C)

S29PL032J70BAI15 PL032J70BAI15 (-40 - +85 º C)

70 ns

S29PL032J70BAW15 PL032J70BAW15 (-25 - +85 º C)

Valid Combinations for BGA Packages

Order Number Speed V

Range

PL129J, PL127J

PL064J, PL032J 55 (Note)

2.7–3.6

PL129J, PL127J

PL064J, PL032J 60

PL129J, PL127J

PL064J, PL032J 70

PL129J, PL127J 65 1.65–1.95

PL129J, PL127J 70

Valid Combinations for BGA Packages

Order Number Speed V

Range

PL127J

2.7–3.660

32 Mb Products Based on 110 nm Floating Gate Technology

Valid Combinations

GA Packages Package Marking Temperature Speed VIO Package Type

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 11

PRELIMINARY

Product Selector Guide

Note:

Contact factory for availability

Block Diagram

Notes:

1. RY/BY# is an open drain output.

2. Amax = A22 (PL127J), A21 (PL129J and PL064J), A20 (PL032J)

3. For PL129J there are two CE# (CE1# and CE2#)

Part Number

S29PL032J/S29PL064J/S29PL127J/S29PL129J

Speed Option

= 2.7–3.6 V 55 (Note) 60 65 70

= 2.7–3.6 V,

= 1.65–1.95 V (PL127J and

PL129J only)

65 70

Max Access Time, ns (t

ACC

)

55 (Note) 60 25 65 70 70

Max CE# Access, ns (t

)

Max Page Access, ns (t

PACC

)

20 (Note) 25 25 30 30

Max OE# Access, ns (t

)

State

Control

Command

Generator

Detector Timer

Erase Voltage

Generator

Input/Output

Buffers

Sector

Switches

Chip Enable

Output Enable

Logic

Y-Gating

Cell Matrix

Address Latch

Y-Decoder

X-Decoder

Data Latch

RESET#

RY/BY# (See Note)

Amax–A3

A2–A0

CE#

WE#

DQ15–DQ0

OE#

12 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Simultaneous Read/Write Block Diagram

Note: Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J)

Bank A Address

Bank B Address

Amax–A0

RESET#

WE#

CE#

DQ0–DQ15

STATE

CONTROL

COMMAND

RY/BY#

Bank A

X-Decoder

OE#

DQ15–DQ0

Status

Control

Amax–A0

A22–A0A22–A0

DQ15–DQ0

Mux

Bank B

X-Decoder

Y-gate

Bank C

X-Decoder

Bank D

X-Decoder

Y-gate

Bank C Address

Bank D Address

WP#/ACC

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 13

PRELIMINARY

Simultaneous Read/Write Block Diagram (PL129J)

Notes:

1. Amax = A21 (PL129J)

VCC

VSS

Bank 1A Address

Bank 1B Address

A21–A0

RESET#

WE#

CE1#

DQ0–DQ15

CE2#

STATE

CONTROL

COMMAND

RY/BY#

Bank 1A

X-Decoder

OE#

DQ15–DQ0

Status

Control

A21–A0

A21–A0A21–A0

DQ15–DQ0

Mux

Bank 1B

X-Decoder

Y-gate

Bank 2A

X-Decoder

Bank 2B

X-Decoder

Y-gate

Bank 2A Address

Bank 2B Address

CE1#=L

CE2#=H

CE1#=H

CE2#=L

WP#/ACC

14 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Connection Diagrams

80-Ball Fine-pitch BGA

Note:

Pinout shown for PL127J, for PL129J, H7(NC)= CE2# and H2 (CE#) = CE1#

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages

(TSOP, BGA, PDIP, SSOP, PLCC).

The package and/or data integrity may be compromised if the package body is

exposed to temperatures above 150°C for prolonged periods of time.

B2 D2 E2 F2 G2 H2 J2

D3 E3 F3 G3 H3 J3

D4 E4 F4 G4 H4 J4

D5 E5 F5 G5 H5 J5

D6 E6 F6 G6 H6 J6

B7 D7 E7 F7 G7 H7 J7

NC DQ15A16A15A14A12A13NC

DQ14 DQ13DQ7A11A10A8A9

DQ12 VCC

DQ5A19A21RESET#WE#

DQ10 DQ11DQ2A20A18WP#/ACCRY/BY#

DQ8 DQ9DQ0A5A6A17A7

CE# OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

A0A1A2A4A3NC

B1 D1 E1 F1 G1 H1 J1

VIO NCNCNCNCNCNCNC

B8 D8

C8 E8 F8 G8 H8 J8

NC NC

NCVSS

VIO

NCA22NCNC

80-Ball Fine-pitch BGA

(PL127J/PL129J)

Top View, Balls Facing Down

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 15

PRELIMINARY

64-Ball Fine-pitch BGA—MCP Compatible

Note: Pinout shown for PL127J. For PL129J, F9 (A22) = RFU, and B5 (RFU) = CE2#.

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages

(TSOP, BGA, PDIP, SSOP, PLCC).

The package and/or data integrity may be compromised if the package body is

exposed to temperatures above 150°C for prolonged periods of time.

64-Ball Fine-pitch BGA—MCP Compatible

(PL127J/PL129J)

Top View, Balls Facing Down

F7 F8 F9

G3 G4 G7 G8 G9G2

H3 H4 H5 H6 H7 H8 H9H2

NC NC

B5 B6

C4 C5 C6 C7 C8

D2 D3 D4 D5 D6 D7 D8 D9

E2 E3 E4 E5 E6 E7 E8 E9

F2 F3 F4

J3 J4 J5 J6 J7 J8 J9J2

K3 K4 K5 K6 K7 K8

L5 L6

NC NC

M1 M10

A1 A10

A5 A18 RY/BY # A20 A9 A13 A21

A6 RFU RESET# RFU A19 A12 A15

A7 RFU WP#/ACC WE# A8 A11

A22A14A10A17A4A1

RFUDQ15DQ13DQ4DQ3DQ9OE#CE#f1

RFU RFU

A16RFUDQ6DQ1VSSA0

VSSDQ7DQ12RFUVCCfDQ10DQ0RFU

DQ14DQ5RFUDQ11DQ2DQ8

RFUVCCf

16 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

48-Ball Fine-pitch BGA

Note: Pinout shows for PL064J. For PL032J, C4(A21) = NC

B3 C3 D3 E3 F3 G3 H3

B4 C4 D4 E4 F4 G4 H4

B5 C5 D5 E5 F5 G5 H5

B6 C6 D6 E6 F6 G6 H6

VSS

DQ15NCA16A15A14A12

DQ6DQ13DQ14DQ7A11A10A8

DQ4VCC

DQ12DQ5A19A21RESET#

DQ3DQ11DQ10DQ2A20A18WP#/ACC

A13

WE#

RY/BY#

B2 C2 D2 E2 F2 G2 H2

DQ1DQ9DQ8DQ0A5A6A17

B1 C1 D1 E1 F1 G1 H1

VSS

OE#CE#A0A1A2A4

48-Ball Fine-pitch BGA (PL064J/PL032J)

Top View, Balls Facing Down

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 17

PRELIMINARY

Connection Diagram (PL064J and PL032J)

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultra-

sonic cleaning methods. The package and/or data integrity may be compromised

if the package body is exposed to temperatures above 150°C for prolonged peri-

ods of time.

UB#

A18

A17

DQ1

DQ9

DQ10

DQ2

LB#

CE2s

A20

DQ4

VCCs

RFU

WE#

A19

A10

DQ6

DQ13

DQ12

DQ5

RST#

RY/BY#

DQ3

VCCf

DQ11

WP#/ACC

A12

A13

A14

RFU

DQ15

DQ7

DQ14

A11

A15

A21

RFU

A16

RFU

VSS

OE#

DQ0CE1#s

DQ8

CE1#f

F5F4

B1 B8

A3 A5 A6A4 A7A2

56-ball Fine-Pitch Ball Grid Array

(Top View, Balls Facing Down)

18 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

56-pin TSOP 20 x 14 mm Configuration (PL127J)

For this family of products, a single multi-chip compatible package is offered for

each density to allow both standalone and multi-chip qualification using a single,

adaptable package. This new methodology allows package standardization

resulting in faster development. The multi-chip compatible package includes all

the pins required for standalone device operation and verification. In addition,

extra pins are included for insertion of common data storage or logic devices to

be used for multi-chip products. If a standalone device is required, the extra

multi-chip specific pins are not connected and the standalone device operates

normally. The multi-chip compatible package sizes were chosen to serve the

largest number of combinations possible. There are only a few cases where a

larger package size would be required to accommodate the multi-chip

combination. This multi-chip compatible package set does not allow for direct

package migration from the Am29BDS128H, Am29BDS128G, Am29BDS640G

products, which use legacy standalone packages.

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages

(TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be

compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

RESET#

RY/BY#

VCC

DQ0

DQ1

DQ2

DQ3

VSSQ

DQ4

DQ5

DQ6

DQ7

VSS

WP#/ACC

WE#

A22

A21

A20

OE#

CE#

VSS

DQ15

DQ14

DQ13

DQ12

VSSQ

VCCQ

DQ11

DQ10

DQ9

DQ8

VCC

A19

A10

A11

A12

A18

A17

A16

A15

A14

A13

VCCQ

56-pin TSOP

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 19

PRELIMINARY

Pin Description

Amax–A0 = Address bus

DQ15–DQ0 = 16-bit data inputs/outputs/float

CE# = Chip Enable Inputs

OE# = Output Enable Input

WE# = Write Enable

VSS = Device Ground

NC = Pin Not Connected Internally

RY/BY# = Ready/Busy output and open drain.

When RY/BY#= VIH, the device is ready to accept

read operations and commands. When RY/BY#=

VOL, the device is either executing an embedded

algorithm or the device is executing a hardware

reset operation.

WP#/ACC = Write Protect/Acceleration Input.

When WP#/ACC= VIL, the highest and lowest two

4K-word sectors are write protected regardless of

other sector protection configurations. When

WP#/ACC= VIH, these sector are unprotected unless

the DYB or PPB is programmed. When WP#/ACC=

12V, program and erase operations are accelerated.

VIO = Input/Output Buffer Power Supply

(1.65 V to 1.95 V (for PL127J and PL129J) or 2.7 V

to 3.6 V (for all PLxxxJ devices))

VCC = Chip Power Supply

(2.7 V to 3.6 V or 2.7 to 3.3 V)

RESET# = Hardware Reset Pin

CE1#, CE2# = Chip Enable Inputs.

CE1# controls the 64Mb in Banks 1A and 1B. CE2#

controls the 64 Mb in Banks 2A and 2B. (Only for

PL129J)

Notes:

1. Amax = A22 (PL127J), A21 (PL129J and PL064J), A20 (PL032J)

Logic Symbol

max+1

DQ15–DQ0

Amax–A0

CE#

OE#

WE#

RESET# RY/BY#

WP#/ACC

CCQ

)

20 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is a latch

used to store the commands, along with the address and data information

needed to execute the command. The contents of the register serve as inputs to

the internal state machine. The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the inputs and control levels they

require, and the resulting output. The following subsections describe each of

these operations in further detail.

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector

Address, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the

"High Voltage Sector Protection" section section.

2. WP#/ACC must be high when writing to upper two and lower two sectors.

Table 1. PL127J Device Bus Operations

Operation CE# OE# WE# RESET# WP#/ACC

Addresses

(Amax–A0)

DQ15–

DQ0

Read L L H H X A

OUT

Write L H L H X (Note 2)A

Standby V

0.3 V XX

0.3 V X (Note 2)X High-Z

Output Disable L H H H X X High-Z

Reset X X X L X X High-Z

Temporary Sector Unprotect (High Voltage) X X X V

Table 2. PL129J Device Bus Operations

Operation CE1# CE2# OE# WE# RESET# WP#/ACC

Addresses

(A21–A0)

DQ15–

DQ0

Read

LH H X A

OUT

Write

HL H X

(Note 2)A

Standby V

0.3 V

0.3 V XX

0.3 V XXHigh-Z

Output Disable L L H H H X X High-Z

Reset X X X X L X X High-Z

Temporary Sector Unprotect

(High Voltage) XXXXV

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 21

PRELIMINARY

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the OE# and appro-

priate CE# pins (For PL129J - CE1#/CE2# pins) to VIL. In PL129J, CE1# and

CE2# are the power control and select the lower (CE1#) or upper (CE2#) halves

of the device. CE# is the power control. OE# is the output control and gates array

data to the output pins. WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. Each bank remains enabled for read access until the command register

contents are altered.

Refer to Ta b l e 3 3 for timing specifications and to Figure 11 for the timing diagram.

ICC1 in the DC Characteristics table represents the active current specification for

reading array data.

Random Read (Non-Page Read)

Address access time (tACC) is equal to the delay from stable addresses to valid

output data. The chip enable access time (tCE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output inputs. The output enable

access time is the delay from the falling edge of the OE# to valid data at the out-

put inputs (assuming the addresses have been stable for at least tACC–tOE time).

Page Mode Read

The device is capable of fast page mode read and is compatible with the page

mode Mask ROM read operation. This mode provides faster read access speed for

random locations within a page. Address bits Amax–A3 select an 8 word page,

and address bits A2–A0 select a specific word within that page. This is an asyn-

chronous operation with the microprocessor supplying the specific word location.

The random or initial page access is tACC or tCE and subsequent page read ac-

cesses (as long as the locations specified by the microprocessor falls within that

page) is equivalent to tPACC. When CE# (CE1# and CE#2 in PL129J) is deasserted

(=VIH), the reassertion of CE# (CE1# or CE#2 in PL129J) for subsequent access

has access time of tACC or tCE. Here again, CE# (CE1# /CE#2 in PL129J)selects

the device and OE# is the output control and should be used to gate data to the

output inputs if the device is selected. Fast page mode accesses are obtained by

keeping Amax–A3 constant and changing A2–A0 to select the specific word within

that page.

Ta b l e 3 . Page Select

Word A2 A1 A0

Word 0 0 0 0

Word 1 0 0 1

Word 2 0 1 0

Word 3 0 1 1

Word 4 1 0 0

Word 5 1 0 1

22 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Simultaneous Read/Write Operation

In addition to the conventional features (read, program, erase-suspend read, and

erase-suspend program), the device is capable of reading data from one bank of

memory while a program or erase operation is in progress in another bank of

memory (simultaneous operation). The bank can be selected by bank addresses

(PL127J: A22–A20, PL129J and PL064J: A21–A19, PL032J: A20–A18) with zero

latency.

The simultaneous operation can execute multi-function mode in the same bank.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# (CE1# or CE#2 in PL129J) to VIL, and OE# to VIH.

The device features an Unlock Bypass mode to facilitate faster programming.

Once a bank enters the Unlock Bypass mode, only two write cycles are required

to program a word, instead of four. The “Word Program Command Sequence”

section has details on programming data to the device using both standard and

Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Ta b l e 4 indicates the set of address space that each sector occupies. A “bank ad-

dress” is the set of address bits required to uniquely select a bank. Similarly, a

“sector address” refers to the address bits required to uniquely select a sector.

The “Command Definitions” section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

Word 6 1 1 0

Word 7 1 1 1

Table 4. Bank Select

Bank

PL127J: A22–A20

PL064J: A21–A19

PL032J: A20–A18

Bank A 000

Bank B 001, 010, 011

Bank C 100, 101, 110

Bank D 111

Bank CE1# CE2# PL129J: A21–A20

Bank 1A 0 1 00

Bank 1B 0 1 01, 10, 11

Bank 2A 1 0 00, 01, 10

Bank 2B 1 0 11

Ta b l e 3 . Page Select (Continued)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 23

PRELIMINARY

ICC2 in the DC Characteristics table represents the active current specification for

the write mode. See the timing specification tables and timing diagrams in the

"Reset" section for write operations.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This

function is primarily intended to allow faster manufacturing throughput at the

factory.

If the system asserts VHH on this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the time required for program

operations. The system would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin re-

turns the device to normal operation. Note that VHH must not be asserted on

WP#/ACC for operations other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin should be raised to VCC when not in

use. That is, the WP#/ACC pin should not be left floating or unconnected; incon-

sistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

read cycle timings apply in this mode. Refer to the "SecSiTM Sector Addresses"

section and "Autoselect Command Sequence" section for more information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# (CE1#,CE#2 in

PL129J) and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more

restricted voltage range than VIH.) If CE# (CE1#,CE#2 in PL129J) and RESET#

are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device requires standard access time

(tCE) for read access when the device is in either of these standby modes, before

it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

ICC3 in “DC Characteristics” represents the CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. Note that during automatic sleep mode, OE# must be at VIH before

the device reduces current to the stated sleep mode specification. ICC5 in “DC

Characteristics” represents the automatic sleep mode current specification.

24 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of tRP

, the

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a “0” (busy) until the internal reset operation is complete, which requires

a time of tREADY (during Embedded Algorithms). The system can thus monitor

RY/BY# to determine whether the reset operation is complete. If RESET# is as-

serted when a program or erase operation is not executing (RY/BY# pin is “1”),

the reset operation is completed within a time of tREADY (not during Embedded Al-

gorithms). The system can read data tRH after the RESET# pin returns to VIH.

Refer to the "AC Characteristic" section tables for RESET# parameters and to 13

for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins

(except for RY/BY#) are placed in the highest Impedance state

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 25

PRELIMINARY

Table 5. PL127J Sector Architecture

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

Bank A

SA0 00000000000 4 000000h–000FFFh

SA1 00000000001 4 001000h–001FFFh

SA2 00000000010 4 002000h–002FFFh

SA3 00000000011 4 003000h–003FFFh

SA4 00000000100 4 004000h–004FFFh

SA5 00000000101 4 005000h–005FFFh

SA6 00000000110 4 006000h–006FFFh

SA7 00000000111 4 007000h–007FFFh

SA8 00000001XXX 32 008000h–00FFFFh

SA9 00000010XXX 32 010000h–017FFFh

SA10 00000011XXX 32 018000h–01FFFFh

SA11 00000100XXX 32 020000h–027FFFh

SA12 00000101XXX 32 028000h–02FFFFh

SA13 00000110XXX 32 030000h–037FFFh

SA14 00000111XXX 32 038000h–03FFFFh

SA15 00001000XXX 32 040000h–047FFFh

SA16 00001001XXX 32 048000h–04FFFFh

SA17 00001010XXX 32 050000h–057FFFh

SA18 00001011XXX 32 058000h–05FFFFh

SA19 00001100XXX 32 060000h–067FFFh

SA20 00001101XXX 32 068000h–06FFFFh

SA21 00001110XXX 32 070000h–077FFFh

SA22 00001111XXX 32 078000h–07FFFFh

SA23 00010000XXX 32 080000h–087FFFh

SA24 00010001XXX 32 088000h–08FFFFh

SA25 00010010XXX 32 090000h–097FFFh

SA26 00010011XXX 32 098000h–09FFFFh

SA27 00010100XXX 32 0A0000h–0A7FFFh

SA28 00010101XXX 32 0A8000h–0AFFFFh

SA29 00010110XXX 32 0B0000h–0B7FFFh

SA30 00010111XXX 32 0B8000h–0BFFFFh

SA31 00011000XXX 32 0C0000h–0C7FFFh

SA32 00011001XXX 32 0C8000h–0CFFFFh

SA33 00011010XXX 32 0D0000h–0D7FFFh

SA34 00011011XXX 32 0D8000h–0DFFFFh

SA35 00011100XXX 32 0E0000h–0E7FFFh

SA36 00011101XXX 32 0E8000h–0EFFFFh

SA37 00011110XXX 32 0F0000h–0F7FFFh

SA38 00011111XXX 32 0F8000h–0FFFFFh

26 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank B

SA39 00100000XXX 32 100000h–107FFFh

SA40 00100001XXX 32 108000h–10FFFFh

SA41 00100010XXX 32 110000h–117FFFh

SA42 00100011XXX 32 118000h–11FFFFh

SA43 00100100XXX 32 120000h–127FFFh

SA44 00100101XXX 32 128000h–12FFFFh

SA45 00100110XXX 32 130000h–137FFFh

SA46 00100111XXX 32 138000h–13FFFFh

SA47 00101000XXX 32 140000h–147FFFh

SA48 00101001XXX 32 148000h–14FFFFh

SA49 00101010XXX 32 150000h–157FFFh

SA50 00101011XXX 32 158000h–15FFFFh

SA51 00101100XXX 32 160000h–167FFFh

SA52 00101101XXX 32 168000h–16FFFFh

SA53 00101110XXX 32 170000h–177FFFh

SA54 00101111XXX 32 178000h–17FFFFh

SA55 00110000XXX 32 180000h–187FFFh

SA56 00110001XXX 32 188000h–18FFFFh

SA57 00110010XXX 32 190000h–197FFFh

SA58 00110011XXX 32 198000h–19FFFFh

SA59 00110100XXX 32 1A0000h–1A7FFFh

SA60 00110101XXX 32 1A8000h–1AFFFFh

SA61 00110110XXX 32 1B0000h–1B7FFFh

SA62 00110111XXX 32 1B8000h–1BFFFFh

SA63 00111000XXX 32 1C0000h–1C7FFFh

SA64 00111001XXX 32 1C8000h–1CFFFFh

SA65 00111010XXX 32 1D0000h–1D7FFFh

SA66 00111011XXX 32 1D8000h–1DFFFFh

SA67 00111100XXX 32 1E0000h–1E7FFFh

SA68 00111101XXX 32 1E8000h–1EFFFFh

SA69 00111110XXX 32 1F0000h–1F7FFFh

SA70 00111111XXX 32 1F8000h–1FFFFFh

SA71 01000000XXX 32 200000h–207FFFh

SA72 01000001XXX 32 208000h–20FFFFh

SA73 01000010XXX 32 210000h–217FFFh

SA74 01000011XXX 32 218000h–21FFFFh

SA75 01000100XXX 32 220000h–227FFFh

SA76 01000101XXX 32 228000h–22FFFFh

SA77 01000110XXX 32 230000h–237FFFh

SA78 01000111XXX 32 238000h–23FFFFh

Table 5. PL127J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 27

PRELIMINARY

Bank B

SA79 01001000XXX 32 240000h–247FFFh

SA80 01001001XXX 32 248000h–24FFFFh

SA81 01001010XXX 32 250000h–257FFFh

SA82 01001011XXX 32 258000h–25FFFFh

SA83 01001100XXX 32 260000h–267FFFh

SA84 01001101XXX 32 268000h–26FFFFh

SA85 01001110XXX 32 270000h–277FFFh

SA86 01001111XXX 32 278000h–27FFFFh

SA87 01010000XXX 32 280000h–287FFFh

SA88 01010001XXX 32 288000h–28FFFFh

SA89 01010010XXX 32 290000h–297FFFh

SA90 01010011XXX 32 298000h–29FFFFh

SA91 01010100XXX 32 2A0000h–2A7FFFh

SA92 01010101XXX 32 2A8000h–2AFFFFh

SA93 01010110XXX 32 2B0000h–2B7FFFh

SA94 01010111XXX 32 2B8000h–2BFFFFh

SA95 01011000XXX 32 2C0000h–2C7FFFh

SA96 01011001XXX 32 2C8000h–2CFFFFh

SA97 01011010XXX 32 2D0000h–2D7FFFh

SA98 01011011XXX 32 2D8000h–2DFFFFh

SA99 01011100XXX 32 2E0000h–2E7FFFh

SA100 01011101XXX 32 2E8000h–2EFFFFh

SA101 01011110XXX 32 2F0000h–2F7FFFh

SA102 01011111XXX 32 2F8000h–2FFFFFh

SA103 01100000XXX 32 300000h–307FFFh

SA104 01100001XXX 32 308000h–30FFFFh

SA105 01100010XXX 32 310000h–317FFFh

SA106 01100011XXX 32 318000h–31FFFFh

SA107 01100100XXX 32 320000h–327FFFh

SA108 01100101XXX 32 328000h–32FFFFh

SA109 01100110XXX 32 330000h–337FFFh

SA110 01100111XXX 32 338000h–33FFFFh

SA111 01101000XXX 32 340000h–347FFFh

SA112 01101001XXX 32 348000h–34FFFFh

SA113 01101010XXX 32 350000h–357FFFh

SA114 01101011XXX 32 358000h–35FFFFh

SA115 01101100XXX 32 360000h–367FFFh

SA116 01101101XXX 32 368000h–36FFFFh

SA117 01101110XXX 32 370000h–377FFFh

SA118 01101111XXX 32 378000h–37FFFFh

Table 5. PL127J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

28 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank B

SA119 01110000XXX 32 380000h–387FFFh

SA120 01110001XXX 32 388000h–38FFFFh

SA121 01110010XXX 32 390000h–397FFFh

SA122 01110011XXX 32 398000h–39FFFFh

SA123 01110100XXX 32 3A0000h–3A7FFFh

SA124 01110101XXX 32 3A8000h–3AFFFFh

SA125 01110110XXX 32 3B0000h–3B7FFFh

SA126 01110111XXX 32 3B8000h–3BFFFFh

SA127 01111000XXX 32 3C0000h–3C7FFFh

SA128 01111001XXX 32 3C8000h–3CFFFFh

SA129 01111010XXX 32 3D0000h–3D7FFFh

SA130 01111011XXX 32 3D8000h–3DFFFFh

SA131 01111100XXX 32 3E0000h–3E7FFFh

SA132 01111101XXX 32 3E8000h–3EFFFFh

SA133 01111110XXX 32 3F0000h–3F7FFFh

SA134 01111111XXX 32 3F8000h–3FFFFFh

Bank C

SA135 10000000XXX 32 400000h–407FFFh

SA136 10000001XXX 32 408000h–40FFFFh

SA137 10000010XXX 32 410000h–417FFFh

SA138 10000011XXX 32 418000h–41FFFFh

SA139 10000100XXX 32 420000h–427FFFh

SA140 10000101XXX 32 428000h–42FFFFh

SA141 10000110XXX 32 430000h–437FFFh

SA142 10000111XXX 32 438000h–43FFFFh

SA143 10001000XXX 32 440000h–447FFFh

SA144 10001001XXX 32 448000h–44FFFFh

SA145 10001010XXX 32 450000h–457FFFh

SA146 10001011XXX 32 458000h–45FFFFh

SA147 10001100XXX 32 460000h–467FFFh

SA148 10001101XXX 32 468000h–46FFFFh

SA149 10001110XXX 32 470000h–477FFFh

SA150 10001111XXX 32 478000h–47FFFFh

SA151 10010000XXX 32 480000h–487FFFh

SA152 10010001XXX 32 488000h–48FFFFh

SA153 10010010XXX 32 490000h–497FFFh

SA154 10010011XXX 32 498000h–49FFFFh

SA155 10010100XXX 32 4A0000h–4A7FFFh

SA156 10010101XXX 32 4A8000h–4AFFFFh

SA157 10010110XXX 32 4B0000h–4B7FFFh

SA158 10010111XXX 32 4B8000h–4BFFFFh

Table 5. PL127J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 29

PRELIMINARY

Bank C

SA159 10011000XXX 32 4C0000h–4C7FFFh

SA160 10011001XXX 32 4C8000h–4CFFFFh

SA161 10011010XXX 32 4D0000h–4D7FFFh

SA162 10011011XXX 32 4D8000h–4DFFFFh

SA163 10011100XXX 32 4E0000h–4E7FFFh

SA164 10011101XXX 32 4E8000h–4EFFFFh

SA165 10011110XXX 32 4F0000h–4F7FFFh

SA166 10011111XXX 32 4F8000h–4FFFFFh

SA167 10100000XXX 32 500000h–507FFFh

SA168 10100001XXX 32 508000h–50FFFFh

SA169 10100010XXX 32 510000h–517FFFh

SA170 10100011XXX 32 518000h–51FFFFh

SA171 10100100XXX 32 520000h–527FFFh

SA172 10100101XXX 32 528000h–52FFFFh

SA173 10100110XXX 32 530000h–537FFFh

SA174 10100111XXX 32 538000h–53FFFFh

SA175 10101000XXX 32 540000h–547FFFh

SA176 10101001XXX 32 548000h–54FFFFh

SA177 10101010XXX 32 550000h–557FFFh

SA178 10101011XXX 32 558000h–15FFFFh

SA179 10101100XXX 32 560000h–567FFFh

SA180 10101101XXX 32 568000h–56FFFFh

SA181 10101110XXX 32 570000h–577FFFh

SA182 10101111XXX 32 578000h–57FFFFh

SA183 10110000XXX 32 580000h–587FFFh

SA184 10110001XXX 32 588000h–58FFFFh

SA185 10110010XXX 32 590000h–597FFFh

SA186 10110011XXX 32 598000h–59FFFFh

SA187 10110100XXX 32 5A0000h–5A7FFFh

SA188 10110101XXX 32 5A8000h–5AFFFFh

SA189 10110110XXX 32 5B0000h–5B7FFFh

SA190 10110111XXX 32 5B8000h–5BFFFFh

SA191 10111000XXX 32 5C0000h–5C7FFFh

SA192 10111001XXX 32 5C8000h–5CFFFFh

SA193 10111010XXX 32 5D0000h–5D7FFFh

SA194 10111011XXX 32 5D8000h–5DFFFFh

SA195 10111100XXX 32 5E0000h–5E7FFFh

SA196 10111101XXX 32 5E8000h–5EFFFFh

SA197 10111110XXX 32 5F0000h–5F7FFFh

SA198 10111111XXX 32 5F8000h–5FFFFFh

Table 5. PL127J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

30 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank C

SA199 11000000XXX 32 600000h–607FFFh

SA200 11000001XXX 32 608000h–60FFFFh

SA201 11000010XXX 32 610000h–617FFFh

SA202 11000011XXX 32 618000h–61FFFFh

SA203 11000100XXX 32 620000h–627FFFh

SA204 11000101XXX 32 628000h–62FFFFh

SA205 11000110XXX 32 630000h–637FFFh

SA206 11000111XXX 32 638000h–63FFFFh

SA207 11001000XXX 32 640000h–647FFFh

SA208 11001001XXX 32 648000h–64FFFFh

SA209 11001010XXX 32 650000h–657FFFh

SA210 11001011XXX 32 658000h–65FFFFh

SA211 11001100XXX 32 660000h–667FFFh

SA212 11001101XXX 32 668000h–66FFFFh

SA213 11001110XXX 32 670000h–677FFFh

SA214 11001111XXX 32 678000h–67FFFFh

SA215 11010000XXX 32 680000h–687FFFh

SA216 11010001XXX 32 688000h–68FFFFh

SA217 11010010XXX 32 690000h–697FFFh

SA218 11010011XXX 32 698000h–69FFFFh

SA219 11010100XXX 32 6A0000h–6A7FFFh

SA220 11010101XXX 32 6A8000h–6AFFFFh

SA221 11010110XXX 32 6B0000h–6B7FFFh

SA222 11010111XXX 32 6B8000h–6BFFFFh

SA223 11011000XXX 32 6C0000h–6C7FFFh

SA224 11011001XXX 32 6C8000h–6CFFFFh

SA225 11011010XXX 32 6D0000h–6D7FFFh

SA226 11011011XXX 32 6D8000h–6DFFFFh

SA227 11011100XXX 32 6E0000h–6E7FFFh

SA228 11011101XXX 32 6E8000h–6EFFFFh

SA229 11011110XXX 32 6F0000h–6F7FFFh

SA230 11011111XXX 32 6F8000h–6FFFFFh

Table 5. PL127J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31

PRELIMINARY

Bank D

SA231 11100000XXX 32 700000h–707FFFh

SA232 11100001XXX 32 708000h–70FFFFh

SA233 11100010XXX 32 710000h–717FFFh

SA234 11100011XXX 32 718000h–71FFFFh

SA235 11100100XXX 32 720000h–727FFFh

SA236 11100101XXX 32 728000h–72FFFFh

SA237 11100110XXX 32 730000h–737FFFh

SA238 11100111XXX 32 738000h–73FFFFh

SA239 11101000XXX 32 740000h–747FFFh

SA240 11101001XXX 32 748000h–74FFFFh

SA241 11101010XXX 32 750000h–757FFFh

SA242 11101011XXX 32 758000h–75FFFFh

SA243 11101100XXX 32 760000h–767FFFh

SA244 11101101XXX 32 768000h–76FFFFh

SA245 11101110XXX 32 770000h–777FFFh

SA246 11101111XXX 32 778000h–77FFFFh

SA247 11110000XXX 32 780000h–787FFFh

SA248 11110001XXX 32 788000h–78FFFFh

SA249 11110010XXX 32 790000h–797FFFh

SA250 11110011XXX 32 798000h–79FFFFh

SA251 11110100XXX 32 7A0000h–7A7FFFh

SA252 11110101XXX 32 7A8000h–7AFFFFh

SA253 11110110XXX 32 7B0000h–7B7FFFh

SA254 11110111XXX 32 7B8000h–7BFFFFh

SA255 11111000XXX 32 7C0000h–7C7FFFh

SA256 11111001XXX 32 7C8000h–7CFFFFh

SA257 11111010XXX 32 7D0000h–7D7FFFh

SA258 11111011XXX 32 7D8000h–7DFFFFh

SA259 11111100XXX 32 7E0000h–7E7FFFh

SA260 11111101XXX 32 7E8000h–7EFFFFh

SA261 11111110XXX 32 7F0000h–7F7FFFh

SA262 11111111000 4 7F8000h–7F8FFFh

SA263 11111111001 4 7F9000h–7F9FFFh

SA264 11111111010 4 7FA000h–7FAFFFh

SA265 11111111011 4 7FB000h–7FBFFFh

SA266 11111111100 4 7FC000h–7FCFFFh

SA267 11111111101 4 7FD000h–7FDFFFh

SA268 11111111110 4 7FE000h–7FEFFFh

SA269 11111111111 4 7FF000h–7FFFFFh

Table 5. PL127J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

32 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Table 6. PL064J Sector Architecture

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

Bank A

SA0 0000000000 4 000000h–000FFFh

SA1 0000000001 4 001000h–001FFFh

SA2 0000000010 4 002000h–002FFFh

SA3 0000000011 4 003000h–003FFFh

SA4 0000000100 4 004000h–004FFFh

SA5 0000000101 4 005000h–005FFFh

SA6 0000000110 4 006000h–006FFFh

SA7 0000000111 4 007000h–007FFFh

SA8 0000001XXX 32 008000h–00FFFFh

SA9 0000010XXX 32 010000h–017FFFh

SA10 0000011XXX 32 018000h–01FFFFh

SA11 0000100XXX 32 020000h–027FFFh

SA12 0000101XXX 32 028000h–02FFFFh

SA13 0000110XXX 32 030000h–037FFFh

SA14 0000111XXX 32 038000h–03FFFFh

SA15 0001000XXX 32 040000h–047FFFh

SA16 0001001XXX 32 048000h–04FFFFh

SA17 0001010XXX 32 050000h–057FFFh

SA18 0001011XXX 32 058000h–05FFFFh

SA19 0001100XXX 32 060000h–067FFFh

SA20 0001101XXX 32 068000h–06FFFFh

SA21 0001110XXX 32 070000h–077FFFh

SA22 0001111XXX 32 078000h–07FFFFh

Bank B

SA23 0010000XXX 32 080000h–087FFFh

SA24 0010001XXX 32 088000h–08FFFFh

SA25 0010010XXX 32 090000h–097FFFh

SA26 0010011XXX 32 098000h–09FFFFh

SA27 0010100XXX 32 0A0000h–0A7FFFh

SA28 0010101XXX 32 0A8000h–0AFFFFh

SA29 0010110XXX 32 0B0000h–0B7FFFh

SA30 0010111XXX 32 0B8000h–0BFFFFh

SA31 0011000XXX 32 0C0000h–0C7FFFh

SA32 0011001XXX 32 0C8000h–0CFFFFh

SA33 0011010XXX 32 0D0000h–0D7FFFh

SA34 0011011XXX 32 0D8000h–0DFFFFh

SA35 0011100XXX 32 0E0000h–0E7FFFh

SA36 0011101XXX 32 0E8000h–0EFFFFh

SA37 0011110XXX 32 0F0000h–0F7FFFh

SA38 0011111XXX 32 0F8000h–0FFFFFh

SA39 0100000XXX 32 100000h–107FFFh

SA40 0100001XXX 32 108000h–10FFFFh

SA41 0100010XXX 32 110000h–117FFFh

SA42 0100011XXX 32 118000h–11FFFFh

SA43 0100100XXX 32 120000h–127FFFh

SA44 0100101XXX 32 128000h–12FFFFh

SA45 0100110XXX 32 130000h–137FFFh

SA46 0100111XXX 32 138000h–13FFFFh

SA47 0101000XXX 32 140000h–147FFFh

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 33

PRELIMINARY

Bank B

SA48 0101001XXX 32 148000h–14FFFFh

SA49 0101010XXX 32 150000h–157FFFh

SA50 0101011XXX 32 158000h–15FFFFh

SA51 0101100XXX 32 160000h–167FFFh

SA52 0101101XXX 32 168000h–16FFFFh

SA53 0101110XXX 32 170000h–177FFFh

SA54 0101111XXX 32 178000h–17FFFFh

SA55 0110000XXX 32 180000h–187FFFh

SA56 0110001XXX 32 188000h–18FFFFh

SA57 0110010XXX 32 190000h–197FFFh

SA58 0110011XXX 32 198000h–19FFFFh

SA59 0110100XXX 32 1A0000h–1A7FFFh

SA60 0110101XXX 32 1A8000h–1AFFFFh

SA61 0110110XXX 32 1B0000h–1B7FFFh

SA62 0110111XXX 32 1B8000h–1BFFFFh

SA63 0111000XXX 32 1C0000h–1C7FFFh

SA64 0111001XXX 32 1C8000h–1CFFFFh

SA65 0111010XXX 32 1D0000h–1D7FFFh

SA66 0111011XXX 32 1D8000h–1DFFFFh

SA67 0111100XXX 32 1E0000h–1E7FFFh

SA68 0111101XXX 32 1E8000h–1EFFFFh

SA69 0111110XXX 32 1F0000h–1F7FFFh

SA70 0111111XXX 32 1F8000h–1FFFFFh

Bank C

SA71 1000000XXX 32 200000h–207FFFh

SA72 1000001XXX 32 208000h–20FFFFh

SA73 1000010XXX 32 210000h–217FFFh

SA74 1000011XXX 32 218000h–21FFFFh

SA75 1000100XXX 32 220000h–227FFFh

SA76 1000101XXX 32 228000h–22FFFFh

SA77 1000110XXX 32 230000h–237FFFh

SA78 1000111XXX 32 238000h–23FFFFh

SA79 1001000XXX 32 240000h–247FFFh

SA80 1001001XXX 32 248000h–24FFFFh

SA81 1001010XXX 32 250000h–257FFFh

SA82 1001011XXX 32 258000h–25FFFFh

SA83 1001100XXX 32 260000h–267FFFh

SA84 1001101XXX 32 268000h–26FFFFh

SA85 1001110XXX 32 270000h–277FFFh

SA86 1001111XXX 32 278000h–27FFFFh

Bank C

SA87 1010000XXX 32 280000h–287FFFh

SA88 1010001XXX 32 288000h–28FFFFh

SA89 1010010XXX 32 290000h–297FFFh

SA90 1010011XXX 32 298000h–29FFFFh

SA91 1010100XXX 32 2A0000h–2A7FFFh

SA92 1010101XXX 32 2A8000h–2AFFFFh

SA93 1010110XXX 32 2B0000h–2B7FFFh

SA94 1010111XXX 32 2B8000h–2BFFFFh

SA95 1011000XXX 32 2C0000h–2C7FFFh

Table 6. PL064J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

34 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank C

SA96 1011001XXX 32 2C8000h–2CFFFFh

SA97 1011010XXX 32 2D0000h–2D7FFFh

SA98 1011011XXX 32 2D8000h–2DFFFFh

SA99 1011100XXX 32 2E0000h–2E7FFFh

SA100 1011101XXX 32 2E8000h–2EFFFFh

SA101 1011110XXX 32 2F0000h–2F7FFFh

SA102 1011111XXX 32 2F8000h–2FFFFFh

SA103 1100000XXX 32 300000h–307FFFh

SA104 1100001XXX 32 308000h–30FFFFh

SA105 1100010XXX 32 310000h–317FFFh

SA106 1100011XXX 32 318000h–31FFFFh

SA107 1100100XXX 32 320000h–327FFFh

SA108 1100101XXX 32 328000h–32FFFFh

SA109 1100110XXX 32 330000h–337FFFh

SA110 1100111XXX 32 338000h–33FFFFh

SA111 1101000XXX 32 340000h–347FFFh

SA112 1101001XXX 32 348000h–34FFFFh

SA113 1101010XXX 32 350000h–357FFFh

SA114 1101011XXX 32 358000h–35FFFFh

SA115 1101100XXX 32 360000h–367FFFh

SA116 1101101XXX 32 368000h–36FFFFh

SA117 1101110XXX 32 370000h–377FFFh

SA118 1101111XXX 32 378000h–37FFFFh

Bank D

SA119 1110000XXX 32 380000h–387FFFh

SA120 1110001XXX 32 388000h–38FFFFh

SA121 1110010XXX 32 390000h–397FFFh

SA122 1110011XXX 32 398000h–39FFFFh

SA123 1110100XXX 32 3A0000h–3A7FFFh

SA124 1110101XXX 32 3A8000h–3AFFFFh

SA125 1110110XXX 32 3B0000h–3B7FFFh

SA126 1110111XXX 32 3B8000h–3BFFFFh

SA127 1111000XXX 32 3C0000h–3C7FFFh

SA128 1111001XXX 32 3C8000h–3CFFFFh

SA129 1111010XXX 32 3D0000h–3D7FFFh

SA130 1111011XXX 32 3D8000h–3DFFFFh

SA131 1111100XXX 32 3E0000h–3E7FFFh

SA132 1111101XXX 32 3E8000h–3EFFFFh

SA133 1111110XXX 32 3F0000h–3F7FFFh

SA134 1111111000 4 3F8000h–3F8FFFh

SA135 1111111001 4 3F9000h–3F9FFFh

SA136 1111111010 4 3FA000h–3FAFFFh

SA137 1111111011 4 3FB000h–3FBFFFh

SA138 1111111100 4 3FC000h–3FCFFFh

SA139 1111111101 4 3FD000h–3FDFFFh

SA140 1111111110 4 3FE000h–3FEFFFh

SA141 1111111111 4 3FF000h–3FFFFFh

Table 6. PL064J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 35

PRELIMINARY

Table 7. PL032J Sector Architecture

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

Bank A

SA0 000000000 4 000000h–000FFFh

SA1 000000001 4 001000h–001FFFh

SA2 000000010 4 002000h–002FFFh

SA3 000000011 4 003000h–003FFFh

SA4 000000100 4 004000h–004FFFh

SA5 000000101 4 005000h–005FFFh

SA6 000000110 4 006000h–006FFFh

SA7 000000111 4 007000h–007FFFh

SA8 000001XXX 32 008000h–00FFFFh

SA9 000010XXX 32 010000h–017FFFh

SA10 000011XXX 32 018000h–01FFFFh

SA11 000100XXX 32 020000h–027FFFh

SA12 000101XXX 32 028000h–02FFFFh

SA13 000110XXX 32 030000h–037FFFh

SA14 000111XXX 32 038000h–03FFFFh

Bank B

SA15 001000XXX 32 040000h–047FFFh

SA16 001001XXX 32 048000h–04FFFFh

SA17 001010XXX 32 050000h–057FFFh

SA18 001011XXX 32 058000h–05FFFFh

SA19 001100XXX 32 060000h–067FFFh

SA20 001101XXX 32 068000h–06FFFFh

SA21 001110XXX 32 070000h–077FFFh

SA22 001111XXX 32 078000h–07FFFFh

SA23 010000XXX 32 080000h–087FFFh

SA24 010001XXX 32 088000h–08FFFFh

SA25 010010XXX 32 090000h–097FFFh

SA26 010011XXX 32 098000h–09FFFFh

SA27 010100XXX 32 0A0000h–0A7FFFh

SA28 010101XXX 32 0A8000h–0AFFFFh

SA29 010110XXX 32 0B0000h–0B7FFFh

SA30 010111XXX 32 0B8000h–0BFFFFh

SA31 011000XXX 32 0C0000h–0C7FFFh

SA32 011001XXX 32 0C8000h–0CFFFFh

SA33 011010XXX 32 0D0000h–0D7FFFh

SA34 011011XXX 32 0D8000h–0DFFFFh

SA35 011100XXX 32 0E0000h–0E7FFFh

SA36 011101XXX 32 0E8000h–0EFFFFh

SA37 011110XXX 32 0F0000h–0F7FFFh

SA38 011111XXX 32 0F8000h–0FFFFFh

36 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank C

SA39 100000XXX 32 100000h–107FFFh

SA40 100001XXX 32 108000h–10FFFFh

SA41 100010XXX 32 110000h–117FFFh

SA42 100011XXX 32 118000h–11FFFFh

SA43 100100XXX 32 120000h–127FFFh

SA44 100101XXX 32 128000h–12FFFFh

SA45 100110XXX 32 130000h–137FFFh

SA46 100111XXX 32 138000h–13FFFFh

SA47 101000XXX 32 140000h–147FFFh

SA48 101001XXX 32 148000h–14FFFFh

SA49 101010XXX 32 150000h–157FFFh

SA50 101011XXX 32 158000h–15FFFFh

SA51 101100XXX 32 160000h–167FFFh

SA52 101101XXX 32 168000h–16FFFFh

SA53 101110XXX 32 170000h–177FFFh

SA54 101111XXX 32 178000h–17FFFFh

SA55 110000XXX 32 180000h–187FFFh

SA56 110001XXX 32 188000h–18FFFFh

SA57 110010XXX 32 190000h–197FFFh

SA58 110011XXX 32 198000h–19FFFFh

SA59 110100XXX 32 1A0000h–1A7FFFh

SA60 110101XXX 32 1A8000h–1AFFFFh

SA61 110110XXX 32 1B0000h–1B7FFFh

SA62 110111XXX 32 1B8000h–1BFFFFh

Bank D

SA63 111000XXX 32 1C0000h–1C7FFFh

SA64 111001XXX 32 1C8000h–1CFFFFh

SA65 111010XXX 32 1D0000h–1D7FFFh

SA66 111011XXX 32 1D8000h–1DFFFFh

SA67 111100XXX 32 1E0000h–1E7FFFh

SA68 111101XXX 32 1E8000h–1EFFFFh

SA69 111110XXX 32 1F0000h–1F7FFFh

SA70 111111000 4 1F8000h–1F8FFFh

SA71 111111001 4 1F9000h–1F9FFFh

SA72 111111010 4 1FA000h–1FAFFFh

SA73 111111011 4 1FB000h–1FBFFFh

SA74 111111100 4 1FC000h–1FCFFFh

SA75 111111101 4 1FD000h–1FDFFFh

SA76 111111110 4 1FE000h–1FEFFFh

SA77 111111111 4 1FF000h–1FFFFFh

Table 7. PL032J Sector Architecture (Continued)

Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 37

PRELIMINARY

Table 8. S29PL129J Sector Architecture

Bank Sector CE1# CE2#

Sector Address

(A21-A12)

Sector Size

(Kwords) Address Range (x16)

Bank 1A

SA1-0 0 1 0000000000 4 000000h–000FFFh

SA1-1 0 1 0000000001 4 001000h–001FFFh

SA1-2 0 1 0000000010 4 002000h–002FFFh

SA1-3 0 1 0000000011 4 003000h–003FFFh

SA1-4 0 1 0000000100 4 004000h–004FFFh

SA1-5 0 1 0000000101 4 005000h–005FFFh

SA1-6 0 1 0000000110 4 006000h–006FFFh

SA1-7 0 1 0000000111 4 007000h–007FFFh

SA1-8 0 1 0000001XXX 32 008000h–00FFFFh

SA1-9 0 1 0000010XXX 32 010000h–017FFFh

SA1-10 0 1 0000011XXX 32 018000h–01FFFFh

SA1-11 0 1 0000100XXX 32 020000h–027FFFh

SA1-12 0 1 0000101XXX 32 028000h–02FFFFh

SA1-13 0 1 0000110XXX 32 030000h–037FFFh

SA1-14 0 1 0000111XXX 32 038000h–03FFFFh

SA1-15 0 1 0001000XXX 32 040000h–047FFFh

SA1-16 0 1 0001001XXX 32 048000h–04FFFFh

SA1-17 0 1 0001010XXX 32 050000h–057FFFh

SA1-18 0 1 0001011XXX 32 058000h–05FFFFh

SA1-19 0 1 0001100XXX 32 060000h–067FFFh

SA1-20 0 1 0001101XXX 32 068000h–06FFFFh

SA1-21 0 1 0001110XXX 32 070000h–077FFFh

SA1-22 0 1 0001111XXX 32 078000h–07FFFFh

SA1-23 0 1 0010000XXX 32 080000h–087FFFh

SA1-24 0 1 0010001XXX 32 088000h–08FFFFh

SA1-25 0 1 0010010XXX 32 090000h–097FFFh

SA1-26 0 1 0010011XXX 32 098000h–09FFFFh

SA1-27 0 1 0010100XXX 32 0A0000h–0A7FFFh

SA1-28 0 1 0010101XXX 32 0A8000h–0AFFFFh

SA1-29 0 1 0010110XXX 32 0B0000h–0B7FFFh

SA1-30 0 1 0010111XXX 32 0B8000h–0BFFFFh

SA1-31 0 1 0011000XXX 32 0C0000h–0C7FFFh

SA1-32 0 1 0011001XXX 32 0C8000h–0CFFFFh

SA1-33 0 1 0011010XXX 32 0D0000h–0D7FFFh

SA1-34 0 1 0011011XXX 32 0D8000h–0DFFFFh

SA1-35 0 1 0011100XXX 32 0E0000h–0E7FFFh

SA1-36 0 1 0011101XXX 32 0E8000h–0EFFFFh

SA1-37 0 1 0011110XXX 32 0F0000h–0F7FFFh

SA1-38 0 1 0011111XXX 32 0F8000h–0FFFFFh

38 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank 1B

SA1-39 0 1 0100000XXX 32 100000h–107FFFh

SA1-40 0 1 0100001XXX 32 108000h–10FFFFh

SA1-41 0 1 0100010XXX 32 110000h–117FFFh

SA1-42 0 1 0100011XXX 32 118000h–11FFFFh

SA1-43 0 1 0100100XXX 32 120000h–127FFFh

SA1-44 0 1 0100101XXX 32 128000h–12FFFFh

SA1-45 0 1 0100110XXX 32 130000h–137FFFh

SA1-46 0 1 0100111XXX 32 138000h–13FFFFh

SA1-47 0 1 0101000XXX 32 140000h–147FFFh

SA1-48 0 1 0101001XXX 32 148000h–14FFFFh

SA1-49 0 1 0101010XXX 32 150000h–157FFFh

SA1-50 0 1 0101011XXX 32 158000h–15FFFFh

SA1-51 0 1 0101100XXX 32 160000h–167FFFh

SA1-52 0 1 0101101XXX 32 168000h–16FFFFh

SA1-53 0 1 0101110XXX 32 170000h–177FFFh

SA1-54 0 1 0101111XXX 32 178000h–17FFFFh

SA1-55 0 1 0110000XXX 32 180000h–187FFFh

SA1-56 0 1 0110001XXX 32 188000h–18FFFFh

SA1-57 0 1 0110010XXX 32 190000h–197FFFh

SA1-58 0 1 0110011XXX 32 198000h–19FFFFh

SA1-59 0 1 0110100XXX 32 1A0000h–1A7FFFh

SA1-60 0 1 0110101XXX 32 1A8000h–1AFFFFh

SA1-61 0 1 0110110XXX 32 1B0000h–1B7FFFh

SA1-62 0 1 0110111XXX 32 1B8000h–1BFFFFh

SA1-63 0 1 0111000XXX 32 1C0000h–1C7FFFh

SA1-64 0 1 0111001XXX 32 1C8000h–1CFFFFh

SA1-65 0 1 0111010XXX 32 1D0000h–1D7FFFh

SA1-66 0 1 0111011XXX 32 1D8000h–1DFFFFh

SA1-67 0 1 0111100XXX 32 1E0000h–1E7FFFh

SA1-68 0 1 0111101XXX 32 1E8000h–1EFFFFh

SA1-69 0 1 0111110XXX 32 1F0000h–1F7FFFh

SA1-70 0 1 0111111XXX 32 1F8000h–1FFFFFh

SA1-71 0 1 1000000XXX 32 200000h–207FFFh

SA1-72 0 1 1000001XXX 32 208000h–20FFFFh

SA1-73 0 1 1000010XXX 32 210000h–217FFFh

SA1-74 0 1 1000011XXX 32 218000h–21FFFFh

SA1-75 0 1 1000100XXX 32 220000h–227FFFh

SA1-76 0 1 1000101XXX 32 228000h–22FFFFh

SA1-77 0 1 1000110XXX 32 230000h–237FFFh

SA1-78 0 1 1000111XXX 32 238000h–23FFFFh

SA1-79 0 1 1001000XXX 32 240000h–247FFFh

SA1-80 0 1 1001001XXX 32 248000h–24FFFFh

SA1-81 0 1 1001010XXX 32 250000h–257FFFh

SA1-82 0 1 1001011XXX 32 258000h–25FFFFh

Table 8. S29PL129J Sector Architecture (Continued)

Bank Sector CE1# CE2#

Sector Address

(A21-A12)

Sector Size

(Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 39

PRELIMINARY

Bank 1B

SA1-83 0 1 1001100XXX 32 260000h–267FFFh

SA1-84 0 1 1001101XXX 32 268000h–26FFFFh

SA1-85 0 1 1001110XXX 32 270000h–277FFFh

SA1-86 0 1 1001111XXX 32 278000h–27FFFFh

SA1-87 0 1 1010000XXX 32 280000h–287FFFh

SA1-88 0 1 1010001XXX 32 288000h–28FFFFh

SA1-89 0 1 1010010XXX 32 290000h–297FFFh

SA1-90 0 1 1010011XXX 32 298000h–29FFFFh

SA1-91 0 1 1010100XXX 32 2A0000h–2A7FFFh

SA1-92 0 1 1010101XXX 32 2A8000h–2AFFFFh

SA1-93 0 1 1010110XXX 32 2B0000h–2B7FFFh

SA1-94 0 1 1010111XXX 32 2B8000h–2BFFFFh

SA1-95 0 1 1011000XXX 32 2C0000h–2C7FFFh

SA1-96 0 1 1011001XXX 32 2C8000h–2CFFFFh

SA1-97 0 1 1011010XXX 32 2D0000h–2D7FFFh

SA1-98 0 1 1011011XXX 32 2D8000h–2DFFFFh

SA1-99 0 1 1011100XXX 32 2E0000h–2E7FFFh

SA1-100 0 1 1011101XXX 32 2E8000h–2EFFFFh

SA1-101 0 1 1011110XXX 32 2F0000h–2F7FFFh

SA1-102 0 1 1011111XXX 32 2F8000h–2FFFFFh

SA1-103 0 1 1100000XXX 32 300000h–307FFFh

SA1-104 0 1 1100001XXX 32 308000h–30FFFFh

SA1-105 0 1 1100010XXX 32 310000h–317FFFh

SA1-106 0 1 1100011XXX 32 318000h–31FFFFh

SA1-107 0 1 1100100XXX 32 320000h–327FFFh

SA1-108 0 1 1100101XXX 32 328000h–32FFFFh

SA1-109 0 1 1100110XXX 32 330000h–337FFFh

SA1-110 0 1 1100111XXX 32 338000h–33FFFFh

SA1-111 0 1 1101000XXX 32 340000h–347FFFh

SA1-112 0 1 1101001XXX 32 348000h–34FFFFh

SA1-113 0 1 1101010XXX 32 350000h–357FFFh

SA1-114 0 1 1101011XXX 32 358000h–35FFFFh

SA1-115 0 1 1101100XXX 32 360000h–367FFFh

SA1-116 0 1 1101101XXX 32 368000h–36FFFFh

SA1-117 0 1 1101110XXX 32 370000h–377FFFh

SA1-118 0 1 1101111XXX 32 378000h–37FFFFh

SA1-119 0 1 1110000XXX 32 380000h–387FFFh

SA1-120 0 1 1110001XXX 32 388000h–38FFFFh

SA1-121 0 1 1110010XXX 32 390000h–397FFFh

SA1-122 0 1 1110011XXX 32 398000h–39FFFFh

SA1-123 0 1 1110100XXX 32 3A0000h–3A7FFFh

SA1-124 0 1 1110101XXX 32 3A8000h–3AFFFFh

SA1-125 0 1 1110110XXX 32 3B0000h–3B7FFFh

SA1-126 0 1 1110111XXX 32 3B8000h–3BFFFFh

Table 8. S29PL129J Sector Architecture (Continued)

Bank Sector CE1# CE2#

Sector Address

(A21-A12)

Sector Size

(Kwords) Address Range (x16)

40 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank 1B

SA1-127 0 1 1111000XXX 32 3C0000h–3C7FFFh

SA1-128 0 1 1111001XXX 32 3C8000h–3CFFFFh

SA1-129 0 1 1111010XXX 32 3D0000h–3D7FFFh

SA1-130 0 1 1111011XXX 32 3D8000h–3DFFFFh

SA1-131 0 1 1111100XXX 32 3E0000h–3E7FFFh

SA1-132 0 1 1111101XXX 32 3E8000h–3EFFFFh

SA1-133 0 1 1111110XXX 32 3F0000h–3F7FFFh

SA1-134 0 1 1111111XXX 32 3F8000h–3FFFFFh

Bank 2A

SA2-0 1 0 0000000XXX 32 000000h–007FFFh

SA2-1 1 0 0000001XXX 32 008000h–00FFFFh

SA2-2 1 0 0000010XXX 32 010000h–017FFFh

SA2-3 1 0 0000011XXX 32 018000h–01FFFFh

SA2-4 1 0 0000100XXX 32 020000h–027FFFh

SA2-5 1 0 0000101XXX 32 028000h–02FFFFh

SA2-6 1 0 0000110XXX 32 030000h–037FFFh

SA2-7 1 0 0000111XXX 32 038000h–03FFFFh

SA2-8 1 0 0001000XXX 32 040000h–047FFFh

SA2-9 1 0 0001001XXX 32 048000h–04FFFFh

SA2-10 1 0 0001010XXX 32 050000h–057FFFh

SA2-11 1 0 0001011XXX 32 058000h–05FFFFh

SA2-12 1 0 0001100XXX 32 060000h–067FFFh

SA2-13 1 0 0001101XXX 32 068000h–06FFFFh

SA2-14 1 0 0001110XXX 32 070000h–077FFFh

SA2-15 1 0 0001111XXX 32 078000h–07FFFFh

SA2-16 1 0 0010000XXX 32 080000h–087FFFh

SA2-17 1 0 0010001XXX 32 088000h–08FFFFh

SA2-18 1 0 0010010XXX 32 090000h–097FFFh

SA2-19 1 0 0010011XXX 32 098000h–09FFFFh

SA2-20 1 0 0010100XXX 32 0A0000h–0A7FFFh

SA2-21 1 0 0010101XXX 32 0A8000h–0AFFFFh

SA2-22 1 0 0010110XXX 32 0B0000h–0B7FFFh

SA2-23 1 0 0010111XXX 32 0B8000h–0BFFFFh

SA2-24 1 0 0011000XXX 32 0C0000h–0C7FFFh

SA2-25 1 0 0011001XXX 32 0C8000h–0CFFFFh

SA2-26 1 0 0011010XXX 32 0D0000h–0D7FFFh

SA2-27 1 0 0011011XXX 32 0D8000h–0DFFFFh

SA2-28 1 0 0011100XXX 32 0E0000h–0E7FFFh

SA2-29 1 0 0011101XXX 32 0E8000h–0EFFFFh

SA2-30 1 0 0011110XXX 32 0F0000h–0F7FFFh

SA2-31 1 0 0011111XXX 32 0F8000h–0FFFFFh

SA2-32 1 0 0100000XXX 32 100000h–107FFFh

SA2-33 1 0 0100001XXX 32 108000h–10FFFFh

SA2-34 1 0 0100010XXX 32 110000h–117FFFh

SA2-35 1 0 0100011XXX 32 118000h–11FFFFh

Table 8. S29PL129J Sector Architecture (Continued)

Bank Sector CE1# CE2#

Sector Address

(A21-A12)

Sector Size

(Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 41

PRELIMINARY

Bank 2A

SA2-36 1 0 0100100XXX 32 120000h–127FFFh

SA2-37 1 0 0100101XXX 32 128000h–12FFFFh

SA2-38 1 0 0100110XXX 32 130000h–137FFFh

SA2-39 1 0 0100111XXX 32 138000h–13FFFFh

SA2-40 1 0 0101000XXX 32 140000h–147FFFh

SA2-41 1 0 0101001XXX 32 148000h–14FFFFh

SA2-42 1 0 0101010XXX 32 150000h–157FFFh

SA2-43 1 0 0101011XXX 32 158000h–15FFFFh

Bank 2A

SA2-44 1 0 0101100XXX 32 160000h–167FFFh

SA2-45 1 0 0101101XXX 32 168000h–16FFFFh

SA2-46 1 0 0101110XXX 32 170000h–177FFFh

SA2-47 1 0 0101111XXX 32 178000h–17FFFFh

SA2-48 1 0 0110000XXX 32 180000h–187FFFh

SA2-49 1 0 0110001XXX 32 188000h–18FFFFh

SA2-50 1 0 0110010XXX 32 190000h–197FFFh

SA2-51 1 0 0110011XXX 32 198000h–19FFFFh

SA2-52 1 0 0110100XXX 32 1A0000h–1A7FFFh

SA2-53 1 0 0110101XXX 32 1A8000h–1AFFFFh

SA2-54 1 0 0110110XXX 32 1B0000h–1B7FFFh

SA2-55 1 0 0110111XXX 32 1B8000h–1BFFFFh

SA2-56 1 0 0111000XXX 32 1C0000h–1C7FFFh

SA2-57 1 0 0111001XXX 32 1C8000h–1CFFFFh

SA2-58 1 0 0111010XXX 32 1D0000h–1D7FFFh

SA2-59 1 0 0111011XXX 32 1D8000h–1DFFFFh

SA2-60 1 0 0111100XXX 32 1E0000h–1E7FFFh

SA2-61 1 0 0111101XXX 32 1E8000h–1EFFFFh

SA2-62 1 0 0111110XXX 32 1F0000h–1F7FFFh

SA2-63 1 0 0111111XXX 32 1F8000h–1FFFFFh

SA2-64 1 0 1000000XXX 32 200000h–207FFFh

SA2-65 1 0 1000001XXX 32 208000h–20FFFFh

SA2-66 1 0 1000010XXX 32 210000h–217FFFh

SA2-67 1 0 1000011XXX 32 218000h–21FFFFh

SA2-68 1 0 1000100XXX 32 220000h–227FFFh

SA2-69 1 0 1000101XXX 32 228000h–22FFFFh

SA2-70 1 0 1000110XXX 32 230000h–237FFFh

SA2-71 1 0 1000111XXX 32 238000h–23FFFFh

SA2-72 1 0 1001000XXX 32 240000h–247FFFh

SA2-73 1 0 1001001XXX 32 248000h–24FFFFh

SA2-74 1 0 1001010XXX 32 250000h–257FFFh

SA2-75 1 0 1001011XXX 32 258000h–25FFFFh

SA2-76 1 0 1001100XXX 32 260000h–267FFFh

SA2-77 1 0 1001101XXX 32 268000h–26FFFFh

SA2-78 1 0 1001110XXX 32 270000h–277FFFh

SA2-79 1 0 1001111XXX 32 278000h–27FFFFh

Table 8. S29PL129J Sector Architecture (Continued)

Bank Sector CE1# CE2#

Sector Address

(A21-A12)

Sector Size

(Kwords) Address Range (x16)

42 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Bank 2A

SA2-80 1 0 1010000XXX 32 280000h–287FFFh

SA2-81 1 0 1010001XXX 32 288000h–28FFFFh

SA2-82 1 0 1010010XXX 32 290000h–297FFFh

SA2-83 1 0 1010011XXX 32 298000h–29FFFFh

SA2-84 1 0 1010100XXX 32 2A0000h–2A7FFFh

SA2-85 1 0 1010101XXX 32 2A8000h–2AFFFFh

SA2-86 1 0 1010110XXX 32 2B0000h–2B7FFFh

SA2-87 1 0 1010111XXX 32 2B8000h–2BFFFFh

SA2-88 1 0 1011000XXX 32 2C0000h–2C7FFFh

SA2-89 1 0 1011001XXX 32 2C8000h–2CFFFFh

SA2-90 1 0 1011010XXX 32 2D0000h–2D7FFFh

SA2-91 1 0 1011011XXX 32 2D8000h–2DFFFFh

SA2-92 1 0 1011100XXX 32 2E0000h–2E7FFFh

SA2-93 1 0 1011101XXX 32 2E8000h–2EFFFFh

SA2-94 1 0 1011110XXX 32 2F0000h–2F7FFFh

SA2-95 1 0 1011111XXX 32 2F8000h–2FFFFFh

Bank 2B

SA2-96 1 0 1100000XXX 32 300000h–307FFFh

SA2-97 1 0 1100001XXX 32 308000h–30FFFFh

SA2-98 1 0 1100010XXX 32 310000h–317FFFh

SA2-99 1 0 1100011XXX 32 318000h–31FFFFh

SA2-100 1 0 1100100XXX 32 320000h–327FFFh

SA2-101 1 0 1100101XXX 32 328000h–32FFFFh

SA2-102 1 0 1100110XXX 32 330000h–337FFFh

SA2-103 1 0 1100111XXX 32 338000h–33FFFFh

SA2-104 1 0 1101000XXX 32 340000h–347FFFh

SA2-105 1 0 1101001XXX 32 348000h–34FFFFh

SA2-106 1 0 1101010XXX 32 350000h–357FFFh

SA2-107 1 0 1101011XXX 32 358000h–35FFFFh

SA2-108 1 0 1101100XXX 32 360000h–367FFFh

SA2-109 1 0 1101101XXX 32 368000h–36FFFFh

SA2-110 1 0 1101110XXX 32 370000h–377FFFh

SA2-111 1 0 1101111XXX 32 378000h–37FFFFh

SA2-112 1 0 1110000XXX 32 380000h–387FFFh

SA2-113 1 0 1110001XXX 32 388000h–38FFFFh

SA2-114 1 0 1110010XXX 32 390000h–397FFFh

SA2-115 1 0 1110011XXX 32 398000h–39FFFFh

SA2-116 1 0 1110100XXX 32 3A0000h–3A7FFFh

SA2-117 1 0 1110101XXX 32 3A8000h–3AFFFFh

SA2-118 1 0 1110110XXX 32 3B0000h–3B7FFFh

SA2-119 1 0 1110111XXX 32 3B8000h–3BFFFFh

SA2-120 1 0 1111000XXX 32 3C0000h–3C7FFFh

SA2-121 1 0 1111001XXX 32 3C8000h–3CFFFFh

SA2-122 1 0 1111010XXX 32 3D0000h–3D7FFFh

SA2-123 1 0 1111011XXX 32 3D8000h–3DFFFFh

Table 8. S29PL129J Sector Architecture (Continued)

Bank Sector CE1# CE2#

Sector Address

(A21-A12)

Sector Size

(Kwords) Address Range (x16)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 43

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector

protection verification, through identifier codes output on DQ7–DQ0. This mode

is primarily intended for programming equipment to automatically match a device

to be programmed with its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID on ad-

dress pin A9. Address pins must be as shown in Table 10 and Table 11. In

addition, when verifying sector protection, the sector address must appear on the

appropriate highest order address bits (see Ta b le 4). Tab l e 1 0 and Tab le 1 1 show

the remaining address bits that are don’t care. When all necessary bits have been

set as required, the programming equipment may then read the corresponding

identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed

in-system through the command register, for instances when the device is erased

or programmed in a system without access to high voltage on the A9 pin. The

command sequence is illustrated in Tab l e 21. Note that if a Bank Address (BA)

(on address bits PL127J: A22–A20, PL129J and PL064J: A21–A19, PL032J:

A20–A18) is asserted during the third write cycle of the autoselect command, the

host system can read autoselect data that bank and then immediately read array

data from the other bank, without exiting the autoselect mode.

To access the autoselect codes in-system, the host system can issue the autose-

lect command via the command register, as shown in Tab le 2 1 . This method does

not require VID. Refer to the "Autoselect Command Sequence" section for more

information.

Bank 2B

SA2-124 1 0 1111100XXX 32 3E0000h–3E7FFFh

SA2-125 1 0 1111101XXX 32 3E8000h–3EFFFFh

SA2-126 1 0 1111110XXX 32 3F0000h–3F7FFFh

SA2-127 1 0 1111111000 4 3F8000h–3F8FFFh

SA2-128 1 0 1111111001 4 3F9000h–3F9FFFh

SA2-129 1 0 1111111010 4 3FA000h–3FAFFFh

SA2-130 1 0 1111111011 4 3FB000h–3FBFFFh

SA2-131 1 0 1111111100 4 3FC000h–3FCFFFh

SA2-132 1 0 1111111101 4 3FD000h–3FDFFFh

SA2-133 1 0 1111111110 4 3FE000h–3FEFFFh

SA2-134 1 0 1111111111 4 3FF000h–3FFFFFh

Table 9. SecSiTM Sector Addresses

Sector Size Address Range

Factory-Locked Area 64 words 000000h-00003Fh

Customer-Lockable Area 64 words 000040h-00007Fh

Table 8. S29PL129J Sector Architecture (Continued)

Bank Sector CE1# CE2#

Sector Address

(A21-A12)

Sector Size

(Kwords) Address Range (x16)

44 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences

Table 10. Autoselect Codes (High Voltage Method)

Description CE# OE# WE#

Amax

A12 A10 A9 A8 A7 A6

A4 A3 A2 A1 A0

DQ15

to DQ0

Manufacturer

Spansion

products

LLHBAXV

X L L X L L L L 0001h

Device ID

Read

Cycle 1 L

LHBAXV

XL L L

L L L H 227Eh

Read

Cycle 2 LHHHL

2220h (PL127J)

2202h (PL064J)

220Ah (PL032J)

Read

Cycle 3 LHHHH

2200h (PL127J)

2201h (PL064J)

2201h (PL032J)

Sector

Protection

Verification

LLHSAXV

XL L L LLHL 0001h (protected),

0000h (unprotected)

SecSi Indicator

Bit (DQ7,

DQ6)

LLHBAXV

XXL X LLHH

DQ7=1 (factory locked),

DQ6=1 (factory and

customer locked)

Table 11. Autoselect Codes for PL129J

Description CE1# CE2# OE# WE#

A21

A12 A10 A9 A8 A7 A6

A4 A3 A2 A1 A0

DQ15

to DQ0

Manufacturer

Spansion

products

LHXX

X L L X L L L L 0001h

Device ID

Read

Cycle 1

LHXX

XL L L

L L L H 227Eh

Read

Cycle 2

LH H H H L 2221h

Read

Cycle 3

LH H H H H 2200h

Sector

Protection

Verification

LHSAX

XL L L LLHL 0001h (protected),

0000h (unprotected)

SecSi

Indicator Bit

(DQ7, DQ6)

LHXX

XXL X LLHH

DQ7=1 (factory locked),

DQ6=1 (factory and

customer locked)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 45

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Table 12. PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector A22-A12

Sector/

Sector Block Size Sector A22-A12

Sector/

Sector Block Size

SA0 00000000000 4 Kwords SA131-SA134 011111XXXXX 128 (4x32) Kwords

SA1 00000000001 4 Kwords SA135-SA138 100000XXXXX 128 (4x32) Kwords

SA2 00000000010 4 Kwords SA139-SA142 100001XXXXX 128 (4x32) Kwords

SA3 00000000011 4 Kwords SA143-SA146 100010XXXXX 128 (4x32) Kwords

SA4 00000000100 4 Kwords SA147-SA150 100011XXXXX 128 (4x32) Kwords

SA5 00000000101 4 Kwords SA151-SA154 100100XXXXX 128 (4x32) Kwords

SA6 00000000110 4 Kwords SA155-SA158 100101XXXXX 128 (4x32) Kwords

SA7 00000000111 4 Kwords SA159-SA162 100110XXXXX 128 (4x32) Kwords

SA8 00000001XXX 32 Kwords SA163-SA166 100111XXXXX 128 (4x32) Kwords

SA9 00000010XXX 32 Kwords SA167-SA170 101000XXXXX 128 (4x32) Kwords

SA10 00000011XXX 32 Kwords SA171-SA174 101001XXXXX 128 (4x32) Kwords

SA11-SA14 000001XXXXX 128 (4x32) Kwords SA175-SA178 101010XXXXX 128 (4x32) Kwords

SA15-SA18 000010XXXXX 128 (4x32) Kwords SA179-SA182 101011XXXXX 128 (4x32) Kwords

SA19-SA22 000011XXXXX 128 (4x32) Kwords SA183-SA186 101100XXXXX 128 (4x32) Kwords

SA23-SA26 000100XXXXX 128 (4x32) Kwords SA187-SA190 101101XXXXX 128 (4x32) Kwords

SA27-SA30 000101XXXXX 128 (4x32) Kwords SA191-SA194 101110XXXXX 128 (4x32) Kwords

SA31-SA34 000110XXXXX 128 (4x32) Kwords SA195-SA198 101111XXXXX 128 (4x32) Kwords

SA35-SA38 000111XXXXX 128 (4x32) Kwords SA199-SA202 110000XXXXX 128 (4x32) Kwords

SA39-SA42 001000XXXXX 128 (4x32) Kwords SA203-SA206 110001XXXXX 128 (4x32) Kwords

SA43-SA46 001001XXXXX 128 (4x32) Kwords SA207-SA210 110010XXXXX 128 (4x32) Kwords

SA47-SA50 001010XXXXX 128 (4x32) Kwords SA211-SA214 110011XXXXX 128 (4x32) Kwords

SA51-SA54 001011XXXXX 128 (4x32) Kwords SA215-SA218 110100XXXXX 128 (4x32) Kwords

SA55-SA58 001100XXXXX 128 (4x32) Kwords SA219-SA222 110101XXXXX 128 (4x32) Kwords

SA59-SA62 001101XXXXX 128 (4x32) Kwords SA223-SA226 110110XXXXX 128 (4x32) Kwords

SA63-SA66 001110XXXXX 128 (4x32) Kwords SA227-SA230 110111XXXXX 128 (4x32) Kwords

SA67-SA70 001111XXXXX 128 (4x32) Kwords SA231-SA234 111000XXXXX 128 (4x32) Kwords

SA71-SA74 010000XXXXX 128 (4x32) Kwords SA235-SA238 111001XXXXX 128 (4x32) Kwords

SA75-SA78 010001XXXXX 128 (4x32) Kwords SA239-SA242 111010XXXXX 128 (4x32) Kwords

SA79-SA82 010010XXXXX 128 (4x32) Kwords SA243-SA246 111011XXXXX 128 (4x32) Kwords

SA83-SA86 010011XXXXX 128 (4x32) Kwords SA247-SA250 111100XXXXX 128 (4x32) Kwords

SA87-SA90 010100XXXXX 128 (4x32) Kwords SA251-SA254 111101XXXXX 128 (4x32) Kwords

SA91-SA94 010101XXXXX 128 (4x32) Kwords SA255-SA258 111110XXXXX 128 (4x32) Kwords

SA95-SA98 010110XXXXX 128 (4x32) Kwords SA259 11111100XXX 32 Kwords

SA99-SA102 010111XXXXX 128 (4x32) Kwords SA260 11111101XXX 32 Kwords

SA103-SA106 011000XXXXX 128 (4x32) Kwords SA261 11111110XXX 32 Kwords

SA107-SA110 011001XXXXX 128 (4x32) Kwords SA262 11111111000 4 Kwords

SA111-SA114 011010XXXXX 128 (4x32) Kwords SA263 11111111001 4 Kwords

SA115-SA118 011011XXXXX 128 (4x32) Kwords SA264 11111111010 4 Kwords

SA119-SA122 011100XXXXX 128 (4x32) Kwords SA265 11111111011 4 Kwords

SA123-SA126 011101XXXXX 128 (4x32) Kwords

SA127-SA130 011110XXXXX 128 (4x32) Kwords

46 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Table 13. PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection

CE1# Control CE2# Control

Sector Group A21-12

Sector/Sector Block

Size Sector Group A21-12

Sector/Sector Block

Size

SA1-0 0000000000 4 Kwords

SA2-0–SA2-3 00000XXXXX 128 (4x32) Kwords

SA1-1 0000000001 4 Kwords

SA2-4–SA2-7 00001XXXXX 128 (4x32) Kwords

SA1-2 0000000010 4 Kwords

SA2-8–SA2-11 00010XXXXX 128 (4x32) Kwords

SA1-3 0000000011 4 Kwords

SA2-12–SA2-15 00011XXXXX 128 (4x32) Kwords

SA1-4 0000000100 4 Kwords

SA2-16–SA2-19 00100XXXXX 128 (4x32) Kwords

SA1-5 0000000101 4 Kwords

SA2-20–SA2-23 00101XXXXX 128 (4x32) Kwords

SA1-6 0000000110 4 Kwords

SA2-24–SA2-27 00110XXXXX 128 (4x32) Kwords

SA1-7 0000000111 4 Kwords

SA2-28–SA2-31 00111XXXXX 128 (4x32) Kwords

SA1-8 0000001XXX 32 Kwords

SA2-32–SA2-35 01000XXXXX 128 (4x32) Kwords

SA1-9 0000010XXX 32 Kwords

SA2-36–SA2-39 01001XXXXX 128 (4x32) Kwords

SA1-10 0000011XXX 32 Kwords

SA2-40–SA2-43 01010XXXXX 128 (4x32) Kwords

SA1-11 - SA1-14 00001XXXXX 128 (4x32) Kwords

SA2-44–SA2-47 01011XXXXX 128 (4x32) Kwords

SA1-15 - SA1-18 00010XXXXX 128 (4x32) Kwords

SA2-48–SA2-51 01100XXXXX 128 (4x32) Kwords

SA1-19 - SA1-22 00011XXXXX 128 (4x32) Kwords

SA2-52–SA2-55 01101XXXXX 128 (4x32) Kwords

SA1-23 - SA1-26 00100XXXXX 128 (4x32) Kwords

SA2-56–SA2-59 01110XXXXX 128 (4x32) Kwords

SA1-27 - SA1-30 00101XXXXX 128 (4x32) Kwords

SA2-60–SA2-63 01111XXXXX 128 (4x32) Kwords

SA1-31 - SA1-34 00110XXXXX 128 (4x32) Kwords

SA2-64–SA2-67 10000XXXXX 128 (4x32) Kwords

SA1-35 - SA1-38 00111XXXXX 128 (4x32) Kwords

SA2-68–SA2-71 10001XXXXX 128 (4x32) Kwords

SA1-39 - SA1-42 01000XXXXX 128 (4x32) Kwords

SA2-72–SA2-75 10010XXXXX 128 (4x32) Kwords

SA1-43 - SA1-46 01001XXXXX 128 (4x32) Kwords

SA2-76–SA2-79 10011XXXXX 128 (4x32) Kwords

SA1-47 - SA1-50 01010XXXXX 128 (4x32) Kwords

SA2-80–SA2-83 10100XXXXX 128 (4x32) Kwords

SA1-51 - SA1-54 01011XXXXX 128 (4x32) Kwords

SA2-84–SA2-87 10101XXXXX 128 (4x32) Kwords

SA1-55 - SA1-58 01100XXXXX 128 (4x32) Kwords

SA2-88–SA2-91 10110XXXXX 128 (4x32) Kwords

SA1-59 - SA1-62 01101XXXXX 128 (4x32) Kwords

SA2-92–SA2-95 10111XXXXX 128 (4x32) Kwords

SA1-63 - SA1-66 01110XXXXX 128 (4x32) Kwords

SA2-96–SA2-99 11000XXXXX 128 (4x32) Kwords

SA1-67 - SA1-70 01111XXXXX 128 (4x32) Kwords

SA2-100–SA2-103 11001XXXXX 128 (4x32) Kwords

SA1-71 - SA1-74 10000XXXXX 128 (4x32) Kwords

SA2-104–SA2-107 11010XXXXX 128 (4x32) Kwords

SA1-75 - SA1-78 10001XXXXX 128 (4x32) Kwords

SA2-108–SA2-111 11011XXXXX 128 (4x32) Kwords

SA1-79 - SA1-82 10010XXXXX 128 (4x32) Kwords

SA2-112–SA2-115 11100XXXXX 128 (4x32) Kwords

SA1-83 - SA1-86 10011XXXXX 128 (4x32) Kwords

SA2-116–SA2-119 11101XXXXX 128 (4x32) Kwords

SA1-87 - SA1-90 10100XXXXX 128 (4x32) Kwords

SA2-120–SA2-123 11110XXXXX 128 (4x32) Kwords

SA1-91 - SA1-94 10101XXXXX 128 (4x32) Kwords

SA2-124 1111100XXX 32 Kwords

SA1-95 - SA1-98 10110XXXXX 128 (4x32) Kwords

SA2-125 1111101XXX 32 Kwords

SA1-99 - SA1-102 10111XXXXX 128 (4x32) Kwords

SA2-126 1111110XXX 32 Kwords

SA1-103 - SA1-106 11000XXXXX 128 (4x32) Kwords

SA2-127 1111111000 4 Kwords

SA1-107 - SA1-110 11001XXXXX 128 (4x32) Kwords

SA2-128 1111111001 4 Kwords

SA1-111 - SA1-114 11010XXXXX 128 (4x32) Kwords

SA2-129 1111111010 4 Kwords

SA1-115 - SA1-118 11011XXXXX 128 (4x32) Kwords

SA2-130 1111111011 4 Kwords

SA1-119 - SA1-122 11100XXXXX 128 (4x32) Kwords

SA2-131 1111111100 4 Kwords

SA1-123 - SA1-126 11101XXXXX 128 (4x32) Kwords

SA2-132 1111111101 4 Kwords

SA1-127 - SA1-130 11110XXXXX 128 (4x32) Kwords

SA2-133 1111111110 4 Kwords

SA1-131 - SA1-134 11111XXXXX 128 (4x32) Kwords

SA2-134 1111111111 4 Kwords

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 47

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Table 14. PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector A21-A12 Sector/Sector Block Size

SA0 0000000000 4 Kwords

SA1 0000000001 4 Kwords

SA2 0000000010 4 Kwords

SA3 0000000011 4 Kwords

SA4 0000000100 4 Kwords

SA5 0000000101 4 Kwords

SA6 0000000110 4 Kwords

SA7 0000000111 4 Kwords

SA8 0000001XXX 32 Kwords

SA9 0000010XXX 32 Kwords

SA10 0000011XXX 32 Kwords

SA11-SA14 00001XXXXX 128 (4x32) Kwords

SA15-SA18 00010XXXXX 128 (4x32) Kwords

SA19-SA22 00011XXXXX 128 (4x32) Kwords

SA23-SA26 00100XXXXX 128 (4x32) Kwords

SA27-SA30 00101XXXXX 128 (4x32) Kwords

SA31-SA34 00110XXXXX 128 (4x32) Kwords

SA35-SA38 00111XXXXX 128 (4x32) Kwords

SA39-SA42 01000XXXXX 128 (4x32) Kwords

SA43-SA46 01001XXXXX 128 (4x32) Kwords

SA47-SA50 01010XXXXX 128 (4x32) Kwords

SA51-SA54 01011XXXXX 128 (4x32) Kwords

SA55-SA58 01100XXXXX 128 (4x32) Kwords

SA59-SA62 01101XXXXX 128 (4x32) Kwords

SA63-SA66 01110XXXXX 128 (4x32) Kwords

SA67-SA70 01111XXXXX 128 (4x32) Kwords

SA71-SA74 10000XXXXX 128 (4x32) Kwords

SA75-SA78 10001XXXXX 128 (4x32) Kwords

SA79-SA82 10010XXXXX 128 (4x32) Kwords

SA83-SA86 10011XXXXX 128 (4x32) Kwords

SA87-SA90 10100XXXXX 128 (4x32) Kwords

SA91-SA94 10101XXXXX 128 (4x32) Kwords

SA95-SA98 10110XXXXX 128 (4x32) Kwords

SA99-SA102 10111XXXXX 128 (4x32) Kwords

SA103-SA106 11000XXXXX 128 (4x32) Kwords

SA107-SA110 11001XXXXX 128 (4x32) Kwords

SA111-SA114 11010XXXXX 128 (4x32) Kwords

SA115-SA118 11011XXXXX 128 (4x32) Kwords

SA119-SA122 11100XXXXX 128 (4x32) Kwords

SA123-SA126 11101XXXXX 128 (4x32) Kwords

SA127-SA130 11110XXXXX 128 (4x32) Kwords

SA131 1111100XXX 32 Kwords

SA132 1111101XXX 32 Kwords

SA133 1111110XXX 32 Kwords

SA134 1111111000 4 Kwords

SA135 1111111001 4 Kwords

SA136 1111111010 4 Kwords

SA137 1111111011 4 Kwords

SA138 1111111100 4 Kwords

SA139 1111111101 4 Kwords

SA140 1111111110 4 Kwords

SA141 1111111111 4 Kwords

48 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Selecting a Sector Protection Mode

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See the

"SecSiTM Sector Addresses" section for details.

Table 15. PL032J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector A21-A12 Sector/Sector Block Size

SA0 000000000 4 Kwords

SA1 000000001 4 Kwords

SA2 000000010 4 Kwords

SA3 000000011 4 Kwords

SA4 000000100 4 Kwords

SA5 000000101 4 Kwords

SA6 000000110 4 Kwords

SA7 000000111 4 Kwords

SA8 000001XXX 32 Kwords

SA9 000010XXX 32 Kwords

SA10 000011XXX 32 Kwords

SA11-SA14 0001XXXXX 128 (4x32) Kwords

SA15-SA18 0010XXXXX 128 (4x32) Kwords

SA19-SA22 0011XXXXX 128 (4x32) Kwords

SA23-SA26 0100XXXXX 128 (4x32) Kwords

SA27-SA30 0101XXXXX 128 (4x32) Kwords

SA31-SA34 0110XXXXX 128 (4x32) Kwords

SA35-SA38 0111XXXXX 128 (4x32) Kwords

SA39-SA42 1000XXXXX 128 (4x32) Kwords

SA43-SA46 1001XXXXX 128 (4x32) Kwords

SA47-SA50 1010XXXXX 128 (4x32) Kwords

SA51-SA54 1011XXXXX 128 (4x32) Kwords

SA55-SA58 1100XXXXX 128 (4x32) Kwords

SA59-SA62 1101XXXXX 128 (4x32) Kwords

SA63-SA66 1110XXXXX 128 (4x32) Kwords

SA67 111100XXX 32 Kwords

SA68 111101XXX 32 Kwords

SA69 111110XXX 32 Kwords

SA70 111111000 4 Kwords

SA71 111111001 4 Kwords

SA72 111111010 4 Kwords

SA73 111111011 4 Kwords

SA74 111111100 4 Kwords

SA75 111111101 4 Kwords

SA76 111111110 4 Kwords

SA77 111111111 4 Kwords

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 49

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Sector Protection

The PL127J, PL129J, PL064J, and PL032J features several levels of sector protec-

tion, which can disable both the program and erase operations in certain sectors

or sector groups:

Persistent Sector Protection

A command sector protection method that replaces the old 12 V controlled pro-

tection method.

Password Sector Protection

A highly sophisticated protection method that requires a password before

changes to certain sectors or sector groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase operations in sectors

SA1-133, SA1-134, SA2-0 and SA2-1.

The WP# Hardware Protection feature is always available, independent of the

software managed protection method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector Protection mode. The cus-

tomer must then choose if the Persistent or Password Protection method is most

desirable. There are two one-time programmable non-volatile bits that define

which sector protection method will be used. If the Persistent Sector Protection

method is desired, programming the Persistent Sector Protection Mode Locking

Bit permanently sets the device to the Persistent Sector Protection mode. If the

Password Sector Protection method is desired, programming the Password Mode

Locking Bit permanently sets the device to the Password Sector Protection mode.

It is not possible to switch between the two protection modes once a locking bit

has been set. One of the two modes must be selected when the device is first

programmed. This prevents a program or virus from later setting the Password

Mode Locking Bit, which would cause an unexpected shift from the default Per-

sistent Sector Protection Mode into the Password Protection Mode.

Table 16. Sector Protection Schemes

DYB PPB PPB Lock Sector State

0 0 0 Unprotected—PPB and DYB are changeable

0 0 1 Unprotected—PPB not changeable, DYB is changeable

010

Protected—PPB and DYB are changeable100

110

011

Protected—PPB not changeable, DYB is changeable101

111

50 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See Au-

toselect Mode for details.

Persistent Sector Protection

The Persistent Sector Protection method replaces the 12 V controlled protection

method in previous flash devices. This new method provides three different sec-

tor protection states:

Persistently Locked—The sector is protected and cannot be changed.

Dynamically Locked—The sector is protected and can be changed by a simple

command.

Unlocked—The sector is unprotected and can be changed by a simple com-

mand.

To achieve these states, three types of “bits” are used:

Persistent Protection Bit

Persistent Protection Bit Lock

Persistent Sector Protection Mode Locking Bit

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to a maximum four

sectors (see the sector address tables for specific sector protection groupings).

All 4 Kword boot-block sectors have individual sector Persistent Protection Bits

(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB

Write Command.

The device erases all PPBs in parallel. If any PPB requires erasure, the device

must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth-

erwise, a previously erased sector PPBs can potentially be over-erased. The flash

device does not have a built-in means of preventing sector PPBs over-erasure.

Persistent Protection Bit Lock (PPB Lock)

The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to

“1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.

There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up

or hardware reset. There is no command sequence to unlock the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware

reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through

the DYB Write Command.

When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and

PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are

changeable.

When the device is first powered on the DYBs power up cleared (sectors not pro-

tected). The Protection State for each sector is determined by the logical OR of

the PPB and the DYB related to that sector. For the sectors that have the PPBs

cleared, the DYBs control whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the DYBs will be set or cleared,

thus placing each sector in the protected or unprotected state. These are the

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 51

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so-called Dynamic Locked or Unlocked states. They are called dynamic states be-

cause it is very easy to switch back and forth between the protected and

unprotected conditions. This allows software to easily protect sectors against in-

advertent changes yet does not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared as often as needed.

The PPBs allow for a more static, and difficult to change, level of protection. The

PPBs retain their state across power cycles because they are non-volatile. Indi-

vidual PPBs are set with a command but must all be cleared as a group through

a complex sequence of program and erasing commands. The PPBs are also lim-

ited to 100 erase cycles.

The PPB Lock bit adds an additional level of protection. Once all PPBs are pro-

grammed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB

Lock disables all program and erase commands to the non-volatile PPBs. In ef-

fect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear

the PPB Lock is to go through a power cycle. System boot code can determine if

any changes to the PPB are needed; for example, to allow new system code to

be downloaded. If no changes are needed then the boot code can set the PPB

Lock to disable any further changes to the PPBs during system operation.

The WP#/ACC write protect pin adds a final level of hardware protection to sec-

tors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible

to change the contents of these sectors. These sectors generally hold system

boot code. The WP#/ACC pin can prevent any changes to the boot code that could

override the choices made while setting up sector protection during system

initialization.

For customers who are concerned about malicious viruses there is another level

of security - the persistently locked state. To persistently protect a given sector

or sector group, the PPBs associated with that sector need to be set to “1”. Once

all PPBs are programmed to the desired settings, the PPB Lock should be set to

“1”. Setting the PPB Lock automatically disables all program and erase commands

to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their cur-

rent state. The only way to clear the PPB Lock is to go through a power cycle.

It is possible to have sectors that have been persistently locked, and sectors that

are left in the dynamic state. The sectors in the dynamic state are all unprotected.

If there is a need to protect some of them, a simple DYB Write command se-

quence is all that is necessary. The DYB write command for the dynamic sectors

switch the DYBs to signify protected and unprotected, respectively. If there is a

need to change the status of the persistently locked sectors, a few more steps

are required. First, the PPB Lock bit must be disabled by either putting the device

through a power-cycle, or hardware reset. The PPBs can then be changed to re-

flect the desired settings. Setting the PPB lock bit once again will lock the PPBs,

and the device operates normally again.

The best protection is achieved by executing the PPB lock bit set command early

in the boot code, and protect the boot code by holding WP#/ACC = VIL.

Table 17 contains all possible combinations of the DYB, PPB, and PPB lock relating

to the status of the sector.

In summary, if the PPB is set, and the PPB lock is set, the sector is protected and

the protection can not be removed until the next power cycle clears the PPB lock.

If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB

then controls whether or not the sector is protected or unprotected.

52 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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If the user attempts to program or erase a protected sector, the device ignores

the command and returns to read mode. A program command to a protected sec-

tor enables status polling for approximately 1 µs before the device returns to read

mode without having modified the contents of the protected sector. An erase

command to a protected sector enables status polling for approximately 50 µs

after which the device returns to read mode without having erased the protected

sector.

The programming of the DYB, PPB, and PPB lock for a given sector can be verified

by writing a DYB/PPB/PPB lock verify command to the device. There is an alter-

native means of reading the protection status. Take RESET# to VIL and hold WE#

at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of

the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) will

produce a logical ‘1” code at device output DQ0 for a protected sector or a “0” for

an unprotected sector. In this mode, the other addresses are don’t cares. Address

location with A1 = VIL are reserved for autoselect manufacturer and device

codes.

Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sector Protection mode locking

bit exists to guarantee that the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit prevents programming of the

password protection mode locking bit. This guarantees that a hacker could not

place the device in password protection mode.

Password Protection Mode

The Password Sector Protection Mode method allows an even higher level of se-

curity than the Persistent Sector Protection Mode. There are two main differences

between the Persistent Sector Protection and the Password Sector Protection

Mode:

When the device is first powered on, or comes out of a reset cycle, the PPB Lock

bit set to the locked state, rather than cleared to the unlocked state.

The only means to clear the PPB Lock bit is by writing a unique 64-bit Password

to the device.

The Password Sector Protection method is otherwise identical to the Persistent

Sector Protection method.

A 64-bit password is the only additional tool utilized in this method.

Once the Password Mode Locking Bit is set, the password is permanently set with

no means to read, program, or erase it. The password is used to clear the PPB

Lock bit. The Password Unlock command must be written to the flash, along with

a password. The flash device internally compares the given password with the

pre-programmed password. If they match, the PPB Lock bit is cleared, and the

PPBs can be altered. If they do not match, the flash device does nothing. There

is a built-in 2 µs delay for each “password check.” This delay is intended to thwart

any efforts to run a program that tries all possible combinations in order to crack

the password.

Password and Password Mode Locking Bit

In order to select the Password sector protection scheme, the customer must first

program the password. The password may be correlated to the unique Electronic

Serial Number (ESN) of the particular flash device. Each ESN is different for every

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 53

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flash device; therefore each password should be different for every flash device.

While programming in the password region, the customer may perform Password

Verify operations.

Once the desired password is programmed in, the customer must then set the

Password Mode Locking Bit. This operation achieves two objectives:

Permanently sets the device to operate using the Password Protection Mode. It is

not possible to reverse this function.

Disables all further commands to the password region. All program, and read op-

erations are ignored.

Both of these objectives are important, and if not carefully considered, may lead

to unrecoverable errors. The user must be sure that the Password Protection

method is desired when setting the Password Mode Locking Bit. More importantly,

the user must be sure that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations are disabled, there is no

means to verify what the password is afterwards. If the password is lost after set-

ting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit.

The Password Mode Locking Bit, once set, prevents reading the 64-bit password

on the DQ bus and further password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis-

tent Sector Protection Locking Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory space and is accessible through

the use of the Password Program and Verify commands (see “Password Verify

Command”). The password function works in conjunction with the Password

Mode Locking Bit, which when set, prevents the Password Verify command from

reading the contents of the password on the pins of the device.

Write Protect (WP#)

The Write Protect feature provides a hardware method of protecting the upper

two and lower two sectors without using VID. This function is provided by the WP#

pin and overrides the previously discussed "High Voltage Sector Protection" sec-

tion method.

If the system asserts VIL on the WP#/ACC pin, the device disables program and

erase functions in the two outermost 4 Kword sectors on both ends of the flash

array independent of whether it was previously protected or unprotected.

If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two

and lower two sectors to whether they were last set to be protected or unpro-

tected. That is, sector protection or unprotection for these sectors depends on

whether they were last protected or unprotected using the method described in

the "High Voltage Sector Protection" section.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent

behavior of the device may result.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of

the Password Mode Locking Bit after power-up reset. If the Password Mode Lock

Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the

ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue

54 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

the Password Unlock command. Successful execution of the Password Unlock

command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert-

ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock

Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit

is not set.

If the Password Mode Locking Bit is not set, including Persistent Protection Mode,

the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is

set by issuing the PPB Lock Bit Set command. Once set the only means for clear-

ing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password

Unlock command is ignored in Persistent Protection Mode.

High Voltage Sector Protection

Sector protection and unprotection may also be implemented using programming

equipment. The procedure requires high voltage (VID) to be placed on the RE-

SET# pin. Refer to Figure 1 for details on this procedure. Note that for sector

unprotect, all unprotected sectors must first be protected prior to the first sector

write cycle.

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 55

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Figure 1. In-System Sector Protection/Sector Unprotection Algorithms

Sector Protect:

Write 60h to sector

address with

A7-A0 =

00000010

Set up sector

address

Wait 100 µs

Verify Sector

Protect: Write 40h

to sector address

with A7-A0 =

00000010

Read from

sector address

with A7-A0 =

00000010

START

PLSCNT = 1

RESET# = VID

Wait 4 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

Sector Unprotect:

Write 60h to sector

address with

A7-A0 =

01000010

Set up first sector

address

Wait 1.2 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A7-A0 =

00000010

Read from

sector address

with A7-A0 =

00000010

START

PLSCNT = 1

RESET# = VID

Wait 4 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm

Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

56 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to

change data in-system. The Sector Unprotect mode is activated by setting the

RESET# pin to VID. During this mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector addresses. Once VID is removed from

the RESET# pin, all the previously protected sectors are protected again. 2 shows

the algorithm, and 21 shows the timing diagrams, for this feature. While PPB lock

is set, the device cannot enter the Temporary Sector Unprotection Mode.

SecSi™ (Secured Silicon) Sector Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a Flash memory region that

enables permanent part identification through an Electronic Serial Number (ESN)

The 128-word SecSi sector is divided into 64 factory-lockable words that can be

programmed and locked by the customer. The SecSi sector is located at ad-

dresses 000000h-00007Fh in both Persistent Protection mode and Password

Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the fac-

tory-locked and customer locked status of the part.

The system accesses the SecSi Sector through a command sequence (see the

"Enter SecSi™ Sector/Exit SecSi Sector Command Sequence" section). After the

system has written the Enter SecSi Sector command sequence, it may read the

SecSi Sector by using the addresses normally occupied by the boot sectors. This

mode of operation continues until the system issues the Exit SecSi Sector com-

mand sequence, or until power is removed from the device. On power-up, or

following a hardware reset, the device reverts to sending commands to the nor-

mal address space. Note that the ACC function and unlock bypass modes are not

available when the SecSi Sector is enabled.

Factory-Locked Area (64 words)

The factory-locked area of the SecSi Sector (000000h-00003Fh) is locked when

the part is shipped, whether or not the area was programmed at the factory. The

Notes:

1. All protected sectors unprotected (If WP#/ACC = VIL, upper two and lower two

sectors will remain protected).

2. All previously protected sectors are protected once again

Figure 2. Temporary Sector Unprotect Operation

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 57

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SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. Op-

tional Spansion programming services can program the factory-locked area with

a random ESN, a customer-defined code, or any combination of the two. Because

only FASL can program and protect the factory-locked area, this method ensures

the security of the ESN once the product is shipped to the field. Contact your local

sales office for details on using Spansion’s programming services. Note that the

ACC function and unlock bypass modes are not available when the SecSi sector

is enabled.

Customer-Lockable Area (64 words)

The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped

unprotected, which allows the customer to program and optionally lock the area

as appropriate for the application. The SecSi Sector Customer-locked Indicator

Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the

SecSi Protection Bit Program Command. The SecSi Sector can be read any num-

ber of times, but can be programmed and locked only once. Note that the

accelerated programming (ACC) and unlock bypass functions are not available

when programming the SecSi Sector.

The Customer-lockable SecSi Sector area can be protected using one of the

following procedures:

Write the three-cycle Enter SecSi Sector Region command sequence, and

then follow the in-system sector protect algorithm as shown in Figure 1, ex-

cept that RESET# may be at either VIH or VID. This allows in-system protec-

tion of the SecSi Sector Region without raising any device pin to a high

voltage. Note that this method is only applicable to the SecSi Sector.

To verify the protect/unprotect status of the SecSi Sector, follow the algo-

rithm shown in Figure 3.

Once the SecSi Sector is locked and verified, the system must write the Exit SecSi

Sector Region command sequence to return to reading and writing the remainder

of the array.

The SecSi Sector lock must be used with caution since, once locked, there is no

procedure available for unlocking the SecSi Sector area and none of the bits in

the SecSi Sector memory space can be modified in any way.

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent programming of the SecSi Sector mem-

ory area. Once set, the SecSi Sector memory area contents are non-modifiable.

58 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during VCC

power-up and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This pro-

tects data during VCC power-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

mode. Subsequent writes are ignored until VCC is greater than VLKO. The system

must provide the proper signals to the control pins to prevent unintentional writes

when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#, CE#, (CE1#, CE2# in PL129J) or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# (CE1# = CE2#

in PL129J)= VIH or WE# = VIH. To initiate a write cycle, CE# (CE1# / CE2# in

PL129J) and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# (CE1#, CE2# in PL129J) = VIL and OE# = VIH during power up,

the device does not accept commands on the rising edge of WE#. The internal

state machine is automatically reset to the read mode on power-up.

Figure 3. SecSi Sector Protect Verify

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

VIH or VID

Wait 1 µs

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 59

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Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h, any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 17–20. To

terminate reading CFI data, the system must write the reset command. The CFI

Query mode is not accessible when the device is executing an Embedded Program

or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 17–20. The system must write the reset

command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication

100. Contact your local sales office for copies of these documents.

Table 17. CFI Query Identification String

Addresses Data Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h Primary OEM Command Set

15h

16h

0040h

0000h Address for Primary Extended Table

17h

18h

0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

60 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Table 18. System Interface String

Addresses Data Description

1Bh 0027h V

Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 0036h V

Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 0000h V

Min. voltage (00h = no V

pin present)

1Eh 0000h V

Max. voltage (00h = no V

pin present)

1Fh 0003h Typical timeout per single byte/word write 2

µs

20h 0000h Typical timeout for Min. size buffer write 2

s (00h = not supported)

21h 0009h Typical timeout per individual block erase 2

22h 0000h Typical timeout for full chip erase 2

ms (00h = not supported)

23h 0004h Max. timeout for byte/word write 2

times typical

24h 0000h Max. timeout for buffer write 2

times typical

25h 0004h Max. timeout per individual block erase 2

times typical

26h 0000h Max. timeout for full chip erase 2

times typical (00h = not supported)

Table 19. Device Geometry Definition

Addresses Data Description

27h

0018h (PL127J)

0018h (PL129J)

0017h (PL064J)

0016h (PL032J)

Device Size = 2

byte

28h

29h

0001h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch 0003h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

00FDh (PL127J)

00FDh (PL129J)

007Dh (PL064J)

003Dh (PL032J) Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

32h

33h

34h

0000h

0001h

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 61

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Table 20. Primary Vendor-Specific Extended Query

Addresses Data Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h 0031h Major version number, ASCII (reflects modifications to the silicon)

44h 0033h Minor version number, ASCII (reflects modifications to the CFI table)

45h

TBD

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Silicon Revision Number (Bits 7-2)

46h 0002h Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 0001h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 0007h (PLxxxJ) Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

4Ah

00E7h (PL127J)

00E7h (PL129J)

0077h (PL064J)

003Fh (PL032J)

Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

4Bh 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 0002h (PLxxxJ) Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 0085h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 0095h ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 0001h

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = Both top and bottom boot with write protect,

02h = Bottom Boot Device, 03h = Top Boot Device,

04h = Both Top and Bottom

50h 0001h Program Suspend

0 = Not supported, 1 = Supported

57h 0004h Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

58h

0027h (PL127J)

0027h (PL129J)

0017h (PL064J)

000Fh (PL032J)

Bank 1 Region Information

X = Number of Sectors in Bank 1

59h

0060h (PL127J)

0060h (PL129J)

0030h (PL064J)

0018h (PL032J)

Bank 2 Region Information

X = Number of Sectors in Bank 2

62 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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5Ah

0060h (PL127J)

0060h (PL129J)

0030h (PL064J)

0018h (PL032J)

Bank 3 Region Information

X = Number of Sectors in Bank 3

5Bh

0027h (PL127J)

0027h (PL129J)

0017h (PL064J)

000Fh (PL032J)

Bank 4 Region Information

X = Number of Sectors in Bank 4

Table 20. Primary Vendor-Specific Extended Query (Continued)

Addresses Data Description

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 63

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Command Definitions

Writing specific address and data commands or sequences into the command

sequences. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state. A reset com-

mand is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in

PL129J), whichever happens later. All data is latched on the rising edge of WE#

or CE# (CE1# / CE2# in PL129J), whichever happens first. Refer to the "AC Char-

acteristic" section section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No

commands are required to retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank

enters the erase-suspend-read mode, after which the system can read data from

any non-erase-suspended sector within the same bank. The system can read

array data using the standard read timing, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing

a programming operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See the "Erase Suspend/Erase

Resume Commands" section section for more information.

The system must issue the reset command to return a bank to the read (or

erase-suspend-read) mode if DQ5 goes high during an active program or erase

operation, or if the bank is in the autoselect mode. See the next section, "Reset

Command" section, for more information.

See also "Requirements for Reading Array Data" section in the "Device Bus Op-

erations" section section for more information. The "AC Characteristic" section

table provides the read parameters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read

mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure begins, however, the device

ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program

command sequence before programming begins. This resets the bank to which

the system was writing to the read mode. If the program command sequence is

written to a bank that is in the Erase Suspend mode, writing the reset command

returns that bank to the erase-suspend-read mode. Once programming begins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autoselect mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while

in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode.

64 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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If DQ5 goes high during a program or erase operation, writing the reset command

returns the banks to the read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and device codes, and determine whether or not a sector is protected.

The autoselect command sequence may be written to an address within a bank

that is either in the read or erase-suspend-read mode. The autoselect command

may not be written while the device is actively programming or erasing in the

other bank.

The autoselect command sequence is initiated by first writing two unlock cycles.

This is followed by a third write cycle that contains the bank address and the au-

toselect command. The bank then enters the autoselect mode. The system may

read any number of autoselect codes without reinitiating the command sequence.

Tab le 2 1 shows the address and data requirements. To determine sector protec-

tion information, the system must write to the appropriate bank address (BA) and

sector address (SA). Ta bl e 4 shows the address range and bank number associ-

ated with each sector.

The system must write the reset command to return to the read mode (or

erase-suspend-read mode if the bank was previously in Erase Suspend).

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence

The SecSi Sector region provides a secured data area containing a random, eight

word electronic serial number (ESN). The system can access the SecSi Sector re-

gion by issuing the three-cycle Enter SecSi Sector command sequence. The

device continues to access the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command

sequence returns the device to normal operation. The SecSi Sector is not acces-

sible when the device is executing an Embedded Program or embedded Erase

algorithm. Table 2 1 shows the address and data requirements for both command

sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for

further information. Note that the ACC function and unlock bypass modes are not

available when the SecSi Sector is enabled.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the program set-up com-

mand. The program address and data are written next, which in turn initiate the

Embedded Program algorithm. The system is not required to provide further con-

trols or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Ta b l e 2 1 shows the address and

data requirements for the program command sequence. Note that the SecSi Sec-

tor, autoselect, and CFI functions are unavailable when a [program/erase]

operation is in progress.

When the Embedded Program algorithm is complete, that bank then returns to

the read mode and addresses are no longer latched. The system can determine

the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the

"Write Operation Status" section section for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately terminates the program

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 65

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operation. The program command sequence should be reinitiated once that bank

has returned to the read mode, to ensure data integrity. Note that the SecSi Sec-

tor, autoselect and CFI functions are unavailable when the SecSi Sector is

enabled.

Programming is allowed in any sequence and across sector boundaries. A bit

cannot be programmed from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate

the operation was successful. However, a succeeding read will show that the data

is still “0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program data to a bank faster

than using the standard program command sequence. The unlock bypass com-

mand sequence is initiated by first writing two unlock cycles. This is followed by

a third write cycle containing the unlock bypass command, 20h. That bank then

enters the unlock bypass mode. A two-cycle unlock bypass program command

sequence is all that is required to program in this mode. The first cycle in this se-

quence contains the unlock bypass program command, A0h; the second cycle

contains the program address and data. Additional data is programmed in the

same manner. This mode dispenses with the initial two unlock cycles required in

the standard program command sequence, resulting in faster total programming

time. Tab le 2 1 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-

pass Reset commands are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset command sequence. (See Table 22)

The device offers accelerated program operations through the WP#/ACC pin.

When the system asserts VHH on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock

Bypass program command sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not

be at VHH any operation other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

4 illustrates the algorithm for the program operation. Refer to the "Erase/Program

Operations" section table in the AC Characteristics section for parameters, and

Figure 14 for timing diagrams.

66 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 21 shows the address and data requirements

for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read

mode and addresses are no longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the "Write

Operation Status" section section for information on these status bits.

Any commands written during the chip erase operation are ignored. Note that

SecSi Sector, autoselect, and CFI functions are unavailable when a [pro-

gram/erase] operation is in progress. However, note that a hardware reset

immediately terminates the erase operation. If that occurs, the chip erase com-

mand sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Note: See Table 21 for program command sequence.

Figure 4. Program Operation

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 67

PRELIMINARY

5 illustrates the algorithm for the erase operation. Refer to the "Erase/Program

Operations" section tables in the AC Characteristics section for parameters, and

Figure 16 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Tabl e 2 1 shows the address

and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory

for an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs.

During the time-out period, additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than 50 µs, otherwise erasure

may begin. Any sector erase address and command following the exceeded

time-out may or may not be accepted. It is recommended that processor inter-

rupts be disabled during this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase command is written. If

any command other than 30h, B0h, F0h is input during the time-out pe-

riod, the normal operation will not be guaranteed. The system must rewrite

the command sequence and any additional addresses and commands. Note that

SecSi Sector, autoselect, and CFI functions are unavailable when a [pro-

gram/erase] operation is in progress.

The system can monitor DQ3 to determine if the sector erase timer has timed out

(See the section on DQ3: Sector Erase Timer). The time-out begins from the ris-

ing edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading

array data and addresses are no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read data from the non-erasing

bank. The system can determine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the "Write Operation

Status" section section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is

valid. All other commands are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

5 illustrates the algorithm for the erase operation. Refer to the "Erase/Program

Operations" section tables in the AC Characteristics section for parameters, and

Figure 16 section for timing diagrams.

68 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase

operation and then read data from, or program data to, any sector not selected

for erasure. The bank address is required when writing this command. This com-

mand is valid only during the sector erase operation, including the 80 µs time-out

period during the sector erase command sequence. The Erase Suspend command

is ignored if written during the chip erase operation or Embedded Program

algorithm.

When the Erase Suspend command is written during the sector erase operation,

the device requires a maximum of 35 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written during the sector erase

time-out, the device immediately terminates the time-out period and suspends

the erase operation. Addresses are “don’t-cares” when writing the Erase suspend

command.

After the erase operation has been suspended, the bank enters the erase-sus-

pend-read mode. The system can read data from or program data to any sector

not selected for erasure. (The device “erase suspends” all sectors selected for

erasure.) Reading at any address within erase-suspended sectors produces sta-

tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. Refer

to the "Write Operation Status" section section for information on these status

bits.

After an erase-suspended program operation is complete, the bank returns to the

erase-suspend-read mode. The system can determine the status of the program

Notes:

1. See Table 21 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 5. Erase Operation

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 69

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operation using the DQ7 or DQ6 status bits, just as in the standard Word Program

operation. Refer to the "Write Operation Status" section section for more

information.

In the erase-suspend-read mode, the system can also issue the autoselect com-

mand sequence. The device allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored in the memory array. When

the device exits the autoselect mode, the device reverts to the Erase Suspend

mode, and is ready for another valid operation. Refer to the "SecSiTM Sector Ad-

dresses" section and the "Autoselect Command Sequence" section sections for

details.

To resume the sector erase operation, the system must write the Erase Resume

command (address bits are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command. Further writes of the

Resume command are ignored. Another Erase Suspend command can be written

after the chip has resumed erasing.

If the Persistent Sector Protection Mode Locking Bit is verified as programmed

without margin, the Persistent Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin. If the SecSi Sector

Protection Bit is verified as programmed without margin, the SecSi Sector Pro-

tection Bit Program Command should be reissued to improve program margin.

µµAfter programming a PPB, two additional cycles are needed to determine

whether the PPB has been programmed with margin. If the PPB has been pro-

grammed without margin, the program command should be reissued to improve

the program margin. Also note that the total number of PPB program/erase cycles

is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.

After erasing the PPBs, two additional cycles are needed to determine whether

the PPB has been erased with margin. If the PPBs has been erased without mar-

gin, the erase command should be reissued to improve the program margin. The

programming of either the PPB or DYB for a given sector or sector group can be

verified by writing a Sector Protection Status command to the device.

Note that there is no single command to independently verify the programming

of a DYB for a given sector group.

70 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Command Definitions Tables

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by PL127J: Amax:A20, PL064J

and PL129J: Amax:A19, PL032J: Amax:A18.

PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE# (CE1#/CE2# for PL129J) pulse, whichever

happens later.

PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# (CE1#/CE2# for PL129J) pulse,

whichever happens first.

RA = Read Address (Amax:A0).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing.

WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#.

X = Don’t care

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

5. No unlock or command cycles required when bank is reading array data.

6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend)

when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information).

7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID

or device ID information. See "Autoselect Command Sequence" section section for more information.

8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked.

9. The data is 00h for an unprotected sector group and 01h for a protected sector group.

10. Device ID must be read across cycles 4, 5, and 6. PL127J (X0Eh = 2220h, X0Fh = 2200h), PL129J (X0Eh = 2221h, X0Fh =

2200h),PL064J (X0Eh = 2202h, X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h).

Table 21. Memory Array Command Definitions

Command (Notes)

Cycles

Bus Cycles (Notes 1–4)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5)1RARD

Reset (Note 6) 1 XXX F0

Autoselect

(Note 7)

Manufacturer ID 4 555 AA 2AA 55 (BA)

555 90 (BA)

X00 01

Device ID (Note 10) 6 555 AA 2AA 55 (BA)

555 90 (BA)

X01 227E (BA)

X0E

(Note

10)

(BA)

X0F

(Note

10)

SecSi Sector Factory

Protect (Note 8)4 555 AA 2AA 55 (BA)

555 90 X03 (Note

Sector Group Protect

Verify (Note 9)4 555 AAA 2AA 55 (BA)

555 90 (SA)

X02

XX00/

XX01

Program 4 555 AA 2AA 55 555 A0 PA PD

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Program/Erase Suspend (Note 11) 1 BA B0

Program/Erase Resume (Note 12)1BA30

CFI Query (Note 13) 1 55 98

Accelerated Program (Note 15)2XXA0PAPD

Unlock Bypass Entry (Note 15) 3 555 AA 2AA 55 555 20

Unlock Bypass Program (Note 15)2XXA0PAPD

Unlock Bypass Erase (Note 15) 2 XX 80 XX 10

Unlock Bypass CFI (Notes 13, 15)1XX98

Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 71

PRELIMINARY

11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address.

12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.

13. Command is valid when device is ready to read array data or when device is in autoselect mode.

14. WP#/ACC must be at VID during the entire operation of command.

15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required

to return to the reading array.

72 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

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Legend:

DYB = Dynamic Protection Bit

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A7:A0) is (00001010)

RD(0) = Read Data DQ0 for protection indicator bit.

Table 22. Sector Protection Command Definitions

Command

(Notes)

Cycles

Bus Cycles (Notes 1-4)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXX F0

SecSi Sector

Entry 3 555 AA 2AA 55 555 88

SecSi Sector

Exit 4 555 AA 2AA 55 555 90 XX 00

SecSi

Protection Bit

Program

(Notes 5, 6)

6 555 AA 2AA 55 555 60 OW 68 OW 48 OW RD(0)

SecSi

Protection Bit

Status

5 555 AA 2AA 55 555 60 OW 48 OW RD(0)

Password

Program

(Notes 5, 7,

4 555 AA 2AA 55 555 38 XX[0-3] PD[0-3]

Password

Verify (Notes

6, 8, 9)

4 555 AA 2AA 55 555 C8 PWA[0-3] PWD[0-3]

Password

Unlock

(Notes 7, 10,

11)

7 555 AA 2AA 55 555 28 PWA[0] PWD[0] PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3]

PPB Program

(Notes 5, 6,

12)

6 555 AA 2AA 55 555 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0)

PPB Status 4 555 AA 2AA 55 555 90 (SA)WP RD(0)

All PPB Erase

(Notes 5, 6,

13, 14)

6 555 AA 2AA 55 555 60 WP 60 (SA) 40 (SA)WP RD(0)

PPB Lock Bit

Set 3 555 AA 2AA 55 555 78

PPB Lock Bit

Status (Note

15)

4 555 AA 2AA 55 555 58 SA RD(1)

DYB Write

(Note 7)4 555 AA 2AA 55 555 48 SA X1

DYB Erase

(Note 7)4 555 AA 2AA 55 555 48 SA X0

DYB Status

(Note 6)4 555 AA 2AA 55 555 58 SA RD(0)

PPMLB

Program

(Notes 5, 6,

12)

6 555 AA 2AA 55 555 60 PL 68 PL 48 PL RD(0)

PPMLB

Status (Note

5 555 AA 2AA 55 555 60 PL 48 PL RD(0)

SPMLB

Program

(Notes 5, 6,

12)

6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD(0)

SPMLB

Status (Note

5 555 AA 2AA 55 555 60 SL 48 SL RD(0)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 73

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RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)

WP = PPB Address (A7:A0) is (00000010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

5. The reset command returns device to reading array.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 =

0 in cycle 6, program command must be issued and verified again.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion of password.

9. Command sequence returns FFh if PPMLB is set.

10. The password is written over four consecutive cycles, at addresses 0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase

command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB

overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

Write Operation Status

The device provides several bits to determine the status of a program or erase opera-

tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Ta bl e 2 3 and the following subsections describe

the function of these bits. DQ7 and DQ6 each offer a method for determining whether

a program or erase operation is complete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine whether an Embedded Program

or Erase operation is in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-

gram or Erase algorithm is in progress or completed, or whether a bank is in Erase

Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-

mand sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement

of the datum programmed to DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is complete, the device out-

puts the datum programmed to DQ7. The system must provide the program address

to read valid status information on DQ7. If a program address falls within a protected

sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns

to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide

an address within any of the sectors selected for erasure to read valid status in-

formation on DQ7.

74 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the

bank returns to the read mode. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at an address within

a protected sector, the status may not be valid.

When the system detects DQ7 has changed from the complement to true data,

it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the

completion of an Embedded Program or Erase operation, DQ7 may change asyn-

chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,

the device may change from providing status information to valid data on DQ7.

Depending on when the system samples the DQ7 output, it may read the status

or valid data. Even if the device has completed the program or erase operation

and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid

data on DQ15–DQ0 will appear on successive read cycles.

Tab le 2 3 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling

algorithm. 18 in the "AC Characteristic" section section shows the Data# Polling

timing diagram.

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is

any sector address within the sector being erased. During chip erase, a valid address is

any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously

with DQ5.

Figure 6. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 75

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an

Embedded Algorithm is in progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command sequence. Since RY/BY#

is an open-drain output, several RY/BY# pins can be tied together in parallel with

a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is high (Ready),

the device is in the read mode, the standby mode, or one of the banks is in the

erase-suspend-read mode.

Tab le 2 3 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. The system may use either OE# or CE#

to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 400 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the "DQ7: Data# Polling" section).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 µs after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

Tab le 2 3 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit

algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing di-

agrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical

form. See also the "DQ2: Toggle Bit II" section.

76 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular

sector is actively erasing (that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have

been selected for erasure. (The system may use either OE# or CE# (CE1# / CE2#

for PL129J) to control the read cycles.) But DQ2 cannot distinguish whether the

sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates

whether the device is actively erasing, or is in Erase Suspend, but cannot distin-

guish which sectors are selected for erasure. Thus, both status bits are required

for sector and mode information. Refer to Tab l e 23 to compare outputs for DQ2

and DQ6.

Figure 7 shows the toggle bit algorithm in flowchart form, and the "DQ2: Toggle

Bit II" section explains the algorithm. See also the "DQ6: Toggle Bit I" section.

Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences

between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. Whenever the system initially be-

gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle

bit may stop toggling as DQ5 changes to “1.” See the "DQ6: Toggle Bit I" section and

"DQ2: Toggle Bit II" section for more information.

Figure 7. Toggle Bit Algorithm

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Toggle Bit

= Toggle?

Read Byte Twice

(DQ7–DQ0)

Address = VA

Read Byte

(DQ7–DQ0)

Address =VA

Read Byte

(DQ7–DQ0)

Address =VA

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 77

PRELIMINARY

determine whether a toggle bit is toggling. Typically, the system would note and

store the value of the toggle bit after the first read. After the second read, the

system would compare the new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-

cessfully completed the program or erase operation. If it is still toggling, the

device did not completed the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 has not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, determining the status as de-

scribed in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algo-

rithm when it returns to determine the status of the operation (top of Figure 7).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified inter-

nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the

program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the device halts the opera-

tion, and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return

to the read mode (or to the erase-suspend-read mode if a bank was previously

in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-

termine whether or not erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors are selected for erasure,

the entire time-out also applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also

the "Sector Erase Command Sequence" section.

After the sector erase command is written, the system should read the status of

DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase

algorithm has begun; all further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the device will accept addi-

tional sector erase commands. To ensure the command has been accepted, the

system software should check the status of DQ3 prior to and following each sub-

sequent sector erase command. If DQ3 is high on the second status check, the

last command might not have been accepted.

Tab le 2 3 shows the status of DQ3 relative to the other status bits.

78 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for

further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

Table 23. Write Operation Status

Status

DQ7

(Note 2)DQ6

DQ5

(Note 1)DQ3

DQ2

(Note 2)RY/BY#

Standard

Mode

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 79

PRELIMINARY

Absolute Maximum Ratings

Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . –0.5 V to +13.0 V

WP#/ACC (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V

All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,

input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum

DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or

I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V.

During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS

to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on

pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods

up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the

short circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this data sheet is not implied. Exposure of the device to absolute max-

imum rating conditions for extended periods may affect device reliability.

Figure 8. Maximum Overshoot Waveforms

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform

80 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Operating Ranges

Operating ranges define those limits between which the functionality of the de-

vice is guaranteed.

Industrial (I) Devices

Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Supply Voltages

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7–3.6 V

VIO (see Note)1.65–1.95 V (for PL127J and PL129J) or 2.7–3.6 V (for all PLxxxJ

devices)

Notes:

For all AC and DC specifications, VIO = VCC; contact your local sales office for other VIO

options.

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 81

PRELIMINARY

DC Characteristics

Notes:

1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH.

2. Maximum ICC specifications are tested with VCC = VCCmax.

3. ICC active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep

mode current is 1 mA.

5. Not 100% tested.

6. In S29PL129J there are two CE# (CE1#, CE2#).

7. Valid CE1#/CE2# conditions: (CE1# = VIL, CE2# = VIH,) or (CE1# = VIH, CE2# = VIL) or (CE1# = VIH, CE2# = VIH)

Table 24. CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC,

VCC = VCC max

±1.0 µA

ILIT A9, OE#, RESET# Input Load Current VCC = VCC max; VID= 12.5 V 35 µA

ILR Reset Leakage Current VCC = VCC max; VID= 12.5 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH

VCC = VCC max

±1.0 µA

ICC1 VCC Active Read Current (Notes 1, 2)OE# = VIH, VCC = VCC max

(Note 1)

5 MHz 20 30 mA

10 MHz 45 55

ICC2 VCC Active Write Current (Notes 2, 3)OE# = V

IH, WE# = VIL 15 25 mA

ICC3 VCC Standby Current (Note 2)CE#, RESET#, WP#/ACC

= VIO ± 0.3 V 0.2 5 µA

ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA

ICC5 Automatic Sleep Mode (Notes 2, 4)VIH = VIO ± 0.3 V;

VIL = VSS ± 0.3 V 0.2 5 µA

ICC6

VCC Active Read-While-Program Current

(Notes 1, 2)OE# = VIH,5 MHz 21 45 mA

10 MHz 46 70

ICC7

VCC Active Read-While-Erase Current

(Notes 1, 2)OE# = VIH,5 MHz 21 45 mA

10 MHz 46 70

ICC8

VCC Active Program-While-Erase-

Suspended Current (Notes 2, 5)OE# = VIH 17 25 mA

ICC9 VCC Active Page Read Current (Note 2)OE# = V

IH, 8 word Page Read 10 15 mA

VIL Input Low Voltage VIO = 1.65–1.95 V (PL127J and PL129J) –0.4 0.4 V

VIO = 2.7–3.6 V –0.5 0.8 V

VIH Input High Voltage VIO = 1.65–1.95 V (PL127J AND PL129J) VIO–0.4 VIO+0.4 V

VIO = 2.7–3.6 V 2.0 VCC+0.3 V

VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V

VID

Voltage for Autoselect and Temporary

Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V

VOL Output Low Voltage

IOL = 100 µA, VCC = VCC min, VIO = 1.65–1.95

V (PL127J AND PL129J) 0.1 V

IOL = 2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V 0.4 V

VOH Output High Voltage

IOH = –100 µA, VCC = VCC min, VIO =

1.65–1.95 V (PL127J AND PL129J) VIO–0.1 V

IOH = –2.0 mA, VCC = VCC min, VIO = 2.7–3.6

V2.4 V

VLKO Low VCC Lock-Out Voltage (Note 5)2.32.5V

82 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

AC Characteristic

Test Conditions

Note: Diodes are IN3064 or equivalent

Figure 9. Test Setups

Table 25. Test Specifications

Test Condition All Speeds Unit

Output Load 1 TTL gate

Output Load Capacitance, C

(including jig capacitance) 30 pF

Input Rise and Fall Times

= 1.8 V

(PL127J AND PL129J) 5ns

= 3.0 V

Input Pulse Levels

= 1.8 V

(PL127J AND PL129J) 0.0 - 1.8

= 3.0 V 0.0–3.0

Input timing measurement reference levels V

/2 V

Output timing measurement reference levels V

/2 V

2.7 kΩ

CL6.2 kΩ

Device

Under

Tes t

Device

Under

Tes t

VIO = 3.0 V VIO = 1.8 V (PL127J and PL129J)

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 83

PRELIMINARY

SWITCHING WAVEFORMS

VCC RampRate

All DC characteristics are specified for a VCC ramp rate > 1V/100 µs and VCC

>=VCCQ - 100 mV. If the VCC ramp rate is < 1V/100 µs, a hardware reset

required.+

Ta b l e 2 6 . K E Y TO S W I T C H I N G WAV E F O R M S

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Figure 10. Input Waveforms and Measurement Levels

VIO

0.0 V

VIO/2 VIO/2 OutputMeasurement LevelIn

84 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 25 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE#

high to the data bus driven to VCC /2 is taken as tDF.

4. S29PL129J has two CE# (CE1#, CE2#).

5. Valid CE1# / CE2# conditions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) or (CE1# = VIH, CE2# = VIH)

6. Valid CE1# / CE2# transitions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) to (CE1# = CE2# = VIH)

7. Valid CE1# / CE2# transitions: (CE1# = CE2# = VIH) to (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL)

8. For 70pF Output Load Capacitance, 2 ns will be added to the above tACC,tCE,tPACC,tOE values for all speed grades

Table 27. Read-Only Operations

Parameter

Description

Te s t S e t u p

Speed Options

JEDEC Std. 55 60 65 70 Unit

AVAV

Read Cycle Time (Note 1) Min 55 60 65 70 ns

AVQV

ACC

Address to Output Delay CE#, OE# = V

Max 55606570ns

ELQV

Chip Enable to Output Delay OE# = V

Max 55606570ns

PACC

Page Access Time Max 20252530ns

GLQV

Output Enable to Output Delay Max 20 25 30 ns

EHQZ

Chip Enable to Output High Z (Note 3)Max16ns

GHQZ

Output Enable to Output High Z (Notes 1,

3)Max 16 ns

AXQX

Out pu t Ho l d Ti me Fr o m A ddr e sse s , CE# or

OE#, Whichever Occurs First (Note 3)Min 5 ns

OEH

Output Enable Hold

Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 85

PRELIMINARY

Notes:

1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 11. Read Operation Timings

Notes:

1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 12. Page Read Operation Timings

Data

WE#

Addresses

CE#

OE#

HIGH Z

Valid Data

HIGH Z

Addresses Stable

ACC

OEH

0 V

RY/BY#

RESET#

Amax

CE#

OE#

Data

Same Page

Aa Ab Ac Ad

Qa Qb Qc Qd

tACC

tPACC tPACC tPACC

86 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Reset

Note: Not 100% tested.

Table 28. Hardware Reset (RESET#)

Parameter

Description All Speed Options UnitJEDEC Std

Ready

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

Ready

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

RESET# Pulse Width Min 500 ns

Reset High Time Before Read (See Note) Min 50 ns

RPD

RESET# Low to Standby Mode Min 20 µs

RY/BY# Recovery Time Min 0 ns

Notes:

1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2#

Figure 13. Reset Timings

RESET#

RY/BY#

Ready

Reset Timings NOT during Embedded Algorithms

Ready

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 87

PRELIMINARY

Erase/Program Operations

Notes:

1. Not 100% tested.

2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

3. S29PL129J - There are two CE# (CE1#, CE2#).

4. See the “Erase And Programming Performance” section for more information.

Table 29. Erase and Program Operations

Parameter Speed Options

JEDEC Std

Description

55 60 65 70 Unit

AVAV

Write Cycle Time (Note 1) Min 55 60 65 70 ns

AVWL

Address Setup Time Min 0 ns

ASO

Address Setup Time to OE# low during toggle bit

polling Min 15 ns

WLAX

Address Hold Time Min 30 35 ns

AHT

Address Hold Time From CE# (CE1#, CE#2 in PL129J)

or OE# high during toggle bit polling Min 0 ns

DVWH

Data Setup Time Min 25 30 ns

WHDX

Data Hold Time Min 0 ns

OEPH

Output Enable High during toggle bit polling Min 10 ns

GHWL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

ELWL

CE# (CE1# or CE#2 in PL129J) Setup Time Min 0 ns

WHEH

CE# (CE1# or CE#2 in PL129J) Hold Time Min 0 ns

WLWH

Write Pulse Width Min 35 ns

WHDL

WPH

Write Pulse Width High Min 20 25 ns

SR/W

Latency Between Read and Write Operations Min 0 ns

WHWH1

Programming Operation (Note 4)Typ6µs

WHWH1

Accelerated Programming Operation (Note 4)Typ 4 µs

WHWH2

Sector Erase Operation (Note 4)Typ0.5sec

VCS

Setup Time (Note 1)Min50µs

Write Recovery Time from RY/BY# Min 0 ns

BUSY

Program/Erase Valid to RY/BY# Delay

Max 90 ns

Min 35 ns

88 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Timing Diagrams

Notes:

1. PA = program address, PD = program data, DOUT is the true data at the program address

2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 14. Program Operation Timings

Figure 15. Accelerated Program Timing Diagram

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

WP#/ACC

tVHH

VHH

VIL or VIH VIL or VIH

tVHH

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 89

PRELIMINARY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”

2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 16. Chip/Sector Erase Operation Timings

Figure 17. Back-to-back Read/Write Cycle Timings

OE#

CE#

Addresses

WE#

Data

2AAh SA

WPH

555h for chip erase

10 for Chip Erase

30h

VCS

55h

Status D

OUT

WHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

BUSY

OE#

CE#

WE#

Addresses

Data

Valid

Valid PA Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

CPH

Read Cycle

SR/W

90 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and

array data read cycle

Figure 18. Data# Polling Timings (During Embedded Algorithms)

Notes:

1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

status read cycle, and array data read cycle

2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 19. Toggle Bit Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ7

DQ6–DQ0

RY/BY#

BUSY

Complement Tr u e

Addresses VA

OEH

VA VA

Status Data

Complement

Status Data Tr u e

Valid Data

ACC

OE#

CE#

WE#

Addresses

OEH

AHT

ASO

OEPH

Valid Data

(first read) (second read) (stops toggling)

CEPH

AHT

DQ6/DQ2 Valid Data

Valid

Status

Valid

Status

Valid

Status

RY/BY#

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 91

PRELIMINARY

Protect/Unprotect

Note: Not 100% tested.

Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#

or CE# to toggle DQ2 and DQ6.

Figure 20. DQ2 vs. DQ6

Table 30. Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std

Description

Unit

VIDR

Rise and Fall Time (See Note) Min 500 ns

VHH

Rise and Fall Time (See Note) Min 250 ns

RSP

RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

RRB

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect Min 4 µs

Figure 21. Temporary Sector Unprotect Timing Diagram

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

VID

or V

CE#

WE#

RY/BY#

tVIDR

RSP

Program or Erase Command Sequence

tRRB

92 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Notes:

1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Group Protect/Unprotect Verify

VID

VIH

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 93

PRELIMINARY

Controlled Erase Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Table 31. Alternate CE# Controlled Erase and Program Operations

Parameter Speed Options

JEDEC Std

Description

55 60 65 70 Unit

AVAV

Write Cycle Time (Note 1) Min 55 60 65 70 ns

AVWL

Address Setup Time Min 0 ns

ELAX

Address Hold Time Min 30 35 ns

DVEH

Data Setup Time Min 25 30 ns

EHDX

Data Hold Time Min 0 ns

GHEL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

WLEL

WE# Setup Time Min 0 ns

EHWH

WE# Hold Time Min 0 ns

ELEH

CE# (CE1# or CE#2 in PL129J) Pulse Width Min 35 40 ns

EHEL

CPH

CE# (CE1# or CE#2 in PL129J) Pulse Width High Min 20 25 ns

WHWH1

Programming Operation (Note 2)Typ6µs

WHWH1

Accelerated Programming Operation (Note 2)Typ 4 µs

WHWH2

Sector Erase Operation (Note 2)Typ0.5sec

94 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device

4. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH

5. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#

Table 32. Alternate CE# Controlled Write (Erase/Program) Operation Timings

Table 33. CE1#/CE2# Timing (S29PL129J only)

Parameter

Description All Speed Options UnitJEDEC Std

CCR

CE1#/CE2# Recover Time Min 30 ns

GHEL

OE#

CE#

WE#

RESET#

Data

Addresses

DQ7# D

OUT

CPH

Data# Polling

A0 for program

55 for erase

WHWH1 or 2

RY/BY#

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

BUSY

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 95

PRELIMINARY

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern. All values are subject to change.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 21 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

BGA Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control

Table 34. Erase And Programming Performance

Parameter

Ty p ( Note 1)Max (Note 2) Unit Comments

Sector Erase Time

0.5 2 sec

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

PL127J/129J 135 216 sec

PL064J 71 113.6 sec

PL032J 39 62.4 sec

Word Program Time

6 100 µs

Excludes system level

overhead (Note 5)

Accelerated Word Program Time

460µs

Chip Program Time

(Note 3)

PL127J/129J 50.4 200 sec

PL064J 25.2 50.4 sec

PL032J 12.6 25.2 sec

Parameter Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance V

= 0 6.3 7 pF

OUT

Output Capacitance V

OUT

= 0 7.0 8 pF

IN2

Control Pin Capacitance V

= 0 5.5 8 pF

IN3

WP#/ACC Pin Capacitance V

= 0 11 12 pF

CE1#

CCR

CE2#

96 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Physical Dimensions

VBG080—80-Ball Fine-pitch Ball Grid Array 8 x 11 mm Package (PL127J

and PL129J)

3329 \ 16-038.25b

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBG 080

JEDEC N/A

11.00 mm x 8.00 mm NOM

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.18 --- --- BALL HEIGHT

A2 0.62 --- 0.76 BODY THICKNESS

D 11.00 BSC. BODY SIZE

E 8.00 BSC. BODY SIZE

D1 8.80 BSC. BALL FOOTPRINT

E1 5.60 BSC. BALL FOOTPRINT

MD 12 ROW MATRIX SIZE D DIRECTION

ME 8 ROW MATRIX SIZE E DIRECTION

N 80 TOTAL BALL COUNT

φb 0.33 --- 0.43 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

(A3-A6,B3-B6,L3-L6,M3-M6) DEPOPULATED SOLDER BALLS

TOP VIEW

INDEX MARK

CORNER 10

PIN A1

C0.05

(2X)

C0.05

A1 CORNER

ML JK

BACEDFHG

BCA

φ 0.15

φ 0.08 M

6NXφbSD

BOTTOM VIEW

SIDE VIEW

0.10 C

C0.08

SEATING PLANE

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 97

PRELIMINARY

VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm package

(PL127J)

3330 \ 16-038.25b

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBH 064

JEDEC N/A

11.60 mm x 8.00 mm NOM

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.18 --- --- BALL HEIGHT

A2 0.62 --- 0.76 BODY THICKNESS

D 11.60 BSC. BODY SIZE

E 8.00 BSC. BODY SIZE

D1 8.80 BSC. BALL FOOTPRINT

E1 7.20 BSC. BALL FOOTPRINT

MD 12 ROW MATRIX SIZE D DIRECTION

ME 10 ROW MATRIX SIZE E DIRECTION

N 64 TOTAL BALL COUNT

φb 0.33 --- 0.43 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

(A2-9,B1-4,B7-10,C1-K1, DEPOPULATED SOLDER BALLS

M2-9,C10-K10,L1-4,L7-10,

G5-6,F5-6)

BOTTOM VIEW

TOP VIEW

SIDE VIEW

A1 CORNER

ML JK

C0.05

(2X)

C0.05

BACEDFHG

BCA

φ 0.15

φ 0.08 M

0.10 C

C0.08

NXφb

SEATING PLANE

A1 CORNER

INDEX MARK

98 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

VBK048—48-Ball Fine-pitch Ball Grid Array 8.15 x 6.15 mm package

(PL127J)

3338 \ 16-038.25b

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBK 048

JEDEC N/A

8.15 mm x 6.15 mm NOM

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.18 --- --- BALL HEIGHT

A2 0.62 --- 0.76 BODY THICKNESS

D 8.15 BSC. BODY SIZE

E 6.15 BSC. BODY SIZE

D1 5.60 BSC. BALL FOOTPRINT

E1 4.00 BSC. BALL FOOTPRINT

MD 8 ROW MATRIX SIZE D DIRECTION

ME 6 ROW MATRIX SIZE E DIRECTION

N 48 TOTAL BALL COUNT

φb 0.33 --- 0.43 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

--- DEPOPULATED SOLDER BALLS

SIDE VIEW

TOP VIEW

SEATING PLANE

(4X)

0.10

C0.10

A1 C

C0.08

BOTTOM VIEW

A1 CORNER

φ 0.15 C

BCDEFG

φb

φ 0.08

PIN A1

CORNER

INDEX MARK

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 99

PRELIMINARY

TLC056—56-Ball Fine-pitch BGA 7 x 9mm package (PL064J and PL032J)

3348 \ 16-038.22a

PACKAGE TLC 056

JEDEC N/A

D x E 9.00 mm x 7.00 mm

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.20 PROFILE

A1 0.20 --- --- BALL HEIGHT

A2 0.81 --- 0.97 BODY THICKNESS

D 9.00 BSC. BODY SIZE

E 7.00 BSC. BODY SIZE

D1 5.60 BSC. MATRIX FOOTPRINT

E1 5.60 BSC. MATRIX FOOTPRINT

MD 8 MATRIX SIZE D DIRECTION

ME 8 MATRIX SIZE E DIRECTION

n 56 BALL COUNT

φb 0.35 0.40 0.45 BALL DIAMETER

eE 0.80 BSC. BALL PITCH

eD 0.80 BSC BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

A1,A8,D4,D5,E4,E5,H1,H8 DEPOPULATED SOLDER BALLS

NOTES:

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

DCEFGH

PIN A1

CORNER

BOTTOM VIEW

0.08

0.20 C

0.15

(2X)

0.15

(2X)

INDEX MARK

TOP VIEW

SIDE VIEW

CORNER

56X

0.15 M

0.08

PIN A1

100 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

TS056—20 x 14 mm, 56-pin TSOP (PL127J)

-X-

X = A OR B

e/2

DETAIL B

0.25MM (0.0098") BSC

0˚

DETAIL A

GAGE LINE

PARALLEL TO

SEATING PLANE

(c)

WITH PLATING

BASE METAL

C A-B SM

0.08MM (0.0031")

SECTION B-B

0.10 C

PLANE

SEATING

SEE DETAIL B

SEE DETAIL A

N+1

-A- -B-

TS 056

MO-142 (B) EC

MIN

0.05

0.95

0.17

0.10

18.30

19.80

0.50

0˚

0.08

13.90

0.50 BASIC

MAX

0.15

1.20

0.27

0.16

0.21

5˚

0.20

18.50

14.10

0.70

20.20

0.23

1.05

0.20

1.00

0.22

18.40

20.00

0.60

3˚

14.00

NOM

Symbol

Jedec

Package

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT

HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15MM (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE

BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

May 24, 2004 31107A6 S29PL127J/S29PL129J/S29PL064J/S29PL032J 101

PRELIMINARY

Revision Summary

Revision A (January 29, 2004)

Initial release.

Revision A+1 (February 12, 2004)

Software Features

Included backward compatibility with MBM29xx families.

General Description

48-ball BGA package is not supported and was removed.

Ordering Information

Model numbers for the 48-ball BGA configurations were removed.

64-Ball Fine Pitch BGA—MCP Compatible

An illustration was added to show the pin-out configuration.

Ta b l e 2 0

Added the description of 01h for address 4Fh and removed the 0004 data.

Ta b l e 3 4

Provided the time units of measure for the erase and programming

performances.

Revision A+2 (February 17, 2004)

Table 21, “Memory Array Command Definitions”

Corrected typo in device ID.

Revision A+3 (February 25, 2004)

Architectural Advantages

Added 3V VIO for PL064J and PL032J devices.

Ordering Information

Corrected the voltage rating, ball configuration, and physical dimensions for

model numbers 12 and 13.

Connection Diagrams

Removed the 64-ball, 8x9 mm diagram.

Operating Ranges

Clarified the supply voltages that apply to the PL127J/PL129J and all other PLxxxJ

products.

BGA Pin Capacitance

Added information applicable to the CIN3 symbol.

Package Drawings

Removed the 9x8 mm package drawing.

102 S29PL127J/S29PL129J/S29PL064J/S29PL032J 31107A6 May 24, 2004

PRELIMINARY

Revision A+4 (February 27, 2004)

Connection Diagrams

Added the 56-ball 7x9 mm pinout diagram.

Package Options

Updated to include the 8 x 6 mm, 48-ball Fine pitch BGA and 7 x 9 mm, 56-ball

Fine-pitch BGA options.

Physical Dimensions

Added the VBK048 package drawing.

Revision A+5 (March 15, 2004)

Connection Diagrams

Changed name of "VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm pack-

age (PL127J)" section

Revision A+6 (May 24, 2004)

Global

Removed VIO, added TSOP, fixed SecSi DQ bits.

Product Selector Guide

Updated specs in this table.

Ordering Information

Updated the Model Number offerings.

Valid Combinations Table (128Mb)

Corrected the Package Markings for the 64-ball FBGA packages.

Added combinations for the TLC056 package on the PL064J and PL032J devices.

Valid Combinations for BGA Packages (128Mb)

Updated information in this table.

Package Options

Added the 7 x 9mm 56-ball package.

Connection Diagram

56-ball connection diagram

Erase/Programming Performance Table

Notes 1 and 2 corrected to reflect accurate temperature ranges and cycling.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by

FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is

without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of

third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of

the information in this document.

Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this

publication are for identification purposes only and may be trademarks of their respective companies.