1. General description
The 74HC4052; 7 4HCT4052 is a hig h- spee d Si-g ate CMOS de vice and is pi n co mpatible
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4052; 74HCT4052 is a dual 4-channel analog multipl exer/demultiplexer with
common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to
nY3) and a common inpu t/output (p in nZ). Th e common ch annel select logics include two
digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). Wh en
pin E = LOW, one of the fo ur switches is sele cted (low-impedance ON-state) with pins S0
and S1. When pin E = HIGH, all switches are in the high-i mpedance OFF-state,
independent of pins S0 an d S1.
VCC and GND are the supply volt age pins for the digit al control input s (pins S0, S1 and E).
The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the
74HCT4052. The a nalog input s/output s (pins nY0 to nY3 and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
2. Features
Wide analog input voltage range from −5 V to +5 V
Low ON resistance:
80 Ω (typical) at VCC − VEE = 4.5 V
70 Ω (typical) at VCC − VEE = 6.0 V
60 Ω (typical) at VCC − VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
Typical ‘break before make’ built-in
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exce ed s 200 V
Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 06 — 11 January 2010 Product data sheet
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 2 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4052
74HC4052D −40 °C to +125 °CSO16 plas tic small outline package; 16 leads; body
width 3.9 mm SOT109-1
74HC4052DB −40 °C to +125 °CSSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm SOT338-1
74HC4052N −40 °C to +125 °CDIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC4052PW −40 °C to +125 °CTSSOP16 plastic thin shrink small outline package; 16 leads;
body wid t h 4.4 mm SOT403-1
74HC4052BQ −40 °C to +125 °CDHVQFN16 plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
74HCT4052
74HCT4052D −40 °C to +125 °CSO16 plastic small outline package; 16 leads; body
width 3.9 mm SOT109-1
74HCT4052DB −40 °C to +125 °CSSOP16 plastic shrink small outline package; 16 leads;
body width 5. 3 mm SOT338-1
74HCT4052N −40 °C to +125 °CDIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4052PW −40 °C to +125 °CTSSOP16 plastic thin shrink small outline package; 16 leads;
body wid t h 4.4 mm SOT403-1
74HCT4052BQ −40 °C to +125 °CDHVQFN16 plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aah82
4
1Z
13
S0
S1
E
10
9
6
2Z
3
2Y3
2Y2
2Y1
2Y0
1Y3
1Y2
1Y1
1Y0
4
2
5
1
11
15
14
12
001aah82
5
1
0
G4
MDX
0
3
4 ×
3
2
1
0
4
2
5
1
11
15
14
12
10
9
6
3
13
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 3 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 3. Schematic diagram (one switch)
mnb04
3
from
logic
VCC
VEE
VEE
VCC
VCC
VEE
nYn
nZ
VCC
Fig 4. Functional diagram
001aah872
1-OF-4
DECODER
LOGIC
LEVEL
CONVERSION
78
VEE
VSS
VDD
12
13
16
3
14
15
11
10
9
6
S0
S1
E
1
5
2
1Y0
1Z
2Z
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
4
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 4 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration for DIP16, SO16 and
(T)SSOP16 Fig 6. Pin configuration for DHVQFN16
74HC4052
74HCT4052
2Y0 VCC
2Y2 1Y2
2Z 1Y1
2Y3 1Z
2Y1 1Y0
E 1Y3
VEE S0
GND S1
001aah822
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aah82
3
74HC4052
74HCT4052
V
EE
V
CC(1)
S0
E 1Y3
2Y1 1Y0
2Y3 1Z
2Z 1Y1
2Y2 1Y2
GND
S1
2Y0
V
CC
Transparent top view
7 10
6 11
5 12
413
3 14
2 15
8
9
1
16
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
2Y0 1independent input or output 2Y0
2Y2 2independent input or output 2Y2
2Z 3common input or output 2
2Y3 4independent input or output 2Y3
2Y1 5independent input or output 2Y1
E 6 enable input (active LOW)
VEE 7negative supply voltage
GND 8 ground (0 V)
S1 9select logic input 1
S0 10 select logic input 0
1Y3 11 independent input or output 1Y3
1Y0 12 independent input or output 1Y0
1Z 13 common input or output 1
1Y1 14 independent input or output 1Y1
1Y2 15 independent input or output 1Y2
VCC 16 positive supply voltage
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 5 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
[1] To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must
not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the
voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE.
[2] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table[1]
Input Channel on
ES1 S0
LLLnY0 and nZ
LLHnY1 and nZ
LHLnY2 and nZ
LHHnY3 and nZ
HXXnone
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VEE = GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] −0.5 +11.0 V
IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA
ISK switch clamping current VSW < −0.5 V or VSW > VCC + 0.5 V - ±20 mA
ISW switch current −0.5 V < VSW < VCC + 0.5 V - ±25 mA
IEE supply current -±20 mA
ICC supply current -50 mA
IGND ground current -−50 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C[2] -500 mW
Ppower dissipation per switch -100 mW
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 6 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 5. Recommended operating con ditions
Symbol Parameter Conditions 74HC4052 74HCT4052 Unit
Min Typ Max Min Typ Max
VCC supply voltage see Figure 7
and Figure 8
VCC − GND 2.0 5.0 10.0 4.5 5.0 5.5 V
VCC − VEE 2.0 5.0 10.0 2.0 5.0 10.0 V
VIinput voltage GND - VCC GND - VCC V
VSW switch voltage VEE - VCC VEE - VCC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔVinput transition rise and fall
rate VCC = 2.0 V - 1.67 625 -1.67 139 ns/V
VCC = 4.5 V - 1.67 139 -1.67 139 ns/V
VCC = 6.0 V - 1.67 83 -1.67 139 ns/V
VCC = 10.0 V - 1.67 31 -1.67 139 ns/V
Fig 7. Guaranteed operatin g area as a fu nction of the
supply voltages for 74HC4052 Fig 8. Guaranteed operating area as a function of the
supply voltages for 74HCT4052
mnb044
04 12
12
0
4
8
8
operating area
VCC − VEE (V)
VCC − GND
(V)
mnb045
0
12
6
10
8
2
4
04 128
operating area
VCC − VEE (V)
VCC − GND
(V)
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 7 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
10. Static characteristics
Table 6. RON resistance per switch for 74HC4052 and 74HCT4052
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4052: VCC
−
GND or VCC
−
VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4052: VCC
−
GND = 4.5 V and 5.5 V, VCC
−
VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
RON(peak) ON resistance (peak) Vis = VCC to VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA[2] - - - Ω
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - 100 225 Ω
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - 90 200 Ω
VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - 70 165 Ω
RON(rail) ON resistance (rail) Vis = VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA[2] -150 -Ω
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - 80 175 Ω
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - 70 150 Ω
VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - 60 130 Ω
Vis = VCC
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA - 150 -Ω
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - 90 200 Ω
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - 80 175 Ω
VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - 65 150 Ω
ΔRON ON resistance mismatch
between channels Vis = VCC to VEE
VCC = 2.0 V; VEE = 0 V [2] - - - Ω
VCC = 4.5 V; VEE = 0 V - 9 - Ω
VCC = 6.0 V; VEE = 0 V - 8 - Ω
VCC = 4.5 V; VEE = −4.5 V - 6 - Ω
Tamb = −40 °C to +125 °C
RON(peak) ON resistance (peak) Vis = VCC to VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA[2] - - - Ω
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - - 270 Ω
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - - 240 Ω
VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - - 195 Ω
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 8 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb = 25 °C.
[2] When supply voltages (VCC − VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
2 V, it is recommended to use these devices only for transmitting digital signals.
RON(rail) ON resistance (rail) Vis = VEE
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA[2] - - - Ω
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - - 210 Ω
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - - 180 Ω
VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - - 160 Ω
Vis = VCC
VCC = 2.0 V; VEE = 0 V; ISW = 100 μA[2] - - - Ω
VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - - 240 Ω
VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - - 210 Ω
VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - - 180 Ω
Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 …continued
VI = VIH or VIL; for test circuit see Figure 9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4052: VCC
−
GND or VCC
−
VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4052: VCC
−
GND = 4.5 V and 5.5 V, VCC
−
VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
Symbol Parameter Conditions Min Typ Max Unit
Vis = 0 V to (VCC − VEE). Vis = 0 V to (VCC − VEE).
(1) VCC = 4.5 V
(2) VCC = 6 V
(3) VCC = 9 V
Fig 9. Test circuit for measuring RON Fig 10. Typical RON as a function of input voltage Vis
V
001aah82
6
nYn
Sn
from select
input
nZ
GND VEE
VCC
Vis Isw
Vsw
Vis (V)
0 9.07.23.6 5.41.8
001aai068
40
60
20
80
100
RON
(Ω)
0
(1)
(2)
(3)
RON Vsw
Isw
---------
=
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 9 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Table 7. Static characteristics for 74HC4052
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
VIH HIGH-level input
voltage VCC = 2. 0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VCC = 9.0 V 6.3 4.7 - V
VIL LOW-level input
voltage VCC = 2. 0 V -0.8 0.5 V
VCC = 4.5 V -2.1 1.35 V
VCC = 6.0 V -2.8 1.8 V
VCC = 9.0 V -4.3 2.7 V
IIinput leakage current VEE = 0 V; VI = VCC or GND
VCC = 6.0 V - - ±1.0 μA
VCC = 10.0 V - - ±2.0 μA
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel - - ±1.0 μA
all channels - - ±2.0 μA
IS(ON) ON-state leakage
current VI = VIH or VIL; |VSW| = VCC − VEE;
VCC = 10.0 V; VEE = 0 V; see Figure 12 - - ±2.0 μA
ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC;
Vos = VCC or VEE
VCC = 6.0 V - - 80.0 μA
VCC = 10.0 V - - 160.0 μA
CIinput capacitance -3.5 -pF
Csw switch capacitance independent pins nYn - 5 - pF
common pins nZ -12 -pF
Tamb = −40 °C to +125 °C
VIH HIGH-level input
voltage VCC = 2. 0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VCC = 9.0 V 6.3 - - V
VIL LOW-level input
voltage VCC = 2. 0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VCC = 9.0 V - - 2.7 V
IIinput leakage current VEE = 0 V; VI = VCC or GND
VCC = 6.0 V - - ±1.0 μA
VCC = 10.0 V - - ±2.0 μA
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 10 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb = 25 °C.
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel - - ±1.0 μA
all channels - - ±2.0 μA
IS(ON) ON-state leakage
current VI = VIH or VIL; |VSW| = VCC − VEE;
VCC = 10.0 V; VEE = 0 V; see Figure 12 - - ±2.0 μA
ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC;
Vos = VCC or VEE
VCC = 6.0 V - - 160.0 μA
VCC = 10.0 V - - 320.0 μA
Table 7. Static characteristics for 74HC4052 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Static characteristics for 74HCT4052
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
VIH HIGH-level input
voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input
voltage VCC = 4.5 V to 5.5 V -1.2 0.8 V
IIinput leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V --±1.0 μA
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel --±1.0 μA
all channels --±2.0 μA
IS(ON) ON-state leakage
current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 12 --±2.0 μA
ICC supply current VI = VCC or GND; Vis = VEE or VCC;
Vos = VCC or VEE
VCC = 5.5 V; VEE = 0 V --80.0 μA
VCC = 5.0 V; VEE = −5.0 V --160.0 μA
ΔICC additional supply
current per input; VI = VCC − 2.1 V ; other input s at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V -45 202.5 μA
CIinput capacitance -3.5 -pF
Csw switch capacitance independent pins nYn - 5 - pF
common pins nZ -12 -pF
Tamb = −40 °C to +125 °C
VIH HIGH-level input
voltage VCC = 4.5 V to 5.5 V 2.0 - - V
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 11 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb = 25 °C.
VIL LOW-level input
voltage VCC = 4.5 V to 5.5 V --0.8 V
ILI input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V --±1.0 μA
IS(OFF) OFF-state leakage
current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 11
per channel --±1.0 μA
all channels --±2.0 μA
IS(ON) ON-state leakage
current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
|VSW| = VCC − VEE; see Figure 12 --±2.0 μA
ICC supply current VI = VCC or GND; Vis = VEE or VCC;
Vos = VCC or VEE
VCC = 5.5 V; VEE = 0 V --160.0 μA
VCC = 5.0 V; VEE = −5.0 V --320.0 μA
ΔICC additional supply
current per input; VI = VCC − 2.1 V ; other input s at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V --220.5 μA
Table 8. Static characteristics for 74HCT4052 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Vis = VCC and Vos = VEE.
Vis = VEE and Vos = VCC.
Fig 11. Test circuit for measuring OFF-state current
001aah82
7
nYn
Sn
from select
input
nZ
GND VEE
VCC
Vis Vos
Isw
A
Isw
A
Vis = VCC and Vos = open-circuit.
Vis = VEE and Vos = open-circuit.
Fig 12. Test circuit for measuring ON-state current
Isw
A
001aah82
8
nYn
Sn
HIGH
from select
input
nZ
GND VEE
VCC
Vis
Vos
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 12 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Table 9. Dynamic characteristics for 74HC4052
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
tpd propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 [2]
VCC = 2.0 V; VEE = 0 V -14 75 ns
VCC = 4.5 V; VEE = 0 V - 5 15 ns
VCC = 6.0 V; VEE = 0 V - 4 13 ns
VCC = 4.5 V; VEE = −4.5 V - 4 10 ns
ton turn-on time E, Sn to Vos; RL = ∞ Ω; see Figure 14 [3]
VCC = 2.0 V; VEE = 0 V -105 405 ns
VCC = 4.5 V; VEE = 0 V -38 81 ns
VCC = 6.0 V; VEE = 0 V -30 69 ns
VCC = 4.5 V; VEE = −4.5 V -26 58 ns
toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [4]
VCC = 2.0 V; VEE = 0 V -74 315 ns
VCC = 4.5 V; VEE = 0 V -27 63 ns
VCC = 6.0 V; VEE = 0 V -22 54 ns
VCC = 4.5 V; VEE = −4.5 V -22 48 ns
CPD power dissipation
capacitance per switch; VI = GND to VCC [5] -57 -pF
Tamb = −40 °C to +125 °C
tpd propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 [2]
VCC = 2.0 V; VEE = 0 V --90 ns
VCC = 4.5 V; VEE = 0 V --18 ns
VCC = 6.0 V; VEE = 0 V --15 ns
VCC = 4.5 V; VEE = −4.5 V --12 ns
ton turn-on time E, Sn to Vos; RL = ∞ Ω; see Figure 14 [3]
VCC = 2.0 V; VEE = 0 V --490 ns
VCC = 4.5 V; VEE = 0 V --98 ns
VCC = 6.0 V; VEE = 0 V --83 ns
VCC = 4.5 V; VEE = −4.5 V --69 ns
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 13 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH.
[3] ton is the same as tPZH and tPZL.
[4] toff is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
Σ{(CL + Csw) × VCC2 × fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [4]
VCC = 2.0 V; VEE = 0 V --375 ns
VCC = 4.5 V; VEE = 0 V --75 ns
VCC = 6.0 V; VEE = 0 V --64 ns
VCC = 4.5 V; VEE = −4.5 V --57 ns
Table 9. Dynamic characteristics for 74HC4052 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Table 10. Dynamic characteristics for 74HCT4052
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
tpd propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 [2]
VCC = 4.5 V; VEE = 0 V - 5 15 ns
VCC = 4.5 V; VEE = −4.5 V - 4 10 ns
ton turn-on time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [3]
VCC = 4.5 V; VEE = 0 V -41 88 ns
VCC = 4.5 V; VEE = −4.5 V -28 60 ns
toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [4]
VCC = 4.5 V; VEE = 0 V -26 63 ns
VCC = 4.5 V; VEE = −4.5 V -21 48 ns
CPD power dissipation
capacitance per switch; VI = GND to VCC − 1.5 V [5] -57 -pF
Tamb = −40 °C to +125 °C
tpd propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 [2]
VCC = 4.5 V; VEE = 0 V - - 18 ns
VCC = 4.5 V; VEE = −4.5 V - - 12 ns
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 14 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH.
[3] ton is the same as tPZH and tPZL.
[4] toff is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
Σ{(CL + Csw) × VCC2 × fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
ton turn-on time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [3]
VCC = 4.5 V; VEE = 0 V - - 105 ns
VCC = 4.5 V; VEE = −4.5 V - - 72 ns
toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [4]
VCC = 4.5 V; VEE = 0 V - - 75 ns
VCC = 4.5 V; VEE = −4.5 V - - 57 ns
Table 10. Dynamic characteristics for 74HCT4052 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Fig 13. Inpu t (Vis) to output (Vos) propagation delays
001aad55
5
t
PLH
t
PHL
50 %
50 %
V
is
input
V
os
output
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 15 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
For 74HC4052: VM = 0.5 × VCC.
For 74HCT4052: VM = 1.3 V.
Fig 14. Turn-on and turn-off times
001aae33
0
tPLZ
tPHZ
switch OFF switch ON
switch ON
Vos output
Vos output
E, Sn inputs VM
VI
0 V
90 %
10 %
tPZL
tPZH
50 %
50 %
Definitions for test circuit; see Table 11:
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
S1 = Test selection switch.
Fig 15. Test circuit for measuring AC performance
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aae38
2
VCC VCC
open
GND
VEE
VIVos
DUT
CL
RT
RLS1
PULSE
GENERATOR
Vis
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 16 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor.
[2] VI values:
a) For 74HC4052: VI = VCC
b) For 74HCT4052: VI = 3 V
12. Additional dynamic characteristics
[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω).
[2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 Ω).
Table 11. Test data
Test Input Load S1 position
VIVis tr, tfCLRL
at fmax other[1]
tPHL, tPLH [2] pulse < 2 ns 6 ns 50 pF 1 kΩopen
tPZH, tPHZ [2] VCC < 2 ns 6 ns 50 pF 1 kΩVEE
tPZL, tPLZ [2] VEE < 2 ns 6 ns 50 pF 1 kΩVCC
Table 12. Additional dynamic characteristics
Recommended conditions and typical values; GND = 0 V; Tamb = 25
°
C; CL = 50 pF.
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
dsin sine-wave distortion fi = 1 kHz; RL = 10 kΩ; see Figure 16
Vis = 4.0 V (p-p); VCC = 2.25 V ; VEE = −2.25 V -0.04 - %
Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V -0.02 - %
fi = 10 kHz; RL = 10 kΩ; see Figure 16
Vis = 4.0 V (p-p); VCC = 2.25 V ; VEE = −2.25 V -0.12 - %
Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V -0.06 - %
αiso isolation (OFF-state) RL = 600 Ω; fi = 1 MHz; see Figure 17
VCC = 2.25 V; VEE = −2.25 V [1] -−50 -dB
VCC = 4.5 V; VEE = −4.5 V [1] -−50 -dB
Xtalk crosstalk between two switches/multipl exers;
RL = 600 Ω; fi = 1 MHz; see Figure 18
VCC = 2.25 V; VEE = −2.25 V [1] -−60 -dB
VCC = 4.5 V; VEE = −4.5 V [1] -−60 -dB
Vct crosstalk voltage peak-to-peak value; between control and any
switch; RL = 600 Ω; fi = 1 MHz; E or Sn square
wave between VCC and GND; tr = tf = 6 ns;
see Figure 19
VCC = 4.5 V; VEE = 0 V -110 -mV
VCC = 4.5 V; VEE = −4.5 V -220 -mV
f(−3dB) −3 dB frequency response RL = 50 Ω; see Figure 20
VCC = 2.25 V; VEE = −2.25 V [2] -170 -MHz
VCC = 4.5 V; VEE = −4.5 V [2] -180 -MHz
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 17 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 16. Test circuit for measuring sine-wave distortion
dB
001aah82
9
nYn/nZ
10 μF
V
is
V
os
nZ/nYn
CL
RL
Sn
GNDV
EE
V
CC
VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ.
a. Test circuit
b. Isolation (OFF-state) as a function of frequency
Fig 17. Test circui t for meas uring isolation (OFF-state)
dB
001aah87
1
nYn/nZ
0.1 μF
V
is
V
os
nZ/nYn
CL
RL
Sn
GNDV
EE
V
CC
001aae332
fi (kHz)
10 105106
104
102103
−60
−40
−80
−20
0
αiso
(dB)
−100
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 18 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 18. Test circuit s for measuring crosstalk between any two switches/multiplexers
dB
001aah87
3
nYn/nZ V
os
nZ/nYn
CL
RL
RL
Sn
GNDV
EE
V
CC
nYn/nZ
0.1 μF
V
is
nZ/nYn
CL
RL
RL
Sn
GNDV
EE
V
CC
Fig 19. Test circuit for measuring crosstalk between control input and any switch
oscilloscope
001aah91
3
nYn
Vct
nZ
2RL2RL
2RL2RL
Sn, E
GNDVEE
VCC
G
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 19 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ.
a. Test circuit
b. Typical fre quency response
Fig 20. Test circuit for frequency response
dB
001aah82
9
nYn/nZ
10 μF
V
is
V
os
nZ/nYn
CL
RL
Sn
GNDV
EE
V
CC
001aad551
f (kHz)
10 105106
104
102103
−1
1
−3
3
5
Vos
(dB)
−5
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 20 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
13. Package outline
Fig 21. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8 1.27 6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15 0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
S
O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109
-1
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 21 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 22. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05
1.80
1.65 0.25 0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2 0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
S
SOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338
-1
A
max.
2
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 22 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 23. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05 0.2542.54 7.62 8.25
7.80
10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12 0.010.1 0.3 0.32
0.31
0.39
0.33 0.030.17 0.02 0.13
D
IP16: plastic dual in-line package; 16 leads (300 mil) SOT38
-4
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 23 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 24. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403
-1
A
max.
1.1
pin 1 index
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 24 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 25. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4
1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763
-1
D
HVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
1
6 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
A
A1
c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
C
B
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 25 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
14. Abbreviations
15. Revision history
Table 13. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4052_6 20100111 Product data sheet -74HC_HCT4052_5
Modifications: •Added type number 74HCT4052PW (TSSOP16 / SOT403-1 package).
74HC_HCT4052_5 20080505 Product data sheet -74HC_HCT4052_4
74HC_HCT4052_4 20041111 Product specification -74HC_HCT4052_3
74HC_HCT4052_3 20030516 Product specification -74HC_HCT4052_CNV_2
74HC_HCT4052_CNV_2 19901201 - - -
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 06 — 11 January 2010 26 of 27
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
16.3 Disclaimers
General — In formation in this document is believed to be accurate and
reliable. However, NXP Semiconductors d oes not give any represent ations or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and with out
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause pe rmanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertain i ng to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patent s or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objec tive specification for product development.
Preliminary [short] dat a sheet Qualification This document contains dat a from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 January 2010
Document identifier: 74HC_HCT4052_6
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 12
12 Additional dynamic characteristics . . . . . . . . 16
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
17 Contact information. . . . . . . . . . . . . . . . . . . . . 26
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
