FUJITSU SEMICONDUCTOR DATA SHEET DS04-29117-2E Spread Spectrum Clock Generator MB88152 DESCRIPTION MB88152 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency. FEATURES * * * * * * * * * * Input frequency : 16.6 MHz to 134 MHz Output frequency : 16.6 MHz to 134 MHz Modulation rate : 0.5%, 1.5% (Center spread), - 1.0%, - 3.0% (Down spread) Equipped with oscillation circuit: Range of oscillation 16.6 MHz to 48 MHz Modulation clock output Duty : 40% to 60% Modulation clock Cycle-Cycle Jitter : Less than 100 ps Low current consumption by CMOS process : 5 mA (24 MHz : Typ-sample, no load) Power supply voltage : 3.3 V 0.3 V Operating temperature : - 40 C to +85 C Package : SOP 8 pin PACKAGE 8-pin plastic SOP (FPT-8P-M02) MB88152 PRODUCT LINE-UP MB88152 has three kinds of input frequency, and two kinds of modulation type (center/down spread), total six lineups. Product Input/Output Frequency Modulation type Modulation enable pin MB88152-100 16.6 MHz to 134 MHz MB88152-101 16.6 MHz to 67 MHz MB88152-102 40 MHz to 134 MHz MB88152-110 16.6 MHz to 134 MHz MB88152-111 16.6 MHz to 67 MHz MB88152-112 40 MHz to 134 MHz No Down spread Yes No Center spread Yes PIN ASSIGNMENT TOP VIEW XIN 1 8 XENS XIN 1 MB88152-101, 7 FREQ MB88152-102, VSS 3 MB88152-111, 6 VDD SEL 4 MB88152-112 5 CKOUT XOUT 2 FPT-8P-M02 8 FREQ1 MB88152-100, 7 FREQ0 3 MB88152-110 6 VDD XOUT 2 VSS SEL 4 5 CKOUT FPT-8P-M02 PIN DESCRIPTION 2 Pin name I/O Pin no. Description XIN I 1 Crystal resonator connection Pin/clock input pin XOUT O 2 Crystal resonator connection Pin VSS 3 GND pin SEL I 4 Modulation rate setting pin CKOUT O 5 Modulated clock output pin VDD 6 Power supply voltage pin FREQ/FREQ0 I 7 Frequency setting pin XENS/FREQ1 I 8 Modulation enable setting pin/frequency setting pin MB88152 I/O CIRCUIT TYPE Pin Circuit type Remarks * CMOS hysteresis input SEL FREQ FREQ0 FREQ1 XENS * CMOS output * IOL = 4 mA CKOUT Note : For XIN and XOUT pins, see "OSCILLATION CIRCUIT". 3 MB88152 HANDLING DEVICES Preventing Latchup A latchup can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS. The latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. The attention when the external clock is used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between VSS and VDD near the device, as a bypass capacitor. Oscillation Circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and resonator (or ceramic oscillator) do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground. 4 MB88152 BLOCK DIAGRAM VDD SEL Modulation rate setting Frequency setting FREQ/FREQ0 XENS/FREQ1 XOUT Modulation enable / frequency setting PLL block CKOUT Clock output Reference clock Rf = 1 M XIN VSS 1 - M Phase compare Reference clock 1 - N Charge pump V/I conversion IDAC ICO Modulation clock output Loop filter 1 - L Modulation logic MB88152 PLL block Modulation rate setting/ Modulation enable setting A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. 5 MB88152 PIN SETTING When changing the pin setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the modulation clock takes the maximum value of Lock-Up time in " ELECTRICAL CHARACTERISTICS * AC characteristics Lock-Up time". Modulation enable setting XENS Modulation L Modulation H No modulation MB88152-101, 102, 111, 112 Note : MB88152-100 and 110 do not have XENS pin. SEL modulation rate setting SEL L H Modulation rate Remarks 0.5% MB88152-110, 111, 112 Center spread - 1.0% MB88152-100, 101, 102 Down spread 1.5% MB88152-110, 111, 112 Center spread - 3.0% MB88152-100, 101, 102 Down spread Note : The modulation rate can be changed at the level of the terminal. Frequency setting FREQ Frequency L H 16.6 MHz to 40 MHz MB88152-101, 111 40 MHz to 80 MHz MB88152-102, 112 33 MHz to 67 MHz MB88152-101, 111 66 MHz to 134 MHz MB88152-102, 112 Note : MB88152-100 and 110 do not have FREQ pin. Frequency setting FREQ1 FREQ0 Frequency L L 16.6 MHz to 40 MHz L H 33 MHz to 67 MHz H L 40 MHz to 80 MHz H H 66 MHz to 134 MHz Note : MB88152-101, 111, 102 and 112 have neither FREQ0 pin nor FREQ1 pin. 6 MB88152-100, 110 MB88152 * Center spread Spectrum is spread (modulated) by centering on the input frequency. 3.0% modulation width Radiation level -1.5% +1.5% Frequency Input frequency Center spread example of 1.5% Modulation rate * Down spread Spectrum is spread (modulated) below the input frequency. 3.0% modulation width Radiation level -3.0% Frequency Input frequency Down spread example of - 3.0% Modulation rate 7 MB88152 ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max VDD - 0.5 + 4.0 V Input voltage* VI VSS - 0.5 VDD + 0.5 V Output voltage* VO VSS - 0.5 VDD + 0.5 V Storage temperature TST - 55 + 125 C Operation junction temperature TJ - 40 + 125 C Output current IO - 14 + 14 mA Overshoot VIOVER VDD + 1.0 (tOVER 50 ns) V Undershoot VIUNDER VSS - 1.0 (tUNDER 50 ns) V Power supply voltage* * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER 50 ns VIOVER VDD + 1.0 V VDD Input pin VSS tOVER 50 ns 8 VIUNDER VSS - 1.0 V MB88152 RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V) Parameter Symbol Pin Conditions Power supply voltage VDD VDD SEL FREQ/FREQ0, XENS/FREQ1 "H" level input voltage VIH XIN VIL XIN Input clock duty cycle tDCI XIN Operating temperature Ta Unit Min Typ Max 3.0 3.3 3.6 V VDD x 0.80 VDD + 0.3 V Input through rate 3 V / ns VDD x 0.80 16.6 MHz to 100 MHz VDD + 0.3 V Input through rate 3 V / ns 100 MHz to 134 MHz VDD x 0.90 VDD + 0.3 V VSS VDD x 0.20 V Input through rate 3 V / ns 16.6 MHz to 100 MHz VSS VDD + 0.20 V Input through rate 3 V / ns 100 MHz to 134 MHz VSS VDD + 0.10 V 16.6 MHz to 100 MHz 40 50 60 100 MHz to 134 MHz 45 50 55 -40 + 85 SEL FREQ/FREQ0, XENS/FREQ1 "L" level input voltage Value % C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb CKIN 1.5 V 9 MB88152 ELECTRICAL CHARACTERISTICS * DC Characteristics (Ta = -40 C to + 85 C, VDD = 3.3 V 0.3 V, VSS = 0.0 V) Parameter Power supply current Symbol Pin Conditions ICC VDD VOH CKOUT Output voltage VOL Output impedance Input capacitance Load capacitance 10 Value Unit Min Typ Max 24 MHz output No load capacitance 5.0 7.0 mA "H" level output IOH = - 4 mA VDD - 0.5 VDD V "L" level output IOL = 4 mA VSS 0.4 V ZO CKOUT 16.6 MHz to 134 MHz 45 CIN XIN, SEL, FREQ/ FREQ0, XENS/ FREQ1 Ta = + 25 C VDD = VI = 0.0 V f = 1 MHz 16 pF 16.6 MHz to 67 MHz 15 67 MHz to 100 MHz 10 100 MHz to 134 MHz 7 CL CKOUT pF MB88152 * AC Characteristics (Ta = -40 C to + 85 C, VDD = 3.3 V 0.3 V, VSS = 0.0 V) Parameter Oscillation frequency Input frequency Output frequency Symbol Pin Conditions fx XIN, XOUT fin fOUT XIN CKOUT Value Min Typ Max Fundamental oscillation 16.6 40 3rd over tone 40 48 MB88152-100, 110 16.6 134 MB88152-101, 111 16.6 67 MB88152-102, 112 40 134 MB88152-100, 110 16.6 134 MB88152-101, 111 16.6 67 MB88152-102, 112 40 134 Unit MHz MHz MHz Output slew rate SR CKOUT 0.4 V to 2.4 V Load capacitance 15 pF 0.4 4.0 V/ns Output clock duty cycle tDCC CKOUT 1.5 V 40 60 % Modulation cycle fMOD CKOUT 12.5 kHz tLK CKOUT 2 5 ms CKOUT No load capacitance, Ta = + 25 C, VDD = 3.3 V, Standard deviation 100 ps Lock-Up time Cycle-cycle jitter tJC 11 MB88152 OUTPUT CLOCK DUTY CYCLE (tDCC = tb/ta) ta tb 1.5 V CKOUT INPUT FREQUENCY (fin = 1/tin) tin 0.8 VDD CKIN OUTPUT SLEW RATE (SR) 2.4 V 0.4 V CKOUT tr tf Note : SR = (2.4-0.4) /tr, SR = (2.4-0.4) /tf CYCLE-CYCLE JITTER (tJC = | tn - tn + 1 |) CKOUT tn tn+1 Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) . 12 MB88152 MODULATION WAVEFORM * 1.5% modulation rate, Example of center spread CKOUT output frequency + 1.5 % Frequency at modulation OFF Time - 1.5 % fMOD = 12.5 kHz (Typ) * -1.0% modulation rate, Example of down spread CKOUT output frequency Frequency at modulation OFF Time - 0.5 % - 1.0 % fMOD = 12.5 kHz (Typ) 13 MB88152 LOCK-UP TIME VDD 3.0 V Internal clock stabilization wait time XIN Setting pin VIH SEL FREQ1/XENS FREQ0/FREQ tLK (lock-up time ) CKOUT If the setting pin is fixed at the "H" or "L" level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time "tLK"). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. XIN VIH XENS tLK (lock-up time ) VIL tLK (lock-up time ) CKOUT For modulation enable control using the XENS pin during normal operation, the set clock signal is output from CKOUT pin at most the lock-up time (tLK) after the level at the XENS pin is determined. Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cyclecycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. 14 MB88152 OSCILLATION CIRCUIT The left side of figures below shows the connection example about general resonator. The oscillation circuit has the built-in feedback resistance (1 M). The value of capacity (C1 and C2) is required adjusting to the most suitable value of an individual resonator. The right side of figures below shows the example of connecting for the 3rd over-tone resonator. The value of capacity (C1, C2 and C3) and inductance (L1) is needed adjusting to the most suitable value of an individual resonator. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most suitable value. When an external clock is used (the resonator is not used), input the clock to XIN pin and do not connect anything with XOUT pin. * When using the resonator Internal Rf (1 M) Rf (1 M) XIN Pin XOUT Pin XIN Pin XOUT Pin External L1 C1 C2 C2 C1 C3 Fundamental resonator 3rd over tone resonator * When using an external clock LSI Internal Rf (1 M) XIN Pin XOUT Pin LSI External External clock Note : OPEN Note that a jitter characteristic of an input clock may cause an affect a cycle-cycle jitter characteristic. 15 MB88152 INTERCONNECTION CIRCUIT EXAMPLE XENS/FREQ1 1 8 7 2 FREQ/FREQ0 MB88152 C2 C1 SEL C1, C2 C3 C4 R1 16 3 6 4 5 + C4 C3 R1 : Oscillation stabilization capacitance (see " OSCILLATION CIRCUIT".) : Capacitor of 10 F or higher : Capacitor about 0.01 F (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) : Impedance matching resistor for board pattern MB88152 EXAMPLE CHARACTERISTICS The condition of the examples of the characteristics is shown as follows : Input frequency = 20 MHz (Output frequency = 20 MHz : Use for MB88152-111) Power-supply voltage = 3.3 V, None load capacity, Modulation rate = 1.5% (center spread) . Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with, RBW = 1 kHz (ATT use for -6 dB) . CH B Spectrum 10 dB /REF 0 dBm No modulation -7.44 dBm Avg 4 1.5% modulation -25.75 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 20 MHZ ATT 6 dB SWP 2.505 s SPAN 4 MHZ 17 MB88152 ORDERING INFORMATION Part number 18 Input/Output Frequency Modulation type Modulation enable pin MB88152PNF-G-100-JNE1 16.6 MHz to 134 MHz Down spread No MB88152PNF-G-101-JNE1 16.6 MHz to 67 MHz Down spread Yes MB88152PNF-G-102-JNE1 40 MHz to 134 MHz Down spread Yes MB88152PNF-G-110-JNE1 16.6 MHz to 134 MHz Center spread No MB88152PNF-G-111-JNE1 16.6 MHz to 67 MHz Center spread Yes MB88152PNF-G-112-JNE1 40 MHz to 134 MHz Center spread Yes MB88152PNF-G-100-JN-EFE1 16.6 MHz to 134 MHz Down spread No MB88152PNF-G-101-JN-EFE1 16.6 MHz to 67 MHz Down spread Yes MB88152PNF-G-102-JN-EFE1 40 MHz to 134 MHz Down spread Yes MB88152PNF-G-110-JN-EFE1 16.6 MHz to 134 MHz Center spread No MB88152PNF-G-111-JN-EFE1 16.6 MHz to 67 MHz Center spread Yes MB88152PNF-G-112-JN-EFE1 40 MHz to 134 MHz Center spread Yes MB88152PNF-G-100-JN-ERE1 16.6 MHz to 134 MHz Down spread No MB88152PNF-G-101-JN-ERE1 16.6 MHz to 67 MHz Down spread Yes MB88152PNF-G-102-JN-ERE1 Down spread Yes MB88152PNF-G-110-JN-ERE1 16.6 MHz to 134 MHz Center spread No MB88152PNF-G-111-JN-ERE1 16.6 MHz to 67 MHz Center spread Yes MB88152PNF-G-112-JN-ERE1 Yes 40 MHz to 134 MHz 40 MHz to 134 MHz Center spread Package Remarks 8-pin plastic SOP (FPT-8P-M02) 8-pin plastic SOP (FPT-8P-M02) Embos taping (EF type) 8-pin plastic SOP (FPT-8P-M02) Embos taping (ER type) MB88152 PACKAGE DIMENSION Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 8-pin plastic SOP (FPT-8P-M02) +0.25 +.010 +0.03 *1 5.05 -0.20 .199 -.008 0.22 -0.07 +.001 .009 -.003 8 5 *2 3.900.30 6.000.40 (.154.012) (.236.016) Details of "A" part 45 1.550.20 (Mounting height) (.061.008) 0.25(.010) 0.40(.016) 1 "A" 4 1.27(.050) 0.440.08 (.017.003) 0.13(.005) 0~8 M 0.500.20 (.020.008) 0.600.15 (.024.006) 0.150.10 (.006.004) (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F08004S-c-4-7 Dimensions in mm (inches). Note : The values in parentheses are reference values. 19 MB88152 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. 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