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1
Rev. O
07/02/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
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IS63LV1024
IS63LV1024L
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
• High-speed access times:
8, 10, 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
•CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
– 32-pin STSOP (Type I)
– 36-pin BGA (8mmx10mm)
• Lead-free Available
DESCRIPTION
The ISSI IS63LV1024/IS63LV1024L is a very high-speed,
low power, 131,072-word by 8-bit CMOS static RAM in
revolutionary pinout. The IS63LV1024/IS63LV1024L is fab-
ricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low
power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024/IS63LV1024L operates from a single 3.3V
power supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
JULY 2010
2
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. O
07/02/2010
IS63LV1024
IS63LV1024L
PIN CONFIGURATION
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Data Inputs/Outputs
VDD Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32-Pin STSOP (Type I) (H)
PIN CONFIGURATION
36-mini BGA (B) (8 mm x 10 mm)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0 A1 NC A3 A6 A8
I/O4 A2 WE A4 A7 I/O0
I/O5 NC A5 I/O1
GND VDD
VDD GND
I/O6 NC NC I/O2
I/O7 OE CE A16 A15 I/O3
A9 A10 A11 A12 A13 A14
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Rev. O
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IS63LV1024
IS63LV1024L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to VDD + 0.5 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation VDD Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1 µA
Ind. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. –1 1 µA
Ind. –5 5
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width under Vss < 5ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width over VDD < 5ns). Not 100% tested.
OPERATING RANGE
Range Ambient Temperature VDD
Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C 3.3V ± 0.15V
4
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Rev. O
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IS63LV1024
IS63LV1024L
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
CI/O Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
IS63LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC1VDD Operating VDD = Max., CE = VIL Com. — 100 — 95 — 90 mA
Supply Current IOUT = 0 mA, f = Max. Ind. — 110 — 105 — 100
typ.
(2)
—75 —70 —65
ISB TTL Standby VDD = Max., Com. — 35 — 30 — 25 mA
Current VIN = VIH or VIL Ind. — 40 — 35 — 30
(TTL Inputs) CE ≥ VIH, f = Max
ISB1TTL Standby VDD = Max., Com. — 15 — 15 — 15 mA
Current VIN = VIH or VIL Ind. — 20 — 20 — 20
(TTL Inputs) CE ≥ VIH, f = 0
ISB2CMOS Standby VDD = Max., Com. — 1 — 1 — 1 mA
Current CE ≥ VDD – 0.2V, Ind. — 1.5 — 1.5 — 1.5
typ.
(2)
— 0.05 — 0.05 — 0.05
(CMOS Inputs) VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested.
IS63LV1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC1VDD Operating VDD = Max., CE = VIL Com. — 160 — 150 — 130 mA
Supply Current IOUT = 0 mA, f = Max. Ind. — 170 — 160 — 140
typ.
(2)
— 105 — 95 — 75
Ind. (@15 ns) — 90
ISB TTL Standby VDD = Max., Com. — 55 — 45 — 40 mA
Current VIN = VIH or VIL Ind. — 55 — 45 — 40
(TTL Inputs) CE ≥ VIH, f = Max
ISB1TTL Standby VDD = Max., Com. — 25 — 25 — 25 mA
Current VIN = VIH or VIL Ind. — 30 — 30 — 30
(TTL Inputs) CE ≥ VIH, f = 0
ISB2CMOS Standby VDD = Max., Com. — 5 — 5 — 5 mA
Current CE ≥ VDD – 0.2V, Ind. — 10 — 10 — 10
typ.
(2)
— 0.5 — 0.5 — 0.5
(CMOS Inputs) VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested.
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Rev. O
07/02/2010
IS63LV1024
IS63LV1024L
AC TEST LOADS
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — ns
tAA Address Access Time — 8 — 10 — 12 ns
tOHA Output Hold Time 2 — 2 — 2 — ns
tACE CE Access Time — 8 — 10 — 12 ns
tDOE OE Access Time — 4 — 5 — 6 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — ns
tHZOE
(2)
OE to High-Z Output 0 4 0 5 0 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — ns
tHZCE
(2)
CE to High-Z Output 0 4 0 5 0 6 ns
tPU CE to Power Up Time 0 — 0 — 0 — ns
tPD CE to Power Down Time — 8 — 10 — 12 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
loading specified in Figure 1.
2. Tested with the loading specified in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Figure 1
OUTPUT
VT = 1.5V
ZOUT = 50 Ω
50 Ω
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 2
6
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. O
07/02/2010
IS63LV1024
IS63LV1024L
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t AA
t OHA
t OHA
t RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
DOUT
t
HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
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IS63LV1024
IS63LV1024L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — ns
tSCE CE to Write End 7 — 7 — 8 — ns
tAW Address Setup Time to 8 — 8 — 8 — ns
Write End
tHA Address Hold from 0 — 0 — 0 — ns
Write End
tSA Address Setup Time 0 — 0 — 0 — ns
tPWE
1
(1)
WE Pulse Width (OE High) 7 — 7 — 8 — ns
tPWE
2
(2)
WE Pulse Width (OE Low) 8 — 10 — 12 — ns
tSD Data Setup to Write End 5 — 5 — 6 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 4 — 5 — 6 ns
tLZWE
(2)
WE HIGH to Low-Z Output 3 — 3 — 3 — ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
8
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. O
07/02/2010
IS63LV1024
IS63LV1024L
AC WAVEFORMS
WRITE CYCLE NO. 2(1)
(WE Controlled, = HIGH during Write Cycle)
(WE Controlled: OE is LOW During Write Cycle)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
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Rev. O
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IS63LV1024
IS63LV1024L
(CE Controlled)
Symbol Parameter Test Condition Options Min. Typ.
(1)
Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 2.0 — 3.6 V
IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V IS63LV1024 — 0.5 10 mA
IS63LV1024L — 0.05 1.5
tSDR Data Retention Setup Time See Data Retention Waveform 0 — — ns
tRDR Recovery Time See Data Retention Waveform tRC ——ns
Note 1: Typical values are measured at V
DD
= 3.0V, T
A
= 25
O
C and not 100% tested.
V
DD
CE ≥ VDD
- 0.2V
tSDR tRDR
VDR
CE
GND
Data Retention Mode
10
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. O
07/02/2010
IS63LV1024
IS63LV1024L
Speed (ns) Order Part No. Package
8 IS63LV1024-8K 400-mil Plastic SOJ
IS63LV1024-8KL 400-mil Plastic SOJ, Lead-free
10 IS63LV1024-10T TSOP (Type II)
IS63LV1024-10J 300-mil Plastic SOJ
IS63LV1024-10K 400-mil Plastic SOJ
12 IS63LV1024-12T TSOP (Type II)
IS63LV1024-12J 300-mil Plastic SOJ
IS63LV1024-12JL 300-mil Plastic SOJ, Lead-free
IS63LV1024-12KL 400-mil Plastic SOJ, Lead-free
Speed (ns) Order Part No. Package
8 IS63LV1024-8KI 400-mil Plastic SOJ
10 IS63LV1024-10KI 400-mil Plastic SOJ
12 IS63LV1024-12TI TSOP (Type II)
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Rev. O
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IS63LV1024
IS63LV1024L
Speed (ns) Order Part No. Package
8 IS63LV1024L-8T TSOP (Type II)
IS63LV1024L-8TL TSOP (Type II), Lead-free
IS63LV1024L-8B mBGA (8mmx10mm)
10 IS63LV1024L-10T TSOP (Type II)
IS63LV1024L-10TL TSOP (Type II), Lead-free
IS63LV1024L-10HL sTSOP (Type I) (8mm x13.4mm), Lead-free
12 IS63LV1024L-12T TSOP (Type II)
IS63LV1024L-12TL TSOP (Type II), Lead-free
IS63LV1024L-12H sTSOP (Type I) (8mm x13.4mm)
IS63LV1024L-12J 300-mil Plastic SOJ
IS63LV1024L-12JL 300-mil Plastic SOJ, Lead-free
IS63LV1024L-12B mBGA (8mmx10mm)
Speed (ns) Order Part No. Package
8 IS63LV1024L-8TI TSOP (Type II)
IS63LV1024L-8JI 300-mil Plastic SOJ
IS63LV1024L-8KI 400-mil Plastic SOJ
IS63LV1024L-8BI mBGA (8mmx10mm)
10 IS63LV1024L-10HI sTSOP (Type I) (8mm x13.4mm)
IS63LV1024L-10JLI 300-mil Plastic SOJ, Lead-free
IS63LV1024L-10KLI 400-mil Plastic SOJ, Lead-free
IS63LV1024L-10TLI TSOP (Type II), Lead-free
12 IS63LV1024L-12BI mBGA (8mmx10mm)
IS63LV1024L-12BLI mBGA (8mmx10mm), Lead-free
IS63LV1024L-12TI TSOP (Type II)
IS63LV1024L-12TLI TSOP (Type II), Lead-free
Speed (ns) Top Mark Order Part No. Package
8 IS63LV1024L-10KLI U788B-8KLI 400-mil Plastic SOJ, Lead-free
IS63LV1024L-10TLI U788A-8TLI TSOP (Type II), Lead-free
12
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07/02/2010
IS63LV1024
IS63LV1024L
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IS63LV1024
IS63LV1024L
NOTE :
2. Dimension D and E1 do not include mold protrusion .
4. Formed leads shall be planar with respect to one another within 0.1mm
3. Dimension b2 does not include dambar protrusion/intrusion.
at the seating plane after final test.
1. Controlling dimension : mm
5. Reference document : JEDEC SPEC MS-027.
SEATING PLANE
12/19/2007
14
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IS63LV1024
IS63LV1024L
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IS63LV1024
IS63LV1024L
16
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. O
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IS63LV1024
IS63LV1024L
NOTE :
2. Reference document : JEDEC MO-207
1. Controlling dimension : mm
Package Outline
08/12/2008
