FDP4D5N10C / FDPF4D5N10C N-Channel Shielded Gate PowerTrench® MOSFET
Semiconductor Components Industries, LLC, 2017 Publication Order Number:
June, 2017, Rev. 1.0 FDP4D5N10C / FDPF4D5N10C/D
1
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FDP4D5N10C / FDPF4D5N10C
N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 128 A, 4.5 mΩ
Features
Max rDS(on) = 4.5 mΩ at VGS = 10 V, ID = 100 A
Extremely Low Reverse Recovery Charge, Qrr
100% UIL Tested
RoHS Compliant
General Description
This N-Channel MV MOSFET is produced using ON
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized to minimize on-state resistance and yet maintain
superior switching performance with best in class soft body
diode.
Applications
Synchronous Rectification for ATX / Server / Telecom PSU
Motor Drives and Uninterruptible Power Supplies
Micro Solar Inverter
G
S
D
TO-220F
DS
G
DS
G
TO-220
MOSFET Maximum Ratings TC = 25 °C unless otherwise noted.
* Drain current limited by maximum junction temperature. Package limitation current is 120A.
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
FDP4D5N10C FDPF4D5N10C
VDS Drain to Source Voltage 100 100 V
VGS Gate to Source Voltage ±20 ±20 V
ID
Drain Current -Continuous TC = 25°C (Note 3) 128* 128*
A -Continuous TC = 100°C (Note 3) 91 91
-Pulsed (Note 1) 512 512
EAS Single Pulse Avalanche Energy (Note 2) 486 mJ
PD
Power Dissipation TC = 25°C 150 37.5 W
Power Dissipation TA = 25°C 2.4 2.4
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +175 -55 to +175 °C
Symbol Parameter FDP4D5N10C FDPF4D5N10C Units
RθJC Thermal Resistance, Junction to Case 1.0 4.0 °C/W
RθJA Thermal Resistance, Junction to Ambient 62.5 62.5
Device Marking Device Package Packing Mode Quantity
FDP4D5N10C FDP4D5N10C TO-220 Tube 50 units
FDPF4D5N10C FDPF4D5N10C TO-220F Tube 50 units
FDP4D5N10C / FDPF4D5N10C N-Channel Shielded Gate PowerTrench® MOSFET
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Electrical Characteristics TJ = 25 °C unless otherwise noted.
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristic
Symbol Parameter Test Conditions Min. Typ. Max. Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 53 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA
VDS = 80 V, TJ= 150°C 500 μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 310 μA 2.0 3.2 4.0 V
rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 100 A 4.0 4.5 mΩ
gFS Forward Transconductance VDS = 5 V, ID = 100 A 134 S
Ciss Input Capacitance VDS = 50 V, VGS = 0 V,
f = 1 MHz
3615 5065 pF
Coss Output Capacitance 2330 3265 pF
Crss Reverse Transfer Capacitance 18 35 pF
RgGate Resistance 0.1 1.1 2.2 Ω
td(on) Turn-On Delay Time
VDD = 50 V, ID = 100 A,
VGS = 10 V, RGEN = 6 Ω
29 47 ns
trRise Time 49 79 ns
td(off) Turn-Off Delay Time 41 66 ns
tfFall Time 13 24 ns
QgTotal Gate Charge VGS = 0 V to 10 V VDD = 50 V,
ID = 100 A
48 68 nC
Qgs Gate to Source Gate Charge 19 nC
Qgd Gate to Drain “Miller” Charge 9 nC
Qoss Output Charge VDD = 50 V, VGS = 0 V 150 nC
ISMaximum Continuous Drain to Source Diode Forward Current - - 128 A
ISM Maximum Pulsed Drain to Source Diode Forward Current - - 512 A
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 100 A 1.0 1.3 V
trr Reverse Recovery Time VGS = 0 V, VDD = 50 V ,
IF = 100 A, dIF/dt = 100 A/μs
82 132 ns
Qrr Reverse Recovery Charge 106 170 nC
trr Reverse Recovery Time VGS = 0 V, VDD = 50 V,
IF = 100 A, dIF/dt = 300 A/μs
71 114 ns
Qrr Reverse Recovery Charge 258 413 nC
Notes:
1. Pulsed Id please refer to Figure “Forward Bias Safe Operating Area” for more details.
2. EAS of 486 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 18 A, VDD = 100 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 58 A.
3. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
FDP4D5N10C / FDPF4D5N10C N-Channel Shielded Gate PowerTrench® MOSFET
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Typical Characteristics TJ = 25 °C unless otherwise noted.
Figure 1.
012345
0
60
120
180
240
300
VGS = 5.5 V
VGS = 10 V
VGS = 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 5 V
VGS = 7 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
0 60 120 180 240 300
0
1
2
3
4
5
VGS = 10 V
VGS = 5 V
VGS = 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 7 V
VGS = 5.5 V
N o r m a l i z e d O n - R e s i s t a n c e
vs. Drain Current and Gate Voltage
F i g u r e 3 . N o r m a l i z e d O n R e s i s t a n c e
-75 -50 -25 0 25 50 75 100 125 150 175
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
ID = 100 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
vs. Junction Temperature
Figure 4.
45678910
0
8
16
24
32
40
TJ = 150 oC
ID = 100 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
O n- R e s is ta nc e v s. Ga t e t o
Source Voltage
Figure 5. Transfer Characteristics
2345678910
0
60
120
180
240
300
TJ = 175 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.00.20.40.60.81.01.2
0.001
0.01
0.1
1
10
100
300
TJ = -55 oC
TJ = 25 oC
TJ = 175 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
S ou r c e to D r a in Di o de
Forward Voltage vs. Source Current
FDP4D5N10C / FDPF4D5N10C N-Channel Shielded Gate PowerTrench® MOSFET
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Figure 7.
0 1020304050
0
2
4
6
8
10
ID = 100 A
VDD = 75 V
VDD = 50 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 25 V
Gate Charge Characteristics Figure 8.
0.1 1 10 100
1
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
C a p a c i t a n c e v s . D r a i n
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100 1000
1
10
100
TJ = 125 oC
TJ = 25 oC
TJ = 150 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
U n c l a m p e d I n d u c t i v e
Switching Capability
Figure 10.
25 50 75 100 125 150 175
0
40
80
120
160
RθJC = 1.0 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
M a x i m u m C o n t i n u o u s D r a i n
Current vs. Case Temperature
Figure 1 1 . F o r w a r d B i as Safe
Operating Area
0.1 1 10 100 400
0.1
1
10
100
1000
CURVE BENT TO
MEASURED DATA
10 μs
100 ms
10 ms
1 ms
100 μs
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 1.0 oC/W
TC = 25 oC
for FDP4D5N10C
Figure 12.
0.1 1 10 100 400
0.1
1
10
100
1000
CURVE BENT TO
MEASURED DATA
10 μs
100 ms
10 ms
1 ms
100 μs
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 4.0 oC/W
TC = 25 oC
F or w ar d B ia s Sa fe
Operating Area for FDPF4D5N10C
Typical Characteristics TJ = 25 °C unless otherwise noted.
FDP4D5N10C / FDPF4D5N10C N-Channel Shielded Gate PowerTrench® MOSFET
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Figure 13.
10-5 10-4 10-3 10-2 10-1 100101102
102
10
100
1000
10000
100000
SINGLE PULSE
RθJC = 1.0 oC/W
TC = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
S i n g l e P u l s e M a x i m u m
Power Dissipation for FDP4D5N10C
Figure 14.
10-5 10-4 10-3 10-2 10-1 100101102
102
10
100
1000
10000
100000
SINGLE PULSE
RθJC = 4.0 oC/W
TC = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
S i n g l e P u l s e M ax i m u m
Power Dissipation for FDPF4D5N10C
Figure 15.
10-5 10-4 10-3 10-2 10-1 100101102
0.001
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 1.0 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJC(t) + TC
Junction-to-Case Transient Thermal Response Curve for FDP4D5N10C
Figure 16.
10-5 10-4 10-3 10-2 10-1 100101102
0.001
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 4.0 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJC(t) + TC
PDM
t1
t2
Junction-to-Case Transient Thermal Response Curve for FDPF4D5N10C
Typical Characteristics TJ = 25 °C unless otherwise noted.
FDP4D5N10C / FDPF4D5N10C N-Channel Shielded Gate PowerTrench® MOSFET
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Dimensional Outline and Pad Layout
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damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or
standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. ON
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FDP4D5N10C / FDPF4D5N10C N-Channel Shielded Gate PowerTrench® MOSFET
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Dimensional Outline and Pad Layout
ON Semiconductor and the ON Logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other
countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or
standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. ON
Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a
critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices
intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is
subject to all applicable copyright laws and is not for resale in any manner.
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