HEF4015BTD-T - NXP Semiconductors / Philips Semiconductors

1. General description

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel

converter). Each shift register has a serial data input (D), a clock input (CP), four fully

buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input

(MR). Information present on D is shifted to the ﬁrst register position, and all the data in

the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A

HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.

The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise

and fall times.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is

also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.

2. Features

nTolerant of slow clock rise and fall times

nFully static operation

n5 V, 10 V, and 15 V parametric ratings

nStandardized symmetrical output characteristics

nOperates across the automotive temperature range −40 °C to +85 °C.

nComplies with JEDEC standard JESD 13-B

3. Applications

nSerial-to-parallel converter

nBuffer stores

nGeneral purpose register

4. Ordering information

HEF4015B

Dual 4-bit static shift register

Rev. 06 — 3 November 2009 Product data sheet

Table 1. Ordering information

All types operate from

−

C to +85

Type number Package

Name Description Version

HEF4015BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4015BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 06 — 3 November 2009 2 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

5. Functional diagram

Fig 1. Functional diagram

Fig 2. Logic diagram for one register

001aae560

SHIFT

4 BITS

SHIFT

4 BITS

910

1CP

1Q0

1Q1

1Q2

1Q3

6 1MR

2D15

2CP

2Q0

2Q1

2Q2

2Q3

14 2MR

001aae562

FF 1

FF 2

FF 3

FF 4

Product data sheet Rev. 06 — 3 November 2009 3 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Dn = either HIGH or LOW;

↑ = positive-going transition; ↓ = negative-going transition.

Fig 3. Pin conﬁguration

HEF4015B

2CP VDD

2Q3 2D

1Q2 2MR

1Q1 2Q0

1Q0 2Q1

1MR 2Q2

1D 1Q3

VSS 1CP

001aae561

Table 2. Pin description

Symbol Pin Description

1Q0 to 1Q3 5, 4, 3, 10 parallel output

2Q0 to 2Q3; 13, 12, 11, 2 parallel output

1MR, 2MR 6, 14 master reset input (active HIGH)

1D, 2D 7, 15 serial data input

VSS 8 ground supply voltage

1CP, 2CP 9, 1 clock input (LOW-to-HIGH edge-triggered)

VDD 16 supply voltage

Table 3. Function table [1]

number of clock

pulse transitions Input Output

CP D MR Q0 Q1 Q2 Q3

1↑D1LD1XXX

2↑D2L D2D1X X

3↑D3L D3D2D1X

4↑D4L D4D3D2D1

↓X L no change no change no change no change

XXHLLLL

Product data sheet Rev. 06 — 3 November 2009 4 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

8. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

9. Recommended operating conditions

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping current VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +85 °C

Ptot total power dissipation Tamb = −40 °C to +85 °C

DIP16 package [1] - 750 mW

SO16 package [2] - 500 mW

P power dissipation per output - 100 mW

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air −40 - +85 °C

∆t/∆V input transition rise and fall rate VDD = 5 V - - 3.75 µs/V

VDD = 10 V - - 0.5 µs/V

VDD = 15 V - - 0.08 µs/V

Product data sheet Rev. 06 — 3 November 2009 5 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

10. Static characteristics

Table 6. Static characteristics

= 0 V; V

= V

or V

unless otherwise speciﬁed.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °C Unit

Min Max Min Max Min Max

VIH HIGH-level input voltage |IO| < 1 µA 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage |IO| < 1 µA 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage |IO| < 1 µA 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage |IO| < 1 µA 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V −1.7 - −1.4 - −1.1 - mA

VO = 4.6 V 5 V −0.52 - −0.44 - −0.36 - mA

VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA

VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - ±0.3 - ±0.3 - ±1.0 µA

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 µA

10 V - 40 - 40 - 300 µA

15 V - 80 - 80 - 600 µA

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 06 — 3 November 2009 6 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

11. Dynamic characteristics

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Table 7. Dynamic characteristics

= 0 V; C

= 50 pF; T

amb

= 25

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay nCP to Qn;

see Figure 4 5 V 103 ns + (0.55 ns/pF)CL- 130 260 ns

10 V 44 ns + (0.23 ns/pF)CL- 55 110 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

nMR to Qn;

see Figure 6 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 34 ns + (0.23 ns/pF)CL-4590ns

15 V 27 ns + (0.16 ns/pF)CL-3570ns

tPLH LOW to HIGH

propagation delay nCP to Qn

see Figure 4 5 V 93 ns + (0.55 ns/pF)CL- 120 240 ns

10 V 44 ns + (0.23 ns/pF)CL- 55 110 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

tttransition time see Figure 4 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

tsu set-up time nD to nCP;

see Figure 5 5 V +25 −15 - ns

10 V +25 −10 - ns

15 V +20 −5- ns

thhold time nD to nCP;

see Figure 5 5 V 40 20 - ns

10 V 20 10 - ns

15 V 15 8 - ns

tWpulse width nCP LOW;

minimum width;

see Figure 5

5 V 60 30 - ns

10 V 30 15 - ns

15 V 20 10 - ns

nMR HIGH;

minimum width;

see Figure 6

5 V 80 40 - ns

10 V 30 15 - ns

15 V 24 12 - ns

trec recovery time pin nMR;

see Figure 6 5 V 50 20 - ns

10 V 30 10 - ns

15 V 20 5 - ns

fmax maximum frequency see Figure 5 5 V 7 15 - MHz

10 V 15 30 - MHz

15 V 22 44 - MHz

Product data sheet Rev. 06 — 3 November 2009 7 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

12. Waveforms

Table 8. Dynamic power dissipation PD

can be calculated from the formulas shown. V

= 0 V; t

= t

≤

20 ns; T

amb

= 25

Symbol Parameter VDD Typical formula for PD (µW) where:

PDdynamic power

dissipation 5V P

D = 1500 × fi + Σ(fo× CL)× VDD2fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

Σ(CL× fo) = sum of the outputs.

10 V PD = 6300 × fi + Σ(fo× CL)× VDD2

15 V PD = 17000 × fi + Σ(fo× CL)× VDD2

Measurement points are given in Table 9.

Fig 4. Waveforms showing nCP propagation delays and nQn transition times

001aaj464

tPHL

tttt

nCP input

nQn output

VSS

VOH

VOL

90 %

10 %

tPLH

The shaded area indicates where the input is permitted to change for predictable output performance.

Set-up and hold times are shown as positive values but may be speciﬁed as negative values;

Measurement points are given in Table 9.

Fig 5. Waveforms showing set-up times, hold times, and minimum clock pulse width

nCP input

nD input

001aae563

VMVM

tsu tsu

1/fmax

VSS

Product data sheet Rev. 06 — 3 November 2009 8 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

Measurement points are given in Table 9.

Fig 6. Waveforms showing MR recovery time, propagation delay and minimum pulse width

tPHL

trec

001aae564

nMR input

nCP input

nQn output VM

VSS

VOH

VOL

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Product data sheet Rev. 06 — 3 November 2009 9 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

a. Input waveforms

b. Test circuit

Test data is given in Table 10.

Deﬁnitions for test circuit:

DUT = Device Under Test;

CL= load capacitance including jig and probe capacitance;

RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 7. Test circuit for measuring switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aaj781

VDD

VIVO

001aag182

DUT

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD ≤20 ns 50 pF

Product data sheet Rev. 06 — 3 November 2009 10 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

13. Package outline

Fig 8. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 06 — 3 November 2009 11 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

Fig 9. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 06 — 3 November 2009 12 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4015B_6 20091103 Product data sheet - HEF4015B_5

Modiﬁcations: •Section 9 “Recommended operating conditions”,∆t/∆V values updated.

HEF4015B_5 20090624 Product data sheet - HEF4015B_4

HEF4015B_4 20090127 Product data sheet - HEF4015B_CNV_3

HEF4015B_CNV_3 19950101 Product speciﬁcation - HEF4015B_CNV_2

HEF4015B_CNV_2 19950101 Product speciﬁcation - -

Product data sheet Rev. 06 — 3 November 2009 13 of 14

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors HEF4015B

Dual 4-bit static shift register

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 November 2009

Document identifier: HEF4015_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16 Contact information. . . . . . . . . . . . . . . . . . . . . 13

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14