CAT24C256YE-GT3 - ON Semiconductor L.L.C.

October, 2012 − Rev. 13

1Publication Order Number:

CAT24C256/D

CAT24C256

256 kb I2C CMOS Serial

EEPROM

Description

The CAT24C256 is a 256 kb Serial CMOS EEPROM, internally

organized as 32,768 words of 8 bits each.

It features a 64−byte page write buffer and supports the Standard

(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.

Write operations can be inhibited by taking the WP pin High (this

protects the entire memory).

External address pins make it possible to address up to eight

CAT24C256 devices on the same bus.

On−Chip ECC (Error Correction Code) makes the device suitable

for high reliability applications.*

Features

•Supports Standard, Fast and Fast−Plus I2C Protocol

•1.8 V to 5.5 V Supply Voltage Range

•64−Byte Page Write Buffer

•Hardware Write Protection for Entire Memory

•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs

(SCL and SDA)

•Low Power CMOS Technology

•1,000,000 Program/Erase Cycles

•100 Year Data Retention

•Industrial and Extended Temperature Range

•PDIP, SOIC, TSSOP, MSOP 8−Lead and

TDFN, UDFN 8−Pad Packages

•This Device is Pb−Free, Halogen Free/BFR Free, and RoHS

Compliant

Figure 1. Functional Symbol

SDA

SCL

CAT24C256

VCC

VSS

A2, A1, A0

* Available for New Product (Rev. E)

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PIN CONFIGURATION

SDA

VCC

VSS

A01

See detailed ordering and shipping information in the package

dimensions section on page 18 of this data sheet.

ORDERING INFORMATION

SOIC−8

W SUFFIX

CASE 751BD

SOIC−8

X SUFFIX

CASE 751BE

SCL

PDIP (L), SOIC (W, X), TSSOP (Y),

TDFN (ZD2)**, UDFN (HU4), MSOP (Z)

PDIP−8

L SUFFIX

CASE 646AA

TSSOP−8

Y SUFFIX

CASE 948AL

Device AddressA0, A1, A2

Serial DataSDA

Serial ClockSCL

Write ProtectWP

Power SupplyVCC

GroundVSS

FunctionPin Name†

PIN FUNCTION

For the location of Pin 1, please consult the

corresponding package drawing.

TDFN−8**

ZD2 SUFFIX

CASE 511AM

UDFN−8

HU4 SUFFIX

CASE 517AZ

** Not recommended for new designs

MSOP−8

Z SUFFIX

CASE 846AD

†The exposed pad for the TDFN/UDFN packages can

be left floating or connected to Ground.

CAT24C256

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Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Storage Temperature –65 to +150 °C

Voltage on any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may

undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units

NEND (Notes 3, 4) Endurance 1,000,000 Program/Erase Cycles

TDR Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, VCC = 5 V, 25°C.

4. The new product revision (E) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when

a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order

to benefit from the maximum number of write cycles.

Table 3. D.C. OPERATING CHARACTERISTICS − Mature Product (Rev D)

(VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, and VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C, unless otherwise speciﬁed.)

Symbol Parameter Test Conditions Min Max Units

ICCR Read Current Read, fSCL = 400 kHz 1 mA

ICC Write Current Write, fSCL = 400 kHz 3 mA

ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 1 mA

TA = −40°C to +125°C 2

ILI/O Pin Leakage Pin at GND or VCC TA = −40°C to +85°C 1 mA

TA = −40°C to +125°C 2

VIL Input Low Voltage −0.5 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 0.5 V

VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V

VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V

Table 4. PIN IMPEDANCE CHARACTERISTICS − Mature Product (Rev D)

(VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, and VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C, unless otherwise speciﬁed.)

Symbol Parameter Conditions Max Units

CIN (Note 5) SDA I/O Pin Capacitance VIN = 0 V 8 pF

CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF

IWP (Note 6) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA

VIN < VIH, VCC = 3.3 V 120

VIN < VIH, VCC = 1.8 V 80

VIN > VIH 1

5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;

therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as

the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. The

variable WP input impedance is available only for Die Rev. C and higher.

CAT24C256

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Table 5. D.C. OPERATING CHARACTERISTICS − New Product (Rev E) (Note 7)

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise speciﬁed.)

Symbol Parameter Test Conditions Min Max Units

ICCR Read Current Read, fSCL = 400 kHz/1 MHz 1 mA

ICCW Write Current 3 mA

ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 2 mA

TA = −40°C to +125°C 5

ILI/O Pin Leakage Pin at GND or VCC TA = −40°C to +85°C 1 mA

TA = −40°C to +125°C 2

VIL1 Input Low Voltage 2.5 V ≤ VCC ≤ 5.5 V −0.5 0.3 VCC V

VIL2 Input Low Voltage 1.8 V ≤ VCC < 2.5 V −0.5 0.25 VCC V

VIH1 Input High Voltage 2.5 V ≤ VCC ≤ 5.5 V 0.7 VCC VCC + 0.5 V

VIH2 Input High Voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 0.5 V

VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V

VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V

Table 6. PIN IMPEDANCE CHARACTERISTICS − New Product (Rev E) (Note 7)

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise speciﬁed.)

Symbol Parameter Conditions Max Units

CIN (Note 8) SDA I/O Pin Capacitance VIN = 0 V 8 pF

CIN (Note 8) Input Capacitance (other pins) VIN = 0 V 6 pF

IWP

, IA (Note 9) WP Input Current, Address Input

Current (A0, A1, A2)

VIN < VIH, VCC = 5.5 V 75 mA

VIN < VIH, VCC = 3.3 V 50

VIN < VIH, VCC = 1.8 V 25

VIN > VIH 2

7. The new product Rev E is identified by letter “E” or a dedicated marking code on top of the package.

8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

9. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively

strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,

as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.

CAT24C256

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Table 7. A.C. CHARACTERISTICS − Mature Product (Rev D) (Notes 10, 11)

(VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, and VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)

Symbol Parameter

Standard Fast

Fast−Plus

VCC = 2.5 V − 5.5 V

TA = −405C to +855C

Units

Min Max Min Max Min Max

FSCL Clock Frequency 100 400 1,000 kHz

tHD:STA START Condition Hold Time 4 0.6 0.25 ms

tLOW Low Period of SCL Clock 4.7 1.3 0.55 ms

tHIGH High Period of SCL Clock 4 0.6 0.25 ms

tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms

tHD:DAT Data In Hold Time 0 0 0 ms

tSU:DAT Data In Setup Time 250 100 50 ns

tR (Note 12) SDA and SCL Rise Time 1,000 300 100 ns

tF (Note 12) SDA and SCL Fall Time 300 300 100 ns

tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms

tBUF Bus Free Time Between

STOP and START

4.7 1.3 0.5 ms

tAA SCL Low to Data Out Valid 3.5 0.9 0.50 ms

tDH Data Out Hold Time 100 100 50 ns

Ti (Note 12) Noise Pulse Filtered at SCL

and SDA Inputs

100 100 100 ns

tSU:WP WP Setup Time 0 0 0 ms

tHD:WP WP Hold Time 2.5 2.5 1 ms

tWR Write Cycle Time 5 5 5 ms

tPU

(Notes 12, 13)

Power-up to Ready Mode 1 1 0.1 1 ms

10.The product Rev D is identified by letter “D” or a dedicated marking code on top of the package.

11. Test conditions according to “A.C. Test Conditions” table.

12.Tested initially and after a design or process change that affects this parameter.

13.tPU is the delay between the time VCC is stable and the device is ready to accept commands.

Table 8. A.C. TEST CONDITIONS

Input Levels 0.2 x VCC to 0.8 x VCC

Input Rise and Fall Times ≤ 50 ns

Input Reference Levels 0.3 x VCC, 0.7 x VCC

Output Reference Levels 0.5 x VCC

Output Load Current Source: IL = 3 mA (VCC ≥ 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF

CAT24C256

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Table 9. A.C. CHARACTERISTICS − New Product (Rev E) (Notes 14, 15)

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)

Symbol Parameter

Standard

VCC = 1.8 V − 5.5 V

Fast

VCC = 1.8 V − 5.5 V

Fast−Plus

VCC = 2.5 V − 5.5 V

TA = −405C to +855C

Units

Min Max Min Max Min Max

FSCL Clock Frequency 100 400 1,000 kHz

tHD:STA START Condition Hold Time 4 0.6 0.25 ms

tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms

tHIGH High Period of SCL Clock 4 0.6 0.40 ms

tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms

tHD:DAT Data In Hold Time 0 0 0 ms

tSU:DAT Data In Setup Time 250 100 50 ns

tR (Note 16) SDA and SCL Rise Time 1,000 300 100 ns

tF (Note 16) SDA and SCL Fall Time 300 300 100 ns

tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms

tBUF Bus Free Time Between

STOP and START

4.7 1.3 0.5 ms

tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms

tDH Data Out Hold Time 50 50 50 ns

Ti (Note 16) Noise Pulse Filtered at SCL

and SDA Inputs

50 50 50 ns

tSU:WP WP Setup Time 0 0 0 ms

tHD:WP WP Hold Time 2.5 2.5 1 ms

tWR Write Cycle Time 5 5 5 ms

tPU

(Notes 16, 17)

Power-up to Ready Mode 1 1 0.1 1 ms

14.Test conditions according to “A.C. Test Conditions” table.

15.The New product Rev E is identified by letter “E” or a dedicated marking code on top of the package.

16.Tested initially and after a design or process change that affects this parameter.

17.tPU is the delay between the time VCC is stable and the device is ready to accept commands.

CAT24C256

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Power-On Reset (POR)

The CAT24C256 Die Rev. C incorporates Power−On

Reset (POR) circuitry which protects the internal logic

against powering up in the wrong state.

The device will power up into Standby mode after VCC

exceeds the POR trigger level and will power down into

Reset mode when VCC drops below the POR trigger level.

This bi−directional POR behavior protects the device

against brown−out failure, following a temporary loss of

power.

Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock

signal generated by the Master.

SDA: The Serial Data I/O pin receives input data and

transmits data stored in EEPROM. In transmit mode, this pin

is open drain. Data is acquired on the positive edge, and is

delivered on the negative edge of SCL.

A0, A1 and A2: The Address pins accept the device address.

These pins have on−chip pull−down resistors.

WP: The Write Protect input pin inhibits all write

operations, when pulled HIGH. This pin has an on−chip

pull−down resistor.

Functional Description

The CAT24C256 supports the Inter−Integrated Circuit

(I2C) Bus data transmission protocol, which defines a device

that sends data to the bus as a transmitter and a device

receiving data as a receiver. Data flow is controlled by a

Master device, which generates the serial clock and all

START and STOP conditions. The CAT24C256 acts as a

Slave device. Master and Slave alternate as either

transmitter or receiver. Up to 8 devices may be connected to

the bus as determined by the device address inputs A0, A1,

and A2.

I2C Bus Protocol

The I2C bus consists of two ‘wires’, SCL and SDA. The

two wires are connected to the VCC supply via pull−up

resistors. Master and Slave devices connect to the 2−wire

bus via their respective SCL and SDA pins. The transmitting

device pulls down the SDA line to ‘transmit’ a ‘0’ and

releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable

while the SCL line is HIGH. An SDA transition while SCL

is HIGH will be interpreted as a START or STOP condition

(Figure 2).

START

The START condition precedes all commands. It consists

of a HIGH to LOW transition on SDA while SCL is HIGH.

The START acts as a ‘wake−up’ call to all receivers. Absent

a START, a Slave will not respond to commands.

STOP

The STOP condition completes all commands. It consists

of a LOW to HIGH transition on SDA while SCL is HIGH.

The STOP starts the internal Write cycle (when following a

Write command) or sends the Slave into standby mode

(when following a Read command).

Device Addressing

The Master initiates data transfer by creating a START

condition on the bus. The Master then broadcasts an 8−bit

serial Slave address. The first 4 bits of the Slave address are

set to 1010, for normal Read/Write operations (Figure 3).

The next 3 bits, A2, A1 and A0, select one of 8 possible Slave

devices. The last bit, R/W, specifies whether a Read (1) or

Write (0) operation is to be performed.

Acknowledge

After processing the Slave address, the Slave responds

with an acknowledge (ACK) by pulling down the SDA line

during the 9th clock cycle (Figure 4). The Slave will also

acknowledge the byte address and every data byte presented

in Write mode. In Read mode the Slave shifts out a data byte,

and then releases the SDA line during the 9th clock cycle. If

the Master acknowledges the data, then the Slave continues

transmitting. The Master terminates the session by not

acknowledging the last data byte (NoACK) and by sending

a STOP to the Slave. Bus timing is illustrated in Figure 5.

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START

CONDITION

STOP

CONDITION

SDA

SCL

Figure 2. Start/Stop Timing

Figure 3. Slave Address Bits

1010

DEVICE ADDRESS

A2A1A0R/W

Figure 4. Acknowledge Timing

189

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP (≥ tSU:DAT)

ACK DELAY (≤ tAA)

Figure 5. Bus Timing

SCL

SDA IN

SDA OUT

tBUF

tSU:STO

tSU:DAT

tAA tDH

tLOW

tHIGH

tLOW

tSU:STA

tHD:STA

tHD:DAT

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WRITE OPERATIONS

Byte Write

In Byte Write mode the Master sends a START, followed

by Slave address, two byte address and data to be written

(Figure 6). The Slave acknowledges all 4 bytes, and the

Master then follows up with a STOP, which in turn starts the

internal Write operation (Figure 7). During internal Write,

the Slave will not acknowledge any Read or Write request

from the Master.

Page Write

The CAT24C256 contains 32,768 bytes of data, arranged

in 512 pages of 64 bytes each. A two byte address word,

following the Slave address, points to the first byte to be

written. The most significant bit of the address word is ‘don’t

care’, the next 9 bits identify the page and the last 6 bits

identify the byte within the page. Up to 64 bytes can be

written in one Write cycle (Figure 8).

The internal byte address counter is automatically

incremented after each data byte is loaded. If the Master

transmits more than 64 data bytes, then earlier bytes will be

overwritten by later bytes in a ‘wrap−around’ fashion

(within the selected page). The internal Write cycle starts

immediately following the STOP.

Acknowledge Polling

Acknowledge polling can be used to determine if the

CAT24C256 is busy writing or is ready to accept commands.

Polling is implemented by interrogating the device with a

‘Selective Read’ command (see READ OPERATIONS).

The CAT24C256 will not acknowledge the Slave address,

as long as internal Write is in progress.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is

protected against Write operations. If the WP pin is left

floating or is grounded, it has no impact on the operation of

the CAT24C256. The state of the WP pin is strobed on the

last falling edge of SCL immediately preceding the first data

byte (Figure 9). If the WP pin is HIGH during the strobe

interval, the CAT24C256 will not acknowledge the data byte

and the Write request will be rejected.

Delivery State

The CAT24C256 is shipped erased, i.e., all bytes are FFh.

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SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BYTE ADDRESS DATA

Figure 6. Byte Write Timing

* = Don’t Care Bit

A15 − A8A7 − A0

Figure 7. Write Cycle Timing

STOP

CONDITION START

CONDITION ADDRESS

ACK8th Bit

Byte n

SCL

SDA

tWR

SLAVE

ADDRESS

BUS

ACTIVITY:

MASTER

SDA LINE

* = Don’t Care Bit

BYTE ADDRESS

DATA DATA n DATA n+63

Figure 8. Page Write Timing

A15 − A8A7 − A0

Figure 9. WP Timing

189

ADDRESS

BYTE

DATA

BYTE

SCL

SDA

tSU:WP

tHD:WP

a7a0d7d0

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READ OPERATIONS

Immediate Address Read

In standby mode, the CAT24C256 internal address

counter points to the data byte immediately following the

last byte accessed by a previous operation. If that ‘previous’

byte was the last byte in memory, then the address counter

will point to the 1st memory byte, etc.

When, following a START, the CAT24C256 is presented

with a Slave address containing a ‘1’ in the R/W bit position

(Figure 10), it will acknowledge (ACK) in the 9th clock cycle,

and will then transmit data being pointed at by the internal

address counter. The Master can stop further transmission by

issuing a NoACK, followed by a STOP condition.

Selective Read

The Read operation can also be started at an address

different from the one stored in the internal address counter.

The address counter can be initialized by performing a

‘dummy’ Write operation (Figure 11). Here the START is

followed by the Slave address (with the R/W bit set to ‘0’)

and the desired two byte address. Instead of following up

with data, the Master then issues a 2nd START, followed by

the ‘Immediate Address Read’ sequence, as described

earlier.

Sequential Read

If the Master acknowledges the 1st data byte transmitted

by the CAT24C256, then the device will continue

transmitting as long as each data byte is acknowledged by

the Master (Figure 12). If the end of memory is reached

during sequential Read, then the address counter will

‘wrap−around’ to the beginning of memory, etc. Sequential

Read works with either ‘Immediate Address Read’ or

‘Selective Read’, the only difference being the starting byte

address.

Figure 10. Immediate Address Read Timing

SCL

SDA 8th Bit

STOPNO ACKDATA OUT

SLAVE

ADDRESS

DATA N

BUS ACTIVITY:

MASTER

SDA LINE

Figure 11. Selective Read Timing

SLAVE

ADDRESS

SLAVE

BYTE ADDRESS

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE *

A15 − A8A7 − A0

* = Don’t Care Bit

Figure 12. Sequential Read Timing

SLAVE

ADDRESS

DATA n

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+1 DATA n+2

DATA n+x

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PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01

ISSUE A

TOP VIEW

SIDE VIEW END VIEW

PIN # 1

IDENTIFICATION

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

SYMBOL MIN NOM MAX

0.38

2.92

0.36

6.10

1.14

0.20

9.02

2.54 BSC

3.30

5.33

4.95

0.56

7.11

1.78

0.36

10.16

eB 7.87 10.92

E 7.62 8.25

2.92 3.80

3.30

0.46

6.35

1.52

0.25

9.27

7.87

CAT24C256

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

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PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL−01

ISSUE O

E1 E

TOP VIEW

SIDE VIEW END VIEW

L1 L

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.80

0.19

0.09

0.50

2.90

6.30

4.30

0.65 BSC

1.00 REF

1.20

0.15

1.05

0.30

0.20

0.75

3.10

6.50

4.50

0.90

0.60

3.00

6.40

4.40

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PACKAGE DIMENSIONS

TDFN8, 3x4.9

CASE 511AM−01

ISSUE A

PIN #1

IDENTIFICATION

PIN #1 IDENTIFICATION

DAP SIZE

2.6 x 3.3mm

DETAIL A

A3A1

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.25 0.30 0.35

D 2.90 3.00 3.10

D2 0.90 1.00 1.10

E 4.90

E2 0.90 1.00 1.10

4.80

0.65 TYP

5.00

L 0.50 0.60 0.70

TOP VIEW SIDE VIEW BOTTOM VIEW

FRONT VIEW

DETAIL A

A2 0.45 0.55 0.65

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PACKAGE DIMENSIONS

SOIC−8, 208 mils

CASE 751BE−01

ISSUE O

SIDE VIEW

TOP VIEW

PIN#1 IDENTIFICATION

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with EIAJ EDR-7320.

SYMBOL MIN NOM MAX

0º 8º

0.05

0.36

0.19

5.13

7.75

5.13

1.27 BSC

2.03

0.25

0.48

0.25

5.33

8.26

5.38

L0.51 0.76

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PACKAGE DIMENSIONS

UDFN8, 2x3 EXTENDED PAD

CASE 517AZ−01

ISSUE O

0.065 REF

Copper Exposed

PIN #1 INDEX AREA

PIN #1

IDENTIFICATION

DAP SIZE 1.8 x 1.8

DETAIL A

TOP VIEW SIDE VIEW

FRONT VIEW

DETAIL A

BOTTOM VIEW

0.065 REF

0.0 - 0.05A3

Notes:

(1) All dimensions are in millimeters.

(2) Refer JEDEC MO-236/MO-252.

SYMBOL MIN NOM MAX

A 0.45 0.50 0.55

A1 0.00 0.02 0.05

A3 0.127 REF

b 0.20 0.25 0.30

D 1.95 2.00 2.05

D2 1.35 1.40 1.45

E 3.00

E2 1.25 1.30 1.35

2.95

0.50 REF

3.05

L 0.25 0.30 0.35

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PACKAGE DIMENSIONS

MSOP 8, 3x3

CASE 846AD−01

ISSUE O

E1E

A1 e b

TOP VIEW

SIDE VIEW END VIEW

DETAIL A

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-187.

SYMBOL MIN NOM MAX

0º 6º

0.05

0.75

0.22

0.13

0.40

2.90

4.80

2.90

0.65 BSC

0.25 BSC

1.10

0.15

0.95

0.38

0.23

0.80

3.10

5.00

3.10

0.60

3.00

4.90

3.00

L1 0.95 REF

0.10

0.85

CAT24C256

http://onsemi.com

EXAMPLE OF ORDERING INFORMATION (Notes 18−22)

Device Order Number

Specific

Device

Marking*

Package

Type Temperature Range Lead Finish Shipping

CAT24C256LI−G 24256E PDIP−8I = Industrial

(−40°C to +85°C)

NiPdAu Tube, 50 Units / Tube

CAT24C256LE−G 24256E PDIP−8E = Extended

(−40°C to +125°C)

NiPdAu Tube, 50 Units / Tube

CAT24C256WI−GT3 24256E SOIC−8, JEDEC I = Industrial

(−40°C to +85°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C256WE−GT3 24256E SOIC−8, JEDEC E = Extended

(−40°C to +125°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C256XI−T2 24256E SOIC−8, EIAJ I = Industrial

(−40°C to +85°C)

Matte−Tin Tape & Reel,

2,000 Units / Reel

CAT24C256XE−T2 24256E SOIC−8, EIAJ E = Extended

(−40°C to +125°C)

Matte−Tin Tape & Reel,

2,000 Units / Reel

CAT24C256YI−GT3 C56E TSSOP−8I = Industrial

(−40°C to +85°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C256YE−GT3 C56E TSSOP−8E = Extended

(−40°C to +125°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C256ZD2IGT2

(Note 23, 24)

CCHN TDFN−8I = Industrial

(−40°C to +85°C)

NiPdAu Tape & Reel,

2,000 Units / Reel

CAT24C256HU4IGT3

(Note 24)

C8U UDFN−8I = Industrial

(−40°C to +85°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C256HU4EGT3

(Note 24)

C8U UDFN−8E = Extended

(−40°C to +125°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C256ZI−GT3 C8 MSOP−8I = Industrial

(−40°C to +85°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

CAT24C256ZE−GT3 C8 MSOP−8E = Extended

(−40°C to +125°C)

NiPdAu Tape & Reel,

3,000 Units / Reel

18.All packages are RoHS-compliant (Lead-free, Halogen-free).

19.The standard lead finish is NiPdAu.

20.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.

21.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

22.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com

23.Not recommended for new design.

24.There are NO hyphens in the orderable part numbers.

* Marking for New Product (Rev E)

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

CAT24C256/D

ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loca

Sales Representative