CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
ACPL-5160, ACPL-5161 and 5962-12236*
2.5 Amp Gate Drive Optocoupler with Integrated (VCE)
Desaturation Detection and Fault Status Feedback
Data Sheet
Description
This family of Avago 2.5 Amp Gate Drive Optocouplers
provides Integrated Desaturation (VCE) Detection and Fault
Status Feedback for IGBT VCE fault protection in a rugged,
hermetically-sealed package. The devices are capable of
operation and storage over the full military temperature
range and can be purchased as either commercial-grade
products or in fully MIL-STD compliant versions. The
military standard devices are manufactured and tested
on a MIL-PRF-38534 certied line to Class H specications;
Standard Microcircuit Drawing (SMD) 5962-12236. They
are included in the Defense Logistics Agency (DLA) Land
and Maritime Qualied Manufacturers List, QML-38534
for Hybrid Microcircuits.
Features
• 2.5 A maximum peak output current
• Drive IGBTs up to IC = 150 A, VCE = 1200 V
• Optically isolated, FAULT status feedback
• Hermetically sealed ceramic package
• CMOS/TTL compatible
• 500 ns max. switching speeds
• “Soft” IGBT turn-o
• Integrated fail-safe IGBT protection
– Desat (VCE) detection
– Under Voltage Lock-Out protection (UVLO) with
hysteresis
• User congurable: inverting, noninverting, auto-reset,
auto-shutdown
• Wide operating VCC range: 15 V to 30 V
• –55 °C to +125 °C operating temperature range
• 15 kV/µs Typical Common Mode Rejection (CMR) at
VCM = 1000 V
Fault Protected IGBT Gate Drive
MICROCONTROLLER
M
–HV
+HV
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ACPL - 516x
ISOLATION
BOUNDARY
3-PHASE
INPUT
FAULT
ACPL - 516x ACPL - 516x ACPL - 516x
ACPL - 516x
ACPL - 516x
ACPL - 516x
* SMD pending
2
Desat Condition Pin 6
UVLO Detected on (FAULT)
VIN+ VIN- (VCC2 - VE) Pin 14 Output VOUT
X X Active X X Low
X X X Yes Low Low
Low X X X X Low
X High X X X Low
High Low Not Active No High High
Typical Fault Protected IGBT Gate Drive Circuit
The ACPL-516x is an easy-to-use, intelligent gate driver
which makes IGBT VCE fault protection compact, aord-
able, and easy-to-implement. Features such as user con-
gurable inputs, integrated VCE detection, under volt-
Figure 1. Typical desaturation protected gate drive circuit, noninverting
Output Control
The outputs (VOUT and FAULT) of the ACPL-516x are con-
trolled by the combination of VIN, UVLO and a detected
IGBT Desat condition. As indicated in the below table, the
ACPL-516x can be congured as inverting or non-invert-
ing using the VIN+ or VIN- inputs respectively. When an in-
verting conguration is desired, VIN+ must be held high
and VIN- toggled. When a non-inverting conguration is
desired, VIN- must be held low and VIN+ toggled. Once
UVLO is not active (VCC2 - VE > VUVLO), VOUT is allowed to
go high, and the DESAT (pin 14) detection feature of the
ACPL-516x will be the primary source of IGBT protection.
UVLO is needed to ensure DESAT is functional. Once VU-
VLO+ > 11.6 V, DESAT will remain functional until VUVLO- <
12.4 V. Thus, the DESAT detection and UVLO features of
the ACPL-516x work in conjunction to ensure constant
IGBT protection.
* THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED.
Description of Operation during Fault Condition
1. DESAT terminal monitors the IGBT VCE voltage through
DDESAT.
2. When the voltage on the DESAT terminal exceeds 7 V,
the IGBT gate voltage (VOUT) is slowly lowered.
3. FAULT output goes low, notifying the microcontroller
of the fault condition.
4. Microcontroller takes appropriate action.
age lockout (UVLO), “soft” IGBT turn-o and isolated fault
feed back provide maximum design exibility and circuit
protection.
+
–
+
–
*
*
*
CBLANK
DDESAT
RPULL-DOWN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
ACPL-516x
+
–
µC
RF
VF
+ –
RGVCE
VCE
+
–
+
–
100 Ω
3
Product Overview Description
The ACPL-516x is a highly integrated power control de-
vice that incorporates all the necessary components for
a complete, isolated IGBT gate drive circuit with fault
protection and feedback into one rugged, hermetically
sealed package. TTL input logic levels allow direct in-
terface with a microcontroller, and an optically isolated
power output stage drives IGBTs with power ratings of
up to 150 A and 1200 V. A high speed internal optical link
minimizes the propagation delays between the micro-
controller and the IGBT while allowing the two systems
to operate at very large common mode voltage dier-
ences that are common in industrial motor drives and
other power switching applications. An output IC pro-
vides local protection for the IGBT to prevent damage
during overcurrents, and a second optical link provides
a fully isolated fault status feedback signal for the mi-
crocontroller. A built in “watchdog” circuit monitors the
power stage supply voltage to prevent IGBT damage
caused by insucient gate drive voltages. This integrat-
ed IGBT gate driver is designed to increase the perfor-
mance and reliability of a motor drive without the cost,
size, and complexity of a discrete design.
Two light emitting diodes and two integrated circuits
housed in the same 16-pin ceramic package provide the
input control circuitry, the output power stage, and two
optical channels. The input Buer IC is designed on a bi-
polar process, while the output Detector IC is manufac-
tured on a high voltage BiCMOS/Power DMOS process.
The forward optical signal path, as indicated by LED1,
transmits the gate control signal. The return optical sig-
nal path, as indicated by LED2, transmits the fault status
feedback signal. Both optical channels are completely
controlled by the input and output ICs respectively,
making the internal isolation boundary transparent to
the microcontroller.
Under normal operation, the input gate control signal di-
rectly controls the IGBT gate through the isolated output
detector IC. LED2 remains o and a fault latch in the in-
put buer IC is disabled. When an IGBT fault is detected,
the output detector IC immediately begins a “soft” shut-
down sequence, reducing the IGBT current to zero in a
controlled manner to avoid potential IGBT damage from
inductive overvoltages. Simultaneously, this fault status
is transmitted back to the input buer IC via LED2, where
the fault latch disables the gate control input and the ac-
tive low fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insucient gate volt-
age to the IGBT, by forcing the ACPL-516x’s output low.
Once the output is in the high state, the DESAT (VCE)
detection feature of the ACPL-516x provides IGBT pro-
tection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
SHIELD
HCPL-316J functional diagram
DESAT
FAULT
UVLO
OUTPUT IC
SHIELD
INPUT IC
RESET 5
FAULT 6
V
IN+
1
V
IN-
2
V
CC1
3
V
CC2
13
12
V
OUT
11
V
EE
9,10
V
E
16
DESAT
14
V
C
V
LED2+
GND1
154
V
LED1-
7 8
V
LED1+
LED2
LED1 D
R
I
V
E
R
4
Package Pin Out
HCPL-316J Pkg Pinout
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
E
V
LED2+
DESAT
V
CC2
V
C
V
OUT
V
EE
V
EE
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
Pin Descriptions
Symbol Description Symbol Description
VIN+ Noninverting gate drive voltage output (VOUT) VE Common (IGBT emitter) output supply voltage.
control input.
VIN- Inverting gate drive voltage output VLED2+ LED 2 anode. This pin must be left unconnected
(VOUT) control input. for guaranteed data sheet performance. (For
optical coupling testing only.)
VCC1 Positive input supply voltage. (4.5 V to 5.5 V) DESAT Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference
voltage of 7 V while the IGBT is on, FAULT
output is changed from a high impedance
state to a logic low state within 5 µs. See
Note 25.
GND1 Input Ground. VCC2 Positive output supply voltage.
RESET FAULT reset input. A logic low input for at least VC Collector of output pull-up triple-darlington
0.1 µs, asynchronously resets FAULT output high transistor. It is connected to VCC2 directly or
and enables VIN. Synchronous control of RESET through a resistor to limit output turn-on
relative to VIN is required. RESET is not aected current.
by UVLO. Asserting RESET while VOUT is high does
not aect VOUT.
FAULT Fault output. FAULT changes from a high VOUT Gate drive voltage output.
impedance state to a logic low output within
5 µs of the voltage on the DESAT pin exceeding
an internal reference voltage of 7 V. FAULT
output remains low until RESET is brought low.
FAULT output is an open collector which allows
the FAULT outputs from all ACPL-516x in a
circuit to be connected together in a “wired OR”
forming a single fault bus for interfacing directly
to the microcontroller.
VLED1+ LED 1 anode. This pin must be left unconnected VEE Output supply voltage.
for guaranteed data sheet performance. (For
optical coupling testing only.)
VLED1- LED 1 cathode. This pin must be connected to
ground.
5
Outline Drawings
Note: Dimensions in millimeters (inches)
Selection Guide: Lead Conguration Options
Avago Technologies Part Number and Options
Commercial Grade ACPL-5160
MIL-PRF-38534, Class H ACPL-5161
Standard Lead Finish Gold Plate
Solder Dipped* Option -200
Gull Wing/Soldered* Option -300
SMD Part Number
Gold Plate 5962-1223601HEC
Solder Dipped* 5962-1223601HEA
Gull Wing/Soldered* 5962-1223601HXA
*Solder contains lead
Device Marking
Note 1. Qualied parts only
0.20 (0.008)
4.45 (0.175)
20.06 (0.790)
0.51 (0.020)
2.29 (0.090)
0.51 (0.020)
0.89 (0.035)
8.13 (0.320)
7.36 (0.290)
3.81 (0.150)
20.83 (0.820)
1.65 (0.065)
MAX.
MAX.
MAX.
MIN.
2.79 (0.110)
MIN. 0.33 (0.013)
7.87 (0.310)
COMPLIANCE INDICATOR, [1]
DATE CODE, SUFFIX (IF NEEDED)
A QYYWWZ
COUNTRY OF MFR.
Avago CAGE CODE [1]
Avago LOGO
DLA SMD [1]
PIN ONE/
ESD IDENT
Avago P/N
DLA SMD [1]
XXXXXXXXXX
XXXXXXXXXX
XXXXX XXX
A 50434
6
Hermetic Optocoupler Options
Option Description
200 Lead nish is solder dipped rather than gold plated. This option is available on standard commercial. DLA
Drawing part numbers contain provisions for lead nish.
300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is avail-
able on standard commercial. This option has solder dipped leads.
Solder contains lead.
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.51 (0.020)
MIN.
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
5° MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013) 1.07 (0.042)
1.32 (0.052)
Note: Dimensions in millimeters (inches)
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature Ts -65 150 °C
Operating Temperature TA -55 125
Output IC Junction Temperature TJ 150 1
Peak Output Current |Io(peak)| 2.5 A 2
Fault Output Current IFAULT 8.0 mA
Positive Input Supply Voltage VCC1 -0.5 5.5 V
Input Pin Voltages VIN+, VIN- and VRESET -0.5 VCC1
Total Output Supply Voltage (VCC2 - VEE) -0.5 35
Negative Output Supply Voltage (VE - VEE) -0.5 15 3
Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE)
Gate Drive Output Voltage Vo(peak) -0.5 VCC2
Collector Voltage VC VEE + 5 V VCC2
DESAT Voltage VDESAT VE VE + 10
Output IC Power Dissipation PO 600 mW 1
Input IC Power Dissipation PI 150
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Operating Temperature TA -55 +125 °C
Input Supply Voltage VCC1 4.5 5.5 V 25
Total Output Supply Voltage (VCC2 - VEE) 15 30 6
Negative Output Supply Voltage (VE - VEE) 0 15 3
Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE)
Collector Voltage VC VEE + 6 VCC2
7
Electrical Specications (DC)
Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Logic Low Input Voltages VIN+L, VIN-L, 0.8 V
VRESETL
Logic High Input Voltages VIN+H, VIN-H, 2.0
VRESETH
Logic Low Input Currents IIN+L, IIN-L, -0.5 -0.36 mA VIN = 0.4 V
IRESETL
FAULT Logic Low Output IFAULTL 5.0 12 VFAULT = 0.4 V 30
Current
FAULT Logic High Output IFAULTH -40 µA VFAULT = VCC1 31
Current
High Level Output Current IOH -0.5 -1.5 A VOUT = VCC2 - 4 V 3, 8, 4
-2.0 VOUT = VCC2 - 15 V 32 2
Low Level Output Current IOL 0.5 2.0 VOUT = VEE + 2.5 V 4, 9, 4
2.0 VOUT = VEE + 15 V 33 2
Low Level Output Current IOLF 90 150 230 mA VOUT - VEE = 14 V 5, 34 5
During Fault Condition
High Level Output Voltage VOH VC - 3.5 VC - 2.5 VC - 1.5 V IOUT = -100 mA 6, 8, 6, 7, 8
VC -2.9 VC - 2.0 VC - 1.2 IOUT = -650 µA 35
VC IOUT = 0
Low Level Output Voltage VOL 0.12 0.5 IOUT = 100 mA 7, 9, 23
36
High Level Input Supply ICC1H 18 22 mA VIN+ = VCC1 = 5.5 V, 10, 37
Current VIN- = 0 V 38
Low Level Input Supply ICCIL 6.5 11 VIN+ = VIN- = 0 V,
Current VCC1 = 5.5 V
Output Supply Current ICC2 2.8 5 VOUT open 11, 12, 8
39, 40
Low Level Collector Current ICL 0.3 1.0 IOUT = 0 15, 59 24
High Level Collector Current ICH 0.3 1.3 IOUT = 0 15, 58 24
1.2 3.0 IOUT = -650 µA 15, 57
VE Low Level Supply IEL -0.7 -0.43 0 14, 61
Current
VE High Level Supply IEH -0.5 -0.16 0 14, 40 22
Current
Blanking Capacitor ICHG -0.13 -0.26 -0.33 VDESAT = 0 - 6 V 13, 41 8, 9
Charging Current -0.18 -0.26 -0.33 VDESAT = 0 - 6 V,
TA = 25°C - 125 °C
Blanking Capacitor IDSCHG 10 37 VDESAT = 7 V 42
Discharge Current
UVLO Threshold VUVLO+ 11.6 12.4 13.5 V VOUT > 5 V 43 6, 8, 10
VUVLO- 11.2 12.4 VOUT < 5 V 6, 8, 11
UVLO Hysteresis (VUVLO+ - 0.4 1.2
VUVLO-)
DESAT Threshold VDESAT 6.5 7.0 7.5 VCC2 - VE > VUVLO- 16, 44 8
8
Switching Specications (AC)
Unless otherwise noted, all typical values at TA = 25 °C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
VIN to High Level Output tPLH 0.10 0.28 0.50 µs Rg = 10 Ω 17,18,19, 12
152Propagation Delay Time Cg = 10 nF, 20,21,22,
VIN to Low Level Output tPHL 0.10 0.29 0.50 f = 10 kHz, 45,54,55
Propagation Delay Time Duty Cycle = 50%
Pulse Width Distortion PWD -0.30 0.01 0.30 13, 14
Propagation Delay Dierence (tPHL - tPLH) -0.35 0.35 14, 15
Between Any Two Parts PDD
10% to 90% Rise Time tr 0.1 45
90% to 10% Fall Time tf 0.1
DESAT Sense to 90% VOUT Delay tDESAT(90%) 0.18 0.5 Rg = 10 Ω, 23,56 16
Cg = 10 nF
DESAT Sense to 10% VOUT Delay tDESAT(10%) 1.9 3.0 VCC2 - VEE = 30 V 24,28,
46,56
DESAT Sense to Low Level FAULT tDESAT(FAULT) 1.5 5 25,47, 17
Signal Delay 56
DESAT Sense to DESAT Low tDESAT(LOW) 0.25 56 18
Propagation Delay
RESET to High Level FAULT Signal tRESET(FAULT) 3 6.5 20 26,27, 19
Delay 56
RESET Signal Pulse Width PWRESET 0.1
UVLO to VOUT High Delay tUVLO ON 4.0 VCC2 = 1.0 ms 49 10
UVLO to VOUT Low Delay tUVLO OFF 6.0 ramp 11
Output High Level Common Mode |CMH| 9 15 kV/µs TA = 25 °C, 50,51, 20
Transient Immunity VCM = 1000 V, 52,53
VCC2 = 30 V
Output Low Level Common Mode |CML| 9 15 TA = 25 °C, 21
Transient Immunity VCM = 1000 V,
VCC2 = 30 V
Package Characteristics
Over recommended operating conditions (TA = –55 to +125 °C) unless otherwise specied.
Parameter Symbol Test Conditions Group A
Subgroups
Limits Units Fig Note
Min. Typ.* Max.
Input-Output
Leakage Current
II-O VI-O = 1500 Vdc, RH ≤ 65%,
t = 5 sec., TA = 25 °C
1 1.0 μA 26, 27
Resistance
(Input-Output)
RI-O VI-O = 500 VDC 1012 Ω27
Capacitance
(Input-Output)
CI-O f = 1 MHz 2.8 pF 27
*All typicals at TA = 25 °C.
9
Notes:
1. To achieve the absolute maximum power dissipation specied, pins 4, 9 and 10 require ground plane connections and may require airow.
For details on how to estimate junction temperature and power dissipation, see the Thermal Model section in the application notes at the
end of this data sheet . The actual power dissipation achievable will depend on the application environment (PCB layout, air ow, part place-
ment, and so on). No power derating is required when operating below 125 °C using a high conductivity board. If a low conductivity board is
used, then output IC power dissipation is derated linearly at 20 mW/°C above 120 °C. Input IC power dissipation is derated linearly at 5 mW/°C
above 120°C.
2. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO
peak minimum = 2.0 A. For additional details on IOH peak, see the Applications section . Derate linearly from 3.0 A at +25 °C to 2.5 A at +125
°C. This compensates for increased IOPEAK due to changes in VOL over temperature.
3. This supply is optional. Required only when negative gate drive is implemented.
4. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%.
5. For further details, see the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet.
6. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VU-
VLO+ threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a DC load current. When driving capacitive loads, VOH
will approach VCC as IOH approaches zero units.
7. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
8. Once VOUT of the ACPL-516x is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-516x will be the primary
source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- <
12.4 V. Therefore, the DESAT detection and UVLO features of the ACPL-516x work in conjunction to ensure constant IGBT protection.
9. For further details, see the Blanking Time Control section in the applications notes at the end of this data sheet.
10. This is the ‘increasing’ (that is, turn-on or ‘positive going’ direction) of VCC2 - VE.
11. This is the ‘decreasing’ (that is, turn-o or ‘negative going’ direction) of VCC2 - VE.
12. This load condition approximates the gate load of a 1200 V/75 A IGBT.
13. Pulse Width Distortion (PWD) is dened as |tPHL - tPLH| for any given unit.
14. As measured from VIN+, VIN- to VOUT.
15. The dierence between tPHL and tPLH between any two ACPL-516x parts under the same test conditions.
16. Supply Voltage Dependent.
17. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
18. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low.
19. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specication of 3 μs is the guaran-
teed minimum FAULT signal pulse width when the ACPL-516x is congured for Auto-Reset. For further details, see the Auto-Reset section in
the applications notes at the end of this data sheet.
20. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3 kΩ pull-up resistor is needed in fault detection mode.
21. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (that is, VO < 1.0 V or FAULT < 0.8 V).
22. Does not include LED2 current during fault or blanking capacitor discharge current.
23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650
μA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-
down resistor is not used.
24. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE.
25. In most applications VCC1 will be powered up rst (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control
of the IGBT gate. In applications where VCC2 is powered up rst, it is important to ensure that Vin+ remains low until VCC1 reaches the proper
operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
26. This is a momentary withstand test, not an operating condition.
27. Device considered a two-terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
10
Figure 3. IOH vs. temperature
Figure 5. IOLF vs. temperature Figure 6. VOH vs. temperature
Figure 7. VOL vs. temperature Figure 8. VOH vs. IOH
Figure 4. IOL vs. temperature
1.0
1.2
1.4
1.6
1.8
2.0
- 55 - 25 5 35 65 95 125
IOH- OUTPUT HIGH CURRENT -A
0
1
2
3
4
5
6
7
-55 - 25 5 35 65 95 125
IOL - OUTPUT LOW CURRENT - A
VOUT = VEE +15 V
VOUT = VEE + 2.5 V
0
25
50
75
100
125
150
175
200
0 5 10 15 20 25 30
IOLF
- LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITION - mA
VOUT -OUTPUT VOLTAGE -V
- 4
- 3
- 2
- 1
0
-55 - 25 5 35 65 95 125
(VOH-V
CC) - HIGH OUTPUT VOLTAGE DROP
-V
0.00
0.05
0.10
0.15
0.20
0.25
- 55 - 25 5 35 65 95 125
VOL-OUTPUT LOW VOLTAGE - V
IOUT = 100 mA
26.4
26.8
27.2
27.6
28.0
28.4
28.8
29.2
0.0 0.2 0.4 0.6 0.8 1.0
IOH - OUTPUT HIGH CURRENT - A
VOH - OUTPUT HIGH VOLTAGE -V
T
A
- TEMPERATURE - oC
T
A
- TEMPERATURE - oC
T
A
- TEMPERATURE - oC
T
A
- TEMPERATURE - oC
–55 oC
25 oC
125 oC
–55 oC
25 oC
125 oC
IOUT = -650 µA
IOUT = -100 mA
Performance Plots
11
0
1
2
3
4
5
0.0 0.5 1.0 1.5 2.0 2.5
VOL - OUTPUT LOW VOLTAGE - V
IOL - OUTPUT LOW CURRENT - A
0
5
10
15
20
- 55 -25 5 35 65 95 125
ICC1 -SUPPLY CURRENT - mA
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
- 55 - 25 5 35 65 95 125 2.65
2.70
2.75
2.80
2.85
15 20 25 30
VCC2 -OUTPUT SUPPLY VOLTAGE -V
-0.30
-0.25
-0.20
-0.15
-55 -25 5 35 65
ICHG-BLANKING CAPACITOR CHARGING
CURRENT -mA
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-55 -25 5 35 65 95 125
IE-VESUPPLY CURRENT - mA ICC2 -SUPPLY CURRENT - mA
ICC2 -SUPPLY CURRENT - mA
TA - TEMPERATURE - oC
TA - TEMPERATURE - oC
TA - TEMPERATURE - oCTA - TEMPERATURE - oC
95 125
–55 oC
25 oC
125 oCICC1L
ICC1H
ICC2L
ICC2H
ICC2L
ICC2H
IeL
IeH
Figure 13. ICHG vs. temperature Figure 14. IE vs. temperature
Figure 12. ICC2 vs. VCC2
Figure 9: VOL vs. IOL Figure 10. ICC1 vs. temperature
Figure 11: ICC2 vs. t emperature
12
Figure 15. IC vs. IOUT Figure 16. DESAT threshold vs. temperature
Figure 17. Propagation delay vs. temperature Figure 18. Propagation delay vs. supply voltage
Figure 19. VIN to high propagation delay vs. temperature (TPLH)Figure 20. VIN to low propagation delay vs. temperature (TPHL)
0
1
2
3
4
0.5 1.0 1.5 2.0
IC- mA
IOUT - mA
6.0
6.5
7.0
7.5
-55 -25 5 35 65 95 125
VDESAT -
DESAT THRESHOLD V
0.20
0.25
0.30
0.35
0.40
0.45
0.50
- 55 - 25 5 35 65 95 125
PROPAGATION DELAY - µs
0.20
0.25
0.30
0.35
0.40
15 20 25 30
VCC - SUPPLY VOLTAGE - V
0.20
0.25
0.30
0.35
0.40
0.45
-55 -25 5 35 65 95 125 0.2
0.25
0.3
0.35
0.4
0.45
-55 -25 5 35 65 95 125
PROPAGATION DELAY - µs
PROPAGATION DELAY - µs
PROPAGATION DELAY - µs
T
A
- TEMPERATURE - oC
TA - TEMPERATURE - oC
TA - TEMPERATURE - oCTA - TEMPERATURE - oC
Tplh
Tphl
Tplh
Tphl
–55 oC
25 oC
125 oC
Vcc1 = 5.5 V
Vcc1 = 5.0 V
Vcc1 = 4.5 V
Vcc1 = 5.5 V
Vcc1 = 5.0 V
Vcc1 = 4.5 V
13
0.20
0.25
0.30
0.35
0.40
0 20 40 60 80 100
DELAY - µs
LOAD CAPACITANCE - nF
Tplh
Tphl
0.20
0.25
0.30
0.35
0.40
0 10 20 30 40 50
DELAY - µs
LOAD RESISTANCE - OHM
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
-55 -25 5 35 65 95 125
DELAY - µs
1.0
1.5
2.0
2.5
3.0
- 55 - 25 5 35 65 95 125
DELAY - µs
Vcc2=30 V
Vcc2=15 V
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
- 55 -25 5 35 65 95 125
DELAY - µs
TA - TEMPERATURE - oC
VEE= 0 V
VEE= -5 V
VEE= -10 V
VEE= -15 V
0
0.002
0.004
0.006
0.008
0 10 20 30 40 50
DELAY - ms
LOAD CAPACITANCE - nF
TA - TEMPERATURE - oCTA - TEMPERATURE - oC
Vcc2=30 V
Vcc2=15 V
Tplh
Tphl
Figure 21. Propagation delay vs. load capacitance Figure 22. Propagation delay vs. load resistance
Figure 23. DESAT sense to 90% Vout delay vs. temperature Figure 24. DESAT sense to 10% Vout delay vs. temperature
Figure 25. DESAT sense to low level fault signal delay vs. temperature Figure 26. DESAT sense to 10% Vout delay vs. load capacitance
14
Figure 27. DESAT sense to 10% Vout delay vs. load resistance Figure 28. RESET to high level fault signal delay vs. temperature
0.0010
0.0015
0.0020
0.0025
0.0030
10 20 30 40 50
DELAY - µs
LOAD RESISTANCE - OHM
Vcc2 = 30 V
Vcc2 = 15 V
4
6
8
10
12
- 55 - 25 5 35 65 95 125
DELAY - µs
TA - TEMPERATURE - oC
Vcc1 = 5.5 V
Vcc1 = 5.0 V
Vcc1 = 4.5 V
15
Test Circuit Diagrams
Figure 32. IOH pulsed test circuit. Figure 33. IOL pulsed test circuit.
Figure 34. IOLF test circuit. Figure 35. VOH pulsed test circuit.
Figure 31. IFAULTH test circuit.Figure 30. IFAULTL test circuit.
0.1 µF
+
–
10 mA
HCPL-316J fig 30
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
4.5 V
IFAULT
–
+
0.4 V
+
–
HCPL-316J fig 31
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
5 V
+
–
I
FAULT
0.1 µF
+
–
0.1 µF
HCPL-316J fig 32
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
+
–
+
–
30 V
30 V
15 V
PULSED
0.1 µF
IOUT
0.1 µF
0.1 µF
HCPL-316J fig 33
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
+
–
30 V
30 V
15 V
PULSED
0.1 µF
IOUT
0.1 µF
0.1 µF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
+
–
30 V
30 V
14 V
0.1
µF
IOUT
+
–
0.1
µF
5 V
0.1 µF
+
–
0.1 µF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
+
–
30 V
30 V
0.1
µF
VOUT
2A
PULSED
16
Figure 36. VOL test circuit. Figure 37. ICC1H test circuit.
Figure 38. ICC1L test circuit. Figure 39. ICC2H test circuit.
Figure 40. ICC2L test circuit. Figure 41. ICHG pulsed test circuit.
0.1 µF
+
–
0.1 µF
HCPL-316J fig 36
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
+
–
30 V
30 V
0.1
µF
VOUT
100
mA
+
–
HCPL-316J fig 37
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5.5 V
ICC1
+
–
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5.5 V
ICC1
0.1
µF
0.1 µF
HCPL-316J fig 39
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
ICC2
0.1 µF
+
–
5 V
0.1
µF
0.1 µF
0.1 µF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
ICC2
0.1 µF
0.1
µF
0.1 µF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
ICHG
0.1 µF
+
–
5 V
0.1
µF
17
Figure 42. IDSCHG test circuit. Figure 43. UVLO threshold test circuit.
Figure 44. DESAT threshold test circuit. Figure 45. tPLH, tPHL, tr, tf test circuit.
Figure 46. tDESAT(10%) test circuit. Figure 47. tDESAT(FAULT) test circuit.
0.1
µF
0.1 µF
HCPL-316J fig 42
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
IDSCHG
+
–
7 V
0.1 µF
+
–
HCPL-316J fig 43
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
SWEEP
0.1 µF
VOUT
0.1
µF
0.1 µF
HCPL-316J fig 44
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
+
–
+
–
15 V
15 V
SWEEP
0.1 µF
+
–
10 mA
0.1 µF
0.1 µF
HCPL-316J fig 45
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
+
–
30 V
30 V
VOUT 0.1
µF
10
nF
10 Ω
+
–
VIN
3 k
0.1
µF
0.1
µF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
+
–
30 V
30 V
VOUT
0.1
µF
10
nF
10 Ω
3 k
VIN
+
–
0.1
µF
0.1
µF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
+
–
30 V
30 V
0.1
µF
10
nF
10 Ω
3 k
VIN
+
–
VFAULT
18
Figure 49. UVLO delay test circuit.
Figure 50. CMR test circuit, LED2 o. Figure 51. CMR test circuit, LED2 on.
Figure 52. CMR test circuit, LED1 o. Figure 53. CMR test circuit, LED1 on.
Figure 48. tRESET(FAULT) test circuit.
HCPL-316J fig 50
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
SCOPE
3 kΩ
100 pF
0.1
µF
10 Ω
0.1 µF
10 nF
VCm
5 V
25 V
HCPL-316J fig 51
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
SCOPE
3 kΩ
100 pF
0.1
µF
10 Ω
10 nF
VCm
+
–
750 Ω
9 V
25 V
5 V
0.1 µF
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
3 kΩ
100
pF
0.1
µF
10 Ω
10 nF
VCm
0.1 µF
SCOPE
25 V
5 V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
SCOPE
3 kΩ
100 pF
0.1
µF
10 Ω
10 nF
VCm
0.1 µF
25 V
5 V
0.1
µF
0.1
µF
HCPL-316J fig 48
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
+
–
+
–
30 V
30 V
0.1
µF
10
nF
10 Ω
3 k
STROBE
8 V
+
–
VFAULT
VIN HIGH
TO LOW
HCPL-316J fig 49
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
µF
5 V
VOUT 0.1
µF
10
nF
10 Ω
3 k
+
–
RAMP
19
Figure 54. VOUT propagation delay waveforms, noninverting conguration. Figure 55. VOUT propagation delay waveforms, inverting conguration.
Figure 56. Desat, VOUT, fault, reset delay waveforms.
HCPL-316J fig 54
V
IN+
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
V
IN-
2.5 V 2.5 V
0 V
HCPL-316J fig 55
V
IN+
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
V
IN-
2.5 V 2.5 V
5.0 V
V
OUT
t
RESET (FAULT)
50% (2.5 V)
50%
10%
7 V
50%
t
DESAT (FAULT)
V
DESAT
FAULT
RESET
t
DESAT (90%)
t
DESAT (LOW)
t
DESAT (10%)
90%
20
Figure 57. ICH test circuit. Figure 58. ICH test circuit.
Figure 59. ICL test circuit. Figure 60. IEH test circuit.
Figure 61. IEL test circuit.
0.1 µF
0.1 µF
HCPL-316J fig 57
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
650 µA
0.1 µF
IC
+
–
0.1
µF
5 V 0.1 µF
0.1 µF
HCPL-316J fig 58
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 µF
IC
+
–
0.1
µF
5 V
0.1 µF
0.1 µF
HCPL-316J fig 59
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 µF
IC
0.1
µF
0.1 µF
HCPL-316J fig 60
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 µF
IE
+
–
0.1
µF
5 V
0.1
µF
0.1 µF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 µF
IE
+
–
0.1
µF
5 V
21
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three phase inverter is sus-
ceptible to several types of failures, most of which are
potentially destructive to the power IGBTs. These failure
modes can be grouped into four basic categories: phase
and/or rail supply short circuits due to user misconnect
or bad wiring, control signal failures due to noise or com-
putational errors, overload conditions induced by the
load, and component failures in the gate drive circuitry.
Under any of these fault conditions, the current through
the IGBTs can increase rapidly, causing excessive power
dissipation and heating. The IGBTs become damaged
when the current load approaches the saturation cur-
rent of the device, and the collector to emitter voltage
rises above the saturation voltage level. The drastically
increased power dissipation very quickly overheats the
power device and destroys it. To prevent damage to the
drive, fault protection must be implemented to reduce
or turn-o the overcurrents during a fault condition.
A circuit providing fast local fault detection and shut-
down is an ideal solution, but the number of required
components, board space consumed, cost, and complex-
ity have until now limited its use to high performance
drives. The features which this circuit must have are high
speed, low cost, low resolution, low power dissipation,
and small size.
Applications Information
The ACPL-516x satises these criteria by combining a
high speed, high output current driver, high voltage op-
tical isolation between the input and output, local IGBT
desaturation detection and shut down, and an optically
isolated fault status feedback signal into a single 16-pin
DIP package.
The fault detection method, which is adopted in the
ACPL-516x, is to monitor the saturation (collector) volt-
age of the IGBT and to trigger a local fault shutdown se-
quence if the collector voltage exceeds a predetermined
threshold. A small gate discharge device slowly reduces
the high short circuit IGBT current to prevent damaging
voltage spikes. Before the dissipated energy can reach
destructive levels, the IGBT is shut o. During the o
state of the IGBT, the fault detect circuitry is simply dis-
abled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is eective if the short
circuit capability of the power device is known, but
this method will fail if the gate drive voltage decreases
enough to only partially turn on the IGBT. By directly
measuring the collector voltage, the ACPL-516x limits
the power dissipation in the IGBT even with insucient
gate drive voltage. Another more subtle advantage of
the desaturation detection method is that power dissi-
pation in the IGBT is monitored, while the current sense
method relies on a preset current threshold to predict
the safe limit of operation. Therefore, an overly conserva-
tive overcurrent threshold is not needed to protect the
IGBT.
Recommended Application Circuit
The ACPL-516x has both inverting and non-inverting
gate control inputs, an active low reset input, and an
open collector fault output suitable for wired ‘OR’ appli-
cations. The recommended application circuit shown in
Figure 62 illustrates a typical gate drive implementation
using the ACPL-516x.
The four supply bypass capacitors (0.1 µF) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the charg-
ing currents, a low current (5 mA) power supply suces.
The desat diode and 100 pF capacitor are the necessary
external components for the fault detection circuitry.
The gate resistor (10 Ω) serves to limit gate charge cur-
rent and indirectly control the IGBT collector voltage
rise and fall times. The open collector fault output has
a passive 3.3 kΩ pull-up resistor and a 330 pF ltering
capacitor. A 47 kΩ pulldown resistor on VOUT provides a
more predictable high level output voltage (VOH). In this
application, the IGBT gate driver will shut down when a
fault is detected and will not resume switching until the
microcontroller applies a reset signal.
22
Figure 62. Recommended application circuit.
Description of Operation/Timing
Figure 63 illustrates input and output waveforms under
the conditions of normal operation, a desat fault condi-
tion, and normal reset behavior.
Normal Operation
During normal operation, VOUT of the ACPL-516x is con-
trolled by either VIN+ or VIN-, with the IGBT collector-to-
emitter voltage being monitored through DDESAT. The
FAULT output is high and the RESET input should be held
high. See Figure 63.
Figure 63. Timing diagram.
Fault Condition
When the voltage on the DESAT pin exceeds 7 V while
the IGBT is on, VOUT is slowly brought low in order to
“softly” turn-o the IGBT and prevent large di/dt induced
voltages. Also activated is an internal feedback channel
which brings the FAULT output low for the purpose of
notifying the micro-controller of the fault condition. See
Figure 63.
Reset
The FAULT output remains low until RESET is brought
low. See Figure 63. While asserting the RESET pin (LOW),
the input pins must be asserted for an output low state
(VIN+ is LOW or VIN- is HIGH). This may be accomplished
either by software control (i.e. of the microcontroller) or
hardware control (see Figures 73 and 74).
HCPL-316J fig 63
VOUT
VDESAT
VIN+
FAULT
RESET
NORMAL
OPERATION
FAULT
CONDITION
RESET
VIN+
VIN-
VIN-
5 V
0 V
5 V
5 V
7 V
NON-INVERTING
CONFIGURED
INPUTS
INVERTING
CONFIGURED
INPUTS
+
–
+
–
100 pF
DDESAT
0.1
µF
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
ACPL-516x
+
–
µC
3.3
kΩ
0.1
µF
5 V
330 pF
Rg
VCC2 = 18 V
VEE = -5 V
47
kΩ
3-PHASE
OUTPUT
0.1
µF 0.1
µF
VF
+ –
Q1
Q2
VCE
+
–
VCE
+
–
100 Ω
23
Slow IGBT Gate Discharge During Fault Condition
When a desaturation fault is detected, a weak pull-down
device in the ACPL-516x output drive stage will turn on
to ‘softly’ turn o the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn o, the large
output pull-down device remains o until the output
voltage falls below VEE + 2 V, at which time the large pull
down device clamps the IGBT gate to VEE.
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
theshold. This time period, called the DESAT blanking
time, is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT ca-
pacitor. The nominal blanking time is calculated in terms
of external capacitance (CBLANK), FAULT threshold volt-
age (VDESAT), and DESAT charge current (ICHG) as tBLANK
= CBLANK x VDESAT / ICHG. The nominal blanking time
with the recommended 100 pF capacitor is 100 pF * 7 V
/ 250 µA = 2.8 µsec. The capacitance value can be scaled
slightly to adjust the blanking time, though a value small-
er than 100 pF is not recommended. This nominal blank-
ing time also represents the longest time it will take for
the ACPL-516x to respond to a DESAT fault condition. If
the IGBT is turned on while the collector and emitter are
shorted to the supply rails (switching into a short), the
soft shut-down sequence will begin after approximately
3 µsec. If the IGBT collector and emitter are shorted to
the supply rails after the IGBT is already on, the response
time will be much quicker due to the parasitic parallel
capacitance of the DESAT diode. The recommended 100
pF capacitor should provide adequate blanking as well
as fault response times for most applications.
Under Voltage Lockout
The ACPL-516x Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insucient gate
voltage to the IGBT by forcing the ACPL-516x output low
during power-up. IGBTs typically require gate voltages
of 15 V to achieve their rated VCE(ON) voltage. At gate
voltages below 13 V typically, their on-voltage increases
dramatically, especially at higher currents. At very low
gate voltages (below 10 V), the IGBT may operate in the
linear region and quickly overheat. The UVLO function
causes the output to be clamped whenever insucient
operating supply (VCC2) is applied. Once VCC2 exceeds
VUVLO+ (the positive-going UVLO threshold), the UVLO
clamp is released to allow the device output to turn on
in response to input signals. As VCC2 is increased from 0 V
(at some level below VUVLO+), rst the DESAT protection
circuitry becomes active. As VCC2 is further increased
(above VUVLO+), the UVLO clamp is released. Before the
time the UVLO clamp is released, the DESAT protection
is already active. Therefore, the UVLO and DESAT FAULT
DETECTION features work together to provide seamless
protection regardless of supply voltage (VCC2).
24
Behavioral Circuit Schematic
The functional behavior of the ACPL-516x is rep-
resented by the logic diagram in Figure 64
which fully describes the interaction and se-
quence of internal and external signals in the
ACPL-516x.
Input IC
In the normal switching mode, no output fault has been
detected, and the low state of the fault latch allows the
input signals to control the signal LED. The fault output
is in the open-collector state, and the state of the Reset
pin does not aect the control of the IGBT gate. When a
fault is detected, the FAULT output and signal input are
both latched. The fault output changes to an active low
state, and the signal LED is forced o (output LOW). The
latched condition will persist until the Reset pin is pulled
low.
Figure 64. Behavioral circuit schematic.
Output IC
Three internal signals control the state of the driver out-
put: the state of the signal LED, as well as the UVLO and
Fault signals. If no fault on the IGBT collector is detected,
and the supply voltage is above the UVLO threshold,
the LED signal will control the driver output state. The
driver stage logic includes an interlock to ensure that the
pull-up and pull-down devices in the output stage are
never on at the same time. If an undervoltage condition
is detected, the output will be actively pulled low by the
50x DMOS device, regardless of the LED state. If an IGBT
desaturation fault is detected while the signal LED is on,
the Fault signal will latch in the high state. The triple dar-
lington AND the 50x DMOS device are disabled, and a
smaller 1x DMOS pull-down device is activated to slowly
discharge the IGBT gate. When the output drops below
2 V, the 50x DMOS device again turns on, clamping the
IGBT gate rmly to Vee. The Fault signal remains latched
in the high state until the signal LED turns o.
V
IN+
(1)
V
IN–
(2)
V
CC1
(3)
GND (4)
FAULT (6)
RESET (5)
DELAY
R S
Q
FAULT
LED
12 V
+
–V
CC2
(13)
7 V
–
+DESAT (14)
V
E
(16)
250 µA
V
C
(12)
V
OUT
(11)
V
EE
(9,10)
50 x
1 x
FAULT
UVLO
25
Other Recommended Components
The application circuit in Figure 62 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor (330 pF), and a FAULT pin pull-up
resistor.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of VCC2. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly VCC2-3(VBE)
to VCC2 within a period of several microseconds. To limit
the output voltage to VCC2-3(VBE), a pull-down resistor
between the output and VEE is recommended to sink a
static current of several 650 µA while the output is high.
Pull-down resistor values are dependent on the amount
of positive supply and can be adjusted according to the
formula, Rpull-down = [VCC2-3 * (VBE)] / 650 µA.
DESAT Pin Protection
The freewheeling of yback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substan-
tial current out of the IC if protection is not used. To limit
this current to levels that will not damage the IC, a 100
ohm resistor should be inserted in series with the DE-
SAT diode. The added resistance will not alter the DESAT
threshold or the DESAT blanking time.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can aect the fault
pin voltage while the fault output is in the high state. A
330 pF capacitor (Fig. 66) should be connected between
the fault pin and ground to achieve adequate CMOS
noise margins at the specied CMR value of 15 kV/µs.
The added capacitance does not increase the fault out-
put delay when a desaturation condition is detected.
Pull-up Resistor on FAULT Pin
The FAULT pin is an open-collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Driving with Standard CMOS/TTL for High CMR
Capacitive coupling from the isolated high voltage
circuitry to the input referred circuitry is the primary
CMR limitation. This coupling must be accounted for to
achieve high CMR perform ance. The input pins VIN+ and
VIN- must have active drive signals to prevent unwanted
switching of the output under extreme common mode
transient conditions. Input drive circuits that use pull-up
or pull-down resistors, such as open collector congu-
rations, should be avoided. Standard CMOS or TTL drive
circuits are recommended.
Figure 65. Output pull-down resistor. Figure 66. DESAT pin protection. Figure 67. FAULT pin CMR protection.
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
100 Ω
100 pF
DDESAT
Rg
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
µC
330 pF
3.3
kΩ
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
ACPL-516x
Rg
RPULL-DOWN
ACPL-516x
ACPL-516x
26
User-Conguration of the ACPL-516x Input Side
The VIN+, VIN-, FAULT and RESET input pins make a wide
variety of gate control and fault congurations possible,
depending on the motor drive requirements. The ACPL-
516x has both inverting and non inverting gate control
inputs, an open collector fault output suitable for wired
‘OR’ applications and an active low reset input.
Driving Input pf ACPL-516x in Non-Inverting/Inverting
Mode
The Gate Drive Voltage Output of the ACPL-516x can
be congured as inverting or non-inverting using the
VIN– and VIN+ inputs. As shown in Figure 68, when a
non-inverting conguration is desired, VIN– is held low
by connecting it to GND1 and VIN+ is toggled. As shown
in Figure 69, when an inverting conguration is desired,
VIN+ is held high by connecting it to VCC1 and VIN– is tog-
gled.
Local Shutdown, Local Reset
As shown in Figure 70, the fault output of each ACPL-
516x gate driver is polled separately, and the individual
reset lines are asserted low independently to reset the
motor controller after a fault condition.
Global-Shutdown, Global Reset
As shown in Figure 71, when congured for inverting op-
eration, the ACPL-516x can be congured to shutdown
automatically in the event of a fault condition by tying
the FAULT output to VIN+. For high reliability drives, the
open collector FAULT outputs of each ACPL-516x can be
wire ‘OR’ed together on a common fault bus, forming a
single fault bus for interfacing directly to the micro-con-
troller. When any of the six gate drivers detects a fault,
the fault output signal will disable all six ACPL-516x gate
drivers simultaneously and thereby provide protection
against further catastrophic failures.
Figure 68. Typical input conguration, noninverting.
Figure 69. Typical Input Conguration, Inverting.
Figure 70. Local shutdown, local reset conguration.
HCPL-316J fig 68
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
ACPL-516x
+
–
µC
HCPL-316J fig 69
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
µC
1
2
3
4
5
6
7
8
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
+
–
µC
ACPL-516x
ACPL-516x
27
Resetting Following a Fault Condition
To resume normal switching operation following a fault
condition (FAULT output low), the RESET pin must rst
be asserted low in order to release the internal fault
latch and reset the FAULT output (high). Prior to assert-
ing the RESET pin low, the input (VIN) switching signals
must be congured for an output (VOL) low state. This
can be handled directly by the microcontroller or by
hardwiring to synchronize the RESET signal with the ap-
propriate input signal. Figure 73a shows how to connect
the RESET to the VIN+ signal for safe automatic reset in
the noninverting input conguration. Figure 73b shows
how to congure the VIN+/RESET signals so that a RESET
signal from the microcontroller causes the input to be
in the “output-o” state. Similarly, Figures 73c and 73d
show automatic RESET and microcontroller RESET safe
congurations for the inverting input conguration.
Figure 71. Global-shutdown, global reset conguration.
Figure 72. Auto-reset conguration.
Auto-Reset
As shown in Figure 72, when the inverting VIN– input is
connected to ground (non-inverting conguration), the
ACPL-516x can be congured to reset automatically by
connecting RESET to VIN+. In this case, the gate control
signal is applied to the non-inverting input as well as the
reset input to reset the fault latch every switching cycle.
During normal operation of the IGBT, asserting the reset
input low has no eect. Following a fault condition, the
gate driver remains in the latched fault state until the
gate control signal changes to the ‘gate low’ state and
resets the fault latch. If the gate control signal is a con-
tinuous PWM signal, the fault latch will always be reset
by the next time the input signal goes high. This cong-
uration protects the IGBT on a cycle-by-cycle basis and
automatically resets before the next ‘on’ cycle. The fault
outputs can be wire ‘OR’ed together to alert the micro-
controller, but this signal would not be used for control
purposes in this (Auto-Reset) conguration. When the
ACPL- 516x is congured for Auto-Reset, the guaranteed
minimum FAULT signal pulse width is 3 µs.
Figure 73a. Safe hardware reset for noninverting input
conguration (automatically resets for every VIN+ input). Figure 73b. Safe hardware reset for noninverting input
conguration.
HCPL-316J fig 71
1
2
3
4
5
6
7
8
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
ACPL-516x
+
–
µC
CONNECT
TO OTHER
FAULTS
CONNECT
TO OTHER
RESETS
1
2
3
4
5
6
7
8
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
+
–
µC
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
µC
VCC
VIN+/
RESET
FAULT
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
µC
VCC
RESET
FAULT
VIN+
ACPL-516x ACPL-516x
ACPL-516x
28
0.5 A, the value of RC can be estimated in the following
way:
RC + RG = [VCC2 – VOH – (VEE)]
IOH,PEAK
= [4 V – (-5 V)]
0.5 A
= 18 Ω
RC = 8 Ω
See “Power and Layout Considerations” section for more
information on calculating value of RG.
User-Conguration of the ACPL-516x Output Side RG
and Optional Resistor RC:
The value of the gate resistor RG (along with VCC2 and VEE)
determines the maximum amount of gate-charging/dis-
charging current (ION,PEAK and IOFF,PEAK) and thus should
be carefully chosen to match the size of the IGBT being
driven. Often it is desirable to have the peak gate charge
current be somewhat less than the peak discharge cur-
rent (ION,PEAK < IOFF,PEAK). For this condition, an optional
resistor (RC) can be used along with RG to independently
determine ION,PEAK and IOFF,PEAK without using a steering
diode. As an example, refer to Figure 74. Assuming that
RG is already determined and that the design IOH,PEAK =
Figure 73d. Safe hardware reset for inverting input conguration
(automatically resets for every VIN- input).
Figure 73c. Safe hardware reset for inverting input conguration.
Figure 74. Use of RC to further limit ION,PEAK.
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
10 Ω
100 pF
RC 8 Ω
10 nF
-5 V15 V
HCPL-316J fig 73c
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
ACPL-516x
µC
VCC
RESET
FAULT
VIN-
VCC
HCPL-316J fig 73d
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
µC
VCC
RESET
FAULT
VIN-
VCC
ACPL-516x
ACPL-516x
29
Figure 75. Current buer for increased drive current.
Power/Layout Considerations
Operating Within the Maximum Allowable Power Ratings
(Adjusting Value of RG):
When choosing the value of RG, it is important to con-
rm that the power dissipation of the ACPL-516x is
within the maximum allowable power rating.
The steps for doing this are:
1. Calculate the minimum desired RG;
Higher Output Current Using an External Current Buf-
fer:
To increase the IGBT gate drive current, a non-inverting
current buer (such as the npn/pnp buer shown in
Figure 75) may be used. Inverting types are not com-
patible with the desatura-tion fault protection circuitry
and should be avoided. To preserve the slow IGBT turn-
o feature during a fault condition, a 10 nF capacitor
should be connected from the buer input to VEE and
a 10 Ω resistor inserted between the output and the
common npn/pnp base. The MJD44H11/MJD45H11
pair is appropriate for currents up to 8A maximum. The
D44VH10/ D45VH10 pair is appropriate for currents up
to 15 A maximum.
DESAT Diode and DESAT Threshold
The DESAT diode’s function is to conduct forward cur-
rent, allowing sensing of the IGBT’s saturated collector-
to-emitter voltage, VCESAT, (when the IGBT is “on”) and to
block high voltages (when the IGBT is “o”). During the
short period of time when the IGBT is switching, there is
commonly a very high dVCE/dt voltage ramp rate across
the IGBT’s collector-to-emitter. This results in ICHARGE (=
CD-DESAT x dVCE/dt) charging current which will charge
the blanking capacitor, CBLANK. In order to minimize
this charging current and avoid false DESAT triggering,
it is best to use fast response diodes. Listed in the be-
low table are fast-recovery diodes that are suitable for
use as a DESAT diode (DDESAT). In the recommended ap-
plication circuit shown in Figure 62, the voltage on pin
14 (DESAT) is VDESAT = VF + VCE, (where VF is the forward
ON voltage of DDESAT and VCE is the IGBT collector-to-
emitter voltage). The value of VCE which triggers DESAT
to signal a FAULT condition, is nominally 7V – VF. If de-
sired, this DESAT threshold voltage can be decreased by
using multiple DESAT diodes in series. If n is the number
of DESAT diodes then the nominal threshold value be-
comes VCE,FAULT(TH) = 7 V – n x VF. In the case of using two
diodes instead of one, diodes with half of the total re-
quired maximum reverse-voltage rating may be chosen.
Max. Reverse Voltage
Part Number Manufacturer trr (ns) Rating, VRRM (V) Package Type
MUR1100E Motorola 75 1000 59-04 (axial leaded)
MURS160T3 Motorola 75 600 Case 403A (surface mount)
UF4007 General Semi. 75 1000 DO-204AL (axial leaded)
BYM26E Philips 75 1000 SOD64 (axial leaded)
BYV26E Philips 75 1000 SOD57 (axial leaded)
BYV99 Philips 75 600 SOD87 (surface mount)
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
10 Ω
ACPL-516x
100 pF
10 nF
MJD44H11 or
D44VH10
4.5 Ω
2.5 Ω
MJD45H11 or
D45VH10
15 V -5 V
2. Calculate total power dissipation in the part referring
to Figure 77. (Average switching energy supplied to
ACPL-516x per cycle vs. RG plot);
3. Compare the input and output power dissipation
calculated in step #2 to the maximum recommended
dissipation for the ACPL-516x. (If the maximum rec-
ommended level has been exceeded, it may be nec-
essary to raise the value of RG to lower the switching
power and repeat step #2.)
30
PO(BIAS) = steady-state power dissipation in the ACPL-
516x due to biasing the device.
PO(SWITCH) = transient power dissipation in the ACPL-
516x due to charging and discharging power device
gate.
ESWITCH = Average Energy dissipated in ACPL-516x due
to switching of the power device over one switching
cycle (µJ/cycle).
fSWITCH = average carrier signal frequency.
For RG = 10.5, the value read from Figure 77 is ESWITCH
= 6.05 µJ. Assume a worst-case average ICC1 = 16.5 mA
(which is given by the average of ICC1H and ICC1L ). Simi-
larly the average ICC2 = 5.5 mA.
PI = 16.5 mA * 5.5 V = 90.8 mW
PO = PO(BIAS) + PO,SWITCH
= 5.5 mA * (18 V – (–5 V)) + 6.051 µJ * 15 kHz
= 126.5 mW + 90.8 mW
= 217.3 mW
Step 3: Compare the calculated power dissipation with the abso-
lute maximum values for the ACPL-516x:
For the example,
PI = 90.8 mW < 150 mW (abs. max.) ) OK
PO = 217.3 mW < 600 mW (abs. max.) ) OK
Therefore, the power dissipation absolute maximum
rating has not been exceeded for the example.
For an explanation on how to calculate the maximum
junction temperature of the ACPL-516x for a given PC
board layout conguration, refer to the following Ther-
mal Model section.
As an example, the total input and output power dis-
sipation can be calculated given the following condi-
tions:
• ION, MAX ~ 2.0 A
• VCC2 = 18 V
• VEE = -5 V
• fCARRIER = 15 kHz
Step 1: Calculate RG minimum from IOL peak specication:
To nd the peak charging lOL assume that the gate is
initially charged the steady-state value of VEE. Therefore
apply the following relationship:
[VOH@650 µA – (VOL+VEE)]
RG = ——————————
IOL,PEAK
[VCC2 – 1 – (VOL + VEE )]
= —————————
IOL,PEAK
18 V – 1 V – (1.5 V + (-5 V))
= ——————————
2.0 A
= 10.25 Ω
≈ 10.5 Ω (for a 1% resistor)
(Note from Figure 76 that the real value of IOL may vary from the value
calculated from the simple model shown.)
Step 2: Calculate total power dissipation in the ACPL-516x:
The ACPL-516x total power dissipation (PT) is equal to
the sum of the input-side power (PI) and output-side
power (PO):
PT = PI + PO
PI = ICC1 * VCC1
PO = PO(BIAS) + PO,SWTICH
= ICC2 * (VCC2–VEE ) + ESWITCH * fSWITCH
where,
Figure 76. Typical peak ION and IOFF currents vs. Rg (for
ACPL-516x output driving an IGBT rated at 600 V/100 A.
Figure 77. Switching energy plot for calculating average Pswitch
(for ACPL-516x output driving an IGBT rated at 600 V/100 A).
ION, IOFF (A)
0
-3
Rg (Ω)
200
3
1
HCPL-316J fig 76
4
20 100
-1
140
-2
0
2
IOFF (MAX.)
MAX. ION, IOFF vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V
40 60 80 120 160 180
ION (MAX.)
Ess (µJ)
0
0
Rg (Ω)
200
8
5
HCPL-316J fig 77
9
50 100
3
150
1
4
7
Ess (Qg = 650 nC)
6
2
SWITCHING ENERGY vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V
31
Thermal Model
R11, R12, R13, R14, R21, R22, R23, R24, R31, R32, R33, R34, R41, R42, R43, R44: Thermal Resistances in °C/W
R11: Thermal Resistance of LED1 due to heating of LED1.
R12: Thermal Resistance of LED1 due to heating of INPUT IC.
R13: Thermal Resistance of LED1 due to heating of LED2
R14: Thermal Resistance of LED1 due to heating of OUTPUT IC
R21: Thermal Resistance of INPUT IC due to heating of LED1.
R22: Thermal Resistance of INPUT IC due to heating of INPUT IC.
R23: Thermal Resistance of INPUT IC due to heating of LED2
R24: Thermal Resistance of INPUT IC due to heating of OUTPUT IC
R31: Thermal Resistance of LED2 due to heating of LED1
R32: Thermal Resistance of LED2 due to heating of INPUT IC
R33: Thermal Resistance of LED2 due to heating of LED2
R34: Thermal Resistance of LED2 due to heating of OUTPUT IC
R41: Thermal Resistance of OUTPUT IC due to heating of LED1
R42: Thermal Resistance of OUTPUT IC due to heating of INPUT IC
R42: Thermal Resistance of OUTPUT IC due to heating of LED2
R42: Thermal Resistance of OUTPUT IC due to heating of OUTPUT IC
Description
This thermal model assumes that the ACPL-516x optocoupler is mounted onto a 76.2 mm × 76.2 mm low and high
conductivity printed circuit board (PCB) per JEDEC standard. The PCB boards are made of FR-4 material and the thick-
ness of the copper traces is per JEDEC standards for low/high conductivity board.
The ACPL-516x is a hybrid device with four die: an input LED1, an input buer IC, an output feedback LED2, and an
output detector IC. The temperature at the LEDs and the ICs of the optocoupler can be calculated by using the fol-
lowing equations:
ΔT1A = R11P1 + R12P2+ R13P3+ R14P4
ΔT2A = R21P1 + R22P2+ R23P3+ R24P4
ΔT3A = R31P1 + R32P2+ R33P3+ R34P4
ΔT4A = R41P1 + R42P2 + R43P3+ R44P4
where:
ΔT1A = Temperature dierence between ambient and LED1
ΔT2A = Temperature dierence between ambient and INPUT IC
ΔT3A = Temperature dierence between ambient and LED2
ΔT4A = Temperature dierence between ambient and OUTPUT IC
P1 = Power dissipation from LED1
P2 = Power dissipation from INPUT IC
P3 = Power dissipation from LED2
P4 = Power dissipation from OUTPUT IC
32
Thermal Coecient Data (units in °C/W)
High Conductivity Board
R11 R12 R13 R24 R21 R22 R23 R24 R31 R32 R33 R34 R41 R42 R43 R44
111 26 28 26 24 66 30 23 23 29 79 25 27 26 26 35
Low Conductivity Board
R11 R12 R13 R24 R21 R22 R23 R24 R31 R32 R33 R34 R41 R42 R43 R44
125 37 41 32 41 70 47 30 36 38 93 28 41 35 40 38
Junction Temperature Calculation
Assume maximum power dissipation, Pmax(buer) = 0.15 W, Pmax(detector)= 0.6 W, P(LED) ~ 0.02 W. If the ambient
temperature is 125 °C, the calculated junction temperature for a high conductivity board is:
T2 = (R21 × P1 + R22 × P2 + R23 × P3 + R24 × P4) + Ta
= (24 × 0.02 + 66 × 0.15 + 30 × 0.02 + 23 × 0.6 ) + 125 ~ 150 °C
T4 = (R41 × P1 + R42 × P2 + R43 × P3 + R44 × P4 ) + Ta
= (27 × 0.02 + 26 × 0.15 + 26 × 0.02 + 35 × 0.6) + 125 ~ 150 °C
The junction temperatures of the input and output IC is ~ 150 °C when operating at 125 °C.
No power derating is required when operating below 125 °C using a high conductivity board.
If low conductivity board is used, the calculated junction temperature is:
T2 = (R21 × P1 + R22 × P2 + R23 × P3 + R24 × P4 ) + Ta
= (41 × 0.02 + 70 × 0.15 + 47 × 0.02 + 30 × 0.6 ) + 125 ~ 155 °C
T4 = (R41 × P1 + R42 × P2 + R43 × P3 + R44 × P4 ) + Ta
= (41 × 0.02 + 35 × 0.15 + 40 × 0.02 + 38 × 0.6) + 125 ~ 155 °C
The junction temperatures of the input and output IC exceeded the abs. max. junction temperature of 150 °C.
Power derating is required so that the junction temperatures do not exceed 150 °C.
Output IC power dissipation is derated linearly at 20 mW/°C above 120 °C.
Input IC power dissipation is derated linearly at 5 mW/°C above 120 °C.
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Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-3964EN - May 1, 2013
Figure 78. Minimum LED Skew for Zero Dead Time. Figure 79. Waveforms for Dead Time Calculation.
System Considerations
Propagation Delay Dierence (PDD)
The ACPL-516x includes a Propagation Delay Dierence
(PDD) specication intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 62) are o.
Any overlap in Q1 and Q2 conduction will result in large
currents owing through the power devices between
the high and low voltage motor rails, a potentially cata-
strophic condi tion that must be prevented.
To minimize dead time in a given design, the turn-on of
the ACPL-516x driving Q2 should be delayed (relative to
the turn-o of the ACPL-516x driving Q1) so that under
worst-case conditions, transistor Q1 has just turned o
when transistor Q2 turns on, as shown in Figure 78. The
amount of delay necessary to achieve this condition is
equal to the maxi mum value of the propagation delay
dierence specication, PDDMAX, which is specied to
be 400 ns over the operating temperature range of -55
°C to 125 °C.
Delaying the ACPL-516x turn-on signals by the maximum
propaga tion delay dierence ensures that the minimum
dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is
equivalent to the dierence between the maximum and
minimum propagation delay dierence specications
as shown in Figure 79. The maximum dead time for the
ACPL-516x is 800 ns (= 400 ns - (-400 ns)) over an operat-
ing temperature range of -55 °C to 125 °C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal tempera tures and test
conditions since the optocouplers under consider a tion
are typically mounted in close proximity to each other
and are switching identical IGBTs.
tPLHMIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHLMAX - tPHLMIN) + (tPLHMAX - tPLHMIN)
= (tPHLMAX - tPLHMIN) – (tPHLMIN - tPLHMAX)
= PDD*MAX – PDD*MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
VIN+2
VOUT2
VIN+1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
tPHLMIN
tPHLMAX
tPLHMAX
= PDD*MAX
(tPHL-tPLH)MAX
tPHLMAX
tPLHMIN
PDD* MAX = (tPHL - tPLH)MAX = tPHLMAX - tPLHMIN
*PDD = PROPAGATION DELAY
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
VIN+2
VOUT2
VIN+1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
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