MAX 7000 Programmable Logic Device Family Features... on RS 3 ee High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation Multiple Array MatriX (MAX) architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (/TAG) interface available in MAX 7000S devices Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX 70008 devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) available Peripheral component interconnect (PC])-compliant devices For information on in-system programmable 3.3-V MAX 7O00A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Devices Advance Information Brief in this data book. Table 1. MAX 7000 Device Features Feature EPM7032 | EPM7064 | EPM7096 | EPM7128E | EPM7160E | EPM7192E | EPM7256E Usable 600 1,250 1,800 2,500 3,200 3,750 5,000 gates Macrocells 32 64 96 128 160 192 256 Logic array 2 4 6 8 10 l2 16 blocks Maximum 36 68 76 100 104 124 164 user I/O pins tpp (ns) 7.5 75 10 12 12 tgy (ns) 6 7 7 7 tesy (ns) 2.5 2.5 3 3 3 3 teo, (ns) 4 4 4.5 45 5 6 6 fent (MHz) 151.5 151.5 125.0 125.0 100.0 90.9 $0.9 Altera Corporation 513 A-DS-M7000-06MAX 7000 Programmable Logic Device Family Data Sheet Table 2. MAX 7000S Device Features Feature EPM70328 EPM7064S EPM7128S | EPM71608 EPM71928 EPM72568 Usable gates 600 1,250 2,500 3,200 3,750 5,000 Macrocells 32 64 128 160 192 256 Logic array 2 4 8 10 12 16 blocks Maximum 36 68 100 104 124 164 user I/O pins tpp (ns) 5 5 6 6 7.5 75 tsy (ns) 2.9 2.9 3.4 3.4 41 3.9 tesy (ns) 2.5 2.5 2.5 2.5 3 3 teo1 (ns) 3.2 3.2 4 3.9 47 47 font (MHz) 175.4 175.4 147.1 149.3 125.0 128.2 ...and More Features 514 a: Open-drain output option in MAX 70005 devices Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a reduction of over 50% in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (POFP), power quad flat pack (ROFP), and 1.0-mm thin quad flat pack (TOQFP) packages Programmable security bit for protection of proprietary designs 3.3-V or 5.0-V operation MultiVolt I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (Multi Volt 1/O operation is not available in 44-pin packages) Pincompatible with low-voltage MAX 7000A and MAX 7000B devices Enhanced features available in MAX 7000E and MAX 70008 devices Six pin- or logic-driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from 1/O pin to macrocell registers Programmable output slew-rate control Software design support and automatic place-and-route provided by Alteras MAX+PLUS I development system for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations, and the Quartus development system for Windows-based PCs and Sun SPARCstation and HP 9000 Series 700 workstations Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet General Description # Additional design entry and simulation support provided by EDIF 200 and 3 0 Onetlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest # Programming support with Alteras Master Programming Unit (MPU}, BitBlaster serial download cable, ByteBlaster parallel port download cable, ByteBlasterMV parallel port download cable, as well as programming hardware from third-party manufacturers The MAX 7000 family of high-density, high-performance PLDs is based on Alteras second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 70008 devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7O00E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2,2. See Table 3 for available speed grades. Table 3. MAX 7000 Speed Grades Device Speed Grade 5 -6 -7 -10P -10 -12P 12 -15 15T -20 EPM7032 af we we ae ~ val EPM7032S of we we EPM7064 ae wv ww we < EPM7064S of we of EPM7096 ee wv va et EPM7128E we we rae se en we EPM7128S of we ww we EPM7160E A ae a wv al EPM7160S we re wv EPM7192E we eM ee we EPM7192S ae a ae EPM7256E wt ae et EPM7256S ne a ae Altera Corporation The MAX 7O00E devicesincluding the EPM7128E, EPM7160E, EPM/7192E, and EPM7256E deviceshave several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. 515MAX 7000 Programmable Logic Device Family Data Sheet In-system programmable MAX 7000 devicescalled MAX 70008 devicesinclude the EPM70325, EPM70645, EPM7128S, EPM7160S, EPM?7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as TAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4. Table 4. MAX 7000 Device Features Feature EPM7032 All All EPM7064 MAX 7O00E | MAX 70008 EPMI7096 Devices Devices ISP via JTAG interface JTAG BST circuitry Open-drain output option ey) 4 Fast input registers SN Six global output enables Twa global clocks Slew-rate control MultiVolt interface (2) we Programmable register S.A) APRT ATA. Parallel expanders Power-saving mode EUR CLCRM EME SECEGEGRS wy Shared expanders ff of we Security bit AEST AY. PCl-compliant devices available Notes: (1) Available in EPM71285, EPM71605, EPM7192S, and EPM72565 devices only. (2) The MultiVolt I/O intertace is not available in 44-pin packages. 516 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture supports 100% TTL emulation and high- density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices are available in a wide range of packages, including PLCC, PGA, POFP, ROFP, and TQFP packages. See Table 5. Table 5. MAX 7000 Maximum User [/0 Pins Note (1) Device 44- | 44- | 44- | G6- | 84- | 100- | 100- | 160- | 160- | 192- | 208- | 208- Pin | Pin | Pin | Pin | Pin | Pin | Pin Pin Pin Pin Pin Pin PLCC | POFP | TOFP | PLCC | PLCC |POFP| TOFP | POFP | PGA | PGA | POFP | ROFP EPM7032 36 36 36 EPM7032S |] 36 36 EPM7064 36 36 52 68 68 EPM7064S | 36 36 68 68 EPM7096 52 64 76 EPM7128E 68 84 100 EPM7128S 68 84 |84 (2) |100 EPM7160E 64 84 104 EPM7160S 64 84 (2) |104 EPM?7192E 124 124 EPM71 928 124 EPM7256E 132 (2) 164 164 EPM7256S 164 (2) | 164 Notes: (1) When the JTAG interface in MAX 7000S devices is used, four 1/O pins become JTAG pins. (2) Perform a complete thermal analysis before committing a design to this device package. See the Operating Regitirements for Altera Devices Data Sheet in this data book for more information. Altera Corporation MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. 517MAX 7000 Programmable Logic Device Family Data Sheet Functional Description 518 a2 Re = MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-oR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high-speed parallel expander product terms to provide up to 32 product terms per macrocell. The MAX 7000 family provides programmable speed / power optimization. Speed-critical portions of a design can run at high speed / full power, while the remaining portions run at reduced speed /low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000 devices (except 44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing MAX 7000 devices to be used in mixed-voltage systems. The MAX 7000 family is supported by the Quartus and MAX+PLUS I development systems, a single, integrated package that allows schematic, textincluding VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The Quartus and MAX+PLUS H software provides EDIF 2 00 and 300, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX-workstation- based EDA tools. The MAX+PLUS II software runs on Windows- based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. The Quartus software runs on Windows-based PCs, as well as Sun SPARCstation and HP 9000 Series 700 workstations. For more information on development tools, go to the MAX+PLUS I Programmable Logic Development System & Software Data Sheet. The MAX 7000 architecture includes the following elements: Logic array blocks Macrocells Expander product terms (shareable and parallel) Programmable interconnect array I/O control blocks BRR Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture inchides four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and 1/O pin. Figure 1 shows the architecture of EPM7082, EPM7064, and EPM7096 devices. Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram INPUT/GLOK1 [> INPUT/GCLRn >> INPUT/OE1n > * . a! INPUT/OE2n [o> I KH eh 8to 16 vo 4 8 to 16 : Control VO pins @ Block Ea Macrocells f 36 H Macrocells 1to 16 : 17 10 32 KH 8 to 16 vO Contre! Block 81016 @ Opins eS B1o 16 vo e mam 8 to 16 Control WG pins @ Block Macrocells 49 to 64 Macrocells 33 to 48 8 to 16 Altera Corporation vO Control Block 81016 @ "Opins 519MAX 7000 Programmable Logic Device Family Data Sheet Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices. Figure 2. MAX 7000E & MAX 700808 Device Block Diagram re =p INPUT/GCLK1 => INPUT/OE2GCLK2 > INPUT/OE1 > INPUT/GCLRn [> j 6 Output Enables yy 6 Output Enables 61016 6 to16 SH LES . ro | ste Macrocells * _ | Macrocells BtoB | ag ~ 6to16/O Pins @ Control he | 17 to 32 i Control @ Sto16 1/0 Pins H . Block : Block SH Yl SH | v v 6 to16 6 to16 SH Yl KS : | . wo | &to16 Macrocells [ * > | Macrocells BtoB) ig e Bto 16/0 Pins @ Control 33 0 48 "] 49 10 64 Control] @ Sto 16 VO Pins Block : Block | _* aH 2 SH I v v Logic Array Blocks The MAX 7000 device architecture is based on the linking of high- performance, flexible, logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2. Multiple LABs are linked together via the programmable interconnect array (PIA), a global bus that is fed by all dedicated inputs, 1/O pins, and macrocells. 520 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: R 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Direct input paths from 1/O pins to the registers that are used for fast setup times for MAX 7000E and MAX 7000S devices Macrocells The MAX 7000 macrocell can be individually configured for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. The macrocell of EPM7032, EPM7064, and EPM7096 devices is shown in Figure 3. Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell Logic Array YUUY Product- Term Select Matrix wv meres 36 Signals from PIA 16 Expander Product Terms Altera Corporation Global Global Clear Clock Parallel Logic Expanders ffrom other Programmable macrocells} Aegisier Register Doo Bypass } PRN . dD OG : Clocks D> Enable ENA Select CLRN CC Clear me De Select Shared Logic To PIA -<- Expanders To /O ontro| Block 521MAX 7000 Programmable Logic Device Family Data Sheet The macrocell of MAX 7OO0E and MAX 7000S devices is shown in Figure 4. Figure 4. MAX 7800E & MAX 7000S Device Macrocell Logic Array Global Global Clear Clocks From Parallel Logic 2 HO pin Expanders from other Fast input Programmable Select Register macrocells) Register Bypass rt 1 To LO Ly Select Select ai CLRN Matrix UUUY Clear 7 aeons rl Select P50. 1 Control . oa Block Product- : Clock/ = > Term Enable ENA Hs To PIA 36 Signals 16 Expander trom PIA Product Terms 522 Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocells register clear, preset, clock, and clock enable control functions. Two kinds of expander product terms (expanders) are available to supplement macrocell logic resources: @ Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The Quartus and MAX+PLUS II software automatically optimizes product-term allocation according to the legic requirements of the design. For registered functions, each macrocell flipflop can be individually programmed to implement D,'T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Quartus and MAX+PLUS II software then selects the mest efficient flipflop operation for each registered function to optimize resource utilization. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Altera Corporation Each programmable register can be clocked in three different modes: # = =Bya global clock signal. This mode achieves the fastest clock-to- output performance. By a global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. By an array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or 1/O pins. In EPM7032, EPM7064, and EPM7096 devices, the global clock signal is available from a dedicated clock pin, GCLK1, as shown in Figure 1. In MAX 7000E and MAX 7000S devices, two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLE2. Each register also supports asynchronous preset and clear functions. As shown in Figures 3 and 4, the product-term select matrix allocates preduct terms to control these operations. Although the product- term-driven preset and clear of the register are active high, active- low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). All MAX 7000E and MAX 7000S I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be driven to an input D flipflop with an extremely fast (2.5-ns) input setup time. Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. Ancther macrocell can be used to supply the required logic resources; however, the MAX 7000 architecture also allows both shareable and parallel expander product terms (expanders) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. 523MAX 7000 Programmable Logic Device Family Data Sheet 524 Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (tsxp) is incurred when shareable expanders are used. Figure 5 shows how shareable expanders can feed multiple macrocells. Figure 5. Shareable Expanders Shareable expanders can be shared by any or all macracelts in an LAB. Macracel! Produci-Term Logie Product-Term Select Matrix Macrocel! Produci-Term Logic eee eee 36 Signals 16 Shared from PIA Expanders Parallel Expanders Parallel expanders are unused product terms that can be allocated toa neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with 5 product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet The Quartus and MAX+PLUS II Compilers can allocate up to 3 sets of up to 5 parallel expanders atitomatically to the macrocells that require additional product terms. Each set of 5 parallel expanders incurs a small, incremental timing delay (tpeyp). For example, if a macrocell requires 14 product terms, the Compiler uses the 5 dedicated product terms within the macrecell and allocates 2 sets of parallel expanders; the first set includes 5 product terms and the second set includes 4 product terms, increasing the total delay by 2x ipexp- Two groups of 8 macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form 2 chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower-numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of 8, the lowest- numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. Figure 6 shows how parallel expanders can be borrowed from a neighboring macrocell. Figure 6. Parallel Expanders Unused product terms in a macroceil can be allocated to a neighboring macrocell. From Previous Macrocell Preset Macrocell Product- Term Logic Macrocell Produci- Term Logie 36 Signals 16 Shared Macrocell from PIA = Expanders Altera Corporation 525MAX 7000 Programmable Logic Device Family Data Sheet 526 Programmable Interconnect Array Logic is routed between LABs via the programmable interconnect array (PIA). This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 7000 dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 7 shows how the PIA signals are routed into the LAB. An EEPROM cell contrels one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. Figure 7. PIA Routing fe to LAB PIA Signals While the routing delays of channel-based routing schemes in masked or field-programmable gate arrays (FPGAs) are cumulative, variable, and path-dependent, the MAX 7000 PIA has a fixed delay. The PIA thus eliminates skew between signals and makes timing performance easy to predict. 1/0 Control Blocks The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All 1/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or Ver. Figure 8 shows the I/O control block for the MAX 7000 family. The I/O control block of EPM7032, EPM7064, and EPM7096 devices has two global output enable signals that are driven by two dedicated active-low output enable pins (CE1 and OE2). The 1/O control block of MAX 7000E and MAX 7000S devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the 1/O pins, or a subset of the I/O macrocells. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Figure 8. 1/0 Control Block of MAX 7006 Devices EPM7032, EPM7064 & EPM7096 Devices vec OE1 q OE2 GND aD From Macrocell rt To PIA ~<a MAX 7O00E & MAX 70008 Devices _ Six Global Output Enable Signals nN VCC PIA +{}- e{} % GND To Other I/O Pins oT From n >e te Macrocell Open-Drain Gutput (7) ty Fast Input to Slaw-Rate Control Macrocell ~~ Ragister To PIA ~a Note: (1) The open-drain output option is available in MAX 70008 devices only. Altera Corporation 527MAX 7000 Programmable Logic Device Family Data Sheet In-System Programma- bility (ISP) 528 RB, oe When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to Vcc, the output is enabled. The MAX 7000 architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an 1/0 pin is configured as an input, the associated macrocell can be used for buried logic. MAX 7000S devices are in-system programmable via an industry- standard 4-pin Joint Test Action Group (TAG) interface (IEEE Std. 1149,1-1990). ISP allows quick, efficient iterations during design development and debugging cycles. The MAX 70005 architecture internally generates the high programming voltage required to program EEPROM cells, allowing in-system programming with only a single 5.0 V power supply. During in-system programming, the I/O pins are tri-stated and pulled-up to eliminate board conflicts. The pull-up value is nominally 50 kQ. ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in-circuit test equipment before they are programmed. MAX 70005 devices can be programmed by downloading the information via in-circuit testers (ICT), embedded processors, or the Altera BitBlaster, ByteBlaster, or ByteBlasterMV download cables. (The ByteBlaster cable is obsolete and is replaced by the ByteBlasterMV cable, which can program and configure 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., OQFP packages) due to device handling and allows devices to be reprogrammed. after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers can not support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm are marked with an F suffix in the ordering code. The Jam programming and test language can be used to program MAX 7000S devices with in-circuit test equipment (e.g., PC, embedded processor). For more information on using the Jam language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor). Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Programmable Speed/Power Control Output Configuration Altera Corporation MAX 7000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic applications require only asmall fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 7000 device for either high-speed (i.e., with the Turbo Bit option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. As a result, speed-critical paths in the design can run at high speed, while the remnaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tp) for the ty ap, tLac, tic tact ten, and tcp yp parameters. MAX 7000 device outputs can be programmed to meet a variety of system-level requirements. Multiolt 1/0 Interface MAX 7000 devicesexcept 44-pin devicessupport the MultiVolt I/O interface feature, which allows MAX 7000 devices to interface with systems that have differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V 1/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCI), The VCCINT pins must always be connected to a 5.0-V power supply. With a5.0-V Voc level, input voltage thresholds are at TTL levels, and are therefore compatible with both 3.3-V and 5.0-V inputs. The Vcc1o pins can be connected to either a3.3-V or a5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V supply, the output levels are compatible with 5.0-V systems. When Vccjo is connected to a 3.3-V supply, the output high is 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with Vccjo levels lower than 4.75 V incur a nominally preater timing delay of top? instead of top). Open-Drain Output Option (MAX 7000S Devices Only) MAX 70008 devices provide an optional open-drain (functionally equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g, interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-or plane. 529MAX 7000 Programmable Logic Device Family Data Sheet Programming with External Hardware 530 Output pins on 5.0-V MAX 70008 devices with Vocig = 3.3 V or 5.0 V (with a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input pins. In this case, the pull-up transistor will turn off when the pin voltage exceeds 3.3 V. Therefore, the pin does not have to be open-drain. Slew-Rate Control The output buffer for each MAX 700CE and MAX 70005 I/O pin has an adjustable output slew rate that can be configured for low-noise or high- speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. In MAX 7O00E devices, when the Turbo Bit is turned off, the slew rate is set for low noise performance. For MAX 7000S devices, each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate ona pin-by-pin basis. MAX 7000 devices can be programmed on Windows-based PCs with the MAX+PLUS I Programmer, an Altera Logic Programmer card, the Master Programming Unit (MPU}, and the appropriate device adapter. The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. The MAX+PLUSI software can use text- or waveform-formiat test vectors created with the MAX+PLUS I Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional behavior of a MAX 7000 device with the results of simulation. Moreover, Data 1/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices. For more information, see Programming Hardware Manufacturers. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet IEEE Std. MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. 1149.1-1990, Table 6 describes the JTAG instructions supported by the 1 1 49 a (JTAG) MAX 7000 family. The pin-out tables starting on page 565 of this data Bou n d ary-Scan sheet show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user 1/O S U p p 0 rt pins. Table 6. MAX 7000 JTAG instructions JTAG Instruction Devices Description SAMPLE/PRELOAD EPM7128S _ | Allows a snapshot of signals at the device pins to be captured and EPM7160S | examined during normal device operation, and permits an initial data EPM7192S | pattern output at the device pins. EPM7256S EXTEST EPM7128S8 _ | Allows the external circuitry and board-level interconnections to be EPM7160S | tested by forcing a test pattern at the output pins and capturing test EPM7192S _ | results at the input pins. EPM7256S BYPASS EPM70328_ | Places the 1-bit bypass register between the TDI and TDo pins, which EPM70648 |allows the BST data to pass synchronously thraugh a selected device EPM71285 __|to adjacent devices during normal device operation. EPM7160S EPM71928 EPM72568 IDCODE EPM7032S8 | Selects the IDCODE register and places it between TDI and TDo, EPM7064S _ |allowing the IDCODE to be serially shifted out of TDo. EPM7128S EPM7160S EPM7192S EPM7256S ISP Instructions EPM7032S _ | These instructions are used when programming MAX 7000S devices EPM7064S _ | via the JTAG ports with the BitBlaster or ByteBlaster download cable, or EPM7128S | using a Jam File (.jam), Jam Byte-Code (.jbe), or Serial Vector Format EPM7160S8 _ | (.svf) file via an embedded processor or test equipment. EPM7192S EPM7256S Altera Corporation 531MAX 7000 Programmable Logic Device Family Data Sheet The instruction register length of MAX 70008 devices is 10 bits. Tables 7 and 8 show the boundary-scan register length and device IDCODE information for MAX 7000S devices. Table 7. MAX 7000S Boundary-Scan Register Length Device Poundary-Scan Register Length EPM7032S 1 (i) EPM7064S 1 (t) EPM7128S 288 EPM7160S 312 EPM7192S 360 EPM7256S 480 Note: (1) This device does not support JTAG boundary-scan testing. Table 8. 32-Bit MAX 7008 Device IDEQDE Note (1) Device IDCODE (32 Bits) Version | PartNumber (16 Bits) | Manufacturers | 1 (1 Bit) (4 Bits) identity (11 Bits)| (2) EPM70328 0000 0111 09900 0011 0010] 00001101110 EPM70648 D000 0111 8000 0110 01007 00001101110 EPM71288 0000 0111 5901 0010 1000] 00001101110 EPM7160S 0000 O111 00901 0110 O000]7 00001101110 EPM71928 D000 0111 0001 10017 00107 00001101110 Pele Jefe de EPM72568 0000 0111 09910 0101 0110] 00001101110 Notes: (1) The most significant bit (MSB) is on the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. 532 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet 8 OR 8 Be Altera Corporation Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7008 JTAG Waveforms TDI x x x xX TOK TDO Signal to Be Captured Signal to Be Driven Table 9 shows the JTAG timing parameters and values for MAX 70008 devices. Table 9. JTAG Timing Parameters & Values for MAX 7000S Devices Symbol Parameter Min | Max | Unit tucp | TCK clock period 100 ns tycH = | TCK clock high time 50 ns tyeL | TICK clock low time 50 ns tupsu | JTAG port setup time 20 ns typH = | YTAG port held time 45 ns tupco |UTAG port clock to output 25 | ns typzx | JTAG port high impedance to valid output 25 ns tupxe |JTAG port valid output to high impedance 25 ns tissu | Capture register setup time 20 ns tus | Capture register hold time 45 ns tusco | Update register clock to output 25 | ns tuszx | Update register high impedance to valid output 25 ns tusxz | Update register valid output to high impedance 25 ns For more information, see Application Note 39 (IEEE 1149.1 GTAG) Boundary-Scan Testing in Altera Devices). 533MAX 7000 Programmable Logic Device Family Data Sheet Design Security Generic Testing QFP Carrier & Development Socket oh FS, ae 534 All MAX 7000 devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security, because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. Each MAX 7000 device is functionally tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 10. Test patterns can be used and then erased during early stages of the production flow. Figure 10. MAX 7000 AC Test Cenditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be vec avoided for accurate measurement. Threshold fests must not be performed 03 31 < under AC conditions. Large-amplitude, fast ground-current transients normally oovice x a occur as the device oufputs discharge uIpu ystem the load capacitances. When these transients flow through the parasitic inductance between the device ground 200 = . pin and the test system ground, [8.06 KQ] = C1 (includes JIG nificant reducti in op bl capacitance) Signiicant freducuions in ODServane Device input ndise immunity can result. Numbers iA vise and tall brackets are for 2.5-V devices and times < 3ns outputs. Numbers without brackets are for 3.3-V devices and outputs. MAX 7000 and MAX 7000E devices in QFP packages with 100 or more pins are shipped in special plastic carriers to protect the OFP leads. The carrier is used with a prototype development socket and special programming hardware available from Altera. This carrier technology makes it possible to program, test, erase, and reprogram a device without exposing the leads to mechanical stress. For detailed information and carrier dimensions, refer to the OFP Carrier & Development Socket Data Sheet. ie MAX 70005 devices are not shipped in carriers. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet 0 p @ rati n g Tables 10 through 15 provide information about absolute maximum ays ratings, recommended operating conditions, operating conditions, Conditi ons and capacitance for 5.0-V MAX 7000 devices. Table 10. MAX 7000 5.8-V Device Absolute Maximum Ratings _ Note (1) Symbol Parameter Conditions Min Max Unit Voc Supply voltage With respect to ground (2) -2.0 7.0 Vv Vv DC input voltage -2.0 7.0 lout DC output current, per pin 25 25 mA Tste Storage temperature No bias -65 150 C TaMB Ambient temperature Under bias -65 135 C Ty Junction temperature Ceramic packages, under bias 150 C PQFP and ROFP packages, under bias 135 C Table 17. MAX 7006 5.8-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit Vecint | Supply voltage for internal logic and | (3), (4) 4.75 5.25 Vv input buffers (4.50) (5.50) Vecio Supply voltage for output drivers, (3), (4) 4.75 5.25 Vv 5.0-V operation (4.50) (5.50) Supply voltage tor output drivers, (3), (4), (5) 3.00 3.60 Vv 3.3-V operation (3.00) (3.60) Vecisp | Supply voltage during ISP (6) 4.75 5.25 Vv Vi Input voltage (2) 0.5/7) [Voor + 90-5] V Vo Output voltage 0 Vecio Vv Ta Ambient temperature For commercial use 0 70 C For industrial use 40 a5 C Ty Junction temperature For commercial use 0 90 C For industrial use 40 105 C tr Input rise time 40 ns te Input fall time 40 ns Altera Corporation 535MAX 7000 Programmable Logic Device Family Data Sheet Table 12. MAX 7000 5.0-V Device DC Operating Conditions Note (8) Symbol Parameter Conditions Min Max Unit Vin High-level input voltage 2.0 Vecint + 9-5] Vit Low-level input voltage (2) -0.5 (7) 0.8 Vv Vou 5.0-V high-level TTL output voltage | loy =4 MA DC, Vecig = 4.75 V (9) 24 Vv 3.3-V high-level TTL output voltage | loy =-4 mA DC, Vociq = 3.00 V (9) 24 Vv 3.3-V high-level CMOS output low =-0.1mADC, Vecio =3.0V (9) Vecio -0.2 Vv voltage VoL 5.0-V low-level TTL output voltage | lo, =12 mA DC, Vocig = 4.75 V (18) 0.45 Vv 3.3-V low-level TTL output voltage | lop =12 MA DC, Vecig = 3.00 V (1a) 0.45 Vv 3.3-V low-level CMOS output lo. = 0.1 MA DE, Vecio = 3.0 V(T0) 0.2 Vv voltage I Leakage current of dedicated input | Vj = Vcc or ground -10 10 HA pins loz \/O pin tri-state output off-state Vo = Voc or ground (71) -40 40 HA current Table 13. MAX 7000 5.0-V Device Capacitance: EPM7032, EPM7064 & EPM7096 Devices _Note (12) Symbol Parameter Conditions Min Max Unit Cin Input pin capacitance Vin =O V, f=1.0 MHz 12 pF Cho pin capacitance Vout = OV. t= 1.0 MHz 12 pF Table 14. MAX 7000 5.8-V Device Capacitance: MAX 7080E Devices Note (12) Symbol Parameter Conditions Min Max Unit Cin Input pin capacitance Vin =0 V. f=1.0 MHz 15 pF Cho /O pin capacitance Vout = OV. f= 1.0 MHz 15 pF Table 15. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Noite (12) Symbol Parameter Conditions Min Max Unit Cin Dedicated input pin capacitance Vin =O V, f=1.0 MHz 10 pF Cio VO pin capacitance Vout = OV, t= 1.0 MHz 10 pF 536 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: () (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) See the Operating Requirements for Altera Devices Data Sheet in this data book. Minimum DC input voltage on I/O pins is -0.5 V and on 4 dedicated input pins is -0.3 V. During transitions, the inputs may undershoot to2.0 V or overshoot to 7.0 V tor input currents less than 100 mA and periods shorter than 20 ns. Numbers in parentheses are for industrial-temperature-range devices. Vee must rise monotonically. 3.3-V 1/0 operation is not available for 44-pin packages. The Vecisp parameter applies only to MAX 70008 devices. During in-system programming, the minimum DC input voltage is -0.3 V. These values are specitied in Table 11 on page 535. The parameter is measured with 50% of the outputs each sourcing the specitied current. The I5;; parameter reters to high-level TTL or CMOS output current. The parameter is measured with 50% of the outputs each sinking the specitied current. The I5;, parameter refers to low-level TTL or CMOS output current. When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically 60 LA. Capacitance is measured at 25 C and is sampletested only. The o1 pin has a maximum capacitance of 20 pF. Figure 11 shows the typical output drive characteristics of MAX 7000 devices. Figure 17. Output Drive Charactaristfics of .0-V MAX 7000 Devices 150 120 Typical lo 99 Output Current (mA) 80 lot Vecio = 5.0 V Room Temperature 150 120 Typical lo 80 Qulpul Current (mA) 60 lot Veoio = 3-3 V Room Temperature lou lou 30, 305 1 2 3 4 5 1 2 333 4 5 Vg Output Voltage (V) Vg Output Voltage (V) Timing Model MAX 7000 device timing can be analyzed with the Quartus or MAX+PLUS H software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 12. MAX 7000 devices have fixed internal delays that enable the desipner to determine the worst-case timing of any design. The Quartus and MAX+PLUS II software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation. Altera Corporation 537MAX 7000 Programmable Logic Device Family Data Sheet Figure 12. MAX 7000 Timing Mode! Internal Output fe} Enable Delay tog (1) Input | Global Control! cC> Delay Delay J} _______ mf Y fin teroa Register Output Parallel Delay Delay Logic Array Expander Delay t t PIA >) Delay | ' su ont | Delay pe f PEXP fy fone (2) for LAD ol ai fons ; cLA fxg il Conn Dele ep taxi = +e frag foome tzx2 (2) tig fesu tzxs (1) fru fen vo Shared Fast Delay PB) Expander Delay tig pe] tgexe pe} Input Delay fein (1) Notes: (1) Only available in MAX 7000E and MAX 70008 devices. (2) Not available in 44-pin devices. The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 13 shows the internal timing relationship of internal and external delay parameters. * ial age 4-2 Application Note 94 (Understanding MAX 7000 Timing) in this data book for more information. 538 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Figure 13. Switching Waveforms tp & fp < Ons. Inputs are driven at 3 V for a logic high and 0 V for a logic low. Alf timing Input Pin characteristics are measured af 7.5 V VO Pin PIA Delay Shared Expander Delay Logic Array Input Parallel Expander Delay Logic Array Output Output Pin Global Clock Pin Global Clock at Register Data or Enable Logic Array Output) Input or FO Pin Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array Register to PIA to Logic Array Register Output to Pin Altera Corporation Combinatorial Mode eto a X ipa: es pat Global Clock Mode i fou ip i<_ ton in i -iciog fsu tty oe Array Clock Mode tat is tag *] le tac, 3 tin bo i fig nn isu fy ; : c x } fap *i i tora fcr, tage ot Se toa x K i fop x oe 539MAX 7000 Programmable Logic Device Family Data Sheet Tables 16 through 23 show the MAX 7000 and MAX 7000E AC operating conditions. Table 16. MAX 7000 & MAX 7000E External Timing Parameters Noite (1) Symbol Parameter Conditions Speed Grade Unit -6 -7 Min Max Min Max tepi Input to non-registered output C1 = 35 pF 6.0 7.5 ns tpp2 VO input to non-registered output C1 = 35 pF 6.0 7.5 ns tsu Global clock setup time 5.0 6.0 ns ty Global clock hold time 0.0 0.0 ns tesu Global clock setup time of fast input | (2) 25 3.0 ns tey Global clock hold time of fast input (2) 0.5 0.5 ns teo1 Global clock to output delay C1 = 35 pF 4.0 45 ns tou Global clock high time 2.5 3.0 ns te Global clock low time 2.5 3.0 ns tasu Array clock setup time 2.5 3.0 ns tau Array clock hold time 2.0 2.0 ns taco1 Array clock to output delay C1 = 35 pF 6.5 7.5 ns tacu Array clock high time 3.0 3.0 ns tact Array clock low time 3.0 3.0 ns toby Qutput data hold time after clock C1 = 35 pF (3) 1.0 1.0 ns tent Minimum global clock period 6.6 8.0 ns font Maximum internal global clack (4) 151.5 125.0 MHz frequency tacnt Minimum array clock period 6.6 8.0 ns taent Maximum internal array clock (4) 151.5 125.0 MHz frequency Tmax Maximum clock frequency (5) 200 166.7 MHz 540 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 17. MAX 7000 & MAX 7000E internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 6 7 Min Max Min Max tiny Input pad and butter delay 04 0.5 ns fig /Q input pad and buffer delay 04 0.5 ns Trin Fast input delay (2) 0.8 1.0 ns toexp Shared expander delay 3.5 4.0 ns tpexp Parallel expander delay 0.8 0.8 ns tap Logic array delay 2.0 3.0 ns bac Logic control array delay 2.0 3.0 ns hoe Internal output enable delay (2) 2.0 ns lon: Output buffer and pad delay C1 =35 pF 2.0 2.0 ns Slow slew rate = off, Vecig = 5.0 V fone Output buffar and pad delay C1 =35 pF (6) 2.5 2.5 ns Slow slew rate = off, Vecig = 3.3 V tons Output buffer and pad delay C1 = 35 pF (2) 7.0 7.0 ns Slow slew rate = on, Vecio =65.0Vor3.3V tg Output buffar enable delay C1 =35 pF 40 40 ns Slow slew rate = off, Vecig = 5.0 V trye Output butter enable delay C1 = 35 pF (6) 45 45 ns Slow slew rate = off, Vecig = 3.3 V tox Output butter enable delay C1 = 35 pF (2) 9.0 9.0 ns Slow slew rate = on Veco =5.0Vor3.3V tyz Output bufter disable delay C1 =5pF 40 4.0 ns tous Register setup time 3.0 3.0 ns ty Ragister hold time 1.5 2.0 ns troy Register setup time of fast input (2) 2.5 3.0 ns trey Ragister hold time of fast input (2) 0.5 0.5 ns tap Ragister delay 0.8 1.0 ns tcome Combinatorial delay 0.8 1.0 ns fic Array clock delay 25 3.0 ns fen Register enable time 2.0 3.0 ns fgroB Global control delay 08 1.0 ns fppe Register preset time 2.0 2.0 ns tora Register clear time 2.0 2.0 ns tpia PIA delay 08 1.0 ns ipa Low-power adder (7) 10.0 10.0 ns Altera Corporation 541MAX 7000 Programmable Logic Device Family Data Sheet Table 18. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-10P) | MAX 7000 (-10) MAX 7000E (-10) Min Max Min Max tepi Input to non-registered output C1 =35 pF 10.0 10.0 ns tpp2 lO input to non-registered output | C1 = 35 pF 10.0 10.0 ns tsu Global clock setup time 7.0 8.0 ns ty Global clock hold time 0.0 0.0 ns tesu Global clock setup time of fast input | (2) 3.0 3.0 ns try Global clock hold time of fast input | (2) 0.5 0.5 ns teo1 Global clock to cutput delay C1 =35 pF 5.0 5 ns tou Global clock high time 4.0 4.0 ns te Global clock low time 4.0 4.0 ns tasu Array clock setup time 2.0 3.0 ns tay Array clock hold time 3.0 3.0 ns taco Array clock to output delay C1 =35 pF 10.0 10.0 ns tacu Array clock high time 40 40 ns tact Array clack low time 4.0 46 ns topy Output data hold time after clock | C1 =35 pF (3) 1.0 1.0 ns tent Minimum global clock period 10.0 10.0 ns font Maximum internal global clack (4) 100.0 100.0 MHz frequency tacnT Minimum array clock period 10.0 10.0 ns Tacnt Maximum internal array clock (4) 100.0 100.0 MHz frequency Tmax Maximum clock frequency (5) 125.0 125.0 MHz 542 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 19. MAX 70008 & MAX 7000E internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit MAX 7O00E (-10P)} MAX 7000 (-10) MAX 7000E (-10) Min Max Min Max fy Input pad and buffer delay 0.5 1.0 ns fig VO input pad and buffer delay 0.5 1.0 ns Trin Fast input delay (2) 1.0 1.0 ns foryp Shared expander delay 5.0 5.0 ns tpexp Parallel expander delay 0.8 0.8 ns tap Logic array delay 5.0 5.0 ns bac Logie control array delay 5.0 5.0 ns hoe Internal cutout enable delay (2) 2.0 2.0 ns lon: Output butter and pad delay C1 =35 pF 1.5 2.0 ns Slow slew rate = off tone Output butter and pad delay C1 = 35 pF (6) 2.0 2.5 ns Slow slew rate = off fons Qutput buffer and pad delay C1 =35 pF (2) 5.5 6.0 ns Slow slew rate = on Vecio =5.0Vor3.3V tox; Output butter enable delay C1 =35 pF 5.0 5.0 ns Slow slew rate = off try Output butter enable delay C1 =35 pF (6) 5.5 5.5 ns Slow slew rate = off lg Qutput buffer enable delay C1 =35 pF (2) 9.0 9.0 ns Slow slew rate = on Vecio =5.0Vor3.3V tyz Output butter disable delay C1 =5 pF 5.0 5.0 ns fous Register setup time 2.0 3.0 ns ty Register hold time 3.0 3.0 ns frou Register setup time of fast input (2) 3.0 3.0 ns fry Register hold time of fast input (2) 05 0.5 ns fan Register delay 2.0 1.0 ns feoms Combinatorial delay 2.0 1.0 ns hie Array clock delay 5.0 5.0 ns ten Register enable time 5.0 5.0 ns teros Global control delay 1.0 1.0 ns tpae Register preset time 3.0 3.0 ns fora Register clear time 3.0 3.0 ns tpi, PIA delay 1.0 1.0 ns ti pa Low-power adder (7) 11.0 11.0 ns Altera Corporation 543MAX 7000 Programmable Logic Device Family Data Sheet Table 20. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions Speed Grade Unit MAX 7000E (-12P)) MAX 7000 (-12) MAX 7000E (-12) Min Max Min Max tepi Input to non-registered output C1 =35 pF 12.0 12.0 ns tpp2 lO input to non-registered output | C1 = 35 pF 12.0 12.0 ns tsu Global clock setup time 7.0 10.0 ns ty Global clock hold time 0.0 0.0 ns tesu Global clock setup time of fast input | (2) 3.0 3.0 ns try Global clock hold time of fast input | (2) 0.0 0.0 ns teo1 Global clock to cutput delay C1 =35 pF 6.0 6.0 ns tou Global clock high time 40 4.0 ns te Global clock low time 40 4.0 ns tasu Array clock setup time 3.0 40 ns tay Array clock hold time 40 40 ns taco Array clock to output delay C1 =35 pF 12.0 12.0 ns tacu Array clock high time 5.0 5.0 ns tact Array clack low time 5.0 5.0 ns topy Output data hold time after clock | C1 =35 pF (3) 1.0 1.0 ns tent Minimum global clock period 11.0 11.0 ns font Maximum internal global clack (4) 90.9 90.9 MHz frequency tacnT Minimum array clock period 11.0 11.0 ns Tacnt Maximum internal array clock (4) 90.9 90.9 MHz frequency Tmax Maximum clock frequency (5) 125.0 125.0 MHz 544 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 21. MAX 7000 & MAX 7000E internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit MAX 7O00E (-12P)| MAX 7000 (-12) MAX 7000E (-12) Min Max Min Max fy Input pad and buffer delay 1.0 2.0 ns fig VO input pad and buffer delay 1.0 2.0 ns Trin Fast input delay (2) 1.0 1.0 ns foryp Shared expander delay 7.0 7.0 ns tpexp Parallel expander delay 1.0 1.0 ns tap Logic array delay 7.0 5.0 ns bac Logie control array delay 5.0 5.0 ns hoe Internal cutout enable delay (2) 2.0 2.0 ns lon: Output butter and pad delay C1 =35 pF 1.0 3.0 ns Slow slew rate = off Vocio = 5.0 tone Output butter and pad delay C1 = 35 pF (6) 2.0 4.0 ns Slow slew rate = off tons Output butter and pad delay C1 = 35 pF (2) 5.0 7.0 ns Slow slew rate = on Vecio =5.0Vor3.3V tox; Output butter enable delay C1 =35 pF 6.0 6.0 ns Slow slew rate = off try Output butter enable delay C1 =35 pF (6) 7.0 7.0 ns Slow slew rate = off lg Qutput buffer enable delay C1 =35 pF (2) 10.0 10.0 ns Slow slew rate = on Vecio =5.0Vor3.3V tyz Output butter disable delay C1 =5 pF 6.0 6.0 ns fous Register setup time 1.0 40 ns ty Register hold time 6.0 4.0 ns frou Register setup time of fast input (2) 40 2.0 ns fry Register hold time of fast input (2) 0.0 2.0 ns fan Register delay 2.0 1.0 ns feoms Combinatorial delay 2.0 1.0 ns hie Array clock delay 5.0 5.0 ns ten Register enable time 7.0 5.0 ns teros Global control delay 2.0 0.0 ns tpae Register preset time 4.0 3.0 ns fora Register clear time 4.0 3.0 ns tpi, PIA delay 1.0 1.0 ns ti pa Low-power adder (7) 12.0 12.0 ns Altera Corporation 545MAX 7000 Programmable Logic Device Family Data Sheet Table 22. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions Speed Grade Unit 15 -15T 20 Min | Max | Min | Max | Min | Max tep1 Input to non-registered output |C1 = 35 pF 15.0 15.0 20.0 ns tpp2 /O input te non-registered C1 =35 pF 15.0 15.0 20.0 ns output tsu Global clock setup time 11.0 11.0 12.0 ns ty Global clock hold time 0.0 0.0 0.0 ns tesu Global clock setup time of fast | (2) 3.0 - 5.0 ns input try Global clock hold time of fast | (2) 0.0 - 0.0 ns input teo1 Global clock to output delay C1 =35 pF 8.0 8.0 12.0 ns tou Global clock high time 5.0 6.0 6.0 ns te Global clock low time 5.0 6.0 6.0 ns tasu Array clock setup time 40 4.0 5.0 ns tau Array clock hold time 40 4.0 5.0 ns tacos Array clock to output delay C1 =35 pF 15.0 15.0 20.0 ns tacu Array clock high time 6.0 6.5 8.0 ns tac. Array clock low time 6.0 6.5 8.0 ns toby Qutput data hold time after C1 =35 pF (3) 1.0 1.0 1.0 ns clock tent Minimum global clock period 13.0 13.0 16.0 ns font Maximum internal global clock | (4) 76.9 76.9 62.5 MHz frequency taent Minimum array clock period 13.0 13.0 16.0 ns taent Maximum internal array clock | (4) 76.9 76.9 62.5 MHz frequency Tmax Maximum clock frequency (5) 100 83.3 83.3 MHz 546 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 23. MAX 7008 & MAX 7000E internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 15 -15T -20 Min | Max | Min | Max | Min | Max tiny Input pad and buffer delay 2.0 2.0 3.0 ns fig lO input pad and butter delay 2.0 2.0 3.0 ns Trin Fast input delay (2) 2.0 - 4.0 ns toexp Shared expander delay 8.0 10.0 9.0 ns tpexp Parallel expander delay 1.0 1.0 2.0 ns tap Logic array delay 6.0 6.0 8.0 ns bac Logic control array delay 6.0 6.0 8.0 ns hoe Internal output enable delay (2) 3.0 - 4.0 ns lon: Output buffer and pad delay C1 =35 pF 4.0 4.0 5.0 ns Slow slaw rate = off Vocio = 5.0 tone Output buffer and pad delay C1 =35 pF (6) 5.0 - 6.0 ns Slow slew rate = off fons Output buffer and pad delay C1 =35pF (2) 8.0 - 9.0 ns Slow slew rate = on Vecio =50Vor3.3V toy Output bufter enable delay C1 =35 pF 6.0 6.0 10.6 ns Slow slew rate = off Vocio = 5.0 try Output butter enable delay C1 =35 pF (6) 7.0 - 11.0 ns Slow slew rate = off lg Output buffer enable delay C1 =35pF (2) 10.0 - 14.0 ns Slow slew rate = on Vecio =50Vor3.3V tyz Output bufter disable delay C1 =5 pF 6.0 6.0 10.6 ns tous Register setup time 4.0 4.0 4.0 ns ty Register hold time 4.0 4.0 5.0 ns frou Register setup time of fast input | (2) 2.0 - 40 ns try Register hold time of fast input | (2) 2.0 - 3.0 ns fan Register delay 1.0 1.0 1.0 ns feoms Combinatorial delay 1.0 1.0 1.0 ns tic Array clock delay 6.0 6.0 8.0 ns ten Register enable time 6.0 6.0 8.0 ns teros Global control delay 1.0 1.0 3.0 ns ippe Register preset time 4.0 4.0 4.0 ns fora Register clear time 4.0 4.0 4.0 ns tpi, PIA delay 2.0 2.0 3.0 ns ti pa Low-power adder (7) 13.0 15.0 15.0 ns Altera Corporation 547MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) These values are specified in Table 11 on page 535. (2). This parameter applies to MAX 7000E devices only. (3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. (4) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (5) The fyzax values represent the highest frequency for pipelined data. (6) Operating conditions: Veco = 3.3 V + 10% for commercial and industrial use. (7) The f;p4 parameter must be added to the fy. ap, frac fice tact fen, and tspxp parameters for macrocells running in the low-power mode. Tables 24 and 25 show the EPM7032S AC operating conditions. Table 24. EPM7032S External Timing Parameters Symbol Parameter Conditions Speed Grade Unit 5 6 7 -10 Min | Max} Min | Max | Min | Max} Min | Max tep1 Input to non-registered output | C1 =35 pF 5.0 6.0 7.5 10.0 ns tpp2 VO input to non-registered Ci =35 pF 5.0 6.0 7.5 10.0 ns output tsu Global clock setup time 2.9 4.0 5.0 7.0 ns ty Global clock hold time 0.0 0.0 0.0 0.0 ns tesu Global clock setup time of fast 2.5 2.5 2.5 3.0 ns input try Global clock hold time of fast 0.0 0.0 0.0 0.5 ns input teo1 Global clock to output delay C1 =35 pF 3.2 3.5 4.3 5.0 ns tou Global clock high time 2.0 25 3.0 4.0 ns te Global clock low time 2.0 2.5 3.0 4.0 ns tasu Array clock setup time 0.7 0.9 14 2.0 ns tau Array clock hold time 1.8 21 2.7 3.0 ns taco1 Array clock to output delay C1 =35 pF 5.4 6.6 8.2 10.0 | ns tacu Array clock high time 2.5 2.5 3.0 4.0 ns tac Array clock low time 2.5 25 3.0 4.0 ns toby Qutput data hold time after C1 =35 pF (7)] 1.0 1.0 1.0 1.0 ns clack tent Minimum global clock period 5.7 7.0 8.6 10.0 | ns font Maximum internal global clock | (2) 1754 142.9 116.3 100.0 MHz frequency taent Minimum array clock period 5.7 7.0 8.6 10.0 | ns taent Maximum internal array clock | (2) 1754 142.9 116.3 100.0 MHz frequency tax Maximum clock frequency (3) 250.0 200.0 166.7 125.0 MHz 548 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 25. EPM7032S Internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 5 6 7 -10 Min | Max | Min | Max | Min | Max | Min | Max tiny Input pad and buifer delay 0.2 0.2 0.3 0.5 ns fig VO input pad and buffer delay 0.2 0.2 0.3 0.5 ns Trin Fast input delay 2.2 21 25 1.0 ns toexp Shared expander delay 3.1 3.8 46 5.0 ns tpexp Parallel expander delay 09 14 14 0.8 | ns tap Logic array delay 2.6 3.3 4.0 5.0 ns bac Logic control array delay 25 3.3 4.0 5.0 ns hoe Internal output enable delay 07 0.8 1.0 2.0 ns lon: Output butfer and pad delay | C1 =35 pF 02 0.3 04 1.5 ns lone Output butfer and pad delay | C1 = 35 pF (4) O7 0.8 09 2.0 ns fons Output butfer and pad delay | C1 = 35 pF 5.2 5.3 5.4 5.5 ns tng Output butfer enable delay Ci = 35 pF 40 40 40 5.0 ns lye Output butfer enable delay C1 = 35 pF 4) 45 45 45 5.5 ns lg Output butfer enable delay Ci = 35 pF 9.0 9.0 9.0 9.0 ns iy Output butfer disable delay [C1 =5 pF 40 40 40 5.0 ns touy Ragister setup time 0.8 1.0 1.3 2.0 ns ty Ragister hold time 17 2.0 2.5 3.0 ns trou Register setup time of tast 1.9 1.8 1.7 3.0 ns input tepy Ragister hold time of fast 0.6 0.7 0.8 0.5 ns input tap Register delay 12 1.6 1.9 2.0 ns fcome Combinatorial delay 09 11 14 2.0 ns hic Array clock delay 27 3.4 42 5.0 ns fey Ragister enable time 2.6 3.3 4.0 5.0 | ns teros Global control delay 1.6 14 17 1.0 ns tpae Ragister preset time 2.0 24 3.0 3.0 ns fora Register clear time 2.0 2.4 3.0 3.0 ns fora PIA delay (5) 14 11 14 1.0 | ns ti pa Low-power adder (6) 12.0 10.0 10.0 11.0 | ns Altera Corporation 549MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: ) parameter applies for both global and array clocking. (2) (3) (4) (5) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fax Values represent the highest frequency for pipelined data. Operating conditions: Vecjg = 3.3 V + 10% for commercial and industrial use. For EPM7064S-5, EPM70645-6, EPM71285-6, EPM71605-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (6) the low-power mode. Tables 26 and 27 show the EPM70645 AC operating conditions. The f; pa parameter must be added to the tp an, frac: fic, fact ten, and fsexp parameters for macrocells running in Table 26. EPM70648 External Timing Parameters Symbol Parameter Conditions Speed Grade Unit 5 -6 7 -10 Min | Max | Min | Max} Min | Max | Min | Max tap; Input to non-registered output | C1 =35 pF 5.0 6.0 7.5 10.0 | ns tppe \/O input to non-registered Ci =35 pF 5.0 6.0 7.5 10.0 |] ns output tsy Global clock setup time 2.9 3.6 6.0 7.0 ns ty Global clack hold time 0.0 0.0 0.0 0.0 ns tesu Global clock setup time of fast 2.5 2.5 3.0 3.0 ns input tey Global clack hold time of fast 0.0 0.0 0.5 05 ns input teo1 Global clock to output delay C1 =35 pF 3.2 4.0 45 5.0 ns ten Global clock high time 2.0 2.5 3.0 40 ns te. Global clock low time 2.0 2.5 3.0 40 ns tasu Array clock setup time 0.7 0.9 3.0 2.0 ns tay Array clock hold time 1.8 2.1 2.0 3.0 ns tacoi Array clock fo output delay Ci =35 pF 54 6.7 7.5 10.0] ns tacu Array clock high time 2.5 2.5 3.0 40 ns tac. Array clock low time 2.5 2.5 3.0 40 ns toby Output data hold time after C1 =35 pF (7) 1.0 1.0 1.0 1.0 ns clock tent Minimum global clock period 5.7 7.1 8.0 10.0 | ns font Maximum internal global clock | (2) 175.4 140.8 125.0 100.0 MHz frequency tacnt Minimum array clock period 5.7 71 8.0 10.0} ns facnt Maximum internal array clock | (2) 175.4 140.8 125.0 100.0 MHz frequency TMax Maximum clock frequency (3) 250.0 200.0 166.7 125.0 MHz 550 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 27. EPM7064S Internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 5 6 7 10 Min | Max | Min | Max | Min | Max | Min | Max tiny Input pad and buffer delay 02 02 0.5 05] ns tio \/G input pad and butfer delay 0.2 0.2 0.5 0.5] ns tein Fast input delay 2.2 2.6 1.0 1.0] ns tsexp Shared expander delay 3.1 3.8 4.0 5.0] ns tpexp Parallel expander delay 0g 14 0.8 0.8] ns trap Logic array delay 2.6 3.2 3.0 5.0 | ns trac Logic control array delay 25 3.2 3.0 5.0] ns toe Internal output enable delay 0.7 0.8 2.0 2.0] ns topr Output butter and paddelay | C1 = 35 pF 0.2 0.3 2.0 1.5] ns tone Output buffer and paddelay | C1 = 35 pF (4) 0.7 0.8 2.5 2.0] ns tons Output buffer and paddelay [61 = 35 pF 5.2 5.3 7.0 5.5 | ns tox Output buffer enable delay C1 = 35 pF 40 40 4.0 5.0 | ns tye Output buffer enable delay C1 = 35 pF 4) 45 45 45 5.5 | ns tog Output buffer enable delay C1 = 38 pF 9.0 9.0 9.0 9.0] ns ig Output buffer disable delay | C1 =5pF 40 40 4.0 5.0] ns tgu Register setup time 0.8 1.0 3.0 2.0 ns ty Register hold time 17 2.0 2.0 3.0 ns trsy Register setup time of fast 18 1.8 3.0 3.0 ns input try Register hold time of fast 0.6 07 0.5 0.5 ns input tap Register delay 12 1.6 1.0 2.0 | ns tcome Combinatorial delay 09 1.0 1.0 2.0] ns tie Array clock delay 27 3.3 3.0 5.0] ns ten Register enable time 2.6 3.2 3.0 5.0] ns teros Global control delay 1.6 1.9 1.0 1.0] ns ipar Register preset time 2.0 2.4 2.0 3.0] ns tour Register clear time 2.0 2.4 2.0 3.0] ns tpia PIA delay (5) 14 1.3 1.0 1.0] ns tipa Low-power adder (6) 12.0 11.0 10.0 11.0] ns Altera Corporation 551MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. (2) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (3) The fyyax values represent the highest frequency for pipelined data. (4) Operating conditions: Very = 3.3 V+ 10% tor commercial and industrial use. (5) For EPM70645-5, EPM70645-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (6) The fy p4 parameter must be added to the ty an, frac. fice fact, ten, and fsexp parameters for macrocells running in the low-power mode. Tables 28 and 29 show the EPM71285 AC operating conditions. Table 28. EPM71288 External Timing Parameters Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 15 Min | Max | Min | Max} Min | Max | Min | Max tap; Input to non-registered output | C1 =35 pF 6.0 7.5 10.0 15.0 | ns tppe \/O input to non-registered Ci =35 pF 6.0 7.5 10.0 15.0 | ns output tsy Global clock setup time 3.4 6.0 7.0 11.0 ns ty Global clack hold time 0.0 0.0 0.0 0.0 ns tesu Global clock setup time of fast 2.5 3.0 3.0 3.0 ns input tey Global clack hold time of fast 0.0 05 0.5 0.0 ns input teo1 Global clock to output delay C1 =35 pF 4.0 45 5.0 8.0 ns ten Global clock high time 3.0 3.0 4.0 5.0 ns te. Global clock low time 3.0 3.0 4.0 5.0 ns tasu Array clock setup time 0.9 3.0 2.0 40 ns tay Array clock hold time 1.8 2.0 5.0 40 ns tacoi Array clock fo output delay Ci =35 pF 6.5 7.5 10.0 15.0] ns tacu Array clock high time 3.0 3.0 4.0 6.0 ns tac. Array clock low time 3.0 3.0 4.0 6.0 ns toby Output data hold time after C1 =35 pF (7) 1.0 1.0 1.0 1.0 ns clock tent Minimum global clock period 6.8 8.0 10.0 13.0 | ns font Maximum internal global clock | (2) 147.1 125.0 100.0 76.9 MHz frequency tacnt Minimum array clock period 6.8 8.0 10.0 13.0} ns facnt Maximum internal array clock | (2) 147.1 125.0 100.0 76.9 MHz frequency TMax Maximum clock frequency (3) 166.7 166.7 125.0 100.0 MHz 552 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 29. EPM7128S Internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 6 7 -10 15 Min | Max | Min | Max | Min | Max | Min | Max tiny Input pad and buffer delay 02 05 0.5 2.0 | ns tio \/G input pad and butfer delay 0.2 0.5 0.5 2.0] ns tein Fast input delay 2.6 1.0 1.0 2.0] ns tsexp Shared expander delay 3.7 40 5.0 8.0] ns tpexp Parallel expander delay 14 0.8 0.8 1.0] ns trap Logic array delay 3.0 3.0 5.0 6.0 | ns trac Logic control array delay 3.0 3.0 5.0 6.0] ns toe Internal output enable delay 0.7 2.0 2.0 3.0] ns topr Output butter and paddelay | C1 = 35 pF 0.4 2.0 1.5 4.0] ns tone Output buffer and paddelay | C1 = 35 pF (4) 0.9 2.5 2.0 5.0] ns tons Output buffer and paddelay [61 = 35 pF 5.4 7.0 5.5 8.0] ns tox Output buffer enable delay C1 = 35 pF 40 40 5.0 6.0 | ns tye Output buffer enable delay C1 = 35 pF 4) 45 45 5.5 7.0] ns tog Output buffer enable delay C1 = 38 pF 9.0 9.0 9.0 10.0 | ns ig Output buffer disable delay | C1 =5pF 40 40 5.0 6.0] ns tgu Register setup time 1.0 3.0 2.0 40 ns ty Register hold time 17 2.0 5.0 40 ns trsy Register setup time of fast 1.9 3.0 3.0 2.0 ns input try Register hold time of fast 06 0.5 0.5 1.0 ns input tap Register delay 14 1.0 2.0 1.0] ns tcome Combinatorial delay 1.0 1.0 2.0 1.0] ns tie Array clock delay 3.1 3.0 5.0 6.0] ns ten Register enable time 3.0 3.0 5.0 6.0] ns teros Global control delay 2.0 1.0 1.0 1.0] ns ipar Register preset time 2.4 2.0 3.0 40] ns tour Register clear time 2.4 2.0 3.0 4.0] ns tpia PIA delay (5) 1.4 1.0 1.0 2.0] ns tipa Low-power adder (6) 11.0 10.0 11.0 13.0 |] ns Altera Corporation 553MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: ) parameter applies for both global and array clocking. (2) (3) (4) (5) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fax Values represent the highest frequency for pipelined data. Operating conditions: Vecjg = 3.3 V + 10% for commercial and industrial use. For EPM7064S-5, EPM70645-6, EPM71285-6, EPM71605-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (6) the low-power mode. Tables 30 and 31 show the EPM71605 AC operating conditions. The f; pa parameter must be added to the tp an, frac: fic, fact ten, and fsexp parameters for macrocells running in Table 30. EPM71608 External Timing Parameters Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 15 Min | Max | Min | Max} Min | Max | Min | Max tap; Input to non-registered output | C1 =35 pF 6.0 7.5 10.0 15.0 | ns tppe \/O input to non-registered Ci =35 pF 6.0 7.5 10.0 15.0 | ns output tsy Global clock setup time 3.4 4.2 7.0 11.0 ns ty Global clack hold time 0.0 0.0 0.0 0.0 ns tesu Global clock setup time of fast 2.5 3.0 3.0 3.0 ns input tey Global clack hold time of fast 0.0 0.0 0.5 0.0 ns input teo1 Global clock to output delay C1 =35 pF 3.9 4.8 5 8 ns ten Global clock high time 3.0 3.0 4.0 5.0 ns te. Global clock low time 3.0 3.0 4.0 5.0 ns tasu Array clock setup time 0.9 14 2.0 40 ns tay Array clock hold time 17 2.1 3.0 40 ns tacoi Array clock fo output delay Ci =35 pF 6.4 7.9 10.0 15.0] ns tacu Array clock high time 3.0 3.0 4.0 6.0 ns tac. Array clock low time 3.0 3.0 4.0 6.0 ns toby Output data hold time after C1 =35 pF (7) 1.0 1.0 1.0 1.0 ns clock tent Minimum global clock period 6.7 8.2 10.0 13.0 | ns font Maximum internal global clock | (2) 1498.3 122.0 100.0 76.9 MHz frequency tacnt Minimum array clock period 6.7 8.2 10.0 13.0} ns facnt Maximum internal array clock | (2) 149.3 122.0 100.0 76.9 MHz frequency TMax Maximum clock frequency (3) 166.7 166.7 125.0 100.0 MHz 554 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 31. EPM7160S Internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 6 7 -10 15 Min | Max | Min | Max | Min | Max | Min | Max tiny Input pad and buffer delay 02 03 0.5 2.0 | ns tio \/G input pad and butfer delay 0.2 0.3 0.5 2.0] ns tein Fast input delay 2.6 3.2 1.0 2.0] ns tsexp Shared expander delay 3.6 43 5.0 8.0] ns tpexp Parallel expander delay 1.0 1.3 0.8 1.0] ns trap Logic array delay 28 3.4 5.0 6.0 | ns trac Logic control array delay 2.8 3.4 5.0 6.0] ns toe Internal output enable delay 0.7 0.9 2.0 3.0] ns topr Output butter and paddelay | C1 = 35 pF 0.4 0.5 1.5 4.0] ns tone Output buffer and paddelay | C1 = 35 pF (4) 0.9 1.0 2.0 5.0] ns tons Output buffer and paddelay [61 = 35 pF 5.4 5.5 5.5 8.0] ns tox Output buffer enable delay C1 = 35 pF 40 40 5.0 6.0 | ns tye Output buffer enable delay C1 = 35 pF 4) 45 45 5.5 7.0] ns tog Output buffer enable delay C1 = 38 pF 9.0 9.0 9.0 10.0 | ns ig Output buffer disable delay | C1 =5pF 40 40 5.0 6.0] ns tgu Register setup time 1.0 1.2 2.0 40 ns ty Register hold time 1.6 2.0 3.0 40 ns trsy Register setup time of fast 1.9 2.2 3.0 2.0 ns input try Register hold time of fast 06 08 0.5 1.0 ns input tap Register delay 13 1.6 2.0 1.0] ns tcome Combinatorial delay 1.0 1.3 2.0 1.0] ns tie Array clock delay 29 3.5 5.0 6.0] ns ten Register enable time 2.8 3.4 5.0 6.0] ns teros Global control delay 2.0 2.4 1.0 1.0] ns ipar Register preset time 2.4 3.0 3.0 40] ns tour Register clear time 2.4 3.0 3.0 4.0] ns tpia PIA delay (5) 1.6 2.0 1.0 2.0] ns tipa Low-power adder (6) 11.0 10.0 11.0 13.0 |] ns Altera Corporation 555MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies tor both global and array clocking. (2) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (3) The fy values represent the highest frequency for pipelined data. (4) Operating conditions: Vecro = 3.3 V + 10% for commercial and industrial use. (5) For EPM70648-5, EPM70645-6, EPM71288-6, EPM71608-6, EPM71608-7, EPM7192S-7, and EPM72568-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (6) The f;p4 parameter must be added to the fy an, trace fice tact, fen, and tspxp parameters for macrocells running in the low-power mode. Tables 32 and 33 show the EPM71925 AC operating conditions. Table 32. EPM7192S External Timing Parameters Symbol Parameter Conditions Speed Grade Unit 7 -10 15 Min | Max | Min | Max | Min | Max tpp1 Input to non-registered output | C1 =35 pF 7.5 10.0 15.0 ns tpp2 /O input to non-registered C1 =35 pF 7.5 10.0 15.0 ns output tsu Global clock setup time 41 7.0 11.0 ns ty Global clock hold time 0.0 0.0 0.0 ns tesu Global clock setup time of fast 3.0 3.0 3.0 ns input tey Global clock hold time of fast 0.0 05 0.0 ns input teoi Global clock to output delay C1 =35 pF 47 5.0 8.0 ns tou Global clock high time 3.0 4.0 5.0 ns tet Global clock low time 3.0 40 5.0 ns tasu Array clock setup time 1.0 2.0 40 ns tay Array clock hold time 18 3.0 40 ns taco Array clock to output delay Ci =35 pF 7.8 10.0 15.0 ns tach Array clock high time 3.0 4.0 6.0 ns tac. Array clock low time 3.0 4.0 6.0 ns toby Output data hold time after Ci =35 pF (7) 1.0 1.0 1.0 ns clock tent Minimum global clock period 8.0 10.0 13.0 ns font Maximum internal global clock | (2) 125.0 100.0 76.9 MHz frequency tacnT Minimum array clock period 8.0 10.0 13.0 ns Tacnt Maximum internal array clock | (2) 125.0 100.0 76.9 MHz frequency Tmax Maximum clock frequency (3) 166.7 125.0 100.0 MHz 556 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 33. EPM7792S Internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min | Max | Min | Max | Min | Max tiny Input pad and buifer delay 0.3 0.5 2.0 ns fig VO input pad and buffer delay 0.3 0.5 2.0 ns Trin Fast input delay 3.2 1.0 2.0 ns toexp Shared expander delay 42 5.0 8.0 ns tpexp Parallel expander delay 1.2 0.8 1.0 ns tap Logic array delay 3.1 5.0 6.0 ns bac Logic control array delay 3.1 5.0 6.0 ns hoe Internal output enable delay 0.9 2.0 3.0 ns lon: Output butfer and pad delay | C1 =35 pF 0.5 1.5 4.0 ns lone Output butfer and pad delay | C1 = 35 pF (4) 1.0 2.0 5.0 ns fons Output butfer and pad delay | C1 = 35 pF 5.5 5.5 7.0 ns tng Output butfer enable delay Ci = 35 pF 46 5.0 6.0 ns lye Output butfer enable delay C1 = 35 pF 4) 45 5.5 7.0 ns lg Output butfer enable delay Ci = 35 pF 9.0 9.0 10.0 ns iy Output butfer disable delay [C1 =5 pF 46 5.0 6.0 ns touy Ragister setup time 1.4 2.0 40 ns ty Ragister hold time 1.7 3.0 4.0 ns trou Register setup time of tast 2.3 3.0 2.0 ns input tepy Ragister hold time of fast 0.7 0.5 1.0 ns input tap Register delay 1.4 2.0 1.0 ns fcome Combinatorial delay 1.2 2.0 1.0 ns hic Array clock delay 3.2 5.0 6.0 ns fey Ragister enable time 3.1 5.0 6.0 ns teros Global control delay 2.5 1.0 1.0 ns tpae Ragister preset time 27 3.0 4.0 ns fora Register clear time 2.7 3.0 4.0 ns tpia PIA delay (5) 2.4 1.0 2.0 ns ti pa Low-power adder (6) 10.0 11.0 13.0 ns Altera Corporation 557MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies tor both global and array clocking. (2) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (3) The fy values represent the highest frequency for pipelined data. (4) Operating conditions: Vecro = 3.3 V + 10% for commercial and industrial use. (5) For EPM70648-5, EPM70645-6, EPM71288-6, EPM71608-6, EPM71608-7, EPM7192S-7, and EPM72568-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (6) The f;p4 parameter must be added to the fy an, trace fice tact, fen, and tspxp parameters for macrocells running in the low-power mode. Tables 34 and 35 show the EPM7256S AC operating conditions. Table 34. EPM7256S8 External Timing Parameters Symbol Parameter Conditions Speed Grade Unit 7 -10 15 Min | Max | Min | Max | Min | Max tpp1 Input to non-registered output | C1 =35 pF 7.5 10.0 15.0 ns tpp2 /O input to non-registered C1 =35 pF 7.5 10.0 15.0 ns output tsu Global clock setup time 3.9 7.0 11.0 ns ty Global clock hold time 0.0 0.0 0.0 ns tesu Global clock setup time of fast 3.0 3.0 3.0 ns input tey Global clock hold time of fast 0.0 05 0.0 ns input teoi Global clock to output delay C1 =35 pF 47 5.0 8.0 ns tou Global clock high time 3.0 4.0 5.0 ns tet Global clock low time 3.0 40 5.0 ns tasu Array clock setup time 08 2.0 40 ns tay Array clock hold time 19 3.0 40 ns taco Array clock to output delay Ci =35 pF 7.8 10.0 15.0 ns tach Array clock high time 3.0 4.0 6.0 ns tac. Array clock low time 3.0 4.0 6.0 ns toby Output data hold time after Ci =35 pF (7) 1.0 1.0 1.0 ns clock tent Minimum global clock period 7.8 10.0 13.0 ns font Maximum internal global clock | (2) 128.2 100.0 76.9 MHz frequency tacnT Minimum array clock period 7.8 10.0 13.0 ns Tacnt Maximum internal array clock | (2) 128.2 100.0 76.9 MHz frequency Tmax Maximum clock frequency (3) 166.7 125.0 100.0 MHz 558 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 35. EPM7256S Internal Timing Parameters Symbol Parameter Conditions Speed Grade Unit 7 10 15 Min | Max | Min | Max | Min | Max tiny Input pad and buifer delay 0.3 05 2.0 ns fig VO input pad and buffer delay 0.3 05 2.0 ns Trin Fast input delay 3.4 1.0 2.0 ns toexp Shared expander delay 3.9 5.0 8.0 ns tpexp Parallel expander delay 11 0.8 1.0 ns tap Logic array delay 2.6 5.0 6.0 ns bac Logic control array delay 2.6 5.0 6.0 ns hoe Internal output enable delay 0.8 2.0 3.0 ns lon: Output butfer and pad delay | C1 =35 pF 0.5 1.5 4.0 ns lone Output butfer and pad delay | C1 = 35 pF (4) 1.0 2.0 5.0 ns fons Output butfer and pad delay | C1 = 35 pF 5.5 5.5 8.0 ns tng Output butfer enable delay Ci = 35 pF 4.0 5.0 6.0 ns lye Output butfer enable delay C1 = 35 pF 4) 45 5.5 7.0 ns lg Output butfer enable delay Ci = 35 pF 9.0 9.0 10.0 ns iy Output butfer disable delay [C1 =5 pF 4.0 5.0 6.0 ns touy Ragister setup time 1.4 2.0 4.0 ns ty Ragister hold time 1.6 3.0 4.0 ns trou Register setup time of tast 2.4 3.0 2.0 ns input tepy Ragister hold time of fast 0.6 0.5 1.0 ns input tap Register delay 1.1 2.0 1.0 ns fcome Combinatorial delay 1.1 2.0 1.0 ns hic Array clock delay 2.9 5.0 6.0 ns fey Ragister enable time 2.6 5.0 6.0 ns teros Global control delay 2.8 1.0 1.0 ns tpae Ragister preset time 27 3.0 4.0 ns fora Register clear time 27 3.0 4.0 ns tpia PIA delay (5) 3.0 1.0 2.0 ns ti pa Low-power adder (6) 10.0 11.0 13.0 ns Altera Corporation 559MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies tor both global and array clocking. (2) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (3) The fy values represent the highest frequency for pipelined data. (4) Operating conditions: Vecro = 3.3 V + 10% for commercial and industrial use. (5) For EPM70648-5, EPM70645-6, EPM71288-6, EPM71608-6, EPM71608-7, EPM7192S-7, and EPM72568-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (6) The f;p4 parameter must be added to the fy an, trace fice tact, fen, and tspxp parameters for macrocells running in the low-power mode. Power Consumption 560 Supply power (P) versus frequency (fax in MHz) for MAX 7000 devices is calculated with the following equation: P= Pint + Plo=Icanr Ver + Pio The Pjg value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices) in this data book. The Iccpyy value, which depends on the switching frequency and the application logic, is calculated with the following equation: IccInt = Ax MCron +Bx (MCpry _ MCron) +Cx MCysep x fax x togic The parameters in this equation are shown below: MCron = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS II Report File (.rpt) MCpry = Number of macrocells in the device MCysgp = Total number of macrocells in the design, as reported in the MAX+PLUS II Report File (.rpt) fax = Highest clock frequency to the device togic = Average ratio of logic cells toggling at each clock (typically 0.125) A,B,C = Constants, shown in Table 36 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Altera Corporation Table 36. MAX 7000 Ip Equation Constants Device A B C EPM7032 1.87 0.52 0.144 EPM7064 1.63 0.74 0.144 EPM7096 1.63 0.74 0.144 EPM7128E 1.17 0.54 0.096 EPM7160E 1.17 0.54 0.096 EPM7192E 1.17 0.54 0.096 EPM7256E 1.17 0.54 0.096 EPM7032S 0.93 0.40 0.040 EPM7064S 0.93 0.40 0.040 EPM7128S 0.93 0.40 0.040 EPM7160S 0.93 0.40 0.040 EPM7192S 0.93 0.40 0.040 EPM7256S 0.93 0.40 0.040 This calculation provides an Icc estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual I values should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. 561MAX 7000 Programmable Logic Device Family Data Sheet Figure 14 shows typical supply current versus frequency for MAX 7000 devices. Figure 14. iee vs. Frequency far MAX 7000 Devices {Part 1 of 2) EPM7032 EPM7064 tool Yoo =5.0V sol Voo=5.0V Room Temperature Room Temperature 151 5 MHz 1515 MHz ns 140- ~ > Aigh Spend . 200 F ~ Aloh Speed TWoical | * ypical loc Typical loc yo, Active (mA) Active (mA) 60 2 MHz 60 2 MHz Law Power Low Power 1 1 L L 1 1 1 1 0 60 100 150 200 0 a0 100 150 200 Frequency (MHz) Frequency (MHz) EPM7096 Veo = 5.0 V Room Temperature 125 MHz Typical log aso Active (mA) 150 Low Power 1 1 i a 50 100 1650 Frequency (MHz) 562 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Figure 14. ire vs. Frequency for MAX 7000 Devices (Part 2 of 2) EPM7128E EPM7160E 500 500 Veo =5.0V Veo =5.0V Room Temperature Room Temperature 4007 100 MHz 125 MHz Typical lag 300F Typical log Active (mA) .. Active (mA) High Gpced *- Hint) Seesd 200 55.5 MHz | 47 6 MHz ns . 100 + ~ . ha Bowser * Law Bower 1 1 1 1 1 1 1 1 0 50 100 150 200 0 50 160 150 200 Frequency (MHz) Frequency (MHz) EPM7192E EPM7256E 500 750 Voc = 5.0 90 9 MHz Veo = 5.0 Room Temperature Room Temperature 400 + E00 - 80 9 MHz Typical lag 300 Typical loc se aged Activa (mA) Active (mA) _ 300 150 bess Boner 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 26 50 76 100 128 0 26 50 78 100 128 Frequency (MHz} Frequency (MHz) Altera Corporation 563MAX 7000 Programmable Logic Device Family Data Sheet Figure 15 shows typical supply current versus frequency for MAX 7000S devices. Figure 15. tne vs. Frequency for MAX 7000S Devices (Part 7 of 2) EPM7032S 60 50 Typical lec 40 Active (mA) 30 20 10 EPM7128S 280 240 200 Typical loc t0 Active (mA) 120 80 40 564 EPM7064S Veo = 5.0V r Room Temperature L 142 9 MH= me Typical loc Naot i u a t a. TET Dee Active (mA) a 58 8 MH= K Lou Pewer 1 1 | 1 0 50 100 150 200 Frequency (MHz) EPM7160S L Veg = 5.0V Room Temperature 147 1 MHz Typical loc Speed Active (mA) Pe 58 2 MH= c faa Pawar 1 1 1 1 0 50 100 150 200 Frequency (MHz) 120 100 80 60 40 20 300 F Voc = 5.0 V r Room Temperature 176 4 MHz ~ High Speed a 58.5 MH= Law Power 1 1 1 1 100 150 200 Frequency (MHz) Voe = 5.0V Room Temperature 149.3 MHz > Law Power 1 1 1 1 100 150 200 Frequency (MHz) Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Figure 15. Ipe vs. Frequency for MAX 70008 Devices (Part 2 of 2) EPM?192S EPM7?256S Vor =5.0V Vog = 5.0 300 b Room Temperature ano t Room Temperature 125 0 MHz 128 2 MHz 240 . . io Speed 300 High Sovad Typical lon Typical loc Active (mA) 180 Active (mA) 200 7 ES 56 2 MHz yo 55 6 MHz %. BO - oy Beaver too F ~ baw Fewer 60 - 1 1 1 L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a 25 30 7a 100 125 a 25 30 75 100 125 Frequency (MHz) Frequency (MHz) D evi ce Tables 37 through 51 show the pin names and numbers for the pins in Pin-Outs each MAX 7000 device package. Table 37. EPM7032 & EPM7032S Dedicated Pin-Outs Pin Name 44-Pin PLCC 44-Pin PQFP/TOFP (7) INPUT/GCLK1 43 37 INPUT/GCLRn 1 39 INPUT/OB1 44 38 INPUT/OBRZ/GCLK2 (2) |2 40 TDI (3) 7 TMS (3) 13 7 TCK (3) 32 26 TDO (3) 38 32 PDn (4) 3 4] GND 10, 22, 30, 42 4,16, 24, 36 VCC 3,15, 23, 35 9,17, 29, 41 No Connect (N.C.) - - Total User I/O Pins (5) | 36 36 Altera Corporation 565MAX 7000 Programmable Logic Device Family Data Sheet Table 38. EPM7032 & EPM76032S 1/0 Pin-Outs LAB Mc 44-Pin 44-Pin LAB Mc 44-Pin 44-Pin PLcc | POFP/TOFP (1) PLCC | POFP/TOFP (1) A 1 4 42 B 17 41 35 2 5 43 18 40 34 3 6 44 19 39 33 4 7 (3) 1 (3) 20 38 (3) 32 (3) 5 8 2 21 37 31 6 9 3 22 36 30 7 11 5 23 34 28 8 12 6 24 33 27 9 13 (3) 7 (3) 25 32 (3) 26 (3) 10 14 8 26 31 25 rT 16 10 27 29 23 12 17 1 28 28 22 13 18 12 29 27 21 14 19 13 30 26 20 15 20 14 31 25 19 16 21 15 32 24 18 Notes ta tables: (1) EPM70325 and EPM7032V devices are not available in the 44-pin PQFP package. (2) The GCLK2 function is available in MAX 7000S and MAX 7000E devices only. (3) This JTAG pin applies te MAX 7000S devices only and this pin may function as either a JTAG port or a user I/O pin. If the device is contigured te use the JTAG ports tor ISP, this pin is not available as a user I/O pin. (4) The PDn pin is available in EPM7032 devices only. (5) The user I/O pin count includes dedicated input pins and all 1/0 pins. 566 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 39. EPM7064 & EPM70648 Dedicated Pin-Outs Dedicated Pin 44-Pin 44-Pin 68-Pin 84-Pin 100-Pin 100-Pin PLCC TOFP PLCC (1) PLCC TOFP (2) | POFP (7) INPUT/GCLK1 43 37 67 83 87 83 INPUT/GCLRn 1 33 1 1 83 91 INPUT/OE1 44 38 68 84 88 30 INPUT/OEZ/GCLKz (3) [2 40 2 2 90 92 TDI (4) 7 1 12 14 4 6 TMs (4) 13 7 19 23 15 17 TCK (4) 32 26 50 62 62 64 Too (4) 38 32 57 71 73 75 GND 10,22,30, |4,16,24, |6, 16, 26,34, | 7, 19, 32, 38, 86, 11, 13, 28, 40, 42 36 38, 48, 58, 42,47,59, |26,43,59, |45, 61, 76, 66 72, 82 74,95 88, 97 VCCINT (5.0 V only) 3,15, 23,35 19,17,29, |3, 35 3,43 39,91 41,93 41 vecio (33 Var5.0Vv) |- - 11,21,31, |18, 26,38, 13,18, 34,51, |5, 20, 36,53, 43,53,63 1|53,66,78 |66, 82 68, 84 No Connect (N.C.) - - - - 1, 2,5, 7, 22, ]1, 2, 7, 9, 24, 24, 27,28, |26, 29, 30, 49, 50, 53, 51, 52, 55, 55, 70, 72, 57, 72, 74, 77,78 79, 80 Total User I/O Pins (5) = |32 32 48 64 64 64 Altera Corporation 567MAX 7000 Programmable Logic Device Family Data Sheet Table 40. EPM7064 & EPM7064S 1/0 Pin-Outs (44-Pin PLCC, 44-Pin TOFP & 68-Pin PLE Packages) LAB} MC 44-Pin 44-Pin 68-Pin LAB |} MC 44-Pin 44-Pin 68-Pin PLCC TOFP PLCC (7) PLCC TOFP PLCC /7) A {1 12 6 18 C 133 24 18 36 2 - - - 34 - - - 3 11 5 17 35 25 19 37 4 3 15 36 26 20 39 5 2 14 37 27 el 40 6 - - 13 38 s|- - Al 7 - - - 39 - - - 8 7 (4) 1 (4) 12 (4) 40 28 22 42 9 - - 10 41 29 23 44 10 - - - 42 - - - 11 6 44 9 43 - - 45 12 - - 8 44 - - 46 13 |- - 7 45 |[- - 47 14 5 43 5 46 31 25 49 15 - - - 47 - - - 16 4 42 4 48 32 (4) 26 (4) 50 (4) B |17 21 15 33 D |49 33 27 51 18 - - - 50 - - - 19 20 14 32 51 34 28 52 20 19 13 30 52 36 30 54 21 18 12 29 53 37 31 55 22 - - 28 54 - - 56 23 - - - 55 - - - 24 17 11 27 56 38 (4) 32 (4) 57 (4) 25 16 10 25 57 39 33 59 26 - - - 58 - - - 27 - - 24 59 - - 60 28 - - 23 60 - - 61 23 - - 22 61 - - 62 30 14 8 20 62 40 34 64 31 - - - 63 - - - 32 13 (4) 7 (4) 19 (4) 64 At 35 65 568 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 41. EPM7064 & EPM7064S 1/0 Pin-Outs (84-Pin PLO, 100-Pin TQFP & 100-Pin POFP Packages) LAB | MC 84-Pin 100-Pin | 100-Pin | LAB MC 84-Pin 100-Pin 100-Pin PLCC TQOFP (2) | POFP (1) PLCC TOFP (2) POFP (7) A {1 22 14 16 Cc {33 44 40 42 2 21 13 15 34 45 Al 43 3 20 12 14 35 46 42 44 4 18 10 12 36 48 44 46 5 17 9 11 37 49 45 47 6 16 8 10 38 50 46 48 7 15 6 8 39 51 47 49 8 14 (4) 4 (4) 6 (4) 40 52 48 50 9 j2 100 4 41 54 52 54 10 11 99 3 42 55 54 56 11 10 98 100 43 56 56 58 12 9 97 939 44 57 57 59 13 8 96 98 45 58 58 60 14 6 94 96 46 60 60 62 15 5 93 95 47 61 61 63 16 4 92 94 48 62 (4) 62 (4) 64 (4) B 17 41 37 39 D 49 63 63 65 18 40 36 38 50 64 64 66 19 39 35 37 51 65 65 67 20 37 33 35 52 67 67 69 21 36 32 34 53 68 68 70 22 35 31 33 54 69 69 71 23 34 30 32 55 70 71 73 a4 33 29 31 56 71 (4) 73 (4) 75 (4) 25 31 25 27 57 73 75 7? 26 30 23 25 58 74 76 78 27 29 21 23 59 75 79 81 28 28 20 22 60 76 80 82 29 ef 19 21 61 7? 81 83 30 25 17 19 62 79 83 85 31 24 16 18 63 80 84 86 32 23 (4) 15 (4) 17 (4) 64 81 85 87 Altera Corporation 569MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) EPM70645 devices are not available in the 100-pin PQFP package or 68-pin PLCC packages. (2) EPM7064 devices are not available in the 100-pin TQFP package. (3) The GcCLK2 function is available in MAX 70005 and MAX 7000E devices only. (4) This JTAG pin applies te MAX 7000S devices only and this pin may function as either a TAG port or a user I/O pin. If the device is contigured te use the JTAG ports for ISP, this pin is not available as a user I/O pin. (5) The user I/O pin count includes dedicated input pins and all 1/O pins. 570 Table 42. EPM7096 Dedicated Pin-Outls Dedicated Pin 68-Pin PLCC 84-Pin PLCC 100-Pin POFP INPUT/GCLK1 67 83 83 INPUT/GCLRn 1 1 91 INPUT/OE1 68 84 90 INPUT/OE2 2 2 92 GND 6, 16, 26, 34, 7, 19, 32, 42, 47, |13, 28, 40, 45, 38,48,58,66 |59, 72, 82 61, 76, 88, 97 VCCINT (5.0 V Only) 3, 35 3,43 41,93 VCCIO (3.3 V or 5.0 V) 11,21, 31,43, |13,26,38,53, 1/5, 20,36, 53, 68, 53, 63 66, 78 84 No Connect (N.C.) - 6, 39, 46, 79 9, 24, 37, 44, 57, 72, 85, 96 Total User I/O Pins (1) 48 60 f2 Note: (1) The userI/O pin count includes dedicated input pins and all 1/O pins. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 43. EPM7096 1/0 Pin-Outs (Part 1 of 2) LAB Mc 68-Pin | 84-Pin | 100-Pin | LAB Mc 68-Pin | 84-Pin | 100-Pin PLCC PLCC PQFP PLCC PLCC POFP A 1 13 16 8 B 17 23 28 23 2 - - - 18 - - - 3 - 15 7 19 22 27 22 4 12 14 6 20 - - 21 5 - - 4 21 20 25 19 6 10 12 3 22 - 24 18 7 - - - 23 - - - 8 9 14 2 24 19 23 17 9 8 10 1 25 18 22 16 10 - - - 26 - - - 14 - 9 100 27 17 21 15 12 7 8 99 28 - 20 14 13 - - 98 29 15 18 12 14 5 5 95 30 - - 11 15 - - - 31 - - - 16 4 4 94 32 14 17 10 Altera Corporation 571MAX 7000 Programmable Logic Device Family Data Sheet Table 43. EPM7096 1/0 Pin-Outs (Part 2 of 2) LAB Mc 68-Pin | 84-Pin | 100-Pin LAB Mc 68-Pin | 84-Pin | 100-Pin PLCC PLCC PQFP PLCC PLCC POFP Cc 33 33 4 39 E 65 46 57 58 34 - - - 66 - - - 35 32 40 38 67 47 58 59 36 - - 35 68 - - 60 37 30 37 34 69 49 60 62 38 - 36 33 70 - 61 63 39 - - - 71 - - - 40 29 35 32 72 50 62 64 44 28 34 31 73 51 63 65 42 - - - 74 - - - 43 27 33 30 75 52 64 86 44 - - 29 76 - 65 67 45 25 31 27 77 54 67 69 46 - 30 26 78 - - 70 47 - - - 79 - - - 48 24 29 25 80 55 68 71 D 49 36 44 42 F 81 56 69 73 50 - - - 82 - - - 51 37 45 43 83 - 70 74 52 - - 46 84 57 71 75 53 39 48 47 85 - - 77 54 - 49 48 86 59 73 78 55 - - - 87 - - - 56 40 50 49 88 60 74 79 57 A 51 50 89 61 75 80 58 - - - 30 - - - 59 42 52 51 31 - 76 81 60 - - 52 92 62 77 82 61 44 54 54 93 - - 83 62 - 55 55 94 64 80 86 63 - - - 95 - - - 64 45 56 56 96 65 81 87 572 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 44. EPM7126E & EPM7128S Dedicated Pin-Outs Dedicated Pin 84-Pin PLCC 100-Pin POFP 100-Pin TOFP 160-Pin POFP (1), (2) INPUT/GCLK1 83 89 87 139 INPUT/GCLRn 1 91 89 141 INPUT/OE1 84 90 88 140 INPUT /OE2/GCLKZ 2 92 90 142 TDI (3) 14 6 4 9 TMs (3) 23 17 15 22 TCK (3) 62 64 62 99 Toe (3) 71 75 73 112 GNDINT 42, 82 40, 88 38, 86 60, 138 GNDIO 7,19, 32,47, 59, 72|13,28,45,61,76, |11, 26,43,59, 74, |17, 42, 66, 95,113 97 95 148 VCCINT (5.0 V only) 3,43 41,93 39, 91 61, 143 vecro (3.3 Vor 5.0 V) 13, 26, 38, 53, 66, 78 5, 20, 36, 53, 68, 84 3, 18, 34, 51, 66, 82 8, 26, 55, 79, 104, 133 No Connect (N.C.) 1,2,3,4,5,6,7, 34 35, 36, 37, 38, 39, 40 44, 45, 46, 47, 74, 75 76, 77, 81, 82, 83, 84, 85, 86, 87, 114, 115, 116, 117, 118, 119 120, 124, 125, 126 127, 154, 155, 156, 157 Total User I/O Pins (4) 64 80 80 96 Altera Corporation 573MAX 7000 Programmable Logic Device Family Data Sheet Table 45. EPM7128E & EPM7128S 1/0 Pin-Outs (Part 1 af 2) LAB | MC | 84-Pin |100-Pin} 100-Pin | 160-Pin] LAB | MC | 84-Pin | 100-Pin | 100-Pin | 160-Pin PLCC | POFP TOFP POFP PLCC | POFP TOFP PQFP (1), (2) (1), (2) A lt - 4 2 160 c [33 [- 27 25 44 2 - - - - 34. | - - - 3 12 3 1 159 35 (31 26 24 33 4 - - - 158 36s - - 32 5 11 2 100 153 37 ~-|[30 25 23 31 6 10 1 99 152 38 [29 24 22 30 7 - - - - 39s - - - 8 9 100 98 151 40 [28 23 21 29 9 - 99 97 150 44 - 22 20 28 to |= - - - 42 |- - - - 11 [8 98 96 149 43 |27 21 19 27 12 |- - - 147 44 |- - - 25 13 [6 96 94 146 45 [25 19 17 24 14 [5 95 93 145 46 [24 18 16 23 is [- - - - 47 |- - - - ie |4 94 92 144 4g |23(3) |17(3) |15(3) |22(3) B |17 |22 16 14 21 D |49 [41 39 37 59 18 |- - - - 50 | - - - 19 |21 15 13 20 51 40 38 36 58 20. |- - - 19 52 |= - - 57 21 |20 14 12 18 53 =| 39 37 35 56 22 |- 12 10 16 54 | 35 33 54 23. =|- - - - 55 |- - - - 24 1/18 11 9 15 56 | 37 34 32 53 25 17 10 8 14 57 (36 33 31 52 en - - - 58 | - - - 27 | 16 9 7 13 59 (35 32 30 51 28 |- - - 12 60. |- - - 50 29 (| 15 8 6 11 61 34 31 29 49 30. (|- 7 5 10 62 |- 30 28 48 31 |- - - - 63 s|- - - - 32 |14(3) |6(3) = |4(3) 9 (3) 64 = [33 29 27 43 574 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 45. EPM7128E & EPM71288 1/0 Pin-Outs (Part 2 of 2) LAB | MC | 84-Pin | 100-Pin| 100-Pin | 160-Pin] LAB | MC | 84-Pin | 100-Pin | 100-Pin |160-Pin PLCC | POFP TOFP PQFP PLCC | POFP TOFP POFP (1), (2) (1), (2) E jes [44 42 40 62 G |s7_ es 65 63 100 66 |- - - - 98 | - - - - 67 | 45 43 At 63 99 | e4 66 64 101 68 |- - - 64 joo |- - - 102 69 |46 44 42 65 jo1 [65 67 65 103 70 |= 46 44 67 102 |- 69 67 105 7 Ie - - - jos |- - - - 72 |48 47 45 68 104 67 70 68 106 73 |49 48 46 69 105 |68 71 69 107 74 |- - - - joe |- - - - 75 =|50 4g 47 70 107 |69 72 70 108 76 |= - - 71 jos |- - - 109 77. 51 50 48 72 109 170 73 71 110 78 |- 51 49 73 tio |- 74 72 111 79 |- - - - ee - - - 80. | 52 52 50 78 112 |713) [75 (3) |733) = |112:(3) F lat |- 54 52 80 H |iig |- 77 75 121 go |- - - - 114 |- - - - 83 54 55 53 88 115 173 78 76 122 84 |- - - 89 116 |- - - 123 85 55 56 54 90 117. 174 79 77 128 s 56 57 55 91 tis [75 80 78 129 87 |= - - - tig |- - - - ga 57 58 56 92 120 |76 81 79 130 gg |- 59 57 93 121 |- 82 80 131 90 |- - - - 122 |- - - - 91 |58 60 58 94 123 177 83 81 132 92 |- - - 96 124 |- - - 134 93 60 62 60 97 125 179 85 83 135 94 61 63 61 98 126 |80 86 84 136 95 |- - - - 127 |- - - - 96 |62(3) |64/3) |62(3) |99 (3) j28 81 87 85 137 Altera Corporation 575MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) Acomplete thermal analysis should be performed before committing a design to this device package. EPM?7128E devices are not available in the 100-pin TQFP package. This JTAG pin applies toe MAX 7000S devices only and this pin may function as either a JTAG port or a user 1/0 pin. It the device is contigured to use the JTAG ports for boundary-scan testing or for ISP, this pin is not available as a user I/O pin. (4) The user I/O pin count includes dedicated input pins and all I/O pins. Table 46. EPM7160E & EPM7160S Dedicated Pin-Ouis Dedicated Pin 84-Pin PLCC 100-Pin TOFP 100-Pin POFP (3) 160-Pin POFP (1), (2) INPUT/GCLK1 83 87 89 139 INPUT/GCLRn 1 89 91 141 INPUT /OE1 84 88 90 140 INPUT /OBZ/GCLKZ 2 90 92 142 TDI (4) 14 4 6 9 TMS (4) 23 15 17 22 TOK (4) 62 62 64 99 TDo (4) 71 73 75 112 GND 7,19, 32,42,47, |38, 86,11, 26,43, |13, 28, 40,45,61, |17, 42, 60, 66, 95 59, 72, 82 59, 74,95 76, 88, 87 113, 138, 148 VCCINT (5.0 only) 3,43 39,91 41, 93 61, 143 VCC To (3.3 V or 5.0 V) 13, 26, 38, 53, 66 78 3, 18, 34, 51, 66, 82 5, 20, 36, 53, 68, 84 8, 26, 55, 79, 104, 133 No Connect (N.C.) 6, 39, 46, 79 1,2,3,4,5, 6, 34,35 36, 37, 38, 39, 40, 45, 46, 47, 74, 75, 76, 81 82, 83, 84, 85, 86, 87, 115, 116, 117, 118 119, 120, 124, 125 126, 127, 154, 155 156, 157 Total User I/O Pins (5) 60 80 80 100 576 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 47. EPM7160E & EPM7168S 1/0 Pin-Outs (Part f of 3) LAB) MC | 84-Pin | 100-Pin | 100-Pin | 160-Pin} LAB | MC | 84-Pin | 100-Pin | 100-Pin | 160-Pin PLCC | TOFP |PQFP (3)| POFP PLCC | TOFP | POFP (3)| POFP (1), (2) (1), (2) A 1 11 100 2 158 Cc 133 - 19 21 27 2 - - - - 34 [= - - - 3 190 99 1 153 35 25 17 19 25 4 - - - - 36 - - - - 5 - - - 152 37 - - - 24 6 - 98 100 151 38 24 16 18 23 7 - - - - 39 - - - - 8 9 97 99 150 40 23 (4) 115 (4) 17 (4) 22 (4) 9 8 S36 98 149 41 - 10 le 16 10 - - - - 42 - - - - 11 5 94 96 147 43 20 12 14 18 12 - - - - 44 - - - - 13 - - - 146 45 - - - 19 14 - 93 95 145 46 21 13 15 20 15 - - - - 47 - - - - 16 4 92 94 144 48 22 14 16 21 B 117 18 9 11 15 D |49 - - - 48 18 I- - - - 50 - - - - 19 17 8 10 14 51 33 28 30 44 20 |- - - - 52 - - - - 21 - - - 13 53 - af 29 43 22 - 7 9 le 54 31 25 27 41 23. |- - - - 55 - - - - 24 16 6 8 11 56 30 24 26 33 25 15 5 7 10 57 - - - 32 26 O|- - - - 58 - - - - 27 14 (4) |4 (4) 6 (4) 9 (4) 59 29 23 25 31 28 Oi- - - - 60 - - - - 29 - - - 7 61 - 22 24 30 30 - 2 4 160 62 28 21 23 29 31 - - - - 63 - - - - 32 12 1 3 159 64 27 20 22 28 Altera Corporation 577MAX 7000 Programmable Logic Device Family Data Sheet Table 47. EPM7160E & EPM77608 1/0 Pin-Outs (Part 2 of 3) LAB) MC | 84-Pin | 100-Pin | 100-Pin | 160-Pin) LAB | MC | 84-Pin | 100-Pin | 100-Pin | 160-Pin PLec | TOFP |PQFP (3)| POFP PLec | TOFP |POFP (3)} POFP (1), (2) (1), (2) E les [- - - 59 a ls7 [- - - 73 66 |- - - - 93_s| - - - 67 (| 41 37 39 58 99 =|[52 49 51 77 68 |- - - - too |- - - - 69 |- 36 38 57 toi |= 50 52 78 70 |40 35 37 56 to2 [54 52 54 80 71 Of - - - 103 |- - - - 72 |37 33 35 54 104 [55 53 55 88 73 I- - - 53 105 |- - - 89 74 [- - - - 106 |- - - - 75 |36 32 34 52 107 |56 54 56 90 76 |- - - - tog |- - - - 77 |- 31 33 51 109 |- 55 57 91 78 |35 30 32 50 110. [57 56 58 92 79 |- - - - Wi [= - - - so |34 29 31 49 112 158 57 59 93 F lsi |- - - 62 H |113 |= 58 60 94 a2 |- - - - 14 J- - - - 8344. 40 42 63 115 |60 60 62 96 84 - - - - 116 J- - - - rn 41 43 64 117 J- - - 97 86 | 45 42 44 65 tis et 61 63 98 87 |- - - - 119 J- - - - 88 | 48 44 46 67 120 |62(4) |62(4) |64(4) [99 (4) sg - - - 68 121 |- 67 69 105 90 |- - - - 122 |- - - - 91 |49 45 47 69 123. |65 65 67 103 g2 |- - - - 124 |- - - - 93 |- 46 48 70 125 |- - - 102 94 |50 47 49 71 126 |64 64 66 101 95 |- - - - 127 |- - - - 96 51 48 50 72 128 |63 63 65 100 578 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 47. EPM7160E & EPM7168S 1/0 Pin-Outs (Part 3 of 3) LAB) MC | 84-Pin | 100-Pin | 100-Pin | 160-Pin} LAB | MC | 84-Pin | 100-Pin | 100-Pin | 160-Pin PLec | TOFP |ParFP (3)| POFP PLec | TOFP | PQFP (3)| POFP (1), (2) (1), 2) | |129 |67 68 70 106 J 145 74 77 79 123 130 |- - - - 146 [- - - - 131 68 69 71 107 147 75 78 80 128 132 |- - - - 148 [- - - - 133 |- - - 108 149 - - - 129 134 |- 70 72 109 150 [- 79 81 130 ee - - - 151 [- - - - 136 |69 71 73 110 152 76 80 82 131 137 170 72 74 111 153 [77 at 83 132 138 |- - - - 154 [- - - - 139 [71 (4) |734) |75 (4) [112 (4) 155 [80 83 85 134 140 |- - - - 156 [- - - - 141 |- - - 114 157. [- - - 135 142 |- 75 77 121 158 - 84 86 136 143 [- - - - 159 [- - - - 144 173 76 78 122 160 [at 85 87 137 Notes fo tables: EPM/?7160E devices are not available in the 100-pin TQFP package. A complete thermal analysis should be performed before committing a design to this device package. EPM/71605 devices are not available in the 100-pin PQFP package. This JTAG pin applies to MAX 7000S devices only and this pin may function as either a JTAG port ora user 1/O pin. If the device is contigured to use the JTAG ports for BST or with ISP, this pin is not available as a user I/O pin. The user 1/O pin count includes dedicated input pins and all 1/O pins. () (2) (3) (4) (5) Altera Corporation 579MAX 7000 Programmable Logic Device Family Data Sheet Table 48. EPM7192E & EPM7192S Dedicated Pin-Outs Dedicated Pin 160-Pin PGA /7) 160-Pin POQFP INPUT/GCLK1 M8 139 INPUT/GCLRn N8 141 INPUT/OE1 P8 140 INPUT/OBZ/GCLK2 R8 142 TDI (2) P9 146 TMS (2) G15 23 TCK (2) Ge 98 TDO (2) R7 135 GND C4, C6, C11, D7, DS, D13, G4, H12, J4, |3, 18, 32, 47, 57, 64, 66, 81, 96, 111, 126, M7, Mg, M13, N4, N11 138, 143, 148 VCCINT (5.0 V Only) C7, C9, N7, N9 56, 65, 137, 144 VCCTO (3.3 V or 5.0 V) 5, C10, C12, D3, G12, H4, J12, M3, N5, N12 10, 25, 40, 55, 74, 89, 103, 118, 133, 155 No Connect (N.C.) Al, A2, A14, A15, Ri, R2, R14, R15 1, 11, 39,54, 67, 82, 110, 120 Total User I/O Pins (3) |120 120 Table 49. EPM7192E & EPM7192S i/0 Pin-Outs (Part 1 of 3) LAB MC | 160-Pin | 160-Pin| LAB MC | 160-Pin | 160-Pin} LAB MC | 160-Pin | 160-Pin PGA (1)| POFP PGA (1)| POFP PGA (1) | PQFP A 1 M12 156 B |17 Li4 8 Cc 133 Hi4 21 2 - - 18 - - 34 - - 3 Pi 154 19 M14 7 35 J13 20 4 - - 20 - - 36 - - 5 P12 153 21 M15 6 37 H15 19 6 P10 152 22 N14 5 38 J15 17 7 - - 23 - - 39 - - 8 Ri2 151 24 N15 4 40 J14 16 9 Nio 150 25 P15 2 41 K15 15 10 - - 26 - - 42 - - 11 Ri 149 27 N13 160 43 K13 14 12 - - 28 - - 44 - - 13 Rio 147 29 P14 159 45 Lis 13 14 PS (2) | 146 (2) 30 P13 158 46 K14 12 15 - - 31 - - 47 - - 16 Rg 145 32 R13 157 48 L13 9 580 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 49. EPM7192E & EPM7192S 1/0 Pin-Outs (Part 2 of 3) LAB | MC | 160-Pin | 160-Pin|] LAB | MC | 160-Pin|160-Pin} LAB | MC | 160-Pin | 160-Pin PGA (7) | POFP PGA (7) | PQFP PGA (7) | PQFP D 49 D15 33 F 81 D8 60 H 113 A3 76 50 - - 82 - - 114 - - 51 E15 31 83 AS 59 115 B4 7? 52 - - 84 - - 116 - - 53 E14 30 85 c8 58 117 B3 78 54 F15 29 86 BS 53 118 C3 79 55 - - 87 - - 119 - - 56 F13 28 88 AiO 52 120 B2 80 57 G14 27 89 Bio 51 121 Bi 83 58 - - 90 - - 122 - - 59 Fi4 26 91 All 50 123 Ce 84 60 - - 92 - - 124 - - 61 G13 24 93 B11 49 125 C1 85 62 G15 (2) |23 (2) 94 Al2 48 126 |De 86 63 - - 95 - - 127 - - 64 H13 22 96 Al3 46 128 D1 87 E 65 Ble 45 G 97 A8 61 | 129 E3 88 66 - - 98 - - 130 - - 67 B13 44 99 B8 62 131 F3 30 68 - - 100 - - 132 - - 69 C13 43 101 AZT 63 133 E2 91 70 Bl4 42 102 AG 68 134 Fe 92 71 - - 103 - - 135 - - 72 C14 A 104 B7 69 136 E1 93 73 Di2 38 105 AS 70 137 G3 94 74 - - 106 - - 138 - - 75 Bis 37 107 B 71 139 FA 95 76 - - 108 - - 140 - - 77 D1i4 36 109 Ad 72 141 Gl 97 78 C15 35 110 =| BS 73 142 |G2 (2) |98 (2) 79 - - 111 - - 143 - - 80 E13 34 112 D4 75 144 H1 99 Altera Corporation 581MAX 7000 Programmable Logic Device Family Data Sheet Table 49. EPM7192E & EPM71928 1/0 Pin-Outs (Part 3 of 3) LAB MC | 160-Pin| 160-Pin| LAB MC | 160-Pin| 160-Pin] LAB MC | 160-Pin | 160-Pin PGA (7) | POFP PGA (7)}| POFP PGA (7) | POFP J 4145) THe 100 K |iei [Le 113 L |177 [Rs 125 146 [- - 162 [- - 178 [- - 147 [J 101 163 [Nt 114 179 |[R4 127 148 [- - 164 [- - 180 |- - 149 [H3 102 165 |[L3 115 1ei [M4 128 150 [J3 104 166 [PI 116 182 [RS 129 151. [- - 167 [- - 183 [- - 152. [Kt 105 168 [M2 117 184 [P5 130 153 [J2 106 169 -|[N2 119 185 |Re 131 154 [- - 170 [- - 1s6[- - 155 [K2 107 171 [Pe 121 187 [Pe 132 156 [- - 172 |- - 18g [- - 157 -[K3 108 173 [N3 122 189 |N 134 158 [Lt 109 174 [Ps 123 190 =[R7 (2) [135 (2) 159 [- - 175 [- - igi [- - 160 [mi 112 176 |[P4 124 192 |P7 136 Notes to tables: (1) EPM/71925 devices are not available in the 160-pin PGA package. (2) This JTAG pin applies te MAX 7000S devices only and this pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for ISP, this pin is not available as a user I/O pin. (3) The user I/O pin count includes dedicated input pins and all 1/O pins. 582 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 50. EPM7256E & EPM7256S8 Dedicated Pin-Outs Dedicated Pin 160-Pin POFP (7), (2) 192-Pin PGA (2) 208-Pin ROFP/POFP (3) INPUT/GCLK1 139 P9 184 INPUT/GCLRn 141 R9 182 INPUT/OE1 140 TS 183 INPUT/OEZ /GCLK2 142 Us 181 TDI (4) 146 U10 176 TMs (4) 23 H1i5 127 TCK (4) 98 H3 30 Too (4) 135 U8 189 GND 3, 18, 32, 47,57, 64,66, |C7, C13, D4, D8, D10, 14, 32, 50, 72, 75, 82, 94, 81,96, 111, 126, 138, 143, 148 G14, H4, K14, L4, P8, P10, P15, R4, R14 116, 134, 152, 174, 180 185, 200 VCCINT (5.0 V only) 56, 65, 137, 144 D7, D11, P7, P11 74, 83, 179, 186 Vecro (3.3 Vor 5.0 V) 10, 25, 40, 55, 74, 89, 103 C5, C11, D014, G4, H14, 5, 23, 41, 63, 85, 107, 125 118, 133, 155 K4,L14, P3, R5, R14 143, 165, 191 No Connect (N.C.) - - 1,2, 51, 52, 53, 54, 108, 104, 105, 106, 155, 156 157, 158, 207, 208 Total User I/O Pins (5) 128 160 160 Altera Corporation 583MAX 7000 Programmable Logic Device Family Data Sheet Table 51. EPM7256E & EPM72568 1/0 Pin-Outs (Part 1 of 5) LAB MC | 160-Pin | 192-Pin | 208-Pin LAB MC | 160-Pin | 192-Pin | 208-Pin POFP | PGA (2) | ROFP/POFP POFP | PGA (2) | ROFP/POFP (1), (2) (1), (2) (3) A 1 2 U17 153 Cc 33 39 B17 108 2 - - - 34 - - - 3 1 R16 154 35 38 Ci5 109 4 - - - 36 - - - 5 160 P14 159 37 37 C17 110 6 - U16 160 38 - C16 111 7 - - - 39 - - - 8 159 R15 161 40 36 D17 112 9g 158 U15 162 At 35 Di5 113 10 - - - 42 - - - 11 157 T15 163 43 34 E17 114 12 - - - 44 - - - 13 156 U14 164 45 33 Di6 115 14 - U13 166 AG - E15 117 15 - - - 47 - - - 16 154 714 167 48 31 Fi 118 B 17 12 N17 141 D 49 49 Al4 92 18 - - - 50 - - - 19 11 M16 142 51 48 Bi2 93 20 - - - 52 - - - 21 9 M15 144 53 46 Bi3 95 22 - P17 145 54 - AI5 96 23 - - - 55 - - - 24 8 N16 146 56 45 B14 97 25 7 R17 147 57 44 A16 98 26 - - - 58 - - - 27 6 P16 148 59 43 G14 99 28 - - - 60 - - - 29 5 T17 149 61 42 Bi 100 30 - Nis 150 62 - B15 101 31 - - - 63 - - - 32 4 T16 151 64 Al Al7 102 584 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 51. EPM7256E & EPM7256S 1/0 Pin-Outs (Part 2 of 5) LAB MC | 160-Pin | 192-Pin | 208-Pin LAB MC | 160-Pin | 192-Pin | 208-Pin POFP | PGA (2) | ROFP/POFP POFP | PGA (2) | ROFP/POFP (1), (2) (1), (2) (3) E 65 153 Ui2 168 G 97 30 E16 119 66 - - - 98 - - - 67 152 R13 169 99 29 F7 120 68 - - - 100 - - - 69 151 U11 170 101 28 F15 121 70 - T13 171 102 - Gi6 122 71 - - - 103 - - - ve 150 T11 172 104 27 G15 123 73 149 Tle 173 105 26 G17 124 74 - - - 106 - - - 75 147 Ri2 175 107 24 H17 126 76 - - - 108 - - - 77 146 (4) |U10 (4) 1176 (4) 109 23 (4) H15 (4) 1127 (4) 78 - R10 177 110 - J17 128 79 - - - 111 - - - 80 145 T10 178 112 22 H1i6 129 F 81 21 J16 130 H 113 60 cg 79 82 - - - 114 - - - 83 20 J15 131 115 59 DS 80 84 - - - 116 - - - 85 19 K17 132 117 58 C10 81 86 - J14 133 118 - A10 84 87 - - - 1190 J- - - 88 17 K16 135 120 54 Al 86 89 16 K15 136 121 53 Bid 87 90 - - - 122 - - - 91 15 Li7 137 123 52 Al2 88 92 - - - 124 - - - 93 14 Li6 138 125 51 B11 89 94 - M17 139 126 - Al3 90 95 - - - 127 - - - 96 13 L15 140 128 50 C12 91 Altera Corporation 585MAX 7000 Programmable Logic Device Family Data Sheet Table 51. EPM7256E & EPM72568 1/0 Pin-Outs (Part 3 of 5) LAB MC | 160-Pin | 192-Pin 208-Pin LAB MC | 160-Pin | 192-Pin 208-Pin POFP | PGA (2) | ROFP/POFP POFP | PGA (2) | ROFP/POFP (1), (2) (1), (2) (3) 129 128 U6 197 J 145 100 J2 27 130 [- - - 146 [- - - 131 |129 T5 196 147 [101 J3 26 132 [- - - 148 [- - - 133 130 U?7 195 149 102 Kl 25 134 [- T 194 150 |[- J4 24. 135 [- - - 151 [- - - 136 131 T? 193 152 104 K2 22 137 132 R6 192 153 105 K3 21 138s [- - - 154 | - - 139 134 R? 190 155 106 Li 20 140 |[- - - 156 | - - 141 [135(4) [UB (4) 189 (4) 157 [107 Le 19 142 |[- R8 188 158 |- M1 18 143. [- - - 159s | - - 144 136 T8 187 160 108 L3 17 586 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Table 57. EPM7256E & EPM7256S 1/0 Pin-Outs (Part 4 of 5) LAB MC | 160-Pin | 192-Pin 208-Pin LAB MC | 160-Pin | 192-Pin 208-Pin POFP | PGA /2) | ROFP/POFP POFP | PGA (2) | ROFP/POFP (1), (2) (1), (2) (3) K [tei [ot F3 38 mM iss |ti9 Ut 4 162 [- - - 194 [- - - 163 92 F1 37 195 120 R2 3 tea [- - - 196s [- - - 165 93 E2 36 197 121 R3 206 166 [- G2 35 198s [- U2 205 167 - = - 199 = - = 168 94 G3 34 200 122 P4 204 169 [95 Gi 33 201/123 U3 203 170 - = - 202 = - - 171 37 H1 31 203 124 T3 202 172 - - - 204 - - - 173 |98/4) [H3(4) |30 (4) 205 [125 U4 201 174 - J1 293 206 = U5 199 175 [- - - 207. |[- - - 176 [99 H2 28 208 | 127 T4 198 L 177 61 Bs 78 N 209 103s N1 16 178 [- - - 210 [- - - 179 62 C8 77 211 1190 Me 15 180 [- - - 212. [- - - 181 63 Ag 76 213 112 M3 13 182 | A8 73 214. [= Py 12 183s - - 215 [- - - 184 [67 AZ 71 216/113 Ne2 11 185 [68 Be 70 217.( 114 Ri 10 186 - - - 218 - - - 187 [69 AG 69 219 | 115 P2 9 188 - = - 220 - = - 189 |70 B7 68 221 |116 TI 8 190 = [- A5 67 222 |- N3 7 191 - - - 223 - - - 192 (71 C 66 224 =|117 T2 6 Altera Corporation 587MAX 7000 Programmable Logic Device Family Data Sheet Table 51. EPM7256E & EPM72568 1/0 Pin-Outs (Part 3 of 5) LAB | Mc | 160-Pin | 192-Pin| 208-Pin | LAB | McC | 160-Pin | 192-Pin | 208-Pin POFP | PGA (2) | ROFP/POFP POFP | PGA (2) | ROFP/POFP (1), (2) (1), (2) (3) Oo 225 82 B1 49 P 241 72 A4 65 226 = - = 242 - = - eof 83 C3 48 243 73 B&6 64 228 = - = 244 - - = 229 84 C1 47 245 75 B5 62 230 - D3 46 246 - AS 61 231 = - = 247 = - = 232 85 D1 45 248 76 B4 60 233 86 Ce 44 249 V7? A2 59 234 - - - 250 - - - 235 87 E1 43 251 78 C4 58 236 - - - 252 - - - 23f 88 E3 42 253 79 Be 57 238 - D2 40 254 = B3 56 239 - - - 255 - - - 240 30 Fe 39 256 80 Al 55 Notes to tables: (1) (2) (3) (4) (5) 588 A complete thermal analysis should be pertormed betore committing a design to this device package. See the Operating Reqitirements for Altera Devices Data Sheet in this data book for more information. EPM7256S devices is not available in the 160-pin PQFP package. EPM7256E devices are not available in the 208-pin ROFP/PQFP packages. This JTAG pin applies te MAX 7000S devices only and this pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for ISP, this pin is not available as a user I/O pin. The user I/O pin count includes dedicated input pins and all 1/O pins. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Figures 16 through 22 show the package pin-out diagrams for MAX 7000 devices. Figure 16. 44-Pin Package Pin-Out Diagram Package outlines not drawn to scale. Pin functions shown in parentheses are for MAX 7000S or MAX 7000E devices only. = = a = a 5 Ge.% Ss o Aaag ays 4 oagog ucoa EEEE Ogog o2r2 22a 5 5 5 5 2 QQegegess2RZaeg 7, ecoSZEZES ay Pin} = = = Re eee OS = Pi 4 EEEsS$ 2222588 | 6 54 3 2 4 44 2 44 40 {2} WORTD| e Es 0 {2} VOATDI 39 lo vO Es Oro) {2} WO 38 B VOATDO) (3 GND E= 10 GND 36 VO vo E voc HO EPM7032 a A io vo L yo 9) rormusy EPM7032S a P io f 12) UOTE) EPM7032 = to 0 EPM7064 52 VORTOK} 12) vO ES VONTCK) (2) veo EPM7064S atbvo voo = vo WO 30 GND vO F GND 0 298 Vo vO FS vo 1819 20 2122 23 24 25 2627 28 > I Pin 12 BEES geese Pin2 eeeergesees 44-Pin PQFP 44-Pin PLCC = a 4 6s - aque 4 wo w oeos ee Eb a go . oo Got2ctcaz gg . Pind = 2 2 5 SSS OS Pin dd | 2) VORTDH e Ls yo vo ES VONTDO) 42} vo FALWTERA = V0 GND = 10 VO EPM7032 E- vos vo EPM7032S LE 10 {2} VOATMS) EPM7064 Fo vo EPM7064S = vorTok) 2) ei | - GND Ee 0 VOC vO He) Pint2 2k8Ve92R B22 Q Pig 23 o> 44-Pin TQFP Notes: (1) These pins are available in MAX 7000E and MAX 7000S devices only. (2) JIAG ports are available in MAX 7000S devices only. Altera Corporation 589MAX 7000 Programmable Logic Device Family Data Sheet Figure 17. 68-Pin Package Pin-Out Diagram Package outlines not drawn to scale. Pin functions shown in parentheses are for MAX 70008 or MAX 7000E devices only. vo] 10 vocio 11 @)vOuTDI E12 Notes: (1) (2) 590 EPM7064 EPM7096 60 53 58 7 5B 55 54 53 52 51 50 43 48 a7 465 45 44 vo vo PGND FI vSATDD) (2) ve Five ve voce pve pve PI vOnTGR) (2) Avo a vo vo ve vc These pins are available in MAX 7000E and MAX 7000S devices only. JTAG ports are available in MAX 7000S devices only. Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Figure 18. 84-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin functions in parentheses are for MAX 7000S or MAX 70O0E devices only. at g = z Sas 5eeoe ZEEEE BO Seeee2 e058 $2222529998909 DUC LOL o ONT ZSISSPeRERR uO 74 Oo VCCI 73 Oo (3) HOHTDN 72 SND uO FAALTERA 71 1 eoTDO) 3} uO 70 Oo uO 69 Fi uO 68 2 SND EPM7064 67 ie Wo 66 FI vocio uO EPM70648 65 Fo uO 64 CD {3} OTM) EPM7096 63 Flo UO 62 EL VOTCh) (3+ UO EPM7128E 61 in VCCI EPM7128S 60 vo Wo. $3 1 np uO EPM7160E s io uO s7 ro i) EPM7160S 56 Ovo uO $5 Oo GND S40 io S599aeeh SRR 8B WUD OOOO OOOO Qeeoegergeogocs og o a g 8 S 84-Pin PLCC Notes: (1) Pins 6,39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM71605 devices. (2) This pin is available in MAX 7000E and MAX 70008 devices only. (3) JIAG ports are available in MAX 7000S devices only. Altera Corporation 591MAX 7000 Programmable Logic Device Family Data Sheet Figure 19. 100-Pin Package Pin-Out Diagram Package outline not drawn to scale. EPM7064 EPM7096 EPM7128E EPM7128S EPM7160E 100-Pin PQFP EPM7064S EPM7128S EPM7160S Figure 20. 160-Pin Package Pin-Out Diagram Package outline not drawn to scale. rFoOoounmmrg TO AT F277 592 QOOOOOOOQOQDQDOQOOO QOQOODOOOOOOOOOO QOQOODOQOOOOQOOOOOOO QOOQ QOO@ QO@ QO@ QO@ QO Cee) EPM7192E ()e)(e}(e) OOOO Bottom QOOOE) QEso View OOOO OOO 2298 QOQOQ_ @@QOO OOMOOOQQOOOOOOOO) QVOOOOOOQQOOOOOOO) WOOOOQOOQOOOQOOQOOOE) 12 3 4 5 6 B&B 10 11:12 13 14 15 160-Pin PGA Pint ~ J Pin 44 JN De RYAN EPM?7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E Ae Pie 124 o AAACN ONO * en 160-Pin PQFP Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Figure 27. 192-Pin Package Pin-Out Diagram Package outline not drawn to scale. FOO OUMmMmTDe ToCAT FFD DA /, , QOOQODQDOOOOOOOOO OOOOGOOOOOGOMOOOOE) QOOVOOOOGOOOOGOCO) QQOOQO @QOOOCOQ OOO @OE) QO OG) QO] O1010/0) WOME) CHEE IC) EPM7256E OlOLOl0) OOOO Bottom Soe8 QOOE) View OOOO OOQE) OOO QO@ OOO @O@ @@)@) BOC Oe motos OOOO OOOE O09 clotototototototototototots OO) GOOOOOOOOQOQOOOO OO, 192-Pin PGA Figure 22. 208-Pin Package Pin-Out Diagram Package outline not drawn to scale. Altera Corporation Pint Pin 157 Amp ATARI AAT TT Teaco Pin 53 /N Os RYA\ EPM7256E EPM7256S 208-Pin PQFP/RQFP s$S$.q OOOO AU Pin 105 593