CMOS, 330 MHz
Triple 8-Bit High Speed Video DAC
Data Sheet
ADV7125
Rev. D Document Feedback
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FEATURES
330 MSPS throughput rate
Triple 8-bit DACs
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal reference (1.235 V)
Single-supply +5 V/+3.3 V operation
48-lead LQFP and LFCSP
Low power dissipation (30 mW minimum at 3 V)
Low power standby mode (6 mW typical at 3 V)
Industrial temperature range (−40°C to +85°C)
RoHS compliant packages
Qualified for automotive applications
APPLICATIONS
Digital video systems
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
Automotive infotainment units
FUNCTIONAL BLOCK DIAGRAM
8
8
8
8
8
8
DATA
REGISTER DAC
DAC
BLANK
SYNC
R7 TO R0
G7 TO G0
B7 TO B0
PSAVE
CLOCK
DAC
ADV7125
DATA
REGISTER
DATA
REGISTER
BLANK AND
SYNC LOGIC
POWER-DOWN
MODE VOLTAGE
REFERENCE
CIRCUIT
IOR
IOR
IOG
IOG
IOB
VREF
RSET
VAA
COMPGND
IOB
03097-001
Figure 1.
GENERAL DESCRIPTION
The ADV7125 (ADV®) is a triple high speed, digital-to-analog
converter (DAC) on a single monolithic chip. It consists of three
high speed, 8-bit video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7125 has three separate 8-bit-wide input ports. A
single +5 V/+3.3 V power supply and clock are all that are
required to make the device functional. The ADV7125 has
additional video control signals, composite SYNC and BLANK,
as well as a power save mode.
The ADV7125 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7125 is available in 48-
lead LQFP and 48-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1. 330 MSPS (3.3 V only) throughput.
2. Guaranteed monotonic to eight bits.
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
ADV7125* Product Page Quick Links
Last Content Update: 11/01/2016
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Application Notes
•AN-1180: Optimizing Video Platforms for Automated Post-
Production Self-Tests
•AN-349: Keys to Longer Life for CMOS
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Data Sheet
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Video DAC Data Sheet
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•CN0282
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•Digital to Analog Converters ICs Solutions Bulletin
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•ADV7125 Material Declaration
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ADV7125 Data Sheet
Rev. D | Page 2 of 17
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Electrical Characteristics ...................................................... 3
3.3 V Electrical Characteristics ................................................... 4
5 V Timing Specifications ........................................................... 5
3.3 V Timing Specifications ........................................................ 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Terminology .................................................................................... 11
Circuit Description and Operation .............................................. 12
Digital Inputs .............................................................................. 12
Clock Input .................................................................................. 12
Video Synchronization and Control ........................................ 13
Reference Input ........................................................................... 13
DACs ............................................................................................ 13
Analog Outputs .......................................................................... 13
Gray Scale Operation ................................................................. 14
Video Output Buffers ................................................................. 14
PCB Layout Considerations ...................................................... 14
Digital Signal Interconnect ....................................................... 14
Analog Signal Interconnect....................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
Automotive Products ................................................................. 17
REVISION HISTORY
4/16—Rev. C to Re v. D
Changes to Figure 3 and Table 6 ..................................................... 8
Added Figure 4; Renumbered Sequentially .................................. 8
Added Figure 5 and Table 7; Renumbered Sequentially ........... 10
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
2/11—Rev. B to Rev. C
Change to Table 6 ............................................................................. 8
7/10—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to Clock Frequency Parameter, Table 4 ......................... 6
Changes to Figure 2 .......................................................................... 6
Changes to Figure 4 and Figure 5 ................................................. 11
Changes to Table 7 .......................................................................... 12
Changes to Endnotes to Ordering Guide .................................... 15
Added Automotive Products Section .......................................... 15
3/09—Rev. 0 to Re v. A
Updated Format .................................................................. Universal
Changes to Features Section, Applications Section, and
General Description Section ............................................................ 1
Changes to Figure 3 and Table 6 ...................................................... 8
Deleted Ground Planes Section, Power Planes Section, and
Supply Decoupling Section ........................................................... 11
Changes to Figure 5 ........................................................................ 11
Changes to Table 7, Analog Outputs Section, Figure 6, and
Figure 7 ............................................................................................ 12
Changes to Video Output Buffers Section, PCB Layout
Considerations Section, and Figure 9 .......................................... 13
Changes to Analog Signal Interconnect Section and Figure 10 .... 14
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
10/02—Revision 0: Initial Version
Data Sheet ADV7125
Rev. D | Page 3 of 17
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits
Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB
Differential Nonlinearity
−1
+1
LSB
Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current 20 μA
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, SYNC = high
2.0 18.5 mA RGB DAC, SYNC = low
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, ROUT 100 kΩ
Output Capacitance, COUT 10 pF IOUT = 0 mA
Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error2 −5.0 +5.0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, VREF 1.12 1.235 1.35 V
POWER DISSIPATION
Digital Supply Current3 3.4 9 mA fCLK = 50 MHz
10.5 15 mA fCLK = 140 MHz
18 25 mA fCLK = 240 MHz
Analog Supply Current 67 72 mA RSET = 530 Ω
8 mA RSET = 4933 Ω
Standby Supply Current
4
5.0
mA
PSAVE = low, digital, and control inputs at VDD
Power Supply Rejection Ratio 0.1 0.5 %/%
1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
2 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0xFFH) × 4 and K = 7.9896.
3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4 These maximum/minimum specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.
ADV7125 Data Sheet
Rev. D | Page 4 of 17
3.3 V ELECTRICAL CHARACTERISTICS
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.
Table 2.
Parameter2 Min Typ Max Unit Test Conditions/Comments1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits RSET = 680 Ω
Integral Nonlinearity (BSL) −1 ±0.5 +1 LSB RSET = 680 Ω
Differential Nonlinearity −1 ±0.25 +1 LSB RSET = 680 Ω
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current 20 μA
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, SYNC = high
2.0 18.5 mA RGB DAC, SYNC = low
DAC-to-DAC Matching 1.0 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, ROUT 70 kΩ
Output Capacitance, C
OUT
10
pF
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error3 0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE, EXTERNAL
Reference Range, VREF 1.12 1.235 1.35 V
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, VREF 1.235 V
POWER DISSIPATION
Digital Supply Current4
2.2
5.0
mA
f
CLK
= 50 MHz
6.5 12.0 mA fCLK = 140 MHz
11 15 mA fCLK = 240 MHz
16 mA fCLK = 330 MHz
Analog Supply Current 67 72 mA RSET = 560 Ω
8 mA RSET = 4933 Ω
Standby Supply Current
2.1
5.0
mA
PSAVE = low, digital, and control inputs at VDD
Power Supply Rejection Ratio 0.1 0.5 %/%
1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
2 These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
3 Gain error = ((Measured (FSC)/Ideal (FSC) −1) × 100), where Ideal = VREF/RSET × K × (0xFFH) × 4 and K = 7.9896.
4 Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
Data Sheet ADV7125
Rev. D | Page 5 of 17
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 3.
Parameter3 Symbol Min Typ Max Unit Test Conditions/Comments
ANALOG OUTPUTS
Analog Output Delay t6 5.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t9 1 2 ns
CLOCK CONTROL
CLOCK Frequency7 fCLK 0.5 50 MHz 50 MHz grade
0.5 140 MHz 140 MHz grade
0.5 240 MHz 240 MHz grade
Data and Control Setup6 t1 0.5 ns
Data and Control Hold6 t2 1.5 ns
CLOCK Period t3 4.17 ns
CLOCK Pulse Width High6 t4 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width Low6 t5 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width High6 t4 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width Low6 t5 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width High
t
4
8.0
ns
f
CLK_MAX
= 50 MHz
CLOCK Pulse Width Low t5 8.0 ns fCLK_MAX = 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time6 t10 2 10 ns
1 The maximum and minimum specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
ADV7125 Data Sheet
Rev. D | Page 6 of 17
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 4.
Parameter3 Symbol Min Typ Max Unit Test Conditions/Comments
ANALOG OUTPUTS
Analog Output Delay, t6 7.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t9 1 2 ns
CLOCK CONTROL
CLOCK Frequency7 fCLK 50 MHz 50 MHz grade
140 MHz 140 MHz grade
240
MHz
240 MHz grade
330 MHz 330 MHz grade
Data and Control Setup6 t1 0.2 ns
Data and Control Hold6 t2 1.5 ns
CLOCK Period t3 3 ns
CLOCK Pulse Width High6 t4 1.4 ns fCLK_MAX = 330 MHz
CLOCK Pulse Width Low6 t5 1.4 ns fCLK_MAX = 330 MHz
CLOCK Pulse Width High6 t4 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width Low6 t5 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width High6 t4 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width Low6 t5 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width High
t
4
8.0
ns
f
CLK_MAX
= 50 MHz
CLOCK Pulse Width Low t5 8.0 ns fCLK_MAX = 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time6 t10 4 10 ns
1 These maximum and minimum specifications are guaranteed over this range.
2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
t
3
t
1
t
4
t
8
t
2
t
6
t
7
t
5
CLOCK
DIGITAL INPUTS
(R7 T O R0, G7 T O G 0, B7 T O B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. O UTPUT DELAY (
t
6) ME AS URED FRO M THE 50% P OI NT O F T HE RISING E DGE OF CLOCK TO THE 50% P OI NT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t
7) ME AS URED BE TW E E N THE 10% AND 90% P OI NTS OF FUL L-S CALE TRANSIT ION.
3. TRANSITION TIME (
t
8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
03097-002
Figure 2. Timing Diagram
Data Sheet ADV7125
Rev. D | Page 7 of 17
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VAA to GND 7 V
Voltage on Any Digital Pin GND − 0.5 V to VAA + 0.5 V
Ambient Operating Temperature
Range (TA)
−40°C to +85°C
Storage Temperature Range (TS) −65°C to +150°C
Junction Temperature (TJ) 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase Soldering (1 Minute)
220°C
IOUT to GND1 0 V to VAA
1 Analog output short circuit to any power supply or common GND can be of
an indefinite duration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADV7125 Data Sheet
Rev. D | Page 8 of 17
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
VAA
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
CLOCK
48
47
46
45
44
43
42
41
40
39
38
37
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
PSAVE
RSET
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
NOTES
1. THE EX P OSE D P ADDLE M US T BE CONNECTED TO GND.
COMP
VAA
VAA
IOB
IOB
GND
GND
35 VREF
36
34
33
32
31
30
29
28
27
26
25
TOP VIEW
(No t t o Scal e)
ADV7125
PIN 1
INDICATOR
03097-003
IOG
IOG
IOR
IOR
Figure 3. LFCSP Pin Configuration (CP-48-1)
VAA
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
CLOCK
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
PSAVE
RSET
GND
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
NOTES
1. THE EXPOSED PADDLE M US T BE CONNECTED TO GND.
COMP
VAA
VAA
IOB
IOB
GND
GND
VREF
IOG
IOG
IOR
IOR
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
16
15
14
13
44
45
46
47
48
43
42
41
40
39
38
37
ADV7125
TOP VIEW
(No t t o Scal e)
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
03097-100
Figure 4. LFCSP Pin Configuration (CP-48-4)
Table 6. LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 14, 15,
25, 26, 39, 40
GND Ground. All GND pins must be connected.
3 to 10, 16 to
23, 41 to 48
G0 to G7,
B0 to B7,
R0 to R7
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
11 BLANK Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored.
12 SYNC Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output. SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0.
13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected.
24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be
driven by a dedicated TTL buffer.
27, 31, 33 IOB, IOG,
IOR
Differential Blue, Green, and Red Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34 IOB, IOG,
IOR
Blue, Green, and Red Current Outputs. These high impedance current sources are capable of directly driving
a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether
or not they are all being used.
35 COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
36 VREF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
Data Sheet ADV7125
Rev. D | Page 9 of 17
Pin No. Mnemonic Description
37 RSET A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal.
Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship
between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by:
RSET (Ω) = 11,445 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω) (SYNC being asserted)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied
permanently low.
38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is active.
0
EPAD
Exposed Paddle. The exposed paddle must be connected to GND.
ADV7125 Data Sheet
Rev. D | Page 10 of 17
48 47 46 45 44 43 42 41 40 39 38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
13 14 15 16 17 18 19 20 21 22 23 24
03907-101
ADV7125
(No t t o Scal e)
TOP VIEW
V
AA
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
CLOCK
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
PSAVE
R
SET
GND
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
COMP
V
AA
V
AA
IOB
IOB
GND
GND
V
REF
IOG
IOG
IOR
IOR
Figure 5. LQFP Pin Configuration
Table 7. LQFP Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 14, 15,
25, 26, 39, 40
GND Ground. All GND pins must be connected.
3 to 10, 16 to
23, 41 to 48
G0 to G7,
B0 to B7,
R0 to R7
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
11 BLANK Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored.
12
SYNC Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output. SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0.
13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected.
24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
27, 31, 33 IOB, IOG,
IOR
Differential Blue, Green, and Red Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34
IOB, IOG,
IOR
Blue, Green, and Red Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or
not they are all being used.
35 COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
36 VREF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
37
R
SET
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal.
Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship
between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by:
RSET (Ω) = 11,445 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG
(mA) = 11,444.8 ×
VREF
(V)/
RSET
(Ω) (SYNC being asserted)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied
permanently low.
38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is active.
Data Sheet ADV7125
Rev. D | Page 11 of 17
TERMINOLOGY
Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that shuts off the picture
tube, resulting in the blackest possible picture.
Color Video (RGB)
This refers to the technique of combining the three primary
colors of red, green, and blue to produce color pictures within
the usual spectrum. In RGB monitors, three DACs are required,
one for each color.
Sync Signal (SYNC)
The position of the composite video signal that synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the SYNC signal.
Video Signal
The portion of the composite video signal that varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that can be
visually observed.
ADV7125 Data Sheet
Rev. D | Page 12 of 17
CIRCUIT DESCRIPTION AND OPERATION
The ADV7125 contains three 8-bit DACs, with three input
channels, each containing an 8-bit register. Also integrated
on board the device is a reference amplifier. The CRT control
functions, BLANK and SYNC, are integrated on board the
ADV7125.
DIGITAL INPUTS
There are 24 bits of pixel data (color information), R0 to R7,
G0 to G7, and B0 to B7, latched into the device on the rising
edge of each clock cycle. This data is presented to the three 8-bit
DACs and then converted to three analog (RGB) output wave-
forms (see Figure 6).
CLOCK
DATA
DIGITAL INPUTS
(R7 TO R0, G7 TO G0,
B7 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG,
IOB, IOB)
03097-004
Figure 6. Video Data Input/Output
The ADV7125 has two additional control signals that are latched
to the analog video outputs in a similar fashion. BLANK and
SYNC are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs.
Figure 7 shows the analog output, RGB video waveform of the
ADV7125. The influence of SYNC and BLANK on the analog
video waveform is illustrated.
Table 8 details the resultant effect on the analog outputs of
BLANK and SYNC.
All these digital inputs are specified to accept TTL logic levels.
CLOCK INPUT
The CLOCK input of the ADV7125 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, is determined by the
on-screen resolution, according to the following equation:
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh
Rate)/(Retrace Factor)
where:
Horiz Res is the number of pixels per line.
Vert Res is the number of lines per frame.
Refresh Rate is the horizontal scan rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system, or 30 Hz for an interlaced system.
Retrace Factor is the total blank time factor. This takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
Therefore, for a graphics system with a 1024 × 1024 resolution,
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz. All video
data and control inputs are latched into the ADV7125 on the
rising edge of CLOCK, as previously described in the Digital
Inputs section. It is recommended that the CLOCK input to the
ADV7125 be driven by a TTL buffer (for example, the 74F244).
RED AND BLUE
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. VREF = 1.235V, RSET = 530Ω.
3. RS- 343 LEV E LS AND TO LERANCE S AS S UM E D ON AL L L E V E LS.
mA V
18.67 0.7
00
mA V
26.0 0.975 WHITE L EVEL
BLANK LEVE L
SYNC LEVEL
7.2 0.271
0 0
GREEN
03097-005
Figure 7. Typical RGB Video Output Waveform
Data Sheet ADV7125
Rev. D | Page 13 of 17
Table 8. Typical Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)
Video Output Level IOG (mA) IOG (mA) IOR/IOB (mA) IOR/IOB (mA) SYNC BLANK DAC Input Data
White Level 26.0 0 18.67 0 1 1 0xFFH
Video Video + 7.2 18.67 − Video Video 18.67 − Video 1 1 Data
Video to BLANK Video 18.67 − Video Video 18.67 − Video 0 1 Data
Black Level
7.2
18.67
0
18.67
1
1
0x00H
Black to BLANK 0 18.67 0 18.67 0 1 0x00H
BLANK Level 7.2 18.67 0 18.67 1 0 0xXXH (don’t care)
SYNC Level 0 18.67 0 18.67 0 0 0xXXH (don’t care)
VIDEO SYNCHRONIZATION AND CONTROL
The ADV7125 has a single composite sync (SYNC) input
control. Many graphics processors and CRT controllers have the
ability to generate horizontal sync (HSYNC), vertical sync
(VSYNC), and composite SYNC.
In a graphics system that does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry enables the generation of a composite SYNC signal.
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7125, the SYNC input should be tied
to logic low.
REFERENCE INPUT
The ADV7125 contains an on-board voltage reference. The VREF
pin should be connected as shown in Figure 12.
A resistance, RSET, connected between the RSET pin and GND,
determines the amplitude of the output video level according to
Equation 1 and Equation 2 for the ADV7125.
IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω) (1)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) (2)
Equation 1 applies to the ADV7125 only, when SYNC is being
used. If SYNC is not being encoded onto the green channel,
Equation 1 is similar to Equation 2.
Using a variable value of RSET allows for accurate adjustment of
the analog output video levels. Use of a fixed 560 Ω RSET resistor
yields the analog output levels quoted in the Specifications section.
These values typically correspond to the RS-343A video wave-
form values, as shown in Figure 7.
DACs
The ADV7125 contains three matched 8-bit DACs. The DACs
are designed using an advanced, high speed, segmented architec-
ture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = 1) or GND (bit = 0)
by a sophisticated decoding scheme. Because all this circuitry
is on one monolithic device, matching between the three DACs
is optimized. As well as matching, the use of identical current
sources in a monolithic design guarantees monotonicity and
low glitch. The on-board operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
ANALOG OUTPUTS
The ADV7125 has three analog outputs, corresponding to the
red, green, and blue video signals.
The red, green, and blue analog outputs of the ADV7125 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load, such
as a doubly terminated 75 Ω coaxial cable. Figure 8 shows the
required configuration for each of the three RGB outputs
connected into a doubly terminated 75 Ω load. This arrangement
develops RS-343A video output voltage levels across a 75 Ω
monitor.
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 9. The output current levels of the
DACs remain unchanged, but the source termination resistance,
ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
IOR, IOG, IOB
Z
S
= 75Ω
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FO R RE D, G RE E N, AND BLUE DACs
Z
L
= 75Ω
(MONITOR)
Z
0
= 75Ω
(CABLE)
DACs
03097-006
Figure 8. Analog Output Termination for RS-343A
IOR, IOG, IOB
ZS = 150Ω
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FO R RE D, G RE E N, AND BLUE DACs
ZL = 75Ω
(MONITOR)
Z0 = 75Ω
(CABLE)
DACs
03097-007
Figure 9. Analog Output Termination for RS-170
More detailed information regarding load terminations for
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations.
Figure 7 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of
Figure 8. As well as the gray scale levels (black level to white
ADV7125 Data Sheet
Rev. D | Page 14 of 17
level), Figure 7 also shows the contributions of SYNC and
BLANK for the ADV7125. These control inputs add appro-
priately weighted currents to the analog outputs, producing
the specific output level requirements for video applications.
Table 8 details how the SYNC and BLANK inputs modify the
output levels.
GRAY SCALE OPERATION
The ADV7125 can be used for standalone, gray scale (mono-
chrome) or composite video applications (that is, only one channel
used for video information). Any one of the three channels, red,
green, or blue, can be used to input the digital video data. The
two unused video data channels should be tied to Logic 0. The
unused analog outputs should be terminated with the same load
as that for the used channel, that is, if the red channel is used
and IOR is terminated with a doubly terminated 75 Ω load
(37.5 Ω), IOB and IOG should be terminated with 37.5 Ω
resistors (see Figure 10).
R0
R7
G0
ADV7125
G7
B0
B7
IOR
IOG
37.5Ω
DOUBLY
TERMINATED
75Ω LOAD
VIDEO
OUTPUT
37.5Ω
IOB
GND
03097-008
Figure 10. Input and Output Connections for Standalone Gray Scale or
Composite Video
VIDEO OUTPUT BUFFERS
The ADV7125 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in the
Analog Outputs section and illustrated in Figure 11. However,
in some applications, it may be required to drive long transmis-
sion line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able
to supply sufficient current over the complete output voltage
swing. Analog Devices produces a range of suitable op amps for
such applications. These include the AD843, AD844, AD847,
and AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More
information on line driver buffering circuits is given in the
relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
3
7
2
ZL = 75Ω
(MONITOR)
Z0 = 75Ω
Z2Z1
+VS
–VS
0.1µF
0.1µF
75Ω
(CABLE)
GAIN (G) = 1 +
DACs
IOR, IOG, IOB
ZS = 75Ω
(SOURCE
TERMINATION)
AD848
4
6
03097-009
Z1
Z2
Figure 11. AD848 as an Output Buffer
PCB LAYOUT CONSIDERATIONS
The ADV7125 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7125, it is imperative
that great care be given to the PCB layout. Figure 12 shows a
recommended connection diagram for the ADV7125.
The layout should be optimized for lowest noise on the
ADV7125 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of VAA and GND pins
to minimize inductive ringing.
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 12). Optimum
performance is achieved by using 0.1 μF and 0.01 μF ceramic
capacitors. Individually decouple each VAA pin to ground by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7125
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3-
terminal voltage regulator.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7125 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7125 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (VCC) and not to the
analog power plane.
Data Sheet ADV7125
Rev. D | Page 15 of 17
ANALOG SIGNAL INTERCONNECT
Place the ADV7125 as close as possible to the output connectors,
thus minimizing noise pickup and reflections due to impedance
mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high
frequency power supply rejection.
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
should be as close as possible to the ADV7125 to minimize
reflections.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI.
35
36
37
33
31
27
R7 TO R0
41 TO 48
COMPV
AA
V
AA
VAA
VAA
VREF
RSET
IOR
75Ω 75Ω 75Ω
COAXIA
L CABLE
75Ω
POWER SUPPLY DE COUPLI NG
(0.1µF AND 0. 01µ F CAPACITOR
FO R E ACH V
AA
GROUP)
AD1580
ADV7125
MONITOR (CRT)
1
2
BNC
CONNECTORS
COMPLEMENTARY
OUTPUTS
75Ω
1kΩ
R
SET
530Ω
IOG
IOB
12
SYNC
11
BLANK
24
CLOCK
38
PSAVE
GND
1, 2, 14, 15,
25, 26, 39, 40
13, 29,
30
VIDEO
DATA
INPUTS G7 TO G0
3 TO 10
B7 TO B0
16 TO 23
IOR
IOG
IOB
75Ω
75Ω
32
28
34
0.1µF
0.1µF
1µF
0.01µF
03097-010
Figure 12. Typical Connection Diagram
ADV7125 Data Sheet
Rev. D | Page 16 of 17
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC S TANDARDS MS-026-BBC
TOP VIEW
(PI NS DOWN)
1
12 13 25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD P ITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTAT E D 90° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 13. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
COM P LIANT T O JEDE C S TANDARDS M O-220- V KKD- 2
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.80 M AX
0.65 TYP
5.50 REF
COPLANARITY
0.08
0.20 REF
1.00
0.85
0.80 0. 05 MAX
0.02 NO M
SEATING
PLANE
12° M AX
TOP VIEW
0.60 M AX
0.60 M AX
PIN 1
INDICATOR 0.50
REF
PIN 1
INDICATOR
0.25 M IN
7.10
7.00 SQ
6.90
6.85
6.75 SQ
6.65
06-05-2012-A
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
Figure 14. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.85 mm Package Height
(CP-48-1)
Dimensions shown in millimeters
Data Sheet ADV7125
Rev. D | Page 17 of 17
112408-B
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
COM P LIANT T O JEDE C S TANDARDS M O-220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
PIN 1
INDICATOR
5.20
5.10 SQ
5.00
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0. 05 MAX
0.02 NO M
0.25 M IN
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
Figure 15. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Speed Option Package Option
ADV7125KSTZ50 −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] 50 MHz ST-48
ADV7125KSTZ50-REEL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] 50 MHz ST-48
ADV7125KSTZ140 −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] 140 MHz ST-48
ADV7125JSTZ240 0°C to +70°C 48-Lead Low Profile Quad Flat Package [LQFP] 240 MHz ST-48
ADV7125JSTZ330
0°C to +70°C
48-Lead Low Profile Quad Flat Package [LQFP]
330 MHz
ST-48
ADV7125WBSTZ170 −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] 170 MHz ST-48
ADV7125WBSTZ170-RL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] 170 MHz ST-48
ADV7125BCPZ170 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] 170 MHz CP-48-1
ADV7125BCPZ170-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] 170 MHz CP-48-1
ADV7125WBCPZ170 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] 170 MHz CP-48-4
ADV7125WBCPZ170-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] 170 MHz CP-48-4
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 ADV7125JSTZ330 is available in a 3.3 V option only.
AUTOMOTIVE PRODUCTS
The ADV7125W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03097-0-4/16(D)