SST32HF1622C-70-4C-LFS - Silicon Storage Technology

S71253-05-EOL 02/08

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Data Sheet

FEATURES:

• ComboMemories organized as:

– SST32HF1622C: 1M x16 Flash + 128K x16 SRAM

• Single 2.7-3.3V Read and Write Operations

• Concurrent Operation

– Read from or Write to SRAM while

Erase/Program Flash

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 15 mA (typical) for

Flash or SRAM Read

– Standby Current: 12 µA (typical)

• Flexible Erase Capability

– Uniform 2 KWord sectors

– Uniform 32 KWord size blocks

• Erase-Suspend/Erase-Resume Capabilities

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 32 KWord)

• Fast Read Access Times:

– Flash: 70 ns

–SRAM: 70 ns

• Latched Address and Data for Flash

• Flash Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

• Flash Automatic Erase and Program Timing

– Internal VPP Generation

• Flash End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Package Available

– 63-ball LFBGA (8mm x 10mm x 1.4mm)

– 62-ball LFBGA (8mm x 10mm x 1.4mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST32HF1622C ComboMemory device integrates a

CMOS flash memory bank with a CMOS SRAM memory

bank in a Multi-Chip Package (MCP), manufactured with

SST’s proprietary, high performance SuperFlash technol-

ogy. The SST32HF1622C device uses standard SRAM.

Featuring high performance Word-Program, the flash

memory bank provides a maximum Word-Program time of

7 µsec. To protect against inadvertent flash write, the

SST32HF1622C device contains on-chip hardware and

software data protection schemes. The SST32HF1622C

device offers a guaranteed endurance of 10,000 cycles.

Data retention is rated at greater than 100 years.

The SST32HF1622C device consists of two independent

memory banks with respective bank enable signals. The

Flash and SRAM memory banks are superimposed in the

same memory address space. Both memory banks share

common address lines, data lines, WE# and OE#. The

memory bank selection is done by memory bank enable

signals. The SRAM bank enable signal, BES# selects the

SRAM bank. The flash memory bank enable signal, BEF#

selects the flash memory bank. The WE# signal has to be

used with Software Data Protection (SDP) command

sequence when controlling the Erase and Program opera-

tions in the flash memory bank. The SDP command

sequence protects the data stored in the flash memory

bank from accidental alteration.

The SST32HF1622C provides the added functionality of

being able to simultaneously read from or write to the

SRAM bank while erasing or programming in the flash

memory bank. The SRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Word-Program concurrently. All

flash memory Erase and Program operations will automati-

cally latch the input address and data signals and complete

the operation in background without further input stimulus

requirement. Once the internally controlled Erase or Pro-

gram cycle in the flash bank has commenced, the SRAM

bank can be accessed for Read or Write.

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

SST32HF16x2x / 32x2x / 6482x16/32/64Mb Flash + 4/8Mb SRAM, 32Mb Flash + 8Mb SRAM

(x16) MCP ComboMemories

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

The SST32HF1622C device is suited for applications that

use both flash memory and SRAM memory to store code

or data. For systems requiring low power and small form

factor, the SST32HF1622C device significantly improves

performance and reliability while lowering power consump-

tion when compared with multiple chip solutions. The

SST32HF1622C inherently uses less energy during Erase

and Program operations than alternative flash technolo-

gies. The total energy consumed is a function of the

applied voltage, current, and time of application. Since, for

any given voltage range, SuperFlash technology uses less

current to program and has a shorter erase time, the total

energy consumed during any Erase or Program operation

is less than alternative flash technologies.

SuperFlash technology provides fixed Erase and Program

times independent of the number of Erase/Program cycles

that have occurred. Therefore the system software or hard-

ware does not have to be modified or de-rated as is neces-

sary with alternative flash technologies, whose Erase and

Program times increase with accumulated Erase/Program

cycles.

Device Operation

The SST32HF1622C uses BES1#, BES2 and BEF# to

control operation of either the flash or the SRAM memory

bank. When BEF# is low, the flash bank is activated for

Read, Program or Erase operation. When BES1# is low,

and BES2 is high the SRAM is activated for Read and

Write operation. BEF# and BES1# cannot be at low level,

and BES2 cannot be at high level at the same time. If all

bank enable signals are asserted, bus contention will

result and the device may suffer permanent damage.

All address, data, and control lines are shared by flash and

SRAM memory banks which minimizes power consump-

tion and loading. The device goes into standby when BEF#

and BES1# bank enables are raised to VIHC (Logic High) or

when BEF# is high and BES2 is low.

Concurrent Read/Write Operation

The SST32HF1622C provides the unique benefit of being

able to read from or write to SRAM, while simultaneously

erasing or programming the flash. This allows data alter-

ation code to be executed from SRAM, while altering the

data in flash. See Figure 27 for a flowchart. The following

table lists all valid states.

The device will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in progress.

Flash Read Operation

The Read operation of the SST32HF1622C device is con-

trolled by BEF# and OE#. Both have to be low, with WE#

high, for the system to obtain data from the outputs. BEF#

is used for flash memory bank selection. When BEF# is

high, the chip is deselected and only standby power is

consumed. OE# is the output control and is used to gate

data from the output pins. The data bus is in high imped-

ance state when OE# is high. Refer to Figure 7 for further

details.

Concurrent Read/Write State Table

Flash SRAM

Program/Erase Read

Program/Erase Write

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

Flash Word-Program Operation

The flash memory bank of the SST32HF1622C device is

programmed on a word-by-word basis. Before Program

operations, the memory must be erased first. The Program

operation consists of three steps. The first step is the three-

byte load sequence for Software Data Protection. The sec-

ond step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either BEF# or WE#, whichever occurs last.

The data is latched on the rising edge of either BEF# or

WE#, whichever occurs last. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or BEF#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed, within 10

µs. See Figures 8 and 9 for WE# and BEF# controlled Pro-

gram operation timing diagrams and Figure 22 for flow-

charts. During the Program operation, the only valid flash

Read operations are Data# Polling and Toggle Bit. During

the internal Program operation, the host is free to perform

additional tasks. During the command sequence, WP#

should be statically held high or low. Any SDP commands

loaded during the internal Program operation will be

ignored.

Flash Sector/Block-Erase Operation

The Flash Sector/Block-Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST32HF1622C offers both Sector-

Erase and Block-Erase mode. The sector architecture is

based on uniform sector size of 2 KWord. The Block-Erase

mode is based on uniform block size of 32 KWord. The

Sector-Erase operation is initiated by executing a six-byte

command sequence with Sector-Erase command (30H)

and sector address (SA) in the last bus cycle. The address

lines AMS-A11 are used to determine the sector address.

The Block-Erase operation is initiated by executing a six-

byte command sequence with Block-Erase command

(50H) and block address (BA) in the last bus cycle. The

address lines AMS-A15 are used to determine the block

address. The sector or block address is latched on the fall-

ing edge of the sixth WE# pulse, while the command (30H

or 50H) is latched on the rising edge of the sixth WE#

pulse. The internal Erase operation begins after the sixth

WE# pulse. The End-of-Erase operation can be deter-

mined using either Data# Polling or Toggle Bit methods.

See Figures 13 and 14 for timing waveforms. Any com-

mands issued during the Sector- or Block-Erase operation

are ignored, WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing one byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode typically within 20

µs after the Erase-Suspend command had been issued.

Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address

location within erase-suspended sectors/blocks will output

DQ2 toggling and DQ6 at “1”. While in Erase-Suspend

mode, a Word-Program operation is allowed except for the

sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at any address in the last Byte sequence.

Flash Chip-Erase Operation

The SST32HF1622C provides a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 5555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or BEF#, whichever occurs first. During the Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 6 for the command sequence, Figure 11 for tim-

ing diagram, and Figure 26 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored.

Write Operation Status Detection

The SST32HF1622C provides two software means to

detect the completion of a write (Program or Erase) cycle,

in order to optimize the system Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Flash Data# Polling (DQ7)

When the SST32HF1622C flash memory banks are in the

internal Program operation, any attempt to read DQ7 will

produce the complement of the true data. Once the Pro-

gram operation is completed, DQ7 will produce true data.

Note that even though DQ7 may have valid data immedi-

ately following the completion of an internal Write opera-

tion, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent suc-

cessive Read cycles after an interval of 1 µs. During inter-

nal Erase operation, any attempt to read DQ7 will produce

a ‘0’. Once the internal Erase operation is completed, DQ7

will produce a ‘1’. The Data# Polling is valid after the rising

edge of the fourth WE# (or BEF#) pulse for Program opera-

tion. For Sector- or Block-Erase, the Data# Polling is valid

after the rising edge of the sixth WE# (or BEF#) pulse. See

Figure 10 for Data# Polling timing diagram and Figure 23

for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)

is valid after the rising edge of sixth WE# (or BEF#) pulse.

DQ6 will be set to “1” if a Read operation is attempted on an

Erase-Suspended Sector/Block. If Program operation is ini-

tiated in a sector/block not selected in Erase-Suspend

mode, DQ6 will toggle.

An additional Toggle Bit is available on DQ2, which can be

used in conjunction with DQ6 to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bits information. The Toggle Bit

(DQ2) is valid after the rising edge of the last WE# (or

BEF#) pulse of Write operation. See Figure 11 for Toggle

Bit timing diagram and Figure 23 for a flowchart.

Note: DQ7 and DQ2 require a valid address when reading

status information.

Flash Memory Data Protection

The SST32HF1622C flash memory bank provides both

hardware and software features to protect nonvolatile data

from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the flash Write operation. This prevents

inadvertent writes during power-up or power-down.

TABLE 1: Write Operation Status

Status DQ7DQ6DQ2

Normal

Operation

Standard

Program

DQ7# Toggle No Toggle

Standard

Erase

0 Toggle Toggle

Erase-

Suspend

Mode

Read from

Erase-Suspended

Sector/Block

1 1 Toggle

Read from

Non- Erase-Suspended

Sector/Block

Data Data Data

Program DQ7# Toggle N/A

T1.0 1253

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

Hardware Block Protection

The SST32HF1622C supports top hardware block pro-

tection, which protects the top 32 KWord block of the

device. The Boot Block address ranges are described in

Table 2. Program and Erase operations are prevented on

the 32 KWord when WP# is low. If WP# is left floating, it

is internally held high via a pull-up resistor, and the Boot

Block is unprotected, enabling Program and Erase oper-

ations on that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of TRHR is

required after RST# is driven high before a valid Read can

take place (see Figure 18).

The Erase or Program operation that has been interrupted

needs to be reinitiated after the device resumes normal

operation mode to ensure data integrity.

Flash Software Data Protection (SDP)

The SST32HF1622C provides the JEDEC approved soft-

ware data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three byte-load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST32HF1622C device is shipped with the software data

protection permanently enabled. See Table 6 for the spe-

cific software command codes. During SDP command

sequence, invalid commands will abort the device to Read

mode, within TRC. The contents of DQ15-DQ8 can be VIL or

VIH, but no other value, during any SDP command

sequence.

SRAM Read

The SRAM Read operation of the SST32HF1622C is con-

trolled by OE# and BES1#, both have to be low with WE#

and BES2 high for the system to obtain data from the out-

puts. BES1# and BES2 are used for SRAM bank selection.

OE# is the output control and is used to gate data from the

output pins. The data bus is in high impedance state when

OE# is high. Refer to the Read cycle timing diagram, Fig-

ure 4, for further details.

SRAM Write

The SRAM Write operation of the SST32HF1622C is con-

trolled by WE# and BES1#, both have to be low, BES2

must be high for the system to write to the SRAM. During

the Word-Write operation, the addresses and data are ref-

erenced to the rising edge of either BES1#, WE#, or the

falling edge of BES2 whichever occurs first. The write time

is measured from the last falling edge of BES#1 or WE# or

the rising edge of BES2 to the first rising edge of BES1#, or

WE# or the falling edge of BES2. Refer to the Write cycle

timing diagrams, Figures 5 and 6, for further details.

Product Identification

The Product Identification mode identifies the devices as

the SST32HF1622C and manufacturer as SST. This

mode may be accessed by software operations only.

The hardware device ID Read operation, which is typi-

cally used by programmers, cannot be used on this

device because of the shared lines between flash and

SRAM in the multi-chip package. Therefore, applica-

tion of high voltage to pin A9 may damage this device.

Users may use the software Product Identification opera-

tion to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same socket. For details, see

Tables 5 and 6 for software operation, Figure 15 for the

software ID entry and read timing diagram and Figure 24

for the ID entry command sequence flowchart.

TABLE 2: Boot Block Address Ranges

Product Address Range

Top Boot Block

SST32HF1622C 0F8000H-0FFFFFH

T2.1 1253

TABLE 3: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST32HF1622C 0001H 234AH

T3.2 1253

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

Product Identification Mode Exit/Reset

In order to return to the standard read mode, the Software

Product Identification mode must be exited. Exiting is

accomplished by issuing the Exit ID command sequence,

which returns the device to the Read operation. Please

note that the software reset command is ignored during an

internal Program or Erase operation. This command may

also be used to reset the device to Read mode after any

inadvertent transient condition that apparently causes the

device to behave abnormally, e.g. not read correctly. See

Table 6 for software command codes, Figure 16 for timing

waveform and Figure 24 for a flowchart.

Security ID

The SST32HF1622C devices offer a 256-bit Security ID

space. The Secure ID space is divided into two 128-bit seg-

ments - one factory programmed segment and one user

programmed segment. The first segment is programmed

and locked at SST with a random 128-bit number. The user

segment is left un-programmed for the customer to pro-

gram as desired.

To program the user segment of the Security ID, the user

must use the Security ID Word-Program command. To

detect end-of-write for the SEC ID, read the toggle bits. Do

not use Data# Polling. Once this is complete, the Sec ID

should be locked using the User Sec ID Program Lock-Out.

This disables any future corruption of this space. Note that

regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-

byte command sequence with Enter Sec ID command

(88H) at address 5555H in the last byte sequence. To exit

this mode, the Exit Sec ID command should be executed.

Refer to Table 6 for more details.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between VDD and

VSS, e.g., less than 1 cm away from the VDD pin of the

device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from VDD to VSS should be placed within 1 cm of

the VDD pin.

FIGURE 1: Functional Block Diagram

I/O Buffers

1253 B1.1

Address Buffers

DQ15 - DQ8

AMS-A0WE1#

SuperFlash

Memory

SRAM/

PSRAM

Control Logic

BES1#

BES2

BEF#

OE1#

RESET#

WP#

Address Buffers

& Latches

LBS#

UBS#

DQ7 - DQ0

Notes: 1. For LS package only: WE# = WEF# and/or WES#

OE# = OEF# and/or OES#

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 2: Pin Assignments for 62-ball LFBGA (8mm x 10mm)

FIGURE 3: Pin Assignments for 63-ball LFBGA (8mm x 10mm)

1253 62-tfbga P1.2

A20

A16

WEF#

VSSS

WP#

LBS#

A18

A11

RST#

UBS#

A17

A15

A10

A19

OES#

A14

DQ11

A13

DQ15

DQ13

DQ12

DQ9

BEF#

A12

WES#

DQ6

BES2

DQ10

DQ8

VSSF

DQ14

DQ4

VDDS

DQ2

DQ0

OEF#

DQ7

DQ5

VDDF

DQ3

DQ1

BES1#

A B C D E F G H J K

TOP VIEW (balls facing down)

SST32HF1622C

1253 63-tfbga P2.0

A11

WE#

WP#

LBS#

A15

A12

A19

BES2

RST#

UBS#

A21

A13

A20

A18

A14

A10

A17

A16

DQ6

DQ1

VSS

DQ15

DQ13

DQ4

DQ3

DQ9

OE#

BEF#

VSS

DQ7

DQ12

VDDS

VDDF

DQ10

DQ0

BES1#

DQ14

DQ5

DQ11

DQ2

DQ8

A B C D E F G H J K

TOP VIEW (balls facing down)

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

TABLE 4: Pin Description

Symbol Pin Name Functions

AMS1 to A0Address Inputs To provide flash address, AMS-A0.

To provide SRAM address, AMS-A0

DQ15-DQ0Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle. The outputs are in

tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low

BES1# SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low

BES2 SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high

OEF#2Output Enable To gate the data output buffers for Flash2 only

OES#2Output Enable To gate the data output buffers for SRAM2 only

WEF#2Write Enable To control the Write operations for Flash2 only

WES#2Write Enable To control the Write operations for SRAM2 only

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8

LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0

WP# Write Protect To protect and unprotect sectors from Erase or Program operation

RST# Reset To Reset and return the device to Read mode

VSSF2Ground Flash2 only

VSSS2Ground SRAM2 only

VSS Ground

VDDFPower Supply (Flash) 2.7-3.3V Power Supply to Flash only

VDDSPower Supply (SRAM) 2.7-3.3V Power Supply to SRAM only

NC No Connection Unconnected pins

T4.2 1253

1. AMS = Most Significant Address

AMS = A19 for SST32HF1622C

2. LS package only

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

TABLE 5: Operational Modes Selection1

Mode BEF# BES1# BES22OE#3WE#3LBS# UBS# DQ0-7 DQ8-15

Full Standby VIH VIH XXXXXHIGH-ZHIGH-Z

IL XXXX

Output Disable VIH VIL VIH VIH VIH XXHIGH-Z HIGH-Z

VIL VIH XXV

IH VIH

VIL VIH XV

IH VIH XXHIGH-ZHIGH-Z

Flash Read VIL VIH XV

IL VIH XXD

OUT DOUT

Flash Write VIL VIH X VIH VIL XX D

IN DIN

Flash Erase VIL VIH XV

IH VIL XX X X

SRAM Read VIH V

IL VIH VIL VIH VIL V

IL DOUT DOUT

VIH VIL HIGH-Z DOUT

VIL VIH DOUT HIGH-Z

SRAM Write VIH VIL VIH XV

IL VIL VIL DIN DIN

VIH VIL HIGH-Z DIN

VIL VIH DIN HIGH-Z

Product

Identification4

VIL VIH X VIL VIH X X Manufacturer’s ID5

Device ID5

T5.2 1253

1. X can be VIL or VIH, but no other value.

2. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time

3. OE# = OEF# and OES#

WE# = WEF# and WES# for LS package only

4. Software mode only

5. With AMS-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0=0,

SST32HF1622C Device ID = 234AH, is read with A0=1,

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

TABLE 6: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Erase-Suspend XXXXH B0H

Erase-Resume XXXXH 30H

Query Sec ID55555H AAH 2AAAH 55H 5555H 88H

User Security ID

Word-Program

5555H AAH 2AAAH 55H 5555H A5H WA6Data

User Security ID

Program Lock-Out

5555H AAH 2AAAH 55H 5555H 85H XXH60000H

Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit9,10

/Sec ID Exit

5555H AAH 2AAAH 55H 5555H F0H

Software ID Exit9,10

/Sec ID Exit

XXH F0H

T6.2 1253

1. Address format A14-A0 (Hex).

Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST32HF1622C,

2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence

3. WA = Program Word address

4. SAX for Sector-Erase; uses AMS-A11 address lines

BAX, for Block-Erase; uses AMS-A15 address lines

AMS = Most significant address

AMS = A19 for SST32HF1622C

5. With AMS-A4 = 0; Sec ID is read with A3-A0,

SST ID is read with A3 = 0 (Address range = 000000H to 000007H),

User ID is read with A3 = 1 (Address range = 000010H to 000017H).

Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

7. The device does not remain in Software Product ID Mode if powered down.

8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,

SST32HF1622C Device ID = 234AH, is read with A0 = 1,

AMS = Most significant address

AMS = A19 for SST32HF1622C.

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID

mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and

000010H-000017H.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. VDD = VDDF and VDDS

2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

3. Outputs shorted for no more than one second. No more than one output shorted at a time.

Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.3V

Extended -20°C to +85°C 2.7-3.3V

AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 20 and 21

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

TABLE 7: DC Operating Characteristics (VDD = VDDF and VDDS = 2.7-3.3V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Active VDD Current Address input = VILT/VIHT, at f=5 MHz,

VDD=VDD Max, all DQs open

Read OE#=VIL, WE#=VIH

Flash 18 mA BEF#=VIL, BES1#=VIH, or BES2=VIL

SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Concurrent Operation 40 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Write1WE#=VIL

Flash 35 mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH

SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

ISB Standby VDD Current 30 µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC

IRT Reset VDD Current 30 µA Reset=VSS±0.3V

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOLF Flash Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOHF Flash Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

VOLS SRAM Output Low Voltage 0.4 V IOL =1 mA, VDD=VDD Min

VOHS SRAM Output High Voltage 2.2 V IOH =-500 µA, VDD=VDD Min

T7.1 1253

1. IDD active while Erase or Program is in progress.

TABLE 8: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T8.0 1253

TABLE 9: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 12 pF

T9.0 1253

TABLE 10: Flash Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T10.0 1253

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

AC CHARACTERISTICS

TABLE 11: SRAM Read Cycle Timing Parameters

Symbol Parameter Min Max Units

TRCS Read Cycle Time 70 ns

TAAS Address Access Time 70 ns

TBES Bank Enable Access Time 70 ns

TOES Output Enable Access Time 35 ns

TBYES UBS#, LBS# Access Time 70 ns

TBLZS1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 ns

TOLZS1Output Enable to Active Output 0 ns

TBYLZS1UBS#, LBS# to Active Output 0 ns

TBHZS1BES# to High-Z Output 25 ns

TOHZS1Output Disable to High-Z Output 0 25 ns

TBYHZS1UBS#, LBS# to High-Z Output 35 ns

TOHS Output Hold from Address Change 10 ns

T11.1 1253

TABLE 12: SRAM Write Cycle Timing Parameters

Symbol Parameter Min Max Units

TWCS Write Cycle Time 70 ns

TBWS Bank Enable to End-of-Write 60 ns

TAWS Address Valid to End-of-Write 60 ns

TASTS Address Set-up Time 0 ns

TWPS Write Pulse Width 60 ns

TWRS Write Recovery Time 0 ns

TBYWS UBS#, LBS# to End-of-Write 60 ns

TODWS Output Disable from WE# Low 30 ns

TOEWS Output Enable from WE# High 0 ns

TDSS Data Set-up Time 30 ns

TDHS Data Hold from Write Time 0 ns

T12.1 1253

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

TABLE 13: Flash Read Cycle Timing Parameters VDD = 2.7-3.6V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1BEF# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1BEF# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High before Read 50 ns

TRY1,2 RST# Pin Low to Read Mode 20 µs

T13.1 1253

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

TABLE 14: Flash Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Word-Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and BEF# Setup Time 0 ns

TCH WE# and BEF# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP BEF# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1BEF# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

T14.0 1253

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 4: SRAM Read Cycle Timing Diagram

ADDRESSES AMSS-0

DQ15-0

UBS#, LBS#

OE#

BES1#

BES2

TRCS

TAAS

TBES

TOES

TBLZS

TOLZS TBYES

TBYLZS TBYHZS

DATA VALID

TOHZS

TBHZS

TOHS

1253 F03.0

TBES

Note: AMSS = Most Significant SRAM Address

AMSS = A16 for SST32HF1622C

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 5: SRAM Write Cycle Timing Diagram (WE# Controlled)1

TAWS

ADDRESSES AMSS3-0

BES1#

BES2

WE#

UBS#, LBS#

TWPS TWRS

TWCS

TASTS

TBWS

TBYWS

TODWS

TOEWS

TDSS TDHS

1253 F04.0

DQ15-8, DQ7-0 VALID DATA IN

TBWS

NOTE 2 NOTE 2

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A16 for SST32HF1622C

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 6: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)1

ADDRESSES AMSS3-0

WE#

BES1#

BES2

TBWS

TAWS

TWCS

TWPS TWRS

TASTS TBYWS

DQ15-8, DQ7-0 VALID DATA IN

TDSS TDHS

UBS#, LBS#

1253 F05.0

NOTE 2 NOTE 2

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A16 for SST32HF1622C

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 7: Flash Read Cycle Timing Diagram

FIGURE 8: Flash WE# Controlled Program Cycle Timing Diagram

1253 F06.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

BEF#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

1253 F07.0

ADDRESS AMS-0

DQ15-0

TDH

TWPH TDS

TWP

TAH

TAS

TCH

TCS

BEF#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 9: BEF# Controlled Flash Program Cycle Timing Diagram

FIGURE 10: Flash Data# Polling Timing Diagram

1253 F08.0

ADDRESS AMS-0

DQ15-0

TDH

TCPH TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

BEF#

TBP

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

1253 F09.0

ADDRESSES AMSF-0

DQ7Data Data# Data# Data

WE#

OE#

BEF#

TOEH

TOE

TCE

TOES

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 11: Flash Toggle Bit Timing Diagram

FIGURE 12: WE# Controlled Flash Chip-Erase Timing Diagram

1253 F10.0

ADDRESSES AMSF-0

DQ6 and DQ2

WE#

OE#

BEF#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

1253 F11.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

BEF#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14)

X can be VIL or VIH, but no other value.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 13: WE# Controlled Flash Block-Erase Timing Diagram

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

This device also supports BEF# controlled Block-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14.)

BAX = Block Address

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value.

1253 F13.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

BEF#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 14: WE# Controlled Flash Sector-Erase Timing Diagram

1253 F12.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

BEF#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

This device also supports BEF# controlled Sector-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14.)

SAX = Sector Address

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 15: Software ID Entry and Read

FIGURE 16: Software ID Exit and Reset

1253 F14.0

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2 MFG ID

5555 2AAA 5555 0000 0001

OE#

BEF#

THREE-WORD SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BF

DEVICE ID

XX55XXAA XX90

Note: X can be VIL or VIH, but no other value.

Device ID - See Table 3 on page 5

1253 F15.0

ADDRESS A14-0

DQ15-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-WORD SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

BEF#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 17: Flash Sec ID Entry

1253 F26.0

ADDRESS AMSF-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555

OE#

BEF#

THREE-BYTE SEQUENCE FOR

SEC ID ENTRY

TWP

TWPH TAA

XX55XXAA XX88

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF1622C

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 18: RST# Timing Diagram (When no internal operation is in progress)

FIGURE 19: RST# Timing Diagram (During Program or Erase operation)

1253 F23.0

RST#

BEF#/OE#

TRP

TRHR

1253 F24.0

RST#

BEF#/OE#

End-of-Write Detection

(Toggle-Bit)

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 20: AC Input/Output Reference Waveforms

FIGURE 21: A Test Load Example

1253 F16.0

REFERENCE POINTS OUTPUTINPUT

IHT

ILT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te st

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1253 F17.0

TO TESTER

TO DUT

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 22: Word-Program Algorithm

1253 F18.0

Start

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XXA0H

Address: 5555H

Write Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can be VIL or VIH, but no other value

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 23: Wait Options

1253 F19.0

Wait TBP,

TSCE, or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 24: Sec ID/Software ID Command Flowcharts

X can be VIL or VIH, but no other value

1253 F20.0

Load data: XXAAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

Sec ID Query Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX88H

Address: 5555H

Wait TIDA

Read Sec ID

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 25: Software ID/Sec ID Command Flowcharts

1253 F25.0

Load data: XXAAH

Address: 5555H

Software ID Exit/Sec ID Exit

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 26: Erase Command Sequence

1253 F21.0

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

FIGURE 27: Concurrent Operation Flowchart

1253 F22.0

Load SDP

Command

Sequence

Concurrent

Operation

Flash

Program/Erase

Initiated

Wait for End of

Write Indication

Flash Operation

Completed

End Concurrent

Operation

Read or Write

SRAM

End

Wait

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

SST32HFxxxxC - XXX -XX-XXX X

Environmental Attribute

E1 = non-Pb

Package Modifier

FS = 63 ball positions

S = 62 ball positions

Package Type

L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Device

C = Standard SRAM

Hardware Block Protection

2 = Top Boot Block

SRAM Density

2 = 2 Mbit

Flash Density

16 = 16 Mbit

Voltage

H = 2.7-3.3V

Product Series

32 = MPF+ + SRAM ComboMemory

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

Valid combinations for SST32HF1622C

SST32HF1622C-70-4C-LS SST32HF1622C-70-4C-LFS

SST32HF1622C-70-4C-LSE SST32HF1622C-70-4C-LFSE

SST32HF1622C-70-4E-LS SST32HF1622C-70-4E-LFS

SST32HF1622C-70-4E-LSE SST32HF1622C-70-4E-LFSE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

PACKAGING DIAGRAMS

62-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 8mm x 10mm

SST Package Code: LS

63-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 8mm x 10mm

SST Package Code: LFS

A1 CORNER

K J H G F E D C B A

A B C D E F G H J K

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

0.40 ± 0.05

(62X)

A1 CORNER

10.00 ± 0.20

0.80

5.60

0.80

7.20

62-lfbga-LS-8x10-400mic-4

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.32 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE 0.32 ± 0.05

1.30 ± 0.10

0.12

A1 CORNER

K J H G F E D C B A

A B C D E F G H J K

BOTTOM VIEWTOP VIEW

8.0 ± 0.1

0.40 ± 0.05

(63X)

A1 CORNER

10.0 ± 0.1

0.80

5.60

0.80

7.20

63-lfbga-LFS-8x10-400mic-1

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size: 0.32 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE 0.32 ± 0.05

1.3 ± 0.1

0.12

http://store.iiic.cc/

EOL Data Sheet

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1622C

TABLE 15: Revision History

Number Description Date

00 •Initial Release Feb 2004

01 •Added SST32HF1622C device and associated MPNs

•Removed SST32HF3282C and SST32HF6482C devices and associated MPNs

Jun 2004

02 •Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz

See Table 7 on page 12

•Added Table 2 on page 5 for the Boot Block address ranges

•Updated L2S package outline drawing and pin assignments

•Added RoHS compliance information on page 1 and in the

“Product Ordering Information” on page 33

•Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on

page 11.

•Removed all 90 ns information and associated MPNs beginning on page 34

•Added all non-Pb MPNs beginning on page 34

Mar 2005

03 •Removed SST32HF6482 commercial temperature devices and MPNs

•Moved SST32HF6482 extended temperature MPNs to S71299 data sheet

May 2005

04 •EOLed all valid combination of SST32HF1642 / SST32HF1682 / SST32HF1642C /

SST32GF3242 / SST32GF3282 / SST32GF3242C see S71253(01)

Jul 2007

05•End-of-Life data sheet for all devices in S71253

•Recommended replacement device is SST34HF3284-70-4E-LSE in S71335

Feb 2008

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

http://store.iiic.cc/