LT3844
1
3844f
TYPICAL APPLICATIO
U
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
■
Industrial Power Distribution
■
12V and 42V Automotive and Heavy Equipment
■
High Voltage Single Board Systems
■
Distributed Power Systems
■
Avionics
■
Telecom Power
■
High Voltage Operation: Up to 60V
■
Output Voltages up to 36V (Step-Down)
■
Programmable Constant Frequency: 100kHz to
500kHz
■
Synchronizable up to 600kHz
■
Burst Mode
®
Operation: 120µA Supply Current
■
10µA Shutdown Supply Current
■
±1.3% Reference Accuracy
■
Drives N-Channel MOSFET
■
Programmable Soft-Start
■
Programmable Undervoltage Lockout
■
Internal High Voltage Regulator for Gate Drive
■
Thermal Shutdown
■
Current Limit Unaffected by Duty Cycle
■
16-Pin Thermally Enhanced TSSOP Package
High Voltage, Current Mode
Switching Regulator Controller with
Programmable Operating Frequency
Efficiency and Power Loss
vs Load Current
High Voltage Step-Down Regulator 48V to 12V, 50W
The LT
®
3844 is a DC/DC controller used for medium
power, low part count, high efficiency supplies. It offers
a wide 4V-60V input range (7.5V minimum startup volt-
age) and can implement step-down, step-up, inverting
and SEPIC topologies.
The LT3844 includes Burst Mode operation, which re-
duces quiescent current below 120µA and maintains high
efficiency at light loads. An internal high voltage bias
regulator allows for simple biasing.
Additional features include current mode control for fast
line and load transient response; programmable fixed
operating frequency that can be synchronized to an exter-
nal clock for noise sensitive applications; a gate driver
capable of driving large N-channel MOSFETs; a precision
undervoltage lockout function; 10µA shutdown current;
short-circuit protection and a programmable soft-start
function.
The LT3844 is available in a 16-lead thermally enhanced
TSSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5731694, 6498466, 6611131.
V
IN
SHDN
CSS
BURST_EN
VFB
VC
SYNC
fSET
BOOST
TG
SW
V
CC
PGND
SENSE
+
SENSE
–
SGND
LT3844
3844 TA01
R7
49.9k
V
OUT
12V
50W
68µF
680p
22µF
120pF
68µF
10k
10Ω
1000pF
0.22µF
10µH
33µF
0.02Ω
14.7k130k
82.5k
1 MEG
1µF
PDS5100H
Si7850DP
VIN
36V
TO
60V
LOAD CURRENT (A)
76
82
80
78
90
88
86
84
0
3
2
1
7
6
5
4
3844 TA01b
EFFICIENCY (%)
POWER LOSS (W)
0.1 10
1
LOSS
EFFICIENCY
V
IN
= 48V
LT3844
2
3844f
Input Supply Voltage (V
IN
)......................... 65V to –0.3V
Boosted Supply Voltage (BOOST).............. 80V to –0.3V
Switch Voltage (SW) (Note 8) ...................... 65V to –1V
Differential Boost Voltage
(BOOST to SW) ..................................... 24V to –0.3V
Bias Supply Voltage (V
CC
) ......................... 24V to –0.3V
SENSE
+
and SENSE
–
Voltages ................... 40V to –0.3V
Differential Sense Voltage
(SENSE
+
to SENSE
–
) .................................. 1V to –1V
BURST_EN Voltage.................................... 24V to –0.3V
SYNC, V
C
, V
FB
, C
SS
, and SHDN Voltages ..... 5V to –0.3V
SHDN Pin Currents ................................................. 1mA
Operating Junction Temperature Range (Note 2)
LT3844E (Note 3) ..............................–40°C to 125°C
LT3844I .............................................–40°C to 125°C
Storage Temperature .............................–65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
T
JMAX
= 125°C, θ
JA
= 40°C/W, θ
JC
= 10°C/W
EXPOSED PAD IS SGND (PIN 17)
MUST BE SOLDERED TO PCB
LT3844EFE
LT3844IFE
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, RSET = 49.9kΩ,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = SYNC = 0V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Operating Voltage Range (Note 4) ●460V
V
IN
Minimum Start Voltage ●7.5 V
V
IN
UVLO Threshold (Falling) ●3.6 3.8 4 V
V
IN
UVLO Threshold Hysteresis 670 mV
V
IN
Supply Current V
CC
> 9V 20 µA
V
IN
Burst Mode Current V
BURST_EN
= 0V, V
FB
= 1.35V 20 µA
V
IN
Shutdown Current V
SHDN
= 0V ●10 15 µA
BOOST
Operating Voltage Range ●75 V
BOOST
Operating Voltage Range (Note 5) V
BOOST
- V
SW
●20 V
BOOST
UVLO Threshold (Rising) V
BOOST
- V
SW
5V
BOOST
UVLO Threshold Hysteresis V
BOOST
- V
SW
400 mV
BOOST Supply Current (Note 6) 1.4 mA
BOOST Burst Mode Current V
BURST_EN
= 0V 0.1 µA
BOOST Shutdown Current V
SHDN
= 0V 0.1 µA
V
CC
Operating Voltage Range (Note 5) ●20 V
V
CC
Output Voltage Over Full Line and Load Range ●8 8.3 V
V
CC
UVLO Threshold (Rising) 6.25 V
V
CC
UVLO Threshold Hysteresis 500 mV
V
CC
Supply Current (Note 6) ●1.7 2.1 mA
V
CC
Burst Mode Current V
BURST_EN
= 0V 95 µA
V
CC
Shutdown Current V
SHDN
= 0V 20 µA
V
CC
Current Limit ●–40 –120 mA
Consult LTC Marketing for parts specified with wider operating temperature ranges.
FE PART
MARKING
3844EFE
3844IFE
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
VIN
SHDN
CSS
BURST_EN
VFB
VC
SYNC
fSET
BOOST
TG
SW
VCC
PGND
SENSE+
SENSE–
SGND
17
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LT3844
3
3844f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3844 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LT3844E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, R
SET
= 49.9kΩ,
SENSE– = SENSE+ = 10V, SGND = PGND = SW = SYNC = 0V, unless otherwise noted.
LT3844I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 4: V
IN
voltages below the start-up threshold (7.5V) are only
supported when the V
CC
is externally driven above 6.5V.
Note 5: Operating range is dictated by MOSFET absolute maximum V
GS
.
Note 6: Supply current specification does not include switch drive
currents. Actual supply currents will be higher.
Note 7: DC measurement of gate drive output “ON” voltage is typically
8.6V. Internal dynamic bootstrap operation yields typical gate “ON”
voltages of 9.8V during standard switching operation. Standard operation
gate “ON” voltage is not tested but guaranteed by design.
Note 8: The –1V absolute maximum on the SW pin is a transient
condition. It is guaranteed by design and not subject to test.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amp Reference Voltage Measured at V
FB
Pin 1.224 1.231 1.238 V
●1.215 1.245 V
V
FB
Pin Input Current V
FB
= 1.231V 25 nA
SHDN Enable Threshold (Rising) ●1.3 1.35 1.4 V
SHDN Threshold Hysteresis 120 mV
Sense Pins Common Mode Range ●036V
Current Limit Sense Voltage V
SENSE+
– V
SENSE–
●90 100 115 mV
Input Current V
SENSE(CM)
= 0V 350 µA
(I
SENSE+
+ I
SENSE–
) 2V < V
SENSE(CM)
< 3.5V –25 µA
V
SENSE(CM)
> 4V –170 µA
Operating Frequency 290 300 310 kHz
●270 330 kHz
Minimum Programmable Frequency ●100 kHz
Maximum Programmable Frequency ●500 kHz
External Sync Frequency Range ●100 600 kHz
SYNC Input Resistance 40 kΩ
SYNC Voltage Threshold ●1.4 2 V
Soft-Start Capacitor Control Current 2µA
Error Amp Transconductance ●270 340 410 µS
Error Amp DC Voltage Gain 62 dB
Error Amp Sink/Source Current ±30 µA
TG Drive On Voltage (Note 7) C
LOAD
= 2200pF 9.8 V
TG Drive Off Voltage C
LOAD
= 2200pF 0.1 V
TG Drive Rise/Fall Time 10% to 90% or 90% to 10%, C
LOAD
= 2200pF 40 ns
Minimum TG Off Time ●350 500 ns
Minimum TG On Time ●250 350 ns
LT3844
4
3844f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Shutdown Threshold (Rising)
vs Temperature
Shutdown Threshold (Falling)
vs Temperature V
CC
vs Temperature
VCC vs ICC(LOAD) VCC vs VIN ICC Current Limit vs Temperature
VCC UVLO Threshold (Rising)
vs Temperature
Error Amp Transconductance
vs TemperatureICC vs VCC (SHDN = 0V)
3844 G01
SHUTDOWN THRESHOLD, RISING (V)
1.38
1.37
1.36
1.35
1.34
1.33
1.32
TEMPERATURE (°C)
–50 25 75
3844 G02
–25 0 50 100 125
TEMPERATURE (°C)
–50
SHUTDOWN THRESHOLD, FALLING (V)
1.26
1.25
1.24
1.23
1.22
1.21
1.20 25 75
–25 0 50 100 125
3844 G05
V
IN
(V)
V
CC
(V)
9
8
7
6
5
4
34689
57 10 11 12
3844 G07
TEMPERATURE (°C)
–50 25 75–25 0 50 100 125
3844 G08
V
CC
UVLO THRESHOLD, RISING (V)
6.5
6.4
6.3
6.2
6.1
6.0
TEMPERATURE (°C)
–50
ERROR AMP TRANSCONDUCTANCE (µS)
350
345
340
335
330
325
320 25 75
3844 G09
–25 0 50 100 125
I
CC
= 20mA
T
A
= 25°C
TEMPERATURE (°C)
–50 25 75–25 0 50 100 125
3844 G03
8.2
8.1
8.0
7.9
7.8
7.7
7.6
7.5
V
CC
(V)
I
CC
= 20mA
–50 –25 1000 50 12525 75
TEMPERATURE (°C)
200
175
150
125
100
75
50
3844 G06
I
CC
CURRENT LIMIT (mA)
I
CC(LOAD)
(mA)
0
V
CC
(V)
40
3844 G04
10 20 30
8.05
8.00
7.95
7.90
7.85 51525
35
T
A
= 25°C
V
CC
(V)
0
I
CC
(µA)
15
20
25
16
10
5
0246810
12 14 18 20
T
A
= 25°C
LT3844
5
3844f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
I(SENSE+ + SENSE–) vs
VSENSE (CM)
Operating Frequency
vs Temperature
Error Amp Reference
vs Temperature
Maximum Current Sense
Threshold vs Temperature
VIN UVLO Threshold (Rising)
vs Temperature
V
IN
UVLO Threshold (Falling)
vs Temperature
VSENSE (CM) (V)
0
I(SENSE
+
+ SENSE
–
) (µA)
400
300
200
100
0
–100
–200 0.5 1.0 1.5 2.0
3844 G10
2.5 4.53.5 5.04.03.0
TEMPERATURE (°C)
–50 25 75
3844 G12
–25 0 50 100 125
TEMPERATURE (°C)
–50 25 75
–25 0 50 100 125
TEMPERATURE (°C)
–50 25 75
–25 0 50 100 125
1.234
1.233
1.232
1.231
1.230
1.229
1.228
1.227
ERROR AMP REFERENCE (V)
3844 G14 3844 G15
4.54
4.52
4.50
4.48
4.46
4.44
4.42
4.40
VIN UVLO THRESHOLD, RISING (V)
VIN UVLO THRESHOLD, FALLING (V)
3.86
3.84
3.82
3.80
3.78
3.76
TA = 25°C
TEMPERATURE (°C)
–50
CURRENT SENSE THRESHOLD (mV)
102
104
106
25 75
3844 G16
100
98
–25 0 50 100 125
96
94
TEMPERATURE (°C)
–50
290
OPERATING FREQUENCY (kHz)
292
296
298
300
50
308
3844 G17
294
0
–25 75 100
25 125
302
304
306
UU
U
PI FU CTIO S
V
IN
(Pin 1): The V
IN
pin is the main supply pin and should
be decoupled to SGND with a low ESR capacitor located
close to the pin.
SHDN (Pin 2): The SHDN pin has a precision IC enable
threshold of 1.35V (rising) with 120mV of hysteresis. It is
used to implement an undervoltage lockout (UVLO) cir-
cuit. See Application Information section for implement-
ing a UVLO function. When the SHDN pin is pulled below
a transistor V
BE
(0.7V), a low current shutdown mode is
entered, all internal circuitry is disabled and the V
IN
supply
current is reduced to approximately 9µA. Typical pin input
bias current is <10µA and the pin is internally clamped to
6V.
C
SS
(Pin 3): The soft-start pin is used to program the
supply soft-start function. Use the following formula to
calculate C
SS
for a given output voltage slew rate:
C
SS
= 2µA(t
SS
/1.231V)
The pin should be left unconnected when not using the
soft-start function.
LT3844
6
3844f
UU
U
PI FU CTIO S
BURST_EN (Pin 4): The BURST_EN pin is used to enable
or disable Burst Mode operation. Connect the BURST_EN
pin to ground to enable the burst mode function. Connect
the pin to V
FB
or V
CC
to disable the burst mode function.
V
FB
(Pin 5): The output voltage feedback pin, V
FB
, is
externally connected to the supply output voltage via a
resistive divider. The V
FB
pin is internally connected to the
inverting input of the error amplifier. In regulation, V
FB
is
1.231V.
V
C
(Pin 6): The V
C
pin is the output of the error amplifier
whose voltage corresponds to the maximum (peak) switch
current per oscillator cycle. The error amplifier is typically
configured as an integrator circuit by connecting an RC
network from the V
C
pin to SGND. This circuit creates the
dominant pole for the converter regulation control loop.
Specific integrator characteristics can be configured to
optimize transient response. When Burst Mode operation
is enabled (see Pin 4 description), an internal low imped-
ance clamp on the V
C
pin is set at 100mV below the burst
threshold, which limits the negative excursion of the pin
voltage. Therefore, this pin cannot be pulled low with a low
impedance source. If the V
C
pin must be externally ma-
nipulated, do so through a 1kΩ series resistance.
SYNC (Pin 7): The Sync pin provides an external clock
input for synchronization of the internal oscillator. R
SET
is
set such that the internal oscillator frequency is 10% to
25% below the external clock frequency. If unused the
Sync pin is connected to SGND. For more information see
“Oscillator Sync” in the Application Information section of
this datasheet.
f
SET
(Pin 8): The f
SET
pin programs the oscillator fre-
quency with an external resistor, R
SET
. The resistor is
required even when supplying external sync clock signal.
See the Applications Information section for resistor value
selection details.
SGND (Pin 9, 17): The SGND pin is the low noise ground
reference. It should be connected to the –V
OUT
side of the
output capacitors. Careful layout of the PCB is necessary
to keep high currents away from this SGND connection.
See the Application Information section for helpful hints
on PCB layout of grounds.
SENSE
–
(Pin 10): The SENSE
–
pin is the negative input for
the current sense amplifier and is connected to the V
OUT
side of the sense resistor for step-down applications. The
sensed inductor current limit is set to 100mV across the
SENSE inputs.
SENSE
+
(Pin 11): The SENSE
+
pin is the positive input for
the current sense amplifier and is connected to the induc-
tor side of the sense resistor for step-down applications.
The sensed inductor current limit is set to 100mV across
the SENSE inputs.
PGND (Pin 12): The PGND pin is the high-current ground
reference for internal low side switch and the V
CC
regulator
circuit. Connect the pin directly to the negative terminal of
the V
CC
decoupling capacitor. See the Application Infor-
mation section for helpful hints on PCB layout of grounds.
V
CC
(Pin 13): The V
CC
pin is the internal bias supply
decoupling node. Use a low ESR 1µF or greater ceramic
capacitor to decouple this node to PGND. Most internal IC
functions are powered from this bias supply. An external
diode connected from V
CC
to the BOOST pin charges the
bootstrapped capacitor during the off-time of the main
power switch. Back driving the V
CC
pin from an external DC
voltage source, such as the V
OUT
output of the regulator
supply, increases overall efficiency and reduces power
dissipation in the IC. In shutdown mode this pin sinks
20µA until the pin voltage is discharged to 0V.
SW (Pin 14): In step-down applications the SW pin is
connected to the cathode of an external clamping Schottky
diode, the drain of the power MOSFET and the inductor.
The SW node voltage swing is from V
IN
during the on-time
of the power MOSFET, to a Schottky voltage drop below
ground during the off-time of the power MOSFET. In start-
up and in operating modes where there is insufficient
inductor current to freewheel the Schottky diode, an
internal switch is turned on to pull the SW pin to ground
so that the BOOST pin capacitor can be charged. Give
careful consideration in choosing the Schottky diode to
limit the negative voltage swing on the SW pin.
TG (Pin 15): The TG pin is the bootstrapped gate drive for
the top N-Channel MOSFET. Since very fast high currents
are driven from this pin, connect it to the gate of the power
MOSFET with a short and wide, typically 0.02” width, PCB
trace to minimize inductance.
LT3844
7
3844f
BOOST (Pin 16): The BOOST pin is the supply for the
bootstrapped gate drive and is externally connected to a
low ESR ceramic boost capacitor referenced to SW pin.
The recommended value of the BOOST capacitor,C
BOOST
,
is 50 times greater than the total input capacitance of the
topside MOSFET. In most applications 0.1µF is adequate.
The maximum voltage that this pin sees is V
IN
+ V
CC
,
ground referred, and should not exceed 75V.
Exposed Pad (SGND) (Pin 17): The exposed leadframe is
internally connected to the SGND pin. Solder the exposed
pad to the PCB ground for electrical contact and optimal
thermal performance.
UU
U
PI FU CTIO S
FU CTIO AL DIAGRA
UU
W
–+
–+
–
+
–
+
VIN
UVLO
(<4V)
BST
UVLO
8V
REGULATOR
FEEDBACK
REFERENCE
–
+
–
+
1.231V
3.8V
REGULATOR INTERNAL
SUPPLY RAIL
1
9
6
VIN VCC
UVLO
(<6V)
SHDN
DRIVE
CONTROL
NOL
SWITCH
LOGIC
DRIVE
CONTROL
BURST_EN
VC
CSS
SENSE–
VFB
0.5V
2µA
50µA
BURST MODE
OPERATION
R
SQ
OSCILLATOR
SLOPE COMP
GENERATOR
BOOST
TG
SW
VCC
PGND
SYNC
fSET
RSET
SENSE+
SGND
BOOSTED SWITCH
DRIVER
CURRENT
SENSE
COMPARATOR
12
7
8
13
14
10
11
5
3
100mV
4
2
16
15
VREF + 200mV
SOFT-START
BURST DISABLE
DRIVER
FAULT CONDITION:
VIN UVLO
VCC UVLO
VSHDN UVLO
CSS CLAMPED TO
VFB + VBE
VREF
~1V
–
+
gm
ERROR
AMP
–+
M1
D2
D3
D1
L1
(OPTIONAL)
RSENSE
3844 FD
CC2
CC1
R1
RA
RB
VIN
CIN
R2
CBOOST
VOUT
COUT
CVCC
RC
LT3844
8
3844f
The LT3844 is a PWM controller with a constant fre-
quency, current mode control architecture. It is designed
for low to medium power, switching regulator applica-
tions. Its high operating voltage capability allows it to step-
up or down input voltages up to 60V without the need for
a transformer. The LT3844 is used in nonsynchronous
applications, meaning that a freewheeling rectifier diode
(D1 of Function Diagram) is used instead of a bottom side
MOSFET. For circuit operation, please refer to the Func-
tional Diagram of the IC and Typical Application on the
front page of the data sheet. The LT3800 is a similar part
that uses synchronous rectification, replacing the diode
with a MOSFET in a step-down application.
Main Control Loop
During normal operation, the external N-channel MOSFET
switch is turned on at the beginning of each cycle. The
switch stays on until the current in the inductor exceeds a
current threshold set by the DC control voltage, V
C
, which
is the output of the voltage control loop. The voltage
control loop monitors the output voltage, via the V
FB
pin
voltage, and compares it to an internal 1.231V reference.
It increases the current threshold when the V
FB
voltage is
below the reference voltage and decreases the current
threshold when the V
FB
voltage is above the reference
voltage. For instance, when an increase in the load current
occurs, the output voltage drops causing the V
FB
voltage
to drop relative to the 1.231V reference. The voltage
control loop senses the drop and increases the current
threshold. The peak inductor current is increased until the
average inductor current equals the new load current and
the output voltage returns to regulation.
Current Limit/Short-Circuit
The inductor current is measured with a series sense
resistor (see the Typical Application on the front page).
When the voltage across the sense resistor reaches the
maximum current sense threshold, typically 100mV, the
TG MOSFET driver is disabled for the remainder of that
cycle. If the maximum current sense threshold is still
exceeded at the beginning of the next cycle, the entire cycle
is skipped. Cycle skipping keeps the inductor currents to
a reasonable value during a short-circuit, particularly
when V
IN
is high. Setting the sense resistor value is
discussed in the “Application Information” section.
V
CC
/Boosted Supply
An internal V
CC
regulator provides V
IN
derived gate-drive
power for start-up under all operating conditions with
MOSFET gate charge loads up to 90nC. The regulator can
operate continuously in applications with V
IN
voltages up
to 60V, provided the power dissipation of the regulator
does not exceed 250mW. The power dissipation is calcu-
lated as follows:
P
d(REG)
= (V
IN
– 8V) • f
SW
• Q
G
where Q
G
is the MOSFET gate charge.
In applications where these conditions are exceeded, V
CC
must be derived from an external source after start-up.
Maximum continuous regulator power dissipation may be
exceeded for short duration V
IN
transients.
For higher converter efficiency and less power dissipation
in the IC, V
CC
can also be supplied from an external supply
such as the converter output. When an external supply
back drives the internal V
CC
regulator through an external
diode and the V
CC
voltage is pulled to a diode above its
regulation voltage, the internal regulator is disabled and
goes into a low current mode. V
CC
is the bias supply for
most of the internal IC functions and is also used to charge
the bootstrapped capacitor (C
BOOST
) via an external diode.
The external MOSFET switch is biased from the
bootstrapped capacitor. While the external MOSFET switch
is off, an internal BJT switch, whose collector is connected
to the SW pin and emitter is connected to the PGND pin,
is turned on to pull the SW node to PGND and recharge the
bootstrap capacitor. The switch stays on until either the
start of the next cycle or until the bootstrapped capacitor
is fully charged.
MOSFET Driver
The LT3844 contains a high speed boosted driver to turn
on and off an external N-channel MOSFET switch. The
MOSFET driver derives its power from the boost capacitor
which is referenced to the SW pin and the source of the
MOSFET. The driver provides a large pulse of current to
turn on the MOSFET fast to minimize transition times.
Multiple MOSFETs can be paralleled for higher current
operation.
OPERATIO
U
(Refer to Functional Diagram)
LT3844
9
3844f
To eliminate the possibility of shoot through between the
MOSFET and the internal SW pull-down switch, an adap-
tive nonoverlap circuit ensures that the internal pull-down
switch does not turn on until the gate of the MOSFET is
below its turn on threshold.
Low Current Operation (Burst Mode Operation)
To increase low current load efficiency, the LT3844 is
capable of operating in Linear Technology’s proprietary
Burst Mode operation where the external MOSFET oper-
ates intermittently based on load current demand. The
Burst Mode function is disabled by connecting the
BURST_EN pin to V
CC
or V
FB
and enabled by connecting
the pin to SGND.
When the required switch current, sensed via the V
C
pin
voltage, is below 15% of maximum, Burst Mode operation
is employed and that level of sense current is latched onto
the IC control path. If the output load requires less than
this latched current level, the converter will overdrive the
output slightly during each switch cycle. This overdrive
condition is sensed internally and forces the voltage on the
V
C
pin to continue to drop. When the voltage on V
C
drops
150mV below the 15% load level, switching is disabled,
and the LT3844 shuts down most of its internal circuitry,
reducing total quiescent current to 120µA. When the
converter output begins to fall, the V
C
pin voltage begins
to climb. When the voltage on the V
C
pin climbs back to the
15% load level, the IC returns to normal operation and
switching resumes. An internal clamp on the V
C
pin is set
at 100mV below the output disable threshold, which limits
the negative excursion of the pin voltage, minimizing the
converter output ripple during Burst Mode operation.
During Burst Mode operation, the V
IN
pin current is 20µA
and the V
CC
current is reduced to 100µA. If no external
drive is provided for V
CC
, all V
CC
bias currents originate
from the V
IN
pin, giving a total V
IN
current of 120µA. Burst
current can be reduced further when V
CC
is driven using an
output derived source, as the V
CC
component of V
IN
current is then reduced by the converter duty cycle ratio.
Start-Up
The following section describes the start-up of the supply
and operation down to 4V once the step-down supply is up
and running. For the protection of the LT3844 and the
switching supply, there are internal undervoltage lockout
(UVLO) circuits with hysteresis on V
IN
, V
CC
and V
BOOST
, as
shown in the Electrical Characteristics table. Start-up and
continuous operation require that all three of these
undervoltage lockout conditions be satisfied because the
TG MOSFET driver is disabled during any UVLO fault
condition. In startup, for most applications, V
CC
is pow-
ered from V
IN
through the high voltage linear regulator of
the LT3844. This requires V
IN
to be high enough to drive
the V
CC
voltage above its undervoltage lockout threshold.
V
CC
, in turn, has to be high enough to charge the BOOST
capacitor through an external diode so that the BOOST
voltage is above its undervoltage lockout threshold. There
is an NPN switch that pulls the SW node to ground each
cycle during the TG power MOSFET off-time, ensuring the
BOOST capacitor is kept fully charged. Once the supply is
up and running, the output voltage of the supply can
backdrive V
CC
through an external diode. Internal circuitry
disables the high voltage regulator to conserve V
IN
supply
current. Output voltages that are too low or too high to
backdrive V
CC
require additional circuitry such as a voltage
doubler or linear regulator. Once V
CC
is backdriven from a
supply other than V
IN
, V
IN
can be reduced to 4V with
normal operation maintained.
Soft-Start
The soft-start function controls the slew rate of the power
supply output voltage during start-up. A controlled output
voltage ramp minimizes output voltage overshoot, re-
duces inrush current from the V
IN
supply, and facilitates
supply sequencing. A capacitor, C
SS
, connected from the
C
SS
pin to SGND, programs the slew rate. The capacitor is
charged from an internal 2µA current source producing a
ramped voltage. The capacitor voltage overrides the inter-
nal reference to the error amplifier. If the V
FB
pin voltage
OPERATIO
U
(Refer to Functional Diagram)
LT3844
10
3844f
exceeds the C
SS
pin voltage then the current threshold set
by the DC control voltage, V
C
, is decreased and the
inductor current is lowered. This in turn decreases the
output voltage slew rate allowing the C
SS
pin voltage ramp
to catch up to the V
FB
pin voltage. An internal 100mV offset
is added to the V
FB
pin voltage relative to the to C
SS
pin
voltage so that at start-up the soft-start circuit will dis-
charge the V
C
pin voltage below the DC control voltage
equivalent to zero inductor current. This will reduce the
input supply inrush current. The soft-start circuit is dis-
abled once the C
SS
pin voltage has been charged to 200mV
above the internal reference of 1.231V.
During a V
IN
UVLO, V
CC
UVLO or SHDN UVLO event, the
C
SS
pin voltage is discharged with a 50µA current source.
In normal operation the C
SS
pin voltage is clamped to a
diode above the V
FB
pin voltage. Therefore, the value of the
C
SS
capacitor is relevant in how long of a fault event will
retrigger a soft-start. In other words, if any of the above
UVLO conditions occur, the C
SS
pin voltage will be dis-
charged with a 50µA current source. There is a diode worth
of voltage headroom to ride through the fault before the
C
SS
pin voltage enters its active region and the soft-start
function is enabled.
Also, since the C
SS
pin voltage is clamped to a diode above
the V
FB
pin voltage, during a short circuit the C
SS
pin
voltage is pulled low because the V
FB
pin voltage is low.
Once the short has been removed the V
FB
pin voltage starts
to recover. The soft-start circuit takes control of the output
voltage slew rate once the V
FB
pin voltage has exceeded
the slowly ramping C
SS
pin voltage, reducing the output
voltage overshoot during a short circuit recovery.
OPERATIO
U
(Refer to Functional Diagram)
Slope/Antislope Compensation
The IC incorporates slope compensation to eliminate
potential subharmonic oscillations in the current control
loop. The IC’s slope compensation circuit imposes an
artificial ramp on the sensed current to increase the rising
slope as duty cycle increases.
Typically, this additional ramp affects the sensed current
value, thereby reducing the achievable current limit value
by the same amount as the added ramp represents. As
such, the current limit is typically reduced as the duty cycle
increases. The LT3844, however, contains antislope com-
pensation circuitry to eliminate the current limit reduction
associated with slope compensation. As the slope com-
pensation ramp is added to the sensed current, a similar
ramp is added to the current limit threshold. The end result
is that the current limit is not compromised so the LT3844
can provide full power regardless of required duty cycle.
Shutdown
The LT3844 includes a shutdown mode where all the
internal IC functions are disabled and the V
IN
current is
reduced to less than 10µA. The shutdown pin can be used
for undervoltage lockout with hysteresis, micropower
shutdown or as a general purpose on/off control of the
converter output. The shutdown function has two thresh-
olds. The first threshold, a precision 1.23V threshold with
120mV of hysteresis, disables the converter from switch-
ing. The second threshold, approximately a 0.7V refer-
enced to SGND, completely disables all internal circuitry
and reduces the V
IN
current to less than 10µA. See the
Application Information section for more information.
APPLICATIO S I FOR ATIO
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The basic LT3844 step-down (buck) application, shown in
the Typical Application on the front page, converts a larger
positive input voltage to a lower positive or negative
output voltage. This Application Information section as-
sists selection of external components for the require-
ments of the power supply.
R
SENSE
Selection
The current sense resistor, R
SENSE
, monitors the inductor
current of the supply (See Typical Application on front
page). Its value is chosen based on the maximum required
output load current. The LT3844 current sense amplifier
has a maximum voltage threshold of, typically, 100mV.
LT3844
11
3844f
Therefore, the peak inductor current is 100mV/R
SENSE
.
The maximum output load current, I
OUT(MAX)
, is the peak
inductor current minus half the peak-to-peak ripple cur-
rent, ∆I
L
.
Allowing adequate margin for ripple current and external
component tolerances, R
SENSE
can be calculated as
follows:
RmV
I
SENSE OUT MAX
=70
()
Typical values for R
SENSE
are in the range of 0.005Ω
to 0.05Ω.
Operating Frequency
The choice of operating frequency and inductor value is a
trade off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses and gate charge losses. How-
ever, lower frequency operation requires more inductance
for a given amount of ripple current, resulting in a larger
inductor size and higher cost. If the ripple current is
allowed to increase, larger output capacitors may be
required to maintain the same output ripple. For convert-
ers with high step-down V
IN
to V
OUT
ratios, another
consideration is the minimum on-time of the LT3844 (see
the Minimum On-time Considerations section). A final
consideration for operating frequency is that in noise-
sensitive communications systems, it is often desirable to
keep the switching noise out of a sensitive frequency band.
The LT3844 uses a constant frequency architecture that
can be programmed over a 100kHz to 500kHz range with
a single resistor from the f
SET
pin to ground, as shown in
Figure 1. The nominal voltage on the f
SET
pin is 1V and the
current that flows from this pin is used to charge an
internal oscillator capacitor. The value of R
SET
for a given
operating frequency can be chosen from Figure 4 or from
the following equation:
Rk f
SET SW
() .• •
(– . )
Ω=84 10
4131
The following table lists typical resistor values for com-
mon operating frequencies:
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Recommended 1% Standard Values
R
SET
f
SW
191kΩ100kHz
118kΩ150kHz
80.6kΩ200kHz
63.4kΩ250kHz
49.9kΩ300kHz
40.2kΩ350kHz
33.2kΩ400kHz
27.4kΩ450kHz
23.2kΩ500kHz
Figure 1. Timing Resistor (RSET) Value
FREQUENCY (kHz)
0
20
R
SET
(kΩ)
40
80
100
120
400
200
3844 G19
60
200
100 500
300 600
140
160
180
Step-Down Converter: Inductor Selection
The critical parameters for selection of an inductor are
minimum inductance value, volt-second product, satura-
tion current and/or RMS current.
For a given ∆I, The minimum inductance value is calcu-
lated as follows:
LV VV
fV I
OUT IN MAX OUT
SW IN MAX L
≥∆
•–
••
()
()
f
SW
is the switch frequency.
LT3844
12
3844f
The typical range of values for ∆I
L
is (0.2 • I
OUT(MAX)
) to
(0.5 • I
OUT(MAX)
), where I
OUT(MAX)
is the maximum load
current of the supply. Using ∆I
L
= 0.3 • I
OUT(MAX)
yields a
good design compromise between inductor performance
versus inductor size and cost. A value of ∆I
L
= 0.3 •
I
OUT(MAX)
produces a ±15% of I
OUT(MAX)
ripple current
around the DC output current of the supply. Lower values
of ∆I
L
require larger and more costly magnetics. Higher
values of ∆I
L
will increase the peak currents, requiring
more filtering on the input and output of the supply. If ∆I
L
is too high, the slope compensation circuit is ineffective
and current mode instability may occur at duty cycles
greater than 50%. To satisfy slope compensation require-
ments the minimum inductance is calculated as follows:
LV DC
DC
R
f
OUT MAX
MAX
SENSE
SW
>•–••.
21 833
Some magnetics vendors specify a volt-second product in
their datasheet. If they do not, consult the magnetics
vendor to make sure the specification is not being ex-
ceeded by your design. The volt-second product is calcu-
lated as follows:
Volt-second (µsec) =
(–)•
•
()
()
VVV
Vf
IN MAX OUT OUT
IN MAX SW
The magnetics vendors specify either the saturation cur-
rent, the RMS current or both. When selecting an inductor
based on inductor saturation current, use the peak current
through the inductor, I
OUT(MAX)
+ ∆I
L
/2. The inductor
saturation current specification is the current at which the
inductance, measured at zero current, decreases by a
specified amount, typically 30%.
When selecting an inductor based on RMS current rating,
use the average current through the inductor, I
OUT(MAX)
.
The RMS current specification is the RMS current at which
the part has a specific temperature rise, typically 40°C,
above 25°C ambient.
After calculating the minimum inductance value, the volt-
second product, the saturation current and the RMS
current for your design, select an off-the-shelf inductor.
Contact the Application group at Linear Technology for
further support.
For more detailed information on selecting an inductor,
please see the “Inductor Selection” section of Linear
Technology Application Note 44.
Step-Down Converter: MOSFET Selection
The selection criteria of the external N-channel standard
level power MOSFET include on resistance(R
DS(ON)
), re-
verse transfer capacitance (C
RSS
), maximum drain source
voltage (V
DSS
), total gate charge (Q
G
) and maximum
continuous drain current.
For maximum efficiency, minimize R
DS(ON)
and C
RSS
. Low
R
DS(ON)
minimizes conduction losses while low C
RSS
minimizes transition losses. The problem is that R
DS(ON)
is inversely related to C
RSS
. Balancing the transition losses
with the conduction losses is a good idea in sizing the
MOSFET. Select the MOSFET to balance the two losses.
Calculate the maximum conduction losses of the MOSFET:
PI V
VR
COND OUT MAX OUT
IN DS ON
=⎛
⎝
⎜⎞
⎠
⎟
()()
() ()
2
Note that R
DS(ON)
has a large positive temperature depen-
dence. The MOSFET manufacturer’s data sheet contains a
curve, R
DS(ON)
vs Temperature.
Calculate the maximum transition losses:
P
TRAN
= (k)(V
IN
)
2
(I
OUT(MAX)
)(C
RSS
)(f
SW
)
where k is a constant inversely related to the gate driver
current, approximated by k = 2 for LT3844 applications.
The total maximum power dissipation of the MOSFET is
the sum of these two loss terms:
P
FET(TOTAL)
= P
COND
+ P
TRAN
To achieve high supply efficiency, keep the P
FET(TOTAL)
to
less than 3% of the total output power. Also, complete a
thermal analysis to ensure that the MOSFET junction
temperature is not exceeded.
T
J
= T
A
+ P
FET(TOTAL)
• θ
JA
where θ
JA
is the package thermal resistance and T
A
is the
ambient temperature. Keep the calculated T
J
below the
maximum specified junction temperature, typically 150°C.
APPLICATIO S I FOR ATIO
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LT3844
13
3844f
APPLICATIO S I FOR ATIO
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Note that when V
IN
is high and f
SW
is high, the transition
losses may dominate. A MOSFET with higher R
DS(ON)
and
lower C
RSS
may provide higher efficiency. MOSFETs with
higher voltage V
DSS
specification usually have higher
R
DS(ON)
and lower C
RSS
.
Choose the MOSFET V
DSS
specification to exceed the
maximum voltage across the drain to the source of the
MOSFET, which is V
IN(MAX)
plus any additional ringing on
the switch node. Ringing on the switch node can be greatly
reduced with good PCB layout and, if necessary, an RC
snubber.
The internal V
CC
regulator is capable of sourcing up to
40mA which limits the maximum total MOSFET gate
charge, Q
G
, to 40mA/f
SW
. The Q
G
vs V
GS
specification is
typically provided in the MOSFET data sheet. Use Q
G
at V
GS
of 8V. If V
CC
is back driven from an external supply, the
MOSFET drive current is not sourced from the internal
regulator of the LT3844 and the Q
G
of the MOSFET is not
limited by the IC. However, note that the MOSFET drive
current is supplied by the internal regulator when the
external supply back driving V
CC
is not available such as
during startup or short-circuit.
The manufacturer’s maximum continuous drain current
specification should exceed the peak switch current,
I
OUT(MAX)
+ ∆I
L
/2.
During the supply startup, the gate drive levels are set by
the V
CC
voltage regulator, which is approximately 8V.
Once the supply is up and running, the V
CC
can be back
driven by an auxiliary supply such as V
OUT
. It is important
not to exceed the manufacturer’s maximum V
GS
specifica-
tion. A standard level threshold MOSFET typically has a
V
GS
maximum of 20V.
Step-Down Converter: Rectifier Selection
The rectifier diode (D1 on the Functional Diagram) in a
buck converter generates a current path for the inductor
current when the main power switch is turned off. The
rectifier is selected based upon the forward voltage, re-
verse voltage and maximum current. A Schottky diode is
recommended. Its low forward voltage yields the lowest
power loss and highest efficiency. The maximum reverse
voltage that the diode will see is V
IN(MAX)
.
In continuous mode operation, the average diode current
is calculated at maximum output load current and maxi-
mum V
IN
:
II
VV
V
DIODE AVG OUT MAX IN MAX OUT
IN MAX
() ( )()
()
=−
To improve efficiency and to provide adequate margin
for short-circuit operation, a diode rated at 1.5 to 2 times
the maximum average diode current, I
DIODE(AVG)
, is
recommended.
Step-Down Converter: Input Capacitor Selection
A local input bypass capacitor is required for buck con-
verters because the input current is pulsed with fast rise
and fall times. The input capacitor selection criteria are
based on the bulk capacitance and RMS current capability.
The bulk capacitance will determine the supply input ripple
voltage. The RMS current capability is used to keep from
overheating the capacitor.
The bulk capacitance is calculated based on maximum
input ripple, ∆V
IN
:
CIV
Vf V
IN BULK OUT MAX OUT
IN SW IN MIN
() ()
()
•
••
=∆
∆V
IN
is typically chosen at a level acceptable to the user.
100mV-200mV is a good starting point. Aluminum elec-
trolytic capacitors are a good choice for high voltage, bulk
capacitance due to their high capacitance per unit area.
The capacitor’s RMS current is:
II
VVV
V
CIN RMS OUT OUT IN OUT
IN
() (– )
()
=2
If applicable, calculate it at the worst case condition, V
IN
=
2V
OUT
. The RMS current rating of the capacitor is specified
by the manufacturer and should exceed the calculated
I
CIN(RMS)
. Due to their low ESR (Equivalent Series Resis-
tance), ceramic capacitors are a good choice for high
voltage, high RMS current handling. Note that the ripple
current ratings from aluminum electrolytic capacitor manu-
facturers are based on 2000 hours of life. This makes it
LT3844
14
3844f
Figure 3. Undervoltage Lockout Circuit
Figure 2. Output Voltage Feedback Divider
L1
VFB PIN
R2
R1
VOUT
COUT
3844 F02
SHDN PIN
RA
RB
VSUPPLY
3844 F03
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Output Voltage Programming
A resistive divider sets the DC output voltage according to
the following formula:
RR
V
V
OUT
21
1 231 1=⎛
⎝
⎜⎞
⎠
⎟
.–
The external resistor divider is connected to the output of
the converter as shown in Figure 2. Tolerance of the
feedback resistors will add additional error to the output
voltage.
Example: V
OUT
= 12V; R1 = 10kΩ
Rk V
Vk use k210 12
1 231 1 8748 866 1=Ω−
⎛
⎝
⎜⎞
⎠
⎟=Ω− Ω
...%
The V
FB
pin input bias current is typically 25nA, so use of
extremely high value feedback resistors could cause a
converter output that is slightly higher than expected. Bias
current error at the output can be estimated as:
∆V
OUT(BIAS)
= 25nA • R2
Supply UVLO and Shutdown
The SHDN pin has a precision voltage threshold with
hysteresis which can be used as an undervoltage lockout
threshold (UVLO) for the power supply. Undervoltage
lockout keeps the LT3844 in shutdown until the supply
input voltage is above a certain voltage programmed by
the user. The hysteresis voltage prevents noise from
falsely tripping UVLO.
Resistors are chosen by first selecting R
B
. Then
RR V
V
AB
SUPPLY ON
=⎛
⎝
⎜⎞
⎠
⎟
•.–
()
135 1
advisable to further derate the capacitor or to choose a
capacitor rated at a higher temperature than required.
The combination of aluminum electrolytic capacitors and
ceramic capacitors is an economical approach to meeting
the input capacitor requirements. The capacitor voltage
rating must be rated greater than V
IN(MAX)
. Multiple ca-
pacitors may also be paralleled to meet size or height
requirements in the design. Locate the capacitor very
close to the MOSFET switch and use short, wide PCB
traces to minimize parasitic inductance.
Step-Down Converter: Output Capacitor Selection
The output capacitance, C
OUT
, selection is based on the
design’s output voltage ripple, ∆V
OUT
and transient load
requirements. ∆V
OUT
is a function of ∆I
L
and the C
OUT
ESR. It is calculated by:
∆=∆+
⎛
⎝
⎜⎞
⎠
⎟
V I ESR fC
OUT L SW OUT
•(• • )
1
8
The maximum ESR required to meet a ∆V
OUT
design
requirement can be calculated by:
ESR MAX VLf
VV
V
OUT SW
OUT OUT
IN MAX
() ()()()
•–
()
=∆
⎛
⎝
⎜⎞
⎠
⎟
1
Worst-case ∆V
OUT
occurs at highest input voltage. Use
paralleled multiple capacitors to meet the ESR require-
ments. Increasing the inductance is an option to lower the
ESR requirements. For extremely low ∆V
OUT
, an additional
LC filter stage can be added to the output of the supply.
Application Note 44 has some good tips on sizing an
additional output filter.
LT3844
15
3844f
V
SUPPLY(ON)
is the input voltage at which the undervoltage
lockout is disabled and the supply turns on.
Example: Select R
B
= 49.9kΩ, V
SUPPLY(ON)
= 14.5V (based
on a 15V minimum input voltage)
Rk V
V
A=Ω⎛
⎝
⎜⎞
⎠
⎟
49 9 14 5
135 1.•.
.–
= 486.1kΩ (499kΩ resistor is selected)
If low supply current in standby mode is required, select
a higher value of R
B
.
The supply turn off voltage is 9% below turn on. In the
example the V
SUPPLY(OFF)
would be 13.2V.
If additional hysteresis is desired for the enable function,
an external positive feedback resistor can be used from the
LT3844 regulator output.
The shutdown function can be disabled by connecting the
SHDN pin to the V
IN
through a large value pull-up resistor.
This pin contains a low impedance clamp at 6V, so the
SHDN pin will sink current from the pull-up resistor(R
PU
):
IVV
R
SHDN IN
PU
=–6
Because this arrangement will clamp the SHDN pin to the
6V, it will violate the 5V absolute maximum voltage rating
of the pin. This is permitted, however, as long as the
absolute maximum input current rating of 1mA is not
exceeded. Input SHDN pin currents of <100µA are recom-
mended: a 1MΩ or greater pull-up resistor is typically
used for this configuration.
Soft-Start
The desired soft-start time (t
SS
) is programmed via the
C
SS
capacitor as follows:
CµA t
V
SS SS
=2
1 231
•
.
The amount of time in which the power supply can
withstand a V
IN
, V
CC
or V
SHDN
UVLO fault condition
(t
FAULT
) before the C
SS
pin voltage enters its active region
is approximated by the following formula:
tCV
µA
FAULT SS
=•.065
50
Oscillator SYNC
The oscillator can be synchronized to an external clock.
Set the R
SET
resistor at least 10% below the desired sync
frequency.
It is recommended that the SYNC pin be driven with a
square wave that has amplitude greater than 2V, pulse
width greater than 1µs and rise time less than 500ns. The
rising edge of the sync wave form triggers the discharge
of the internal oscillator capacitor.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%.
Express percent efficiency as:
% Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are individual loss terms as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main contributors usually account for most of
the losses in LT3844 circuits:
1. LT3844 V
IN
and V
CC
current loss
2. I
2
R conduction losses
3. MOSFET transition loss
4. Schottky diode conduction loss
1. The V
IN
and V
CC
currents are the sum of the quiescent
currents of the LT3844 and the MOSFET drive currents.
The quiescent currents are in the LT3844 Electrical Char-
acteristics table. The MOSFET drive current is a result of
charging the gate capacitance of the power MOSFET each
cycle with a packet of charge, Q
G
. Q
G
is found in the
MOSFET data sheet. The average charging current is
calculated as Q
G
• f
SW
. The power loss term due to these
currents can be reduced by backdriving V
CC
with a lower
voltage than V
IN
such as V
OUT
.
APPLICATIO S I FOR ATIO
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LT3844
16
3844f
2. I
2
R losses are calculated from the DC resistances of the
MOSFET, the inductor, the sense resistor and the input
and output capacitors. In continuous conduction mode
the average output current flows through the inductor and
R
SENSE
but is chopped between the MOSFET and the
Schottky diode. The resistances of the MOSFET (R
DS(ON)
)
and the R
SENSE
multiplied by the duty cycle can be summed
with the resistances of the inductor and R
SENSE
to obtain
the total series resistance of the circuit. The total conduc-
tion power loss is proportional to this resistance and
usually accounts for between 2% to 5% loss in efficiency.
3. Transition losses of the MOSFET can be substantial with
input voltages greater than 20V. See MOSFET Selection
section.
4. The Schottky diode can be a major contributor of power
loss especially at high input to output voltage ratios (low
duty cycles) where the diode conducts for the majority of
the switch period. Lower V
f
reduces the losses. Note that
oversizing the diode does not always help because as the
diode heats up the V
f
is reduced and the diode loss term
is decreased.
I
2
R losses and the Schottky diode loss dominate at high
load currents. Other losses including C
IN
and C
OUT
ESR
dissipative losses and inductor core losses generally
account for less than 2% total additional loss in efficiency.
PCB Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation.
These items are illustrated graphically in the layout dia-
gram of Figure 3.
1. Keep the signal and power grounds separate. The signal
ground consists of the LT3844 SGND pin, the exposed pad
on the backside of the LT3844 IC and the (–) terminal of
V
OUT
. The signal ground is the quiet ground and does not
contain any high, fast currents. The power ground con-
sists of the Schottky diode anode, the (–) terminal of the
input capacitor and the ground return of the V
CC
capacitor.
This ground has very fast high currents and is considered
the noisy ground. The two grounds are connected to each
other only at the (–) terminal of V
OUT
.
2. Use short wide traces in the loop formed by the
MOSFET, the Schottky diode and the input capacitor to
minimize high frequency noise and voltage stress from
parasitic inductance. Surface mount components are pre-
ferred.
3. Connect the V
FB
pin directly to the feedback resistors
independent of any other nodes, such as the SENSE
–
pin.
Connect the feedback resistors between the (+) and (–)
terminals of C
OUT
. Locate the feedback resistors in close
proximity to the LT3844 to keep the high impedance node,
V
FB
, as short as possible.
4. Route the SENSE
–
and SENSE
+
traces together and keep
as short as possible.
5. Locate the V
CC
and BOOST capacitors in close proximity
to the IC. These capacitors carry the MOSFET driver’s high
peak currents. Place the small signal components away
from high frequency switching nodes (BOOST, SW and
TG). In the layout shown in Figure 3, place all the small
signal components on one side of the IC and all the power
components on the other. This helps to keep the signal and
power grounds separate.
6. A small decoupling capacitor (100pF) is sometimes
useful for filtering high frequency noise on the feedback
and sense nodes. If used, locate as close to the IC as
possible.
7. The LT3844 packaging will efficiently remove heat from
the IC through the exposed pad on the backside of the part.
The exposed pad is soldered to a copper footprint on the
PCB. Make this footprint as large as possible to improve
the thermal resistance of the IC case to ambient air. This
helps to keep the LT3844 at a lower temperature.
8. Make the trace connecting the gate of MOSFET M1 to the
TG pin of the LT3844 short and wide.
APPLICATIO S I FOR ATIO
WUUU
LT3844
17
3844f
Figure 4. LT3844 Layout Diagram (See PCB Layout Checklist).
APPLICATIO S I FOR ATIO
WUUU
3
C
BOOST
R
SENSE
R
A
R
C
R
SET
R2
R1
R
B
V
IN–
V
IN+
V
IN
SHDN
SYNC
f
SET
C
SS
BURST_EN
V
FB
V
C
SGND
BOOST
TG
SW
V
CC
PGND
SENSE
+
SENSE
–
+
–
L1
M1
D3
3844 F04
LT3844
1
2
4
5
6
7
8
9
16
15
14
13
12
11
10
D2
D1
C
VCC
C
IN
C
OUT
V
OUT
C
C2
C
SS
C
C1
17
LT3844
18
3844f
APPLICATIO S I FOR ATIO
WUUU
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LT3844 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required turning on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
tV
Vf t
ON OUT
IN SW ON MIN
=>
•()
where t
ON(MIN)
is typically 350ns worst case.
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LT3844 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
t
ON(MIN)
for the same step-down ratio.
Boost Converter Design
The LT3844 can be used to configure a boost converter to
step-up voltages to as high as hundreds of volts. An
example of a boost converter circuit schematic is shown
in the Typical Applications section. The following sections
are a guide to designing a boost converter:
The maximum duty cycle of the main switch is:
DC VV
V
MAX
OUT IN MIN
OUT
=−()
Boost Converter: Inductor Selection
The critical parameters for selection of an inductor are
minimum inductance value and saturation current. The
minimum inductance value is calculated as follows:
LV
If DC
MIN
IN MIN
LSW MAX
=
()
••
∆
f
SW
is the switch frequency.
Similar to the buck converter, the typical range of values
for ∆I
L
is (0.2 • I
L(MAX)
) to (0.5 • I
L(MAX)
), where I
L(MAX)
is
the maximum average inductor current.
II V
V
L MAX OUT MAX OUT
IN MIN
() () ()
•=
Using ∆I
L
= 0.3 • I
L(MAX)
yields a good design compromise
between inductor performance versus inductor size and
cost.
The inductor must not saturate at the peak operating
current, I
L(MAX)
+ ∆I
L
/2. The inductor saturation current
specification is the current at which the inductance, mea-
sured at zero current, decreases by a specified amount,
typically 30%.
One drawback of boost regulators is that they cannot be
current limited for output shorts because the current
steering diode makes a direct connection between input
and output. Therefore, the inductor current during an
output short circuit is only limited by the available current
of the input supply.
After calculating the minimum inductance value and the
saturation current for your design, select an off-the-shelf
inductor. For more detailed information on selecting an
inductor, please see the “Inductor Selection” section of
Linear Technology Application Note 19.
Boost Converter: MOSFET Selection
The selection criteria of the external N-channel standard
level power MOSFET include on resistance (R
DS(ON)
),
reverse transfer capacitance (C
RSS
), maximum drain source
voltage (V
DSS
), total gate charge (Q
G
) and maximum
continuous drain current.
For maximum efficiency, minimize R
DS(ON)
and C
RSS
. Low
R
DS(ON)
minimizes conduction losses while low C
RSS
minimizes transition losses. The problem is that R
DS(ON)
is inversely related to C
RSS
. Balancing the transition losses
with the conduction losses is a good idea in sizing the
MOSFET. Select the MOSFET to balance the two losses.
Calculate the maximum conduction losses of the MOSFET:
LT3844
19
3844f
PDC
I
DC R
COND MAX
OUT MAX
MAX DS ON
=−
⎛
⎝
⎜⎞
⎠
⎟
()
()
•
1
Note that R
DS(ON)
has large positive temperature depen-
dence. The MOSFET manufacturer’s data sheet contains a
curve, R
DS(ON)
vs Temperature. Calculate the maximum
transition losses:
PkV I C f
DC
TRAN
OUT OUT MAX RSS SW
=
()( )
()
()()
−
2
1
()
(MMAX )
where k is a constant inversely related to the gate driver
current, approximated by k = 2 for LT3844 applications.
The total maximum power dissipation of the MOSFET is
the sum of these two loss terms:
P
FET(TOTAL)
= P
COND
+ P
TRAN
To achieve high supply efficiency, keep the P
FET(TOTAL)
to
less than 3% of the total output power. Also, complete a
thermal analysis to ensure that the MOSFET junction
temperature is not exceeded.
T
J
= T
A
+ P
FET(TOTAL)
• θ
JA
where θ
JA
is the package thermal resistance and T
A
is the
ambient temperature. Keep the calculated T
J
below the
maximum specified junction temperature, typically 150°C.
Note that when V
OUT
is high (>20V), the transition losses
may dominate. A MOSFET with higher R
DS(ON)
and lower
C
RSS
may provide higher efficiency. MOSFETs with higher
voltage V
DSS
specification usually have higher
RDS(ON)
and
lower C
RSS
.
Choose the MOSFET V
DSS
specification to exceed the
maximum voltage across the drain to the source of the
MOSFET, which is V
OUT
plus the forward voltage of the
rectifier, typically less than 1V.
The internal V
CC
regulator is capable of sourcing up to
40mA which limits the maximum total MOSFET gate
charge, Q
G
, to 40mA / f
SW
. The Q
G
vs V
GS
specification is
typically provided in the MOSFET data sheet. Use Q
G
at V
GS
of 8V. If V
CC
is back driven from an external supply, the
MOSFET drive current is not sourced from the internal
regulator of the LT3844 and the Q
G
of the MOSFET is not
limited by the IC. However, note that the MOSFET drive
current is supplied by the internal regulator when the
external supply back driving VCC is not available such as
during startup or short-circuit.
The manufacturer’s maximum continuous drain current
specification should exceed the peak switch current which
is the same as the inductor peak current, I
L(MAX)
+ ∆I
L
/2.
During the supply startup, the gate drive levels are set by
the V
CC
voltage regulator, which is approximately 8V.
Once the supply is up and running, the V
CC
can be back
driven by an auxiliary supply such as V
OUT
. It is important
not to exceed the manufacturer’s maximum V
GS
specifica-
tion. A standard level threshold MOSFET typically has a
V
GS
maximum of 20V.
Boost Converter: Rectifier Selection
The rectifier is selected based upon the forward voltage,
reverse voltage and maximum current. A Schottky diode
is recommended for its low forward voltage and yields the
lowest power loss and highest efficiency. The maximum
reverse voltage that the diode will see is V
OUT
. The average
diode current is equal to the maximum output load cur-
rent, I
OUT(MAX)
. A diode rated at 1.5 to 2 times the
maximum average diode current is recommended. Re-
member boost converters are not short circuit protected.
Boost Converter: Output Capacitor Selection
In boost mode, the output capacitor requirements are
more demanding due to the fact that the current waveform
is pulsed instead of continuous as in a buck converter. The
choice of component(s) is driven by the acceptable ripple
voltage which is affected by the ESR, ESL and bulk
capacitance. The total output ripple voltage is:
∆VI fC
ESR
DC
OUT OUT MAX SW OUT MAX
=+
−
⎛
⎝
⎜⎞
⎠
⎟
() •
1
1
where the first term is due to the bulk capacitance and the
second term due to the ESR.
The choice of output capacitor is also driven by the RMS
ripple current requirement. The RMS ripple current is:
APPLICATIO S I FOR ATIO
WUUU
LT3844
20
3844f
IIVV
V
RMS COUT OUT MAX
OUT IN MIN
IN MIN
() ()
()
()
•=−
At lower output voltages (<30V) it may be possible to
satisfy both the output ripple voltage and RMS require-
ments with one or more capacitors of a single type.
However, at output voltages above 30V where capacitors
with both low ESR and high bulk capacitance are hard to
find, the best approach is to use a combination of alumi-
num electrolytic and ceramic capacitors. The low ESR
ceramic capacitor will minimize the ESR while the Alumi-
num Electrolytic capacitor will supply the required bulk
capacitance.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical than
the output capacitor, due to the fact that the inductor is in
series with the input and the input current waveform is
continuous. The input voltage source impedance deter-
mines the size of the input capacitor, which is typically in
the range of 10µF to 100µF. A low ESR capacitor is
recommended though not as critical as with the output
capacitor. The RMS input capacitor ripple current for a
boost converter is:
IV
Lf DC
RMS CIN
IN MIN
SW MAX()
()
.• ••=03
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors.
Boost Converter: R
SENSE
Selection
The boost application in the “Typical Applications” section
has the location of the current sense resistor in series with
the inductor with one side referenced to V
IN
. This location
was chosen for two reasons. Firstly, the circulating current
is always monitored so in the case of an output overvolt-
age or input over current condition the main switch will
skip cycles to protect the circuitry. Secondly, the V
IN
node
can be considered low noise since it is heavily filtered and
the input current is not pulsed but continuous.
In the case where the input voltage exceeds the voltage
limits on the LT3844 Sense pins, the sense resistor can be
moved to the source of the MOSFET. In both cases the
resistor value is the calculated using the same formula.
The LT3844 current comparator has a maximum thresh-
old of 100mV/R
SENSE
. The current comparator threshold
sets the peak of the inductor current. Allowing adequate
margin for ripple current and external component toler-
ances, RSENSE can be calculated as follows:
RmV
I
SENSE LMAX
=70
()
Where I
L(MAX)
is the maximum average inductor current
as calculated in the “Boost Converter: Inductor Selection”
section.
APPLICATIO S I FOR ATIO
WUUU
LT3844
21
3844f
V
IN
SHDN
C
SS
BURST_EN
V
FB
V
C
SYNC
f
SET
BOOST
TG
SW
V
CC
PGND
SENSE
+
SENSE
–
SGND
LT3844
3844 TA03
R3
49.9k
V
OUT
8V
AT
25W
C2
100pF
C3
680pF
C
IN2
1µF
25V
C
IN1
22µF
x3
25V
C1
3300pF
C5
22µF
x3
25V
C4
1µF
25V
R1
10k
R2
54.9k
R4
1M
R
SENSE
0.01Ω
R5
40.2k
D2
R6
10Ω
R7
10Ω
M1
V
IN
12V
L1 = COILTRONICS, VERSAPAC VP5-0083
C
IN
, C5, C
OUT2
= TDK, C4532X7R1E226M
D2 = ONSEMI, MBRD660
C
OUT
= SANYO OS-CON, 16SVP330M
C
IN
= VISHAY, Si7852DP
56pF
C
OUT2
22µF
25V
C
OUT1
330µF
16V
•
•
L1
L1
4
1
3
2
5
6
7
8
16
15
14
13
12
11
10
9
+
8V to 20V to 8V, 25W SEPIC Application
VIN
SHDN
CSS
BURST_EN
VFB
VC
SYNC
fSET
BOOST
TG
SW
VCC
PGND
SENSE+
SENSE–
SGND
LT3844
3844 TA02
R5
63.4k
VOUT
3.3V
AT 5A
C2
680pF
C3
100pF
CIN
22µF
x3
R4
10k
C1
2200pF
C5
0.22µF
C4
2.2µF
L1
6.8µH
100µF
COUT
x2
RSENSE
0.01Ω
R1
3.32k
R2
5.62k
R3
1M
D1
D2
M1
VIN
24V
L1 = VISHAY, IHLP5050FD-01
M1 = VISHAY, SI7852DP
D1 = DIODES INC, PDS760
COUT = TDK, C4532X5R0J107K
CIN = TDK, C4532X7R2A225K
(VOLTAGE
TRANSIENTS
UP TO 60V)
IN4148
4
1
3
2
5
6
7
8
16
15
14
13
12
11
10
9
All Ceramic Capacitor Application, 24V to 3.3V at 5A, fSW = 250kHz
TYPICAL APPLICATIO S
U
LT3844
22
3844f
Two Phase Spread Spectrum 24V Input to 12V, 6A Output
TYPICAL APPLICATIO S
U
V
IN
SHDN
C
SS
BURST_EN
V
FB
V
C
SYNC
f
SET
BOOST
TG
SW
V
CC
PGND
SENSE
+
SENSE
–
SGND
LT3844
R5
49.9k
R21
49.9K
R22
10K
V
OUT
12V
AT 6A
C2
680pF
C13
47pF
R4
4.99k
C1
2200pF
C5
0.22µF
16V
C4
2.2µF
L1
15µH
C
OUT
22µF
25V
R
SENSE
0.02Ω
R1
10k
C
IN
6.8µF
x3
50V
R2
87.5k
R3
3M
R6
270k
R13
3M
R16
270k
D1
D1a
BAV70
D11a
BAV70
D1b
BAV70
M1
V
IN
SHDN
C
SS
BURST_EN
V
FB
V
C
SYNC
f
SET
BOOST
TG
SW
V
CC
PGND
SENSE
+
SENSE
–
SGND
LT3844
3844 TA04
R15
49.9k
C11
2200pF
C15
0.22µF
16V
C14
2.2µF
L1
15µH
R
SENSE
0.02Ω
R11
10k
R12
87.5k
D11
M11
L1, L11 = VISHAY, IHLP5050FD-01
M1, M11 = VISHAY, Si7850DP
D1, D11 = DIODES INC, PDS760
C
OUT
= TDK, C4532X7R1E226K
C
IN
= TDK, C4532X7R1H685K
V+
DIV
PH
OUT1
SET
MOD
GND
OUT2
OUT V
IN
GND
LTC6902
LT1121-5
V
IN
18V
TO
36V
D11b
BAV70
4
1
3
2
5
6
7
8
16
15
14
13
12
11
10
9
4
1
1
3
3
2
2
5
6
7
8
16
15
14
13
12
11
10
9
10
9
8
5
1
2
3
4
SYNC1 SYNC2
SYNC1
SYNC2
LT3844
23
3844f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
FE16 (BC) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.94
(.116)
0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.94
(.116)
3.58
(.141)
3.58
(.141)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LT3844
24
3844f
PART NUMBER DESCRIPTION COMMENTS
LT1339 High Power Synchronous DC/DC Controller V
IN
up to 60V, Drivers 10000pF Gate Capacitance, I
OUT
= <20A
LTC1624 Switching Controller Buck, Boost, SEPIC, 3.5V ≤ V
IN
≤ 36V; 8-Lead SO Package
LTC1702A Dual 2-Phase Synchronous DC/DC Controller 550kHz Operation, No R
SENSE
, 3V = <V
IN
= <7V, I
OUT
= <20A
LTC1735 Synchronous Step-Down DC/DC Controller 3.5V = <V
IN
= <36V, 0.8V = <V
OUT
= <6V, Current Mode, I
OUT
= <20A
LTC1778 No R
SENSE
Synchronous DC/DC Controller 4V = <V
IN
= <36V, Fast Transient Response, Current Mode, I
OUT
= <20A
LT3010 50mA, 3V to 80V Linear Regulator 1.275V = <V
OUT
= <60V, No Protection Diode Required,
8-Lead MSOP Package
LT3430/LT3431 Monolithic 3A, 200kHz/500kHz Step-Down Regulator 5.5V = <V
IN
= <60V, 0.1Ω Saturation Switch, 16-Lead SSOP Package
LTC3703/LTC3703-5 100V Synchronous Switching Regulator Controllers No R
SENSE
, Voltage Mode Control, GN16 Package
LT3724 High Voltage Current Mode Switching Regulator V
IN
up to 60V, I
OUT
≤ 5A, 16-Lead TSSOP FE Package,
Controllers On Board Bias Regulator, Burst Mode Operation, 200kHz Operation
LT3800 High Voltage Synchronous Regulator Controller V
IN
up to 60V, I
OUT
≤ 20A, Current Mode, On Board Bias Regulator,
Burst Mode Operation, 16-Lead TSSOP FE Package
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0306 • PRINTED IN USA
RELATED PARTS
4
R6
40k
R2
383k
R1
10k
VIN
CSS
BURST_EN
VFB
VC
SYNC
fSET
BOOST
TG
SW
VCC
PGND
SENSE+
SENSE–
SGND
M1
D2
3844 TA05
LT3844
SHDN
1
3
2
5
6
7
8
16
15
14
13
12
11
10
9
C3
4700pF
C2
120pF
C5
2.2µF
25V
C4
4700pF
C1
0.1µF
25V
COUT1
330µF
COUT2
220µF
M1 = VISHAY, Si7370DP
L1 = VISHAY, IHLP5050FD-01
D2 = DIODES INC., PDS560
CIN = SANYO, 25SVP33M
COUT1 = SANYO, 63CE220FST
COUT2 = TDK, C4532X7R2A225K
RSENSE = IRC, LRF2512-01-R010-F
CIN
33µF ×2
25V
VIN 12V
RSENSE
0.01Ω
L1
6.8µHVOUT
48V AT 50W
D1
BAV99
R4
4.7M
R5
33.2k
+
+
12V to 48V 50W Step Up Converter with 400kHz Switching Frequency
TYPICAL APPLICATIO S
U
