LTC3785IUF#TRPBF - Linear Technology Corporation

LTC3785

3785fc

Typical applicaTion

DescripTion

10V, High Efﬁciency,

Synchronous, No RSENSE

Buck-Boost Controller

The LTC

3785 is a high power synchronous buck-boost

controller that drives all N-channel power MOSFETs from

input voltages above, below and equal to the output volt-

age. With an input range of 2.7V to 10V, the LTC3785 is

well suited for a wide variety of single or dual cell Li-Ion

or multicell alkaline/NiMH applications.

The operating frequency can be programmed from

100kHz to 1MHz. The soft-start time and current limit are

also programmable. The soft-start capacitor doubles as

the fault timer which can program the IC to latch off or

recycle after a determined off time. Burst Mode opera-

tion is user controlled and can be enabled by driving the

MODE pin high.

Protection features include foldback current limit, short-

circuit and overvoltage protection.

L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks

of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Efﬁciency vs Input Voltage

FeaTures

applicaTions

n Single Inductor Architecture Allows VIN Above,

Below or Equal to VOUT

n 2.7V to 10V Input and Output Range

n Up to 96% Efﬁciency

n Up to 10A of Output Current

n All N-channel MOSFETs, No RSENSE™

n True Output Disconnect During Shutdown

n Programmable Current Limit and Soft-Start

n Optional Short-Circuit Shutdown Timer

n Output Overvoltage and Undervoltage Protection

n Programmable Frequency: 100kHz to 1MHz

n Selectable Burst Mode

Operation

n Available in 24-Lead (4mm × 4mm) Exposed Pad

QFN Package

n Palmtop Computers

n Handheld Instruments

n Wireless Modems

n Cellular Telephones

VCC

ISVIN

TG1

VSENSE

BG1

TG2

BG2

SW2

3785 TA01a

VBST1

SW1

ISSW1

ISVOUT

VDRV

ISSW2

VBST2

CCM

ILSET

MODE

RUN/SS

VIN

VOUT

LTC3785

GND

4.7µF

VIN

2.7V

TO 10V

VOUT

3.3V

22µF

4.7µH

100µF

0.22µF

270pF

1.3k 205k 121k

12k

42.2k

59k

121k

205k

1nF

VIN (V)

2.5

EFFICIENCY (%)

3785 TA01b

85 45.5 7 8.5

100

ILOAD = 1A

VOUT = 3.3V

FOSC = 500kHz

ILOAD = 2A

LTC3785

3785fc

The l denotes the speciﬁcations which apply over the full operating junction

temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.

pin conFiguraTionabsoluTe MaxiMuM raTings

Input Supply Voltage (VIN) ......................... –0.3V to 11V

ISVOUT

, ISVIN .............................................. –0.3V to 11V

SW1, SW2, ISSW1, ISSW2 Voltage:

DC ............................................................. –1V to 11V

Pulsed, <1µs ............................................. –2V to 12V

RUN/SS, MODE, CCM, VDRV, VCC Voltages .. –0.3V to 6V

VBST1 Voltage ............................................. –0.3V to 16V

With Respect to SW1 ............................... –0.3V to 6V

VBST2 Voltage ............................................. –0.3V to 16V

With Respect to SW2 ............................... –0.3V to 6V

Peak Driver Output Current < 10µs

(TG1, TG2, BG1, BG2) .................................................3A

VCC Average Output Current .................................100mA

Operating Junction Temperature Range

(Note 2) ..................................................–40°C to 125°C

Junction Temperature ........................................... 125°C

Storage Temperature Range ...................–65°C to 150°C

(Note 1)

24 23 22 21 20 19

789

TOP VIEW

GND

UF PACKAGE

24-LEAD (4mm s 4mm) PLASTIC QFN

10 11 12

18RUN/SS

VSENSE

ILSET

CCM

ISSW1

BG1

VDRV

BG2

ISSW2

SW2

VIN

VCC

ISVIN

VBST1

TG1

SW1

MODE

ISVOUT

VBST2

TG2

TJMAX = 125°C, θJA = 40°C/W 1 LAYER BOARD, θJA = 30°C/W 4 LAYER BOARD

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Supply

Input Operating Voltage l2.7 10 V

Quiescent Current—Burst Mode Operation VC = 0V, MODE = 3.6V (Note 4) 86 200 µA

Quiescent Current—Shutdown RUN/SS = 0V, ISVOUT = 3.6V 15 25 µA

Quiescent Current—Active MODE = 0V (Note 4) 0.8 1.5 mA

Error Amp

Feedback Voltage (Note 5) l1.200 1.225 1.25 V

Feedback Input Current 1 500 nA

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3785EUF#PBF LTC3785EUF#TRPBF 3785 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C

LTC3785IUF#PBF LTC3785IUF#TRPBF 3785 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3785EUF LTC3785EUF#TR 3785 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C

LTC3785IUF LTC3785IUF#TR 3785 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

elecTrical characTerisTics

LTC3785

3785fc

The l denotes the speciﬁcations which apply over the full operating junction

temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.

elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS

Error Amp Source Current –500 µA

Error Amp Sink Current 900 µA

Error Amp AVOL 90 dB

Overvoltage Threshold VSENSE Pin % Above FB

LTC3785E

LTC3785I

Undervoltage Threshold VSENSE Pin % Below FB

LTC3785E

LTC3785I

–3.5

–6.5

–9.5

–10.5

VSENSE Input Current VSENSE = Measured FB Voltage 1 500 nA

VCC Regulator

VCC Maximum Regulating Voltage VIN = 5V, IVCC = –20mA l4.15 4.35 4.55 V

VCC Regulation Voltage VIN = 3.6V, IVCC = –20mA l3.3 3.5 3.6 V

VCC Regulator Sink Current ISVOUT = VCC = 5V 800 µA

Run/Soft-Start

RUN/SS Threshold When IC is Enabled

When EA is at Maximum Boost Duty Cycle

l0.35 0.7

1.9 1.1 V

RUN/SS Input Current RUN/SS = 0V –1 µA

RUN/SS Discharge Current During Current Limit 20 30 µA

Current Limit

Current Limit Sense Threshold ISVIN to ISSW1, RILSET = 121k

ISVIN to ISSW1, RILSET = 59k

55 60

105 100

155 mV

Reverse Current Limit Sense Threshold ISSW2 to ISVOUT, CCM > 2V

ISSW2 to ISVOUT, CCM < 0.4V, LTC3785E

ISSW2 to ISVOUT, CCM < 0.4V, LTC3785I

–50 –110

–15

–170

–35

–40

Input Current ISVIN

ISVOUT

ISSW1, ISSW2

0.1

150

µA

CCM Input Threshold (High) l2.2 V

CCM Input Threshold (Low) l0.4 V

CCM Input Current CCM = 3.6V 0.01 1 µA

Burst Mode Operation

Mode Threshold l0.8 1.5 2.2 V

Mode Input Current 0.01 1 µA

tON Time 1.4 µs

Oscillator

Frequency Accuracy l370 509 650 kHz

Switching Characteristics

Maximum Duty Cycle Boost (% Switch BG2 On)

Buck (% Switch TG1 On)

l 80 90

99 %

TG1, TG2 Driver Impedance 2 Ω

BG1, BG2 Driver Impedance 2 Ω

TG1, TG2 Rise Time CLOAD = 3300pF (Note 3) 20 ns

LTC3785

3785fc

The l denotes the speciﬁcations which apply over the full operating junction

temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.

elecTrical characTerisTics

Li-Ion to 3.3V Efﬁciency

vs Load Current

Two Li-Ion to 7V Efﬁciency

vs Load Current

Li-Ion/9V to 5V VOUT Efﬁciency

vs Load Current

Burst Mode Ripple

Line Transient Response

VOUT Load Transient

TA = 25°C, unless otherwise noted.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3785E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3785I is guaranteed

Typical perForMance characTerisTics

LOAD CURRENT (A)

0.0001

EFFICIENCY (%)

100

3785 G01

00.001 0.01 0.1 10

VIN = 4.2V

VIN = 3.6V

VIN = 3V

Burst Mode

OPERATION

FIXED

FREQUENCY

MOSFET Si7940

L = 4.7µH WURTH WE-PD

fOSC = 500kHz

LOAD CURRENT (A)

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

3785 G02

100

VIN = 8.4V

VIN = 7.2V

VIN = 5.4V

MOSFET Si7940

L = 5.6µH MSS1260

fOSC = 430kHz

Burst Mode

OPERATION

FIXED

FREQUENCY

LOAD CURRENT (A)

0.0001 0.001 0.01 0.1 1

EFFICIENCY (%)

3785 G03

100

VIN = 9V

VIN = 4.2V

VIN = 3.6V

VIN = 2.7V

MOSFET Si7940

L = 5.6µH MSS1260

fOSC = 430kHz

Burst Mode

OPERATION

FIXED

FREQUENCY

VOUT

50mV/DIV

COUPLED

INDUCTOR

CURRENT

1A/DIV

5µs/DIVVOUT = 3.3V

COUT = 100µF

3785 G04

VOUT

500mV/

DIV

VIN

3V TO

8.5V

500µs/DIVILOAD = 300mA

VOUT = 5V

COUT = 100µF

3785 G05

VOUT

200mV/

DIV

ILOAD

10mA TO 2A

100µs/DIVVIN = 3.6V

VOUT = 3.3V

COUT = 100µF

3785 G06

to meet performance speciﬁcations over the full –40°C to 125°C operating

junction temperature range.

Note 3: Speciﬁcation is guaranteed by design and not 100% tested in

production.

Note 4: Current measurements are performed when the outputs are not

switching.

Note 5: The IC is tested in a feedback loop to make the measurement.

PARAMETER CONDITIONS MIN TYP MAX UNITS

BG1, BG2 Rise Time CLOAD = 3300pF (Note 3) 20 ns

TG1, TG2 Fall Time CLOAD = 3300pF (Note 3) 20 ns

BG1, BG2 Fall Time CLOAD = 3300pF (Note 3) 20 ns

Buck Driver Nonoverlap Time TG1 to BG1 100 ns

Boost Driver Nonoverlap Time TG2 to BG2 100 ns

LTC3785

3785fc

Typical perForMance characTerisTics

VIN Start-Up Voltage

vs Temperature

VIN Burst Quiescent Current

vs Temperature

OV and UV Thresholds

vs Temperature

VFB vs Temperature

Normalized Oscillator Frequency

vs Temperature

Oscillator Frequency vs RT

TA = 25°C, unless otherwise noted.

pin FuncTions

RUN/SS (Pin 1): Run Control and Soft-Start Input. An

internal 1µA charges the soft-start capacitor and will

charge to approximately 2.5V. During a current limit fault,

the soft-start capacitor will incrementally discharge. Once

the pin drops below 1.225V the IC will enter fault mode,

turning off the outputs for 32 times the soft-start time. If

>5µA (at RUN/SS = 1.225V) is applied externally, the part

will latch off after a fault is detected. If >40µA (at RUN/SS

= 1.225V) is applied externally, current limit faults will not

discharge the SS capacitor.

VC (Pin 2): Error Amp Output. A frequency compensa-

tion network is connected from this pin to the FB pin to

compensate the loop. See Closing the Feedback Loop in

the Applications Information section for guidelines.

FB (Pin 3): Feedback Pin. Connect resistor divider tap

here. The feedback reference voltage is typically 1.225V

The output voltage can be adjusted from 2.7V to 10V ac-

cording to the following formula:

VOUT =1.225V • R1+R2

TEMPERATURE (°C)

–50

1.2255

1.2245

1.2250

1.2240

1.2235

1.2230

1.2225

1.2220

1.2215 25 75

3785 G07

–25 0 50 150125100

VFB (V)

TEMPERATURE (°C)

–50 25 75

–25 0 50 150125100

–1.0

CHANGE FROM 25°C (%)

–0.6

–0.2

0.2

3785 G08

0.6

1.0

–0.8

–0.4

0.4

0.8

RT (kΩ)

OSCILLATOR FREQUENCY (kHz)

200

400

600

800

1000

1200

40 60 80 100

3785 G09

TEMPERATURE (°C)

–50 25 75

–25 0 50 150125100

2.465

VIN START-UP VOLTAGE (V)

2.470

2.475

2.480

2.485

2.490

3785 G10

TEMPERATURE (°C)

–50 25 75

–25 0 50 150125100

VIN CURRENT (µA)

3785 G11

100

TEMPERATURE (°C)

–50 25 75

–25 0 50 150125100

–8

THRESHOLD (%)

–4

3785 G12

–6

–2

OV THRESHOLD

UV THRESHOLD

LTC3785

3785fc

pin FuncTions

VSENSE (Pin 4): Overvoltage and Undervoltage Sense.

The overvoltage threshold is internally set 10% above

the regulated FB voltage and the undervoltage threshold

is internally set 6.5% below the FB regulated voltage. This

pin can be tied to FB but to optimize the response time it

is recommended that a voltage divider from VOUT be ap-

plied. The divider can be skewed from the feedback value

to achieve the desired UV or OV threshold.

ILSET (Pin 5): Current Limit Set. A resistor from this pin

to ground sets the current limit threshold from the ISVIN

and ISSW1 pins.

CCM (Pin 6): Continuous Conduction Mode Control Pin.

When set low, the inductor current is allowed to go slightly

negative (–15mV referenced to the ISVOUT – ISSW2 pins).

When driven high, the reverse current limit is set to the

similar value of the forward current limit set by the ILSET

pin.

RT (Pin 7): Oscillator Programming Pin. A resistor from this

pin to GND sets the free-running frequency of the IC.

fRMHz

OSC T

≅









25000

MODE (Pin 8): Burst Mode Control Pin.

• MODE = High: Enable Burst Mode Operation. In Burst

Mode operation the operation is variable frequency,

which provides a signiﬁcant efﬁciency improvement

at light loads. The Burst Mode operation will continue

until the pin is driven low.

• MODE = Low: Disable Burst Mode operation and maintain

low noise, constant frequency operation.

NC (Pin 9): No Connect. There is no electrical connection

to this pin inside the package.

ISVOUT (Pin 10): Reverse Current Limit Comparator Non-

inverting Input. This pin is normally connected to the drain

of the N-channel MOSFET D (TG2 driven).

VBST2 (Pin 11): Boosted Floating Driver Supply for Boost

Switch D. This pin will swing from a diode below VCC up

to VOUT + VCC – VDIODE.

SW2 (Pin 13): Ground Reference for Driver D. Gate drive

from TG2 will reference to the common point of output

switches C and D.

ISSW2 (Pin 14): Reverse Current Limit Comparator Invert-

ing Input. This pin is normally connected to the source of

the N-channel MOSFET D (TG2 driven).

VDRV (Pin 16): Driver Supply for Ground Referenced

Switches. Connect this pin to VCC potential.

BG1, BG2 (Pins 17, 15): Bottom gate driver pins drive

the ground referenced N-channel MOSFET switches B

and C.

ISSW1 (Pin 18): Forward Current Limit Comparator Non-

inverting Input. This pin is normally connected to the

source of the N-channel MOSFET A (TG1 driven).

SW1 (Pin 19): Ground Reference for Driver A. Gate drive

from TG1 will reference to the common point of output

switches A and B.

TG1, TG2 (Pins 20, 12): Top gate drive pins drive the

top N-channel MOSFET switches A and D with a voltage

swing equal to VCC – VDIODE superimposed on the SW1

and SW2 nodes respectively.

VBST1 (Pin 21): Boosted Floating Driver Supply for the

Buck Switch A. This pin will swing from a diode below

VCC up to VIN + VCC – VDIODE.

ISVIN (Pin 22): Forward Current Limit Comparator Invert-

ing Input. This pin is normally connected to the drain of

N-channel MOSFET A (TG1 driven).

VCC (Pin 23): Internal 4.35V LDO Regulator Output. The

driver and control circuits are powered from this voltage

to limit the maximum VGS drive voltage. Decouple this pin

to power ground with at least a 4.7µF ceramic capacitor.

For low VIN applications, VCC can be bootstrapped from

VOUT through a Schottky diode.

VIN (Pin 24): Input Supply Pin for the VCC Regulator. A

ceramic capacitor of at least 10µF is recommended close

to the VIN and GND pins.

Ground (Exposed Pad Pin 25): The GND and PGND pins

are connected to the exposed pad which must be con-

nected to the PCB ground for electrical contact and rated

thermal performance.

LTC3785

3785fc

block DiagraM

–

2.4V

TSD 1.225V

TG1

BG1

VOUT

LOW

15mV

1X ILIMIT

1/25k

V = 60k/RILSET

X10

V = 90k/RILSET

UVLO

VBE

2µA

ILIM(OUT)

10µA MAX

1µA

RUN/SS

CSS

VSENSE

VOUT

MODE

1.5V

ILIM COMP

IMAX COMP

1.225V

RUN

VREF

–6.5%

FAULT

LOGIC

BURST

LOGIC

ILIMIT

SET

1/2 LIMIT AT VOUT < 1V

GND/PGND

1 = Burst Mode OPERATION

0 = FIXED FREQUENCY

100% DUTY

CHARGE PUMP

100% DUTY

CHARGE PUMP

0 = 15mV

1 = ILIMIT

4.35V REG

SAMPLED

PGND

1.8V

DISABLE

REVERSE

CURRENT LIMIT

(ZERO LIMIT FOR BURST)

IDEAL DIODE

BBM

SW1

DELAY

VCC

VIN

ILIMIT

VIN

2.7V TO 10V

ISVIN

VBST1

VBST2

VOUT

OPT

COUT

TG1 MA CIN

CVCC

CASW1

SW2

SW1

SW2

BG2

VDRV

PGND

ISSW2

ISSW1

ISVOUT

VDRV

BG1

TG2

ADRV

IMAX

SW1

PULSE

SW2

PULSE

TG2

BG2

VREV

BBM

SW2

DELAY

BDRV

CCM

3785 BD

VREV

CDRV

DDRV

REVERSE

LIMIT

–

+10%

OSC

BURST

1.225V

RILSET

–

ILSET

–

VOUT

CP1

LTC3785

3785fc

operaTion

MAIN CONTROL LOOP

The LTC3785 is a buck-boost voltage mode controller that

provides an output voltage above, equal to or below the

input voltage.

The LTC proprietary topology and control architecture also

employs drain-to-source sensing (No RSENSE) for forward

and reverse current limiting. The controller provides

all N-channel MOSFET output switch drive, facilitating

single package multiple power switch technology along

with lower RDS(ON). The error amp output voltage (VC)

determines the output duty cycle of the switches. Since

the VC pin is a ﬁltered signal, it provides rejection of high

frequency noise.

The FB pin receives the voltage feedback signal, which

is compared to the internal reference voltage by the er-

ror ampliﬁer. The top MOSFET drivers are biased from a

ﬂoating bootstrap capacitor, which is normally recharged

during each off cycle through an external diode when the

top MOSFET turns off. Optional Schottky diodes can be

connected across synchronous switch B and D to provide

a lower drop during the dead time and eliminate efﬁciency

loss due to body diode reverse recovery.

The main control loop is shut down by pulling the RUN/

SS pin low. An internal 1µA current source charges the

RUN/SS pin and when the pin voltage is higher than 0.7V

the IC is enabled. The VC voltage is then clamped to the

RUN/SS voltage minus 0.7V while CSS is slowly charged

during start-up. This soft-start clamping prevents inrush

current draw from the input power supply.

POWER SWITCH CONTROL

Figure 1 shows a simpliﬁed diagram of how the four power

switches are connected to the inductor, VIN, VOUT and GND.

Figure 2 shows the regions of operation for the LTC3785

as a function of duty cycle D. The power switches are

properly controlled so that the transfer between modes

is continuous.

Buck Region (VIN > VOUT)

Switch D is always on and switch C is always off during

buck mode. When the error amp output voltage, VC, is ap-

proximately above 0.1V, output A begins to switch. During

the off time of switch A, synchronous switch B turns on for

the remainder of the switching period. Switches A and B will

alternate similar to a typical synchronous buck regulator.

As the control voltage increases, the duty cycle of switch

A increases until the max duty cycle of the converter in

buck mode reaches DMAX_BUCK, given by:

DMAX_BUCK = 100 – D4(SW)%

where D4(SW) = duty cycle % of the four switch range.

D4(SW) = (300ns • f) • 100%

where f = operating frequency, Hz.

Beyond this point the four switch or buck-boost region

is reached.

Buck-Boost or Four Switch (VIN ~ VOUT)

When the error amp output voltage, VC, is above ap-

proximately 0.65V, switch pair AD remain on for duty

cycle DMAX_BUCK, and the switch pair AC begin to phase

in. As switch pair AC phases in, switch pair BD phases

out accordingly. When the VC voltage reaches the edge of

Figure 1. Output Switch Conﬁguration

Figure 2. Operation Mode vs VC Voltage

SW2

BG1 C

3785 F01

SW1

B BG2

VOUT

VIN

TG1 D

A TG2

BOOST REGION

BUCK/BOOST REGIONFOUR SWITCH PWM

90%

DMAX

BOOST

DMIN

BOOST

A ON, B OFF

PWM C, D SWITCHES

BUCK REGION

DMIN

BUCK 3785 F02

DMAX

BUCK

D ON, C OFF

PWM A, B SWITCHES

LTC3785

3785fc

operaTion

the buck-boost range, approximately 0.7V, the AC switch

pair completely phase out the BD pair, and the boost phase

begins at duty cycle, D4(SW).

The input voltage, VIN, where the four switch region begins

is given by:

VIN =VOUT

1– 300ns • f

( )

the point at which the four switch region ends is given

by:

VIN = VOUT(1 – D) = VOUT(1 – 300ns • f) V

Boost Region (VIN < VOUT)

Switch A is always on and switch B is always off during

boost mode. When the error amp output voltage, VC, is ap-

proximately above 0.7V, switch pair C and D will alternately

switch to provide a boosted output voltage. This operation

is typical to a synchronous boost regulator. The maximum

duty cycle of the converter is limited to 90% typical.

Burst Mode OPERATION

During Burst Mode operation, the LTC3785 delivers energy

to the output until it is regulated and then goes into a sleep

state where the outputs are off and the IC is consuming

only 86µA. In Burst Mode operation, the output ripple

has a variable frequency component, which is dependent

upon load current.

During the period where the converter is delivering en-

ergy to the output, the inductor will reach a peak current

determined by an on time, tON, and will terminate at zero

current for each cycle. The on time is given by:

tON =2.4

VIN • f

where f is the oscillator frequency.

The peak current is given by:

IPEAK =VIN

L• tON

IPEAK =2.4

f •L

So the peak current is independent of VIN and inversely

proportional to the f • L product optimizing the energy

transfer for various applications.

In Burst Mode operation the maximum output current is

given by:

IOUT(MAX,BURST) ≈1.2 • VIN

f •L • VOUT +VIN

( )

Burst Mode operation is user-controlled by driving the

MODE pin high to enable and low to disable.

VCC REGULATOR

An internal P-channel low dropout regulator produces

4.35V at the VCC pin from the VIN supply pin. VCC powers

the drivers and internal circuitry of the LTC3785. The VCC

pin regulator can supply a peak current of 100mA and

must be bypassed to ground with a minimum of 4.7µF

placed directly adjacent to the VCC and GND pins. Good

bypassing is necessary to supply the high transient cur-

rent required by the MOSFET gate drivers and to prevent

interaction between channels. If desired, the VCC regulator

can be connected to VOUT through a Schottky diode to

provide higher gate drive in low input voltage applications.

The VCC regulator can also be driven with an external 5V

source directly (without a Schottky diode).

TOPSIDE MOSFET DRIVER SUPPLY (VBST1, VBST2)

The external bootstrap capacitors connected to the VBST1

and VBST2 pins supply the gate drive voltage for the top-

side MOSFET switches A and D. When the top MOSFET

switch A turns on, the switch node SW1 rises to VIN and

the VBST2 pin rises to approximately VIN + VCC. When the

bottom MOSFET switch B turns on, the switch node SW1

drops low and the boost capacitor is charged through the

diode connected to VCC. When the top MOSFET switch D

turns on, the switch node SW2 rises to VOUT and the VBST2

pin rises to approximately VOUT + VCC. When the bottom

MOSFET switch C turns on, the switch node SW2 drops

low and the boost capacitor is charged through the diode

connected to VCC. The boost capacitors need to store about

100 times the gate charge required by the top MOSFET

LTC3785

3785fc

operaTion

switch A and D. In most applications a 0.1µF to 0.47µF,

X5R or X7R dielectric capacitor is adequate.

RUN/SOFT-START (RUN/SS)

The RUN/SS pin serves as the enable to the LTC3785,

soft-start function, and fault programming. A 1µA current

source charges the external capacitor. Once the RUN/SS

voltage is above a diode drop(~0.7V) the IC is enabled. Once

the IC is enabled, the RUN/SS voltage minus a diode drop

(RUN/SS – 0.7V) clamps the output of the error amp (VC)

to limit duty cycle. The range of the duty cycle clamping is

approximately 0.7V to 1.7V. The RUN/SS pin is clamped

to approximately 2.2V. If current limit is reached the pin

will begin to discharge with a current determined by the

magnitude of inductor current overcurrent limit, but not

to exceed 10µA. This function will be described in more

detail in the Forward Current Limit section.

OSCILLATOR

The frequency of operation is set through a resistor from

the RT pin to ground where:

fRMHz

OSC T

≅









25000

ERROR AMP

The error ampliﬁer is a voltage mode ampliﬁer with a

reference voltage of 1.225V internally connected to the

non-inverting input. The loop compensation components

are conﬁgured around the ampliﬁer to provide loop com-

pensation for the converter. The RUN/SS pin will clamp the

error amp output, VC, to provide a soft-start function.

UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

The LTC3785 incorporates overvoltage (OV) and

undervoltage (UV) functions for fault protection and

transient limitation. Both comparators are connected

to the VSENSE pin, which usually has a similar voltage

divider as the error ampliﬁer without the compensation.

The overvoltage threshold is 10% above the reference.

The undervoltage threshold is 6.5% below the reference

with both comparators having 1.5% hysteresis. During

an overvoltage fault, all output switching stops until the

fault ceases. During an undervoltage fault, the IC is com-

manded to run ﬁxed frequency only (disabled Burst Mode

operation). If the design requires a tightened threshold to

one of the comparator thresholds the voltage divider on

the VSENSE pin can be skewed to achieve the threshold.

Since the range is a constant, tightening the UV threshold

will loosen the OV threshold and vice versa.

FORWARD CURRENT LIMIT

The LTC3785 is designed to sense the input current by sam-

pling the voltage across MOSFET A during the on time of the

switch (TG1 = High). The sense pins are ISVIN and ISSW1. A

current sense resistor can be used if increased accuracy is

required. The current limit threshold can be programmed

with a resistor on the ILSET pin. Once the desired current

limit has been chosen, RILSET can be determined by the

following formula:

RILSET =6000

RDS(ON)A •ILIMIT

where RDS(ON)A = RDS(ON) of N-channel MOSFET switch A

and ILIMIT = current limit in Amps.

Once the voltage between ISVIN and ISSW1 exceeds the

threshold, current will be sourced out of FB to take control

of the voltage loop, resulting in a lower output voltage

to regulate the input current. This fault condition causes

the RUN/SS capacitor to begin discharging. The level of

the discharge current depends on how much the current

exceeds the programmed threshold. Figure 3 is a simpli-

ﬁed diagram of the current sense and fault circuitry. If the

current limit fault duration is long enough to discharge the

RUN/SS capacitor below 1.225V, the fault latch is set and

will cycle the RUN/SS capacitor 16 times (1µA charging

and 1µA discharging of the RUN/SS capacitor) to create an

off time of 32 times the soft-start time before the outputs

are allowed to switch to restart the output voltage. If the

current limit fault level exceeds 150% of the programmed

ILIMIT level at any time, the IMAX comparator is tripped and

output switches B and D are turned on to discharge the

inductor current for the remainder of the cycle.

LTC3785

3785fc

operaTion

To have the power converter latch off on a fault, a pull-up

current between 4µA and 7µA on the RUN/SS pin will allow

the RUN/SS capacitor to discharge during an extended

fault, but will prevent cycling of the fault which will cause the

converter to stay off. One method to implement this is by

placing a diode (anode tied to VOUT) and a resistor from VOUT

to the RUN/SS pin. The current sourced into RUN/SS will be

VOUT – 0.7 divided by the resistor value. To ignore all faults

source greater than 40µA into the RUN/SS pin (At 1.225V on

the RUN/SS pin). Since the maximum fault current is limited,

this will prevent any discharging of the RUN/SS capacitor,

the soft-start capacitor will need to be sized accordingly to

accommodate the extra charging current at start-up.

During an output short-circuit or if VOUT is less than 1.8V,

the current limit folds back to 50% of the programmed

level.

REVERSE CURRENT LIMIT

The LTC3785 can be programmed to provide full class D

operation or allowed to source and sink current equal to

the current limit set value. This is achieved by asserting a

high level on the CCM pin. To minimize the reverse output

current, the CCM pin should be driven low or strapped to

ground. During this mode only, –15mV typical is allowed

across output switch D and is sensed with the ISVOUT and

ISSW2 pins.

Figure 3. Block Diagram of Current Limit Fault Circuitry

–

–gm

gm = 1/20k

ILIMIT COMP

IMAX COMP

TURN

SWITCHES

B AND D ON

V = 60k/RILSET

(15k/RILSET WHEN VOUT < 1.8V)

X10

V = 90k/RILSET

0.7V

2µA

2.2V

CSS

1/3 • ILIM(OUT)

10µA MAX

ILIM(OUT)

30µA MAX

1µA

RUN/SS

VOUT

ILIM COMP

IMAX COMP

CP1

1.225V

THERMAL SD

RUN

FAULT

LOGIC

ILIMIT

SET

SAMPLED

REVERSE

CURRENT LIMIT

CCM = HIGH = 6k/RILSET

CCM = LOW = 15mV

ISVIN

VIN

VOUT

COUT

TG1

SW1

SW2

ISSW2

ISSW1

CCM

ISVOUT

+–

TG2

3785 F03

SWITCH D

OFF

1.225V ERROR AMP

–

ILSET

RILSET

BG1

BG2

LTC3785

3785fc

applicaTions inForMaTion

INDUCTOR SELECTION

The high frequency operation of the LTC3785 allows the

use of small surface mount inductors. The inductor cur-

rent ripple is typically set 20% to 40% of the maximum

inductor current. For a given ripple the inductance terms

are given as follows:

L>VIN(MIN)2• VOUT – VIN(MIN)

( )

•100

f •IOUT(MAX) • %Ripple • VOUT2, (Boost Mode)

L>VOUT • VIN(MAX) – VOUT

( )

•100

f •IOUT(MAX) • %Ripple • VIN(MAX)

, (Buck Mode)

where:

f = Operating frequency, Hz

%Ripple = Allowable inductor current ripple, %

VIN(MIN) = Minimum input voltage (limit to VOUT/2

minimum for worst-case), V

VIN(MAX) = Maximum input voltage, V

VOUT = Output voltage, V

IOUT(MAX) = Maximum output load current, A

For high efﬁciency choose an inductor with a high frequency

core material, such as ferrite, to reduce core loses. The

inductor should have low ESR (equivalent series resistance)

to reduce the I2R losses, and must be able to handle the

peak inductor current without saturating. Molded chokes

or chip inductors usually do not have enough core to sup-

port the peak inductor currents in the 3A to 6A region. To

minimize radiated noise, use a toroid, pot core or shielded

bobbin inductor.

CIN AND COUT SELECTION

In boost mode, input current is continuous. In buck mode,

input current is discontinuous. In buck mode, the selection

of input capacitor, CIN, is driven by the need to ﬁlter the

input square wave current. Use a low ESR capacitor, sized

to handle the maximum RMS current. For buck operation,

the maximum RMS capacitor current is given by:

IRMS ~IOUT(MAX) •VOUT

VIN

• 1– VOUT

VIN











This formula has a maximum at VIN = 2VOUT

, where IRMS =

IOUT(MAX)/2. This simple worst-case condition is commonly

used for design because even signiﬁcant deviations do not

offer much relief. Note that ripple current ratings from ca-

pacitor manufacturers are often based on only 2000 hours

of life which makes it advisable to derate the capacitor.

In boost mode, the discontinuous current shifts from the

input to the output, so COUT must be capable of reducing

the output voltage ripple. The effects of ESR (equivalent

series resistance) and the bulk capacitance must be

considered when choosing the right capacitor for a given

output ripple voltage. The steady ripple due to charging

and discharging the bulk capacitance is given by:

VRIPPLE _ BOOST =IOUT(MAX) • VOUT – VIN(MIN)

( )

COUT • VOUT • f

VRIPPLE _ BUCK =VOUT • VIN(MAX) – VOUT

( )

8 •L •COUT • VIN(MAX) • f2

where COUT= output ﬁlter capacitor, F

The steady ripple due to the voltage drop across the ESR

is given by:

 DVBOOST,ESR = IL(MAX,BOOST) • ESR

DVBUCK,ESR =VIN(MAX) – VOUT

( )

• VOUT

L•f•VIN

•ESR

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefﬁcient.

Capacitors are now available with low ESR and high ripple

current ratings such as OS-CON and POSCAP.

POWER N-CHANNEL MOSFET SELECTION AND

EFFICIENCY CONSIDERATIONS

The LTC3785 requires four external N-channel power

MOSFETs, two for the top switches (switches A and D,

shown in Figure 1) and two for the bottom switches

(switches B and C shown in Figure 1). Important param-

LTC3785

3785fc

applicaTions inForMaTion

eters for the power MOSFETs are the breakdown voltage

VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON),

reverse transfer capacitance CRSS and maximum current

IDS(MAX). The drive voltage is set by the 4.5V VCC supply.

Consequently, logic-level threshold MOSFETs must be used

in LTC3785 applications. If the input voltage is expected to

drop below 5V, then sub-logic threshold MOSFETs should

be considered. In order to select the power MOSFETs, the

power dissipated by the device must be known.

For switch A, the maximum power dissipation happens

in boost mode, when it remains on all the time. Its maxi-

mum power dissipation at maximum output current is

given by:

PA(BOOST)=VOUT

VIN

•IOUT(MAX)











•ρT •RDS(ON)

where ρT is a normalization factor (unity at 25°C) ac-

counting for the signiﬁcant variation in on-resistance with

temperature, typically about 0.4%/°C as shown in Figure 4.

For a maximum junction temperature of 125°C, using a

value ρT = 1.5 is reasonable.

Switch B operates in buck mode as the synchronous

rectiﬁer. Its power dissipation at maximum output current

is given by:

PB(BUCK)=VIN – VOUT

VIN

•IOUT(MAX)2•ρT •RDS(ON)

Switch C operates in boost mode as the control switch. Its

power dissipation at maximum current is given by:

PC(BOOST)=VOUT – VIN

( )

• VOUT

VIN2•IOUT(MAX)2•ρT

• RDS(ON) +k • VOUT3•IOUT(MAX)

VIN

•CRSS • f

where CRSS is usually speciﬁed by the MOSFET manufactur-

ers. The constant k, which accounts for the loss caused by

reverse recovery current, is inversely proportional to the

gate drive current and has an empirical value of 1.0.

For switch D, the maximum power dissipation happens in

boost mode when its duty cycle is higher than 50%. Its

maximum power dissipation at maximum output current

is given by:

PD BOOST

( )

=VOUT

VIN

•IOUT(MAX)2•ρT •RDS(ON)

Typically, switch A has the highest power dissipation and

switch B has the lowest power dissipation unless a short

occurs at the output. From a known power dissipated

in the power MOSFET, its junction temperature can be

obtained using the following formula:

TJ = TA + P • RTH(JA)

The RTH(JA) to be used in the equation normally includes

the RTH(JC) for the device plus the thermal resistance from

the case to the ambient temperature (RTH(CA)). This value

of TJ can then be compared to the original, assumed value

used in the iterative calculation process.

SCHOTTKY DIODE (D1, D2) SELECTION

Optional Schottky diodes D1 and D2 shown in the Block

Diagram conduct during the dead time between the conduc-

tion of the power MOSFET switches. They are intended to

prevent the body diode of synchronous switches B and D

from turning on and storing charge during the dead time.

In particular, D2 signiﬁcantly reduces reverse recovery

current between switch D turn off and switch C turn on,

which improves converter efﬁciency and reduces switch C

voltage stress. In order for D2 to be effective,

it must be

located in very close proximity to SWD.

Figure 4. Normalized RDS(ON) vs Temperature

JUNCTION TEMPERATURE (°C)

–50

ρT NORMALIZED ON-RESISTANCE

1.0

1.5

150

3785 F04

0.5

0050 100

2.0

LTC3785

3785fc

applicaTions inForMaTion

CLOSING THE FEEDBACK LOOP

The LTC3785 incorporates voltage mode control. The

control to output gain is given by:

GBUCK =1.6 • VIN, Buck Mode

GBOOST =1.6 • VOUT2

VIN

, Boost Mode

The output ﬁlter exhibits a double-pole response and is

given by:

fFILTER _POLE =1

2 • π• L •COUT

where COUT is the output ﬁlter capacitor.

The output ﬁlter zero is given by:

fFILTER _ ZERO =1

2 • π•RESR •COUT

where RESR is the capacitor equivalent series resistance.

A troublesome feature in boost mode is the right half plane

zero (RHP), and is given by:

fRHPZ =VIN2

2 • π•IOUT •L • VOUT

The loop gain is typically rolled off before the RHP zero

frequency.

A simple Type I compensation network (Figure 5) can be

incorporated to stabilize the loop but at a cost of reduced

bandwidth and slower transient response. To ensure proper

phase margin, the loop must cross over almost a decade

before the L-C double pole.

The unity gain frequency of the error ampliﬁer with the

Type I compensation is given by:

fUG =1

2 • π•R1•CP1

Most applications demand an improved transient response

to allow a smaller output ﬁlter capacitor. To achieve a higher

bandwidth, Type III compensation is required as shown

in Figure 6. Two zeros are required to compensate for the

double pole response.

fPOLE1≈1

2 • π• 32e3 • CP1 •R1 (a very low frequency)

fZERO1 =1

2 • π•RZ•CP1

fZERO2 =1

2 • π•R1•CZ1

fPOLE2 ≈1

2 • π•RZ•CP2

Figure 5. Error Ampliﬁer with Type I Compensation

–

ERROR

AMP

1.225V

3785 F05

VOUT

CP1

Figure 6. Error Ampliﬁer with Type III Compensation

–

ERROR

AMP

1.225V

3785 F06

R1 CZ1

VCRZ

VOUT

CP1

CP2

LTC3785

3785fc

applicaTions inForMaTion

EFFICIENCY CONSIDERATIONS

The percentage efﬁciency of a switching regulator is

equal to the output power divided by the input power

times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Although all dissipative

elements in circuits produce losses, four main sources

account for most of the losses in LTC3785 application

circuits:

1. DC I2R losses. These arise from the resistances of the

MOSFETs, sensing resistor (if used), inductor and PC

board traces and cause the efﬁciency to drop at high

output currents.

2. Transition loss. This loss arises from the brief voltage

transition time of switch A or switch C. It depends upon

the switch voltage, inductor current, driver strength and

MOSFET capacitance, among other factors.

ransition Loss ~ VSW2 • IL • CRSS • f

where CRSS is the reverse transfer capacitance.

3. CIN and COUT loss. The input capacitor has the difﬁcult

job of ﬁltering the large RMS input current to the regula-

tor in buck mode. The output capacitor has the more

difﬁcult job of ﬁltering the large RMS output current

in boost mode. Both CIN and COUT are required to have

low ESR to minimize the AC I2R loss and sufﬁcient

capacitance to prevent the RMS current from causing

additional upstream losses in fuses or batteries.

4. Other losses. Optional Schottky diodes D1 and D2 are

responsible for conduction losses during dead time

and light load conduction periods. Core loss is the

predominant inductor loss at light loads. Turning on

switch C causes reverse recovery current loss in boost

mode. When making adjustments to improve efﬁciency,

the input current is the best indicator of changes in

efﬁciency. If you make a change and the input current

decreases, then the efﬁciency has increased. If there

is no change in input current, then there is no change

in efﬁciency.

5. VCC regulator loss. In applications where the input

voltage is above 5V, such as two Li-Ion cells, the VCC

regulator will dissipate some power due the differential

voltage and the average output current to the drive the

gates of the output switches. The VCC pin can be driven

directly from a high efﬁciency external 5V source if

desired to incrementally improve overall efﬁciency at

lighter loads.

DESIGN EXAMPLE

As a design example, assume VIN = 2.7V to 10V (3.6V

nominal Li-Ion with 9V adapter), VOUT = 3.3V (5%),

IOUT(MAX) = 3A and f = 500kHz.

Determine the Inductor Value

Setting the Inductor Ripple to 40% and using the equations

in the Inductor Selection section gives:

L>2.7

( )

2• 3.3 – 2.7

( )

•100

500 •103• 3 • 40 • 3.3

( )

2=0.67µH

L>3.3 • 10 – 3.3

( )

•100

500 •103• 3 • 40 • 10 =3.7µH

So the worst-case ripple for this application is during buck

mode so a standard inductor value of 3.3µH is chosen.

LTC3785

3785fc

applicaTions inForMaTion

Determine the Proper Inductor Type Selection

The highest inductor current is during boost mode and

is given by:

IL(MAX _ AV) =VOUT •IOUT

VIN •η

where η = estimated efﬁciency in this mode (use 80%).

IL(MAX _ AV) =3.3 • 3

2.7 • 0.8 =4.6A

To limit the maximum efﬁciency loss of the inductor ESR

to below 5% the equation is:

ESRL(MAX) ~VOUT •IOUT • %Loss

IL(MAX _ AV)2•100 =24mΩ

A suitable inductor for this application could be a Coiltron-

ics CD1-3R8 which has a rating DC current of 6A and ESR

of 13mΩ.

Choose a Proper MOSFET Switch

Using the same guidelines for ESR of the inductor, one

suitable MOSFET could be the Siliconix Si7940DP which

is a dual MOSFET in a surface mount package with 25mΩ

at 2.5V and a total gate charge of 12nC.

Checking the power dissipation of each switch will ensure

reliable operation since the thermal resistance of the

package is 60°C/W.

The maximum power dissipation of switch A and C oc-

curs in boost mode. Assuming a junction temperature

of TJ = 100°C with ρ100C = 1.3, the power dissipation at

VIN = 2.7, and using the equations from the Efﬁciency

Considerations section:

PA(BOOST)=3.3

2.7 • 3











• 1.3 •0.025 =0.43W

PC(BOOST)=3.3 – 2.7

( )

• 3.3

2.72• 32• 1.3 • 0.025

+ 1• 3.33•3

2.7 • 0.45 – 9 • 500 • 103

=0.09W

The maximum power dissipation of switch B and D occurs

in buck mode and is given by:

PB(BUCK)=10 – 3.3

10 • 32• 1.3 • 0.025 =0.20W

PD(BOOST)=3.3

10 • 32• 1.3 • 0.025 =0.10W

Now to double check the TJ of the package with 50°C

ambient. Since this is a dual NMOS package we can add

switches A + B and C + D worst-case. For applications

where the MOSFETs are in separate packages each device’s

maximum TJ would have to be calculated.

TJ(PKG1) = TA + θJA(PA + PB)

= 50 + 60 • (0.43 + 0.20) = 88°C

TJ(PKG2) = TA + θJA(PC + PD)

= 50 + 60 • (0.09 + 0.10) = 60°C

Set The Maximum Current Limit

The equation for setting the maximum current limit of the

IC is given by:

RILSET =6000

RDS(ON)A •ILIMIT

The maximum current is set 25% above IL(PEAK) to account

for worst-case variation at 100°C = 6A.

RILSET =6000

0.025 • 6 =42k

Choose the Input and Output Capacitance

The input capacitance should ﬁlter current ripple which is

worst-case in buck mode. Since the input current could

reach 6A, a capacitor ESR of 10mΩ or less will yield an

input ripple of 60mV.

The output capacitance should ﬁlter current ripple which

is worst in boost mode, but is usually dictated by the loop

response, the maximum load transient and the allowable

transient response.

LTC3785

3785fc

applicaTions inForMaTion

PC BOARD LAYOUT CHECKLIST

The basic PC board layout requires a dedicated ground

plane layer. Also, for high current, a multilayer board

provides heat sinking for power components.

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

• Place CIN, switch A, switch B and D1 in one compact

area. Place COUT, switch C, switch D and D2 in one

compact area.

• Use immediate vias to connect the components (includ-

ing the LTC3785’s GND/PGND pin) to the ground plane.

Use several large vias for each power component.

• Use planes for VIN and VOUT to maintain good voltage

ﬁltering and to keep power losses low.

• Flood all unused areas on all layers with copper. Flooding

with copper will reduce the temperature rise of power

components. Connect the copper areas to any DC net

(VIN or GND). When laying out the printed circuit board,

the following checklist should be used to ensure proper

operation of the LTC3785.

• Segregate the signal and power grounds. All small-signal

components should return to the GND pin at one point.

The sources of switch B and switch C should also con-

nect to one point at the GND of the IC.

• Place switch B and switch C as close to the controller

as possible, keeping the PGND, BG and SW traces

short.

• Keep the high dV/dT SW1, SW2, VBST1, VBST2, TG1 and

TG2 nodes away from sensitive small-signal nodes.

• The path formed by switch A, switch B, D1 and the CIN

capacitor should have short leads and PC trace lengths.

The path formed by switch C, switch D, D2 and the

COUT capacitor also should have short leads and PC

trace lengths.

•

The output capacitor (–) terminals should be connected

as close as possible to the (–) terminals of the input

capacitor.

• Connect the VCC decoupling capacitor CVCC closely to

the VCC and PGND pins.

• Connect the top driver boost capacitor CA closely to

the VBST1 and SW1 pins. Connect the top driver boost

capacitor CB closely to the VBST2 and SW2 pins.

• Connect the input capacitors CIN and output capaci-

tors COUT close to the power MOSFETs. These capaci-

tors carry the MOSFET AC current in boost and buck

mode.

• Connect FB and VSENSE pin resistive dividers to the (+)

terminals of COUT and signal ground. If a small VSENSE

decoupling capacitor is used, it should be as close as

possible to the LTC3785 GND pin.

• Route ISVIN and ISSW1 leads together with minimum PC

trace spacing. Ensure accurate current sensing with Kel-

vin connections across MOSFET A or sense resistor.

• Route ISVOUT and ISSW2 leads together with minimum

PC trace spacing. Ensure accurate current sensing

with Kelvin connections across MOSFET D or sense

resistor.

• Connect the feedback network close to IC, between the

VC and FB pins.

LTC3785

3785fc

package DescripTion

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

Typical applicaTion

VCC

ISVIN

TG1VSENSE

BG1FB

TG2

BG2

SW2

3785 TA02

VBST1

SW1

ISSW1

ISVOUT

VDRV

ISSW2

VBST2

CCM

ILSET

MODE

RUN/SS

VIN

1nF

205k

270pF

1.3k

205k

12k

121k

59k

RILSET

42.2k

121k

LTC3785

GND

CVCC

4.7µF Li-Ion

2.7V TO 4.2V

MA = MB = MC = MD = 1/2 Si7940DY

L1 = WÜRTH ELECTRONICS 744311470

D1 = D2 = PMEG2020EJ

9V REGULATED

WALL ADAPTER

VIN

2.7V TO 10V

VOUT

3.3V

CIN

22µF

MB D1

OPTIONAL

0.22µF

CMDSH-3

4.7µH

COUT

100µF

4.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

2423

BOTTOM VIEW—EXPOSED PAD

2.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.45 ± 0.05

(4 SIDES)

3.10 ± 0.05

4.50 ± 0.05

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 s 45° CHAMFER

LTC3785

3785fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

C 3/10 Added LTC3785IUF (I-Grade) Part. Reﬂected Throughout Data Sheet 1 Through 20

(Revision history begins at Rev C)

LTC3785

3785fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LINEAR TECHNOLOGY CORPORATION 2007

LT 0310 REV C • PRINTED IN USA

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC3780 High Efﬁciency (Up to 98%), Synchronous

4-Switch Buck-Boost Controller 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 30V, SSOP-24, 5mm × 5mm QFN-32

LTM4605 High Efﬁciency Buck-Boost DC/DC µModule

Complete Power Supply 4.5V ≤ VIN ≤ 20V, 0.8V ≤ VOUT ≤ 16V, 15mm × 15mm × 2.8mm

LTM4607 High Efﬁciency Buck-Boost DC/DC µModule

Complete Power Supply 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 25V, 15mm × 15mm × 2.8mm

LTM4609 High Efﬁciency Buck-Boost DC/DC µModule

Complete Power Supply 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 34V, 15mm × 15mm × 2.8mm

LTC3533 2A Synchronous Buck-Boost Monolithic DC/DC

Converter 1.8V ≤ VIN ≤ 5.5V, 1.8V ≤ VOUT ≤ 5.25V, IQ = 40µA, ISD < 1µA, 3mm × 4mm DFN-14

LTC3441 1.2A Synchronous Buck-Boost Monolithic DC/DC

Converter 2.4V ≤ VIN ≤ 5.5V, 2.4V ≤ VOUT ≤ 5.25V, IQ = 25µA, ISD < 1µA, 3mm × 4mm DFN-12

LTC3440 600mA Synchronous Buck-Boost Monolithic

DC/DC Converter 2.5V ≤ VIN ≤ 5.5V, 2.5V ≤ VOUT ≤ 5.5V, IQ = 25µA, ISD < 1µA, 3mm × 3mm DFN-10,

MSOP-10

LTC3444 500mA Synchronous Buck-Boost Monolithic

DC/DC Converter 2.7V ≤ VIN ≤ 5.5V, ≤ 0.5V VOUT ≤ 5.25V, Optimized for WCDMA RF Ampliﬁer Bias,

3mm × 3mm DFN-8

LTC3532 500mA Synchronous Buck-Boost Monolithic

DC/DC Converter 2.4V ≤ VIN ≤ 5.5V, 2.4V ≤ VOUT ≤ 5.25V, IQ = 35µA, ISD < 1µA, 3mm × 3mm DFN-10,

MSOP-10

LTC3531

LTC3531-3

LTC3531-3.3

200mA Synchronous Buck-Boost Monolithic

DC/DC Converter 1.8V ≤ VIN ≤ to 5.5V, 2V ≤ VOUT ≤ 5V, IQ = 35µA, ISD < 1µA, 3mm × 3mm DFN-8,

ThinSOT-23

µModule is a registered trademark of Linear Technology Corporation.

VCC

ISVIN

TG1VSENSE

BG1FB

TG2

BG2

SW2

3785 TA03

VBST1

SW1

ISSW1

ISVOUT

VDRV

ISSW2

VBST2

CCM

ILSET

MODE

RUN/SS

VIN

1nF

205k

270pF

1.3k205k

12k

59k

66.5k

42.2k

66.5k

LTC3785

GND

CVCC

4.7µF Li-Ion

2.7V TO 4.2V

MA = MB = MC = MD = 1/2 Si7940DY

L1 = RLF7030T-3R3M4R1

D1 = D2 = PMEG2020EJ

9V REGULATED

WALL ADAPTER

VIN

2.7V TO 10V

VOUT

CIN

22µF

MB D1

OPTIONAL

0.22µF

CMDSH-3

3.3µH

COUT

100µF

Li-Ion/9V Wall Adapter to 5V/2A

relaTeD parTs