LT8330
1
8330f
For more information www.linear.com/LT8330
Typical applicaTion
FeaTures DescripTion
Low IQ Boost/SEPIC/
Inverting Converter
with 1A, 60V Switch
The LT
®
8330 is a current mode DC/DC converter capable
of generating either positive or negative output voltages
using a single feedback pin. It can be configured as a
boost, SEPIC or inverting converter consuming as low as
6µA of quiescent current. Low ripple Burst Mode opera-
tion maintains high efficiency down to very low output
currents while keeping the output ripple below 15mV in
a typical application. The internally compensated current
mode architecture results in stable operation over a wide
range of input and output voltages. Integrated soft-start
and frequency foldback functions are included to control
inductor current during start-up. The 2MHz operation
combined with small package options, enables low cost,
area efficient solutions.
48V Boost Converter
applicaTions
n 3V to 40V Input Voltage Range
n Ultralow Quiescent Current and Low Ripple Burst
Mode
®
Operation: IQ = 6µA
n 1A, 60V Power Switch
n Positive or Negative Output Voltage Programming
with a Single Feedback Pin
n Fixed 2MHz Switching Frequency
n Accurate 1.6V EN/UVLO Pin Threshold
n Internal Compensation and Soft-Start
n Low Profile (1mm) ThinSOT™ Package
n Low Profile (0.75mm) 8-Lead (3mm × 2mm) DFN
Package
n Industrial and Automotive
n Telecom
n Medical Diagnostic Equipment
n Portable Electronics
L, LT, LTC , LT M, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Efficiency and Power Loss
EFFICIENCY
POWER LOSS
LOAD CURRENT (mA)
0
40
80
120
160
0
10
20
30
40
50
60
70
80
90
100
0
100
200
300
400
500
600
700
800
900
1000
EFFICIENCY (%)
POWER LOSS (mW)
8330 TA01b
4.7µF
34.8k
4.7µF
1µF
4.7pF
V
IN
SW
FBX
GND
EN/UVLO
LT8330
VIN
12V
6.8µH
VOUT
48V
135mA
V
CC
INT
1M
LT8330
2
8330f
For more information www.linear.com/LT8330
absoluTe MaxiMuM raTings
SW ............................................................................60V
VIN, EN/UVLO ............................................................40V
EN/UVLO Pin Above VIN Pin ........................................ 6V
INTVCC (Note 2) ..........................................................4V
FBX ...........................................................................±4V
(Note 1)
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8330ES6#PBF LT8330ES6#TRPBF LTGMQ 6-Lead Plastic TSOT-23 –40°C to 125°C
LT8330IS6#PBF LT8330IS6#TRPBF LTGMQ 6-Lead Plastic TSOT-23 –40°C to 125°C
LT8330HS6#PBF LT8330HS6#TRPBF LTGMQ 6-Lead Plastic TSOT-23 –40°C to 150°C
LT8330EDDB#PBF LT8330EDDB#TRPBF LGRC 8-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C
LT8330IDDB#PBF LT8330IDDB#TRPBF LGRC 8-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C
LT8330HDDB#PBF LT8330HDDB#TRPBF LGRC 8-Lead (3mm × 2mm) Plastic DFN –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
TOP VIEW
9
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
5
6
7
8
4
3
2
1FBX
NC
SW
SW
EN/UVLO
INTVCC
VIN
GND
θJA = 60°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
1
2
3
6
5
4
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
VIN
INTVCC
EN/UVLO
SW
GND
FBX
θJA = 125°C/W, θJC = 102°C/W
pin conFiguraTion
Operating Junction Temperature (Note 3)
LT8330E, LT8330I ............................. –40°C to 125°C
LT8330H ............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
LT8330
3
8330f
For more information www.linear.com/LT8330
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, EN/UVLO = 12V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range l3 40 V
VIN Quiescent Current at Shutdown VEN/UVLO = 0.2V
l
0.9
2
2
5
µA
µA
VEN/UVLO = 1.5V
l
2
3.6
5
9.5
µA
µA
VIN Quiescent Current VEN/UVLO = 2V, (Sleep Mode) (Not Switching)
l
5.5
8.5
10
15
µA
µA
VEN/UVLO = 2V, (Active Mode) (Not Switching)
l
780
840
1100
1200
µA
µA
FBX Regulation
FBX Regulation Voltage FBX > 0V
FBX < 0V
l
l
1.568
–0.820
1.6
–0.80
1.632
–0.780
V
V
FBX Line Regulation FBX > 0V, 3V < VIN < 40V
FBX < 0V, 3V < VIN < 40V
0.005
0.005
0.015
0.015
%/V
%/V
FBX Pin Current FBX = 1.6V, –0.8V l–10 10 nA
Oscillator
Switching Frequency (fOSC) VIN = 24V l1.85 2.0 2.15 MHz
Minimum On-Time VIN = 24V 65 105 ns
Minimum Off-Time VIN = 24V 47 65 ns
Switch
Maximum Switch Current Limit Threshold l1.0 1.2 1.4 A
Switch RDS(ON) ISW = 0.5A 330 mΩ
Switch Leakage Current VSW = 60V 0.1 1 µA
EN/UVLO Logic
EN/UVLO Pin Threshold (Rising) Start Switching l1.620 1.68 1.745 V
EN/UVLO Pin Threshold (Falling) Stop Switching l1.556 1.60 1.644 V
EN/UVLO Pin Current VEN/UVLO = 1.6V l–40 40 nA
Soft-Start
Soft-Start Time VIN = 24V 1 ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: INTVCC cannot be externally driven. No additional components or
loading is allowed on this pin.
Note 3: The LT8330E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8330I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT8330H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
Note 4: The IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
LT8330
4
8330f
For more information www.linear.com/LT8330
Typical perForMance characTerisTics
Switching Frequency
vs Temperature Switching Frequency vs VIN
Normalized Switching Frequency
vs FBX Voltage
Switch Current Limit vs Duty
Cycle
Switch Minimum On-Time
vs Temperature
Switch Minimum Off-Time
vs Temperature
FBX Positive Regulation Voltage
vs Temperature
FBX Negative Regulation Voltage
vs Temperature
EN/UVLO Pin Thresholds
vs Temperature
V
IN
= 12V
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
1.570
1.580
1.590
1.600
1.610
1.620
1.630
FBX VOLTAGE (V)
8330 G01
V
IN
= 12V
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
–0.815
–0.810
–0.805
–0.800
–0.795
–0.790
–0.785
FBX VOLTAGE (V)
8330 G02
V
IN
= 24V
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
1.90
1.92
1.94
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
SWITCHING FREQUENCY (MHz)
8330 G04
V
IN
(V)
0
5
10
15
20
25
30
35
40
45
1.85
1.90
1.95
2.00
2.05
2.10
2.15
SWITCHING FREQUENCY (MHz)
8330 G05
V
IN
= 24V
FBX VOLTAGE (V)
–0.8
–0.4
0.0
0.4
0.8
1.2
1.6
0
25
50
75
100
125
NORMALIZED SWITCHING FREQUENCY (%)
8330 G06
V
IN
= 12V
DUTY CYCLE (%)
0
20
40
60
80
100
1.00
1.10
1.20
1.30
1.40
SWITCH CURRENT LIMIT (A)
8330 G07
V
IN
= 24V
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
30
40
50
60
70
80
90
100
MINIMUM ON–TIME (ns)
8330 G08
V
IN
= 24V
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
30
35
40
45
50
55
60
MINIMUM OFF–TIME (ns)
8330 G09
V
IN
= 12V
EN/UVLO RISING (TURN-ON)
EN/UVLO FALLING (TURN-OFF)
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
1.54
1.56
1.58
1.60
1.62
1.64
1.66
1.68
1.70
1.72
1.74
EN/UVLO PIN VOLTAGE (V)
8330 G03
LT8330
5
8330f
For more information www.linear.com/LT8330
Typical perForMance characTerisTics
Switching Waveforms
(in CCM)
Switching Waveforms
(in DCM/Light Burst Mode)
Switching Waveforms
(in Deep Burst Mode)
VOUT Transient Response: Load
Current Transients from 67.5mA to
135mA to 67.5mA
VIN Pin Current (Sleep Mode, Not
Switching) vs Temperature
VIN Pin Current (Active Mode, Not
Switching) vs Temperature Burst Frequency vs Load Current
VOUT Transient Response: Load
Current Transients from 5mA to
135mA to 5mA
V
IN
= 12V
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10.00
V
IN
PIN CURRENT (µA)
8330 G10
V
IN
= 12V
JUNCTION TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
600
650
700
750
800
850
900
950
1000
V
IN
PIN CURRENT (µA)
8330 G11
V
IN
= 12V
V
OUT
= 48V
FRONT PAGE APPLICATION
LOAD CURRENT (mA)
0
10
20
30
40
50
0
0.5
1.0
1.5
2.0
2.5
SWITCHING FREQUENCY (MHz)
8330 G12
V
IN
= 12V, V
OUT
= 48V, I
LOAD
= 135mA
1µs/DIV
FRONT PAGE APPLICATION
V
SW
20V/DIV
IL
500mA/DIV
8330 G13
V
IN
= 12V, V
OUT
= 48V, I
LOAD
= 20mA
1µs/DIV
FRONT PAGE APPLICATION
V
SW
20V/DIV
8330 G14
IL
500mA/DIV
V
IN
= 12V, V
OUT
= 48V, I
LOAD
= 2mA
1µs/DIV
FRONT PAGE APPLICATION
V
SW
20V/DIV
8330 G15
IL
500mA/DIV
FRONT PAGE APPLICATION
V
IN
= 12V
V
OUT
= 48V
100µs/DIV
V
OUT
500mV/DIV
IL
100mA/DIV
8330 G16
FRONT PAGE APPLICATION
V
IN
= 12V
V
OUT
= 48V
100µs/DIV
V
OUT
500mV/DIV
IL
100mA/DIV
8330 G17
LT8330
6
8330f
For more information www.linear.com/LT8330
pin FuncTions
EN/UVLO: Shutdown and Undervoltage Detect Pin. The
LT8330 is shut down when this pin is low and active
when this pin is high. Below an accurate 1.6V threshold
the part enters undervoltage lockout and stops switching.
This allows an undervoltage lockout (UVLO) threshold to
be programmed for system input voltage by resistively
dividing down system input voltage to the EN/UVLO pin.
An 80mV pin hysteresis ensures part switching resumes
when the pin exceeds 1.68V. EN/UVLO pin voltage below
0.2V reduces VIN current below 1µA. If shutdown and
UVLO features are not required, the pin can be tied directly
to system input.
FBX: Voltage Regulation Feedback Pin for Positive or
Negative Outputs. Connect this pin to a resistor divider
between the output and GND. FBX reduces the switching
frequency during start-up and fault conditions when FBX
is close to GND.
GND: Ground Connection for the LT8330. The DFN pack-
age has the best thermal performance due to an exposed
pad (Pin 9) on the bottom of the package. This exposed
pad must be soldered to a ground plane. Pin 5 of the DFN
package (and Pin 2 of the TSOT package) should also be
connected to a ground plane. The ground plane should be
connected to large copper layers to spread heat dissipated
by the LT8330.
INTVCC: Regulated 3V Supply for Internal Loads. The
INTVCC pin must be bypassed with a minimum 1µF low ESR
ceramic capacitor to ground. No additional components
or loading is allowed on this pin.
NC: No Internal Connection. Tie directly to local ground.
SW: The Output of Internal Power Switch. Minimize the
metal trace area connected to this pin to reduce EMI.
VIN: Input Supply. This pin must be locally bypassed. Be
sure to place the positive terminal of the input capacitor as
close as possible to the VIN pin, and the negative terminal
as close as possible to the GND pin.
LT8330
7
8330f
For more information www.linear.com/LT8330
block DiagraM
GND
8330 BD
+
–
+
–
ERROR AMP
SELECT
FREQUENCY
FOLDBACK
INTVCC
UVLO
OSCILLATOR
2MHz
SWITCH
LOGIC
BURST
DETECT
A5
A2
A1
ERROR
AMP
ERROR
AMP
SLOPE
VC
SLOPE
SOFT-START
1.6V
FBX
VOUT
R2
R1
–0.8V
UVLO
–
+
–
+A3
+
–
A4
DRIVER
M1
ILIMIT
RSENSE
PWM COMPARATOR
INTVCC
TJ > 170°C
+
–
A6 1.68V(+)
1.6V(–)
EN/UVLO
INTERNAL
REFERENCE
UVLO
VIN
CIN
SW
R4
OPT R3
OPT
VIN
COUT
CVCC
D
L
VOUT
UVLO 3V REGULATOR
M2
LT8330
8
8330f
For more information www.linear.com/LT8330
operaTion
The LT8330 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation. Op-
eration can be best understood by referring to the Block
Diagram. An internal 2MHz oscillator turns on the internal
power switch at the beginning of each clock cycle. Current
in the inductor then increases until the current comparator
trips and turns off the power switch. The peak inductor
current at which the switch turns off is controlled by the
voltage on the internal VC node. The error amplifier servos
the VC node by comparing the voltage on the FBX pin with
an internal reference voltage (1.60V or –0.80V, depending
on the chosen topology). When the load current increases
it causes a reduction in the FBX pin voltage relative to
the internal reference. This causes the error amplifier to
increase the VC voltage until the new load current is satis-
fied. In this manner, the error amplifier sets the correct
peak switch current level to keep the output in regulation.
The LT8330 is capable of generating either a positive or
negative output voltage with a single FBX pin. It can be
configured as a boost or SEPIC converter to generate a
positive output voltage, or as an inverting converter to
generate a negative output voltage. When configured as
a boost converter, as shown in the Block Diagram, the
FBX pin is pulled up to the internal bias voltage of 1.60V
by a voltage divider (R1 and R2) connected from VOUT
to GND. Amplifier A2 becomes inactive and amplifier A1
performs (inverting) amplification from FBX to VC. When
the LT8330 is in an inverting configuration, the FBX pin
is pulled down to –0.80V by a voltage divider from VOUT
to GND. Amplifier A1 becomes inactive and amplifier A2
performs (non-inverting) amplification from FBX to VC.
If the EN/UVLO pin voltage is below 1.6V, the LT8330
enters undervoltage lockout (UVLO), and stops switching.
When the EN/UVLO pin voltage is above 1.68V (typical),
the LT8330 resumes switching. If the EN/UVLO pin volt-
age is below 0.2V, the LT8330 only draws 1µA from VIN.
To optimize efficiency at light loads, the LT8330 operates
in Burst Mode operation in light load situations. Between
bursts, all circuitry associated with controlling the output
switch is shut down, reducing the input supply current
to 6µA.
ACHIEVING ULTRALOW QUIESCENT CURRENT
To enhance efficiency at light loads the LT8330 uses
a low ripple Burst Mode architecture. This keeps the
output capacitor charged to the desired output voltage
while minimizing the input quiescent current and output
ripple. In Burst Mode operation the LT8330 delivers single
small pulses of current to the output capacitor followed
by sleep periods where the output power is supplied by
the output capacitor. While in sleep mode the LT8330
consumes only 6µA.
As the output load decreases, the frequency of single cur-
rent pulses decreases (see Figure 1) and the percentage
of time the LT8330 is in sleep mode increases, resulting
in much higher light load efficiency than for typical con-
verters. To optimize the quiescent current performance
at light loads, the current in the feedback resistor divider
must be minimized as it appears to the output as load
current. In addition, all possible leakage currents from Figure 1. Burst Frequency vs Load Current
applicaTions inForMaTion
the output should also be minimized as they all add to the
equivalent output load. The largest contributor to leakage
current can be due to the reverse biased leakage of the
Schottky diode (see Diode Selection in the Applications
Information section).
V
IN
= 12V
V
OUT
= 48V
FRONT PAGE APPLICATION
LOAD CURRENT (mA)
0
10
20
30
40
50
0
0.5
1.0
1.5
2.0
2.5
SWITCHING FREQUENCY (MHz)
8330 F01
LT8330
9
8330f
For more information www.linear.com/LT8330
applicaTions inForMaTion
While in Burst Mode operation the current limit of the
switch is approximately 240mA resulting in the output
voltage ripple shown in Figure 2. Increasing the output
capacitance will decrease the output ripple proportionally.
As the output load ramps upward from zero the switch-
ing frequency will increase but only up to the fixed 2MHz
defined by the internal oscillator as shown in Figure 1. The
output load at which the LT8330 reaches the fixed 2MHz
frequency varies based on input voltage, output voltage,
and inductor choice.
Figure 2. Burst Mode Operation
PROGRAMMING INPUT TURN-ON AND TURN-OFF
THRESHOLDS WITH EN/UVLO PIN
The EN/UVLO pin voltage controls whether the LT8330 is
enabled or is in a shutdown state. A 1.6V reference and a
comparator A6 with built-in hysteresis (typical 80mV) allow
the user to accurately program the system input voltage
at which the IC turns on and off (see the Block Diagram).
The typical input falling and rising threshold voltages can
be calculated by the following equations:
VIN(FALLING,UVLO(–)) = 1.60 • (R3+R4)/R4
VIN(RISING, UVLO(+)) = 1.68 • (R3+R4)/R4
VIN current is reduced below 1µA when the EN/UVLO pin
voltage is less than 0.2V. The EN/UVLO pin can be con-
nected directly to the input supply VIN for always-enabled
operation. A logic input can also control the EN/UVLO pin.
When operating in Burst Mode operation for light load
currents, the current through the R3 and R4 network can
easily be greater than the supply current consumed by the
LT8330. Therefore, R3 and R4 should be large enough to
minimize their effect on efficiency at light loads.
INTVCC REGULATOR
A low dropout (LDO) linear regulator, supplied from VIN,
produces a 3V supply at the INTVCC pin. A minimum 1µF
low ESR ceramic capacitor must be used to bypass the
INTVCC pin to ground to supply the high transient currents
required by the internal power MOSFET gate driver.
No additional components or loading is allowed on this
pin. The INTVCC rising threshold (to allow soft start and
switching) is typically 2.6V. The INTVCC falling threshold
(to stop switching and reset soft start) is typically 2.5V.
DUTY CYCLE CONSIDERATION
The LT8330 minimum on-time, minimum off-time and
switching frequency (fOSC) define the allowable minimum
and maximum duty cycles of the converter (see Minimum
On-Time, Minimum Off-Time, and Switching Frequency
in the Electrical Characteristics table).
Minimum Allowable Duty Cycle =
Minimum On-Time(MAX) • fOSC(MAX)
Maximum Allowable Duty Cycle =
1 – Minimum Off-Time(MAX) • fOSC(MAX)
The required switch duty cycle range for a Boost converter
operating in continuous conduction mode (CCM) can be
calculated as:
DMIN = 1– VIN(MAX)/(VOUT + VD)
DMAX = 1– VIN(MIN)/(VOUT + VD)
where VD is the diode forward voltage drop. If the above
duty cycle calculations for a given application violate the
minimum and/or maximum allowed duty cycles for the
LT8330, operation in discontinuous conduction mode
(DCM) might provide a solution. For the same VIN and
VOUT levels, operation in DCM does not demand as low a
duty cycle as in CCM. DCM also allows higher duty cycle
operation than CCM. The additional advantage of DCM is
the removal of the limitations to inductor value and duty
cycle required to avoid sub-harmonic oscillations and the
right half plane zero (RHPZ). While DCM provides these
benefits, the trade-off is higher inductor peak current, lower
available output power and reduced efficiency.
5µs/DIV
V
OUT
5mV/DIV
I
L
200mA/DIV
8330 F02
LT8330
10
8330f
For more information www.linear.com/LT8330
applicaTions inForMaTion
SETTING THE OUTPUT VOLTAGE
The output voltage is programmed with a resistor divider
from the output to the FBX pin. Choose the resistor values
for a positive output voltage according to:
R1 = R2 • (VOUT/1.60V – 1)
Choose the resistor values for a negative output voltage
according to:
R1 = R2 • (|VOUT|/0.80V – 1)
The locations of R1 and R2 are shown in the Block Dia-
gram. 1% resistors are recommended to maintain output
voltage accuracy.
Higher-value FBX divider resistors result in the lowest input
quiescent current and highest light-load efficiency. FBX
divider resistors R1 and R2 are usually in the range from
25k to 1M. Most applications use a phase-lead capacitor
from VOUT to FBX in combination with high-value FBX
divider resistors (see Compensation in the Applications
Information section).
SOFT-START
The LT8330 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since VOUT is far from its final value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT8330 addresses this mechanism with an internal
soft-start function. As shown in the Block Diagram, the
soft-start function controls the ramp of the power switch
current by controlling the ramp of VC through M2. This
allows the output capacitor to be charged gradually toward
its final value while limiting the start-up peak currents.
Figure 3 shows the output voltage and supply current for
the first page Typical Application. It can be seen that both
the output voltage and supply current come up gradually.
Figure 3. Soft-Start Waveforms
INTVCC undervoltage (INTVCC < 2.5V) and/or thermal
lockout (TJ > 170°C) will immediately prevent switching,
will reset the internal soft-start function and will pull down
VC. Once all faults are removed, the LT8330 will soft-start
VC and hence inductor peak current.
FREQUENCY FOLDBACK
During start-up or fault conditions in which VOUT is very
low, extremely small duty cycles may be required to
maintain control of inductor peak current. The minimum
on-time limitation of the power switch might prevent these
low duty cycles from being achievable. In this scenario
inductor current rise will exceed inductor current fall during
each cycle, causing inductor current to ‘walk up’ beyond
the switch current limit. The LT8330 provides protection
from this by folding back switching frequency whenever
FBX pin is close to GND (low VOUT levels). This frequency
foldback provides a larger switch-off time, allowing inductor
current to fall enough each cycle (see Normalized Switch-
ing Frequency vs FBX Voltage in the Typical Performance
Characteristics section).
THERMAL LOCKOUT
If the LT8330 die temperature reaches 170°C (typical),
the part will stop switching and go into thermal lockout.
When the die temperature has dropped by 5°C (nominal),
the part will resume switching with a soft-started inductor
peak current.
500µs/DIV
IL
500mA/DIV
V
OUT
20V/DIV
8330 F03
LT8330
11
8330f
For more information www.linear.com/LT8330
applicaTions inForMaTion
SWITCHING FREQUENCY AND INDUCTOR SELECTION
The LT8330 switches at 2MHz, allowing small value induc-
tors to be used. 0.68µH to 10µH will usually suffice. Choose
an inductor that can handle at least 1.4A without saturating,
and ensure that the inductor has a low DCR (copper-wire
resistance) to minimize I2R power losses. Note that in
some applications, the current handling requirements of
the inductor can be lower, such as in the SEPIC topology
where each inductor only carries one-half of the total
switch current. For better efficiency, use similar valued
inductors with a larger volume. Many different sizes and
shapes are available from various manufacturers. Choose
a core material that has low losses at 2MHz, such as a
ferrite core. The final value chosen for the inductor should
not allow peak inductor currents to exceed 1A in steady
state at maximum load. Due to tolerances, be sure to ac-
count for minimum possible inductance value, switching
frequency and converter efficiency.
Table 1. Inductor Manufacturers
Sumida (847) 956-0666 www.sumida.com
TDK (847) 803-6100 www.tdk.com
Murata (714) 852-2001 www.murata.com
Coilcraft (847) 639-6400 www.coilcraft.com
Würth (605) 886-4385 www.we-online.com
INPUT CAPACITOR
Bypass the input of the LT8330 circuit with a ceramic ca-
pacitor of X7R or X5R type placed as close as possible to
the VIN and GND pins. Y5V types have poor performance
over temperature and applied voltage, and should not be
used. A 4.7µF to 10µF ceramic capacitor is adequate to
bypass the LT8330 and will easily handle the ripple cur-
rent. If the input power source has high impedance, or
there is significant inductance due to long wires or cables,
additional bulk capacitance may be necessary. This can
be provided with a low performance electrolytic capacitor.
A precaution regarding the ceramic input capacitor con-
cerns the maximum input voltage rating of the LT8330.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank cir-
cuit. If the LT8330 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possibly
exceeding the LT8330’s voltage rating. This situation is
easily avoided (see Application Note 88).
OUTPUT CAPACITOR AND OUTPUT RIPPLE
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they are small and have extremely low ESR. Use X5R or
X7R types. This choice will provide low output ripple and
good transient response. A 4.7µF to 15µF output capacitor
is sufficient for most applications, but systems with very
low output currents may need only a 1µF or 2.2µF output
capacitor. Solid tantalum or OS-CON capacitor can be
used, but they will occupy more board area than a ceramic
and will have a higher ESR. Always use a capacitor with a
sufficient voltage rating.
COMPENSATION
The LT8330 is internally compensated. The decision to
use either low ESR (ceramic) capacitors or the higher
ESR (tantalum or OS-CON) capacitors, for the output
capacitor, can affect the stability of the overall system.
The ESR of any capacitor, along with the capacitance
itself, contributes a zero to the system. For the tantalum
and OS-CON capacitors, this zero is located at a lower
frequency due to the higher value of the ESR, while the
zero of a ceramic capacitor is at a much higher frequency
and can generally be ignored.
A phase lead zero can be intentionally introduced by placing
a capacitor in parallel with the resistor between VOUT and
FBX. By choosing the appropriate values for the resistor and
capacitor, the zero frequency can be designed to improve
the phase margin of the overall converter. The typical target
value for the zero frequency is between 30kHz to 60kHz.
A practical approach to compensation is to start with one
of the circuits in this data sheet that is similar to your ap-
plication. Optimize performance by adjusting the output
capacitor and/or the feed forward capacitor (connected
across the feedback resistor from output to FBX pin).
LT8330
12
8330f
For more information www.linear.com/LT8330
CERAMIC CAPACITORS
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT8330 due to their piezoelectric nature.
When in Burst Mode operation, the LT8330’s switching
frequency depends on the load current, and at very light
loads the LT8330 can excite the ceramic capacitor at audio
frequencies, generating audible noise. Since the LT8330
operates at a lower current limit during Burst Mode op-
eration, the noise is typically very quiet to a casual ear.
If this is unacceptable, use a high performance tantalum
or electrolytic capacitor at the output. Low noise ceramic
capacitors are also available.
Table 2. Ceramic Capacitor Manufacturers
Taiyo Yuden (408) 573-4150 www.t-yuden.com
AVX (803) 448-9411 www.avxcorp.com
Murata (714) 852-2001 www.murata.com
DIODE SELECTION
A Schottky diode is recommended for use with the LT8330.
Low leakage Schottky diodes are necessary when low
Figure 4. Suggested Layout – (a) ThinSOT, (b) DFN
quiescent current is desired at low loads. The diode leakage
appears as an equivalent load at the output and should be
minimized. Choose Schottky diodes with sufficient reverse
voltage ratings for the target applications.
Table 3. Recommended Schottky Diodes
PART NUMBER
AVERAGE
FORWARD
CURRENT
(mA)
REVERSE
VOLTAGE
(V)
REVERSE
CURRENT
(µA) MANUFACTURER
PMEG6010CEJ ≤1000 ≤60 50 NXP
PMEG6030EP ≤3000 ≤60 200 NXP
LAYOUT HINTS
The high speed operation of the LT8330 demands care-
ful attention to board layout. Careless layout will result in
performance degradation. Figure 4a shows the recom-
mended component placement for the ThinSOT package.
Figure 4b shows the recommended component placement
for the DFN package. Note the vias under the exposed pad.
These should connect to a local ground plane for better
thermal performance.
applicaTions inForMaTion
R3
R4
R1
R2
GND
C2
C3
(a) (b)
L1
D1
C1
VOUT
VOUT
VIN
8330 F04a 8330 F04b
FB
C2
1
2
3
6
5
4(VIN)
R2
R4
R1
GND
C3
L1
D1
VOUT
VOUT
C4
FB
VIN
1
2
3
4
8
7
6
5C1
C2
R3
(VIN)
LT8330
13
8330f
For more information www.linear.com/LT8330
applicaTions inForMaTion
THERMAL CONSIDERATIONS
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LT8330. The DFN package has the
best thermal performance due to an exposed pad (Pin 9)
on the bottom of the package. This exposed pad must be
soldered to a ground plane. Pin 5 of the DFN package (and
Pin 2 of the TSOT package) should also be connected to a
ground plane. The ground plane should be connected to
large copper layers to spread heat dissipated by the LT8330
and to further reduce the thermal resistance (θJA) values
listed in the Pin Configuration section. Power dissipation
within the LT8330 (PDISS_LT8330) can be estimated by
subtracting the inductor and Schottky diode power losses
from the total power losses calculated in an efficiency
measurement. The junction temperature of LT8330 can
then be estimated by,
TJ (LT8330) = TA + θJA • PDISS_LT8330
ADDITIONAL TOPOLOGIES : SEPIC AND INVERTING
In addition to the Boost topology, the LT8330 can be
configured in a SEPIC or Inverting topology. SEPIC and
Inverting converters are analyzed below.
SEPIC CONVERTER APPLICATIONS
The LT8330 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 5. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
V
OUT
+V
D
V
IN
=
D
1−D
in continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT), the input voltage (VIN) and the diode
forward voltage (VD).
The maximum duty cycle (DMAX) occurs when the converter
operates at the minimum input voltage:
DMAX =
V
OUT
+V
D
VIN(MIN) +VOUT +VD
Conversely, the minimum duty cycle (DMIN) occurs when
the converter operates at the maximum input voltage:
DMIN =
V
OUT
+V
D
VIN(MAX) +VOUT +VD
Be sure to check that DMAX and DMIN obey:
DMAX < 1-Minimum Off-Time(MAX) • fOSC(MAX)
and
DMIN > Minimum On-Time(MAX) • fOSC(MAX)
where Minimum Off-Time, Minimum On-Time and fOSC
are specified in the Electrical Characteristics table.
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
As shown in Figure 5, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but can
Figure 5. LT8330 Configured in a SEPIC Topology
L1
L2
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
V
IN
V
CC
INT
D1
C
IN
C
OUT
C
DC
8330 F05
LT8330
14
8330f
For more information www.linear.com/LT8330
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
IL1(MAX)(AVE) =IIN(MAX)(AVE) =IO(MAX) •
D
MAX
1−DMAX
IL2(MAX)(AVE) =IO(MAX)
In a SEPIC converter, the switch current is equal to IL1 +
IL2 when the power switch is on, therefore, the maximum
average switch current is defined as:
I
SW(MAX)(AVE)
=I
L1(MAX)(AVE)
+I
L2(MAX)(AVE)
=IO(MAX) •1
1−D
MAX
and the peak switch current is:
ISW(PEAK) =1+
c
2
•IO(MAX) •
1
1−D
MAX
The constant c in the preceding equations represents
the percentage peak-to-peak ripple current in the switch,
relative to ISW(MAX)(AVE), as shown in Figure 6. Then, the
switch ripple current ∆ISW can be calculated by:
∆ISW = c • ISW(MAX)(AVE)
The inductor ripple currents ∆IL1 and ∆IL2 are identical:
∆IL1 = ∆IL2 = 0.5 • ∆ISW
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
∆IL requires large inductances and reduces the current
loop gain (the converter will approach voltage mode).
Accepting larger values of ∆IL allows the use of low in-
ductances, but results in higher input current ripple and
greater core losses. It is recommended that c falls in the
range of 0.2 to 0.6.
Due to the current limit of its internal power switch, the
LT8330 should be used in a SEPIC converter whose
maximum output current (IO(MAX)) is less than the output
current capability by a sufficient margin (10% or higher
is recommended):
IO(MAX) < (1 – DMAX) • (1A – 0.5 • ∆ISW) • (0.9)
Given an operating input voltage range, and having cho-
sen ripple current in the inductor, the inductor value (L1
and L2 are independent) of the SEPIC converter can be
determined using the following equation:
L1=L2 =
V
IN(MIN)
0.5 •∆I
SW
•f
OSC
•DMAX
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 47µH.
By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
L=
V
IN(MIN)
∆I
SW
•f
OSC
•DMAX
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
IL1(PEAK) = IL1(MAX) + 0.5 • ∆IL1
IL2(PEAK) = IL2(MAX) + 0.5 • ∆IL2
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
applicaTions inForMaTion
Figure 6. The Switch Current Waveform of the SEPIC Converter
8330 F06
∆ISW = χ • ISW(MAX)(AVE)
ISW
t
DTS
ISW(MAX)(AVE)
TS
LT8330
15
8330f
For more information www.linear.com/LT8330
Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS cur-
rent ratings.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety
margin (a 10V safety margin is usually sufficient).
The power dissipated by the diode is:
PD = IO(MAX) • VD
where VD is diode’s forward voltage drop, and the diode
junction temperature is:
TJ = TA + PD • RθJA
The RθJA used in this equation normally includes the RθJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 5) should be larger than the maximum
input voltage:
VCDC > VIN(MAX)
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •VOUT +VD
VIN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
INVERTING CONVERTER APPLICATIONS
The LT8330 can be configured as a dual-inductor inverting
topology, as shown in Figure 7. The VOUT to VIN ratio is:
V
OUT
−V
D
V
IN
= −
D
1−D
in continuous conduction mode (CCM).
applicaTions inForMaTion
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =
V
OUT
−V
D
VOUT −VD−VIN(MIN)
Conversely, the minimum duty cycle (DMIN) occurs when
the converter operates at the maximum input voltage :
DMIN =
V
OUT
−V
D
VOUT −VD−VIN(MAX)
Figure 7. A Simplified Inverting Converter
CDC
VIN
CIN
L1
D1
COUT VOUT
8330 F07
+
GND
LT8330
SW
L2
+
–
+–
+
LT8330
16
8330f
For more information www.linear.com/LT8330
Be sure to check that DMAX and DMIN obey :
DMAX < 1-Minimum Off-Time(MAX) • fOSC(MAX)
and
DMIN > Minimum On-Time(MAX) • fOSC(MAX)
where Minimum Off-Time, Minimum On-Time and fOSC
are specified in the Electrical Characteristics table.
Inverting Converter: Inductor, Output Diode and Input
Capacitor Selections
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those of
the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
output capacitors are continuous. The output ripple voltage
is produced by the ripple current of L2 flowing through
the ESR and bulk capacitance of the output capacitor:
∆VOUT(P–P) = ∆IL2 •ESRCOUT +1
8•f•COUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) > 0.3 • ∆IL2
Inverting Converter: Selecting the DC Coupling
Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 7) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
VCDC > VIN(MAX) – VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •DMAX
1−DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
applicaTions inForMaTion
LT8330
17
8330f
For more information www.linear.com/LT8330
Typical applicaTions
48V Boost Converter
8V to 16V Input, 24V Boost Converter
3V to 6V Input, 48V Boost Converter
4.7µF
1µF
4.7pF
V
IN
SW
FBX
GND
EN/UVLO
LT8330
V
CC
INT
C1
C2
C3
4.7µF
C4
R1
1M
R2
34.8k
L1
6.8µH
D1
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-MAPI 3015 74438335068
C3: MURATA GRM32ER71H475k
8330 TA02
VIN
12V
VOUT
48V
135mA
71.5k
4.7µF
1µF
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
8V TO 16V
V
IN
24V
V
CC
INT
1M
L1
6.8µH
D1
C1
C2
C3
4.7µF
D1: DIODES INC. SBR140S3
L1: WÜRTH WE-MAPI 3015 74438335068
C3: MURATA GRM32ER71H475k
C4
4.7pF
R3
1M
R4
287k
R1
R2
210mA AT V
IN
= 8V
320mA AT V
IN
= 12V
450mA AT V
IN
= 16V
8330 TA03
4.7µF
4.7µF
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
3V TO 6V
V
IN
48V
V
CC
INT
L1
0.68µH
D1
C1
C2
1µF
C3
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-MAPI 3012 744383340068
C3: MURATA GRM32ER71H475k
R1
1M
R2
34.8k
12mA AT V
IN
= 3V
13mA AT V
IN
= 5V
14mA AT V
IN
= 6V
8330 TA04
Efficiency
Efficiency
Efficiency
V
IN
= 12V
BOOST: V
OUT
= 48V
LOAD CURRENT (mA)
0
40
80
120
160
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA02b
BOOST : V
OUT
= 24V
V
IN
= 8V
V
IN
= 12V
V
IN
= 16V
LOAD CURRENT (mA)
0
100
200
300
400
500
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA03b
BOOST : V
OUT
= 48V
V
IN
= 3V
V
IN
= 5V
V
IN
= 6V
LOAD CURRENT (mA)
0
2
4
6
8
10
12
14
16
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA04b
LT8330
18
8330f
For more information www.linear.com/LT8330
Typical applicaTions
3V to 6V Input, 24V Boost Converter
8V to 30V Input, 24V SEPIC Converter
71.5k
1µF
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
3V TO 6V
V
IN
24V
V
CC
INT
1M
L1
0.68µH
D1
C2
C3
4.7µF
C1
4.7µF
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-MAPI 3012 744383340068
C3: MURATA GRM32ER71H475k
R1
R2
30mA AT V
IN
= 3V
34mA AT V
IN
= 5V
35mA AT V
IN
= 6V
8330 TA05
4.7µF
71.5k
4.7µF
1µF
4.7pF
C5
1µF
L2
6.8µH
1M
287k
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
8V TO 30V
L1
6.8µH
V
IN
24V
V
CC
INT
1M
D1
C1
C2
C3
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-TDC 8038 74489440068
C3: MURATA GRM32ER71H475k
R1
R2
×2
C4
R3
R4
160mA AT V
IN
= 8V
200mA AT V
IN
= 12V
250mA AT V
IN
= 24V
250mA AT V
IN
= 30V
8330 TA06
Efficiency
Efficiency
BOOST : V
OUT
= 24V
V
IN
= 3V
V
IN
= 5V
V
IN
= 6V
LOAD CURRENT (mA)
0
4
8
12
16
20
24
28
32
36
40
30
40
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA05b
SEPIC: V
OUT
= 24V
V
IN
= 8V
V
IN
= 12V
V
IN
= 24V
V
IN
= 30V
LOAD CURRENT (mA)
0
60
120
180
240
300
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA06b
LT8330
19
8330f
For more information www.linear.com/LT8330
Typical applicaTions
4V to 36V Input, 12V SEPIC Converter
4V to 16V Input, 5V SEPIC Converter
4.7µF
154k
4.7µF
1µF
4.7pF
C5
1µF
L1
4.7µH
L2
4.7µH
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
4V TO 36V
V
IN
12V
V
CC
INT
1M
D1
C1
C2
C3
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-TDC 8038 74489440047
C3: MURATA GRM31CR61C475k
R1
R2
×2
C4
R3
1M
R4
806k
170mA AT V
IN
= 4V
270mA AT V
IN
= 12V
280mA AT V
IN
= 24V
280mA AT V
IN
= 36V
8330 TA07
4.7µF
464k
4.7µF
1µF
4.7pF
C5
1µF
L1
2.7µH
L2
2.7µH
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
4V TO 16V
V
IN
5V
V
CC
INT
1M
D1
C1
C2
C3
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-TDC 8018 74489430027
C3: MURATA GRM21BR71C475k
R1
R2
C4
R3
1M
R4
806k
280mA AT V
IN
= 4V
300mA AT V
IN
= 5V
380mA AT V
IN
= 12V
380mA AT V
IN
= 16V
8330 TA08
Efficiency
Efficiency
SEPIC: V
OUT
= 12V
V
IN
= 4V
V
IN
= 12V
V
IN
= 24V
V
IN
= 36V
LOAD CURRENT (mA)
0
60
120
180
240
300
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA07b
V
IN
= 4V
V
IN
= 5V
V
IN
= 12V
V
IN
= 16V
SEPIC: V
OUT
= 5V
LOAD CURRENT (mA)
0
80
160
240
320
400
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA08b
LT8330
20
8330f
For more information www.linear.com/LT8330
Typical applicaTions
8V to 30V Input, –24V Inverting Converter
4V to 36V Input, –12V Inverting Converter
2.2µF
34.8k
4.7µF
1µF
4.7pF
C5
1µF
1M
287k
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
8V TO 30V
V
IN
–24V
V
CC
INT
1M
D1
C1
C2
C3
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-TDC 8038 74489440068
C3: MURATA GRM32ER71H475k
R1
R2
C4
R3
R4
L2
6.8µH
L1
6.8µH
160mA AT V
IN
= 8V
200mA AT V
IN
= 12V
250mA AT V
IN
= 24V
250mA AT V
IN
= 30V
8330 TA09
4.7µF
71.5k
4.7µF
1µF
4.7pF
C5
1µF
1M
806k
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
4V TO 36V
V
IN
–12V
V
CC
INT
1M
D1
C1
C2
C3
D1: NXP PMEG6010CEJ
L1: Coilcraft LPD5030-472MR
C3: MURATA GRM21BR71C475k
R1
R2
C4
R3
R4
L2
4.7µH
L1
4.7µH
170mA AT V
IN
= 4V
270mA AT V
IN
= 12V
280mA AT V
IN
= 24V
280mA AT V
IN
= 36V
8330 TA10
Efficiency
Efficiency
INVERTING: V
OUT
= –24V
V
IN
= 8V
V
IN
= 12V
V
IN
= 24V
V
IN
= 30V
LOAD CURRENT (mA)
0
60
120
180
240
300
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA09b
INVERTING : V
OUT
= –12V
V
IN
=4V
V
IN
=12V
V
IN
=24V
V
IN
=36V
LOAD CURRENT (mA)
0
60
120
180
240
300
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA10b
LT8330
21
8330f
For more information www.linear.com/LT8330
Typical applicaTions
4V to 16V Input, –5V Inverting Converter
191k
4.7µF
1µF
4.7pF
C5
1µF
L1
2.7µH
L2
2.7µH
1M
806k
V
OUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
4V TO 16V
V
IN
–5V
V
CC
INT
1M
D1
C1
C2
C3
4.7µF
D1: NXP PMEG6010CEJ
L1: WÜRTH WE-TDC 8018 74489430027
C3: MURATA GRM21BR71C475k
R1
R2
C4
R3
R4
280mA AT V
IN
= 4V
300mA AT V
IN
= 5V
380mA AT V
IN
= 12V
380mA AT V
IN
= 16V
8330 TA11
Efficiency
INVERTING: V
OUT
= –5V
V
IN
= 4V
V
IN
= 5V
V
IN
= 12V
V
IN
= 16V
LOAD CURRENT (mA)
0
80
160
240
320
400
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA11b
LT8330
22
8330f
For more information www.linear.com/LT8330
package DescripTion
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.56 ±0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.15 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
14
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDB8) DFN 0905 REV B
0.25 ±0.05 0.50 BSC
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
0.25 ±0.05
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
LT8330
23
8330f
For more information www.linear.com/LT8330
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX 0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
LT8330
24
8330f
For more information www.linear.com/LT8330
LINEAR TECHNOLOGY CORPORATION 2015
LT 0715 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT8330
relaTeD parTs
Typical applicaTion
4.7µF
56.2k
4.7µF
1µF
C6
1µF
C5
1µF
–VOUT
V
IN
SW
FBX
GND
EN/UVLO
LT8330
8V TO 40V
V
IN
–15V
V
CC
INT
1M
D1
C1
C2
C3
D1, D2: NXP PMEG6010CEJ
L1A, L1B, L1C: COILTRONICS VP4-0075
C3, C4: MURATA GRM32ER71H475k
R1
R2
R3
1M
R4
287k
C4
4.7µF
+V
OUT
+15V
D2
L1C
6µH
L1B
6µH
L1A
6µH
LOAD
120mA AT V
IN
= 8V
160mA AT V
IN
= 24V
170mA AT V
IN
= 40V
8330 TA12
8V to 40V Input, ±15V Converter
PART NUMBER DESCRIPTION COMMENTS
LT1930/LT1930A 1A (ISW), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC
Converter
VIN = 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, ISD < 1µA,
ThinSOT Package
LT1935 2A (ISW), 40V, 1.2MHz High Efficiency Step-Up DC/DC
Converter
VIN = 2.3V to 16V, VOUT(MAX) = 38V, IQ = 3mA, ISD < 1µA,
ThinSOT Package
LT3467 1.1A (ISW), 1.3MHz High Efficiency Step-Up DC/DC
Converter
VIN = 2.4V to 16V, VOUT(MAX) = 40V, IQ = 1.2mA, ISD < 1µA,
ThinSOT, 2mm × 3mm DFN Packages
LT3580 2A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC
Converter
VIN = 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD = <1µA,
3mm × 3mm DFN-8, MSOP-8E
LT8494 70V, 2A Boost/SEPIC 1.5MHz High Efficiency Step-Up
DC/DC Converter
VIN = 1V to 60V (2.5V to 32V Start-Up), VOUT(MAX) = 70V, IQ = 3µA
(Burst Mode operation), ISD = <1µA, 20-Lead TSSOP
LT8570/LT8570-1 65V, 500mA/250mA Boost/Inverting DC/DC Converter VIN(MIN) = 2.55V, VIN(MAX) = 40V, VOUT(MAX) = ±60V, IQ = 1.2mA,
ISD = <1mA, 3mm × 3mm DFN-8, MSOP-8E
LT8580 1A (ISW), 65V 1.5MHz, High Efficiency Step-Up DC/DC
Converter
VIN: 2.55V to 40V, VOUT(MAX) = 65V, IQ = 1.2mA, ISD = <1µA,
3mm × 3mm DFN-8, MSOP-8E
Efficiency
–V
OUT
= –15V
V
IN
= 8V
V
IN
= 24V
V
IN
= 40V
+V
OUT
= +15V
LOAD CURRENT (mA)
0
40
80
120
160
200
50
60
70
80
90
100
EFFICIENCY (%)
8330 TA12b
