THV1021 - THine Electronics, Inc.

THC63LVDM83E_Rev.1.30_E

7

PLL

TA +/-

TB +/-

TC +/-

TD +/-

TCLK +/-

R/F

/PDWN

TA0-6

TC0-6

TD0-6

TRANSMITTER

(8 to 160MHz)

CMOS/TTL

7

RS

7

TB0-6 7

INPUTS

CLOCK

(LVDS)

8-160MHz

DATA

(LVDS)

(56-1120Mbit/On Each

LVDS Channel)

CLKIN

THC63LVDM83E

CMOS/TTL PARALLEL

TO SERIAL

7

PLL

TA +/-

TB +/-

TC +/-

TD +/-

TCLK +/-

R/F

/PDWN

TA0-6

TC0-6

TD0-6

TRANSMITTER

(8 to 160MHz)

CMOS/TTL

7

RS

7

TB0-6 7

INPUTS

CLOCK

(LVDS)

8-160MHz

DATA

(LVDS)

(56-1120Mbit/On Each

LVDS Channel)

CLKIN

THC63LVDM83E

CMOS/TTL PARALLEL

TO SERIAL

THC63LVDM83E

SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER

General Description

The THC63LVDM83E transmitter is designed to

support pixel data transmission between Host and

Flat Panel Display up to 1080p/WUXGA resolutions.

The THC63LVDM83E converts 28bits of

CMOS/TTL data into LVDS (Low Voltage

Differential Signaling) data stream. The transmitter

can be programmed for rising edge or falling edge

clocks through a dedicated pin. At a transmit clock

frequency of 160MHz, 24bits of RGB data and 4bits

of timing and control data (HSYNC, VSYNC, DE,

CONT1) are transmitted at an effective rate of

1120Mbps per LVDS channel.

Features

･49pin 0.65mm pitch VFBGA Package

･Wide dot clock range: 8-160MHz suited for

TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz)

PC Signal : QVGA(8MHz) - WUXGA(154MHz)

･1.2V to 3.3V CMOS inputs are supported.

･LVDS swing is reducible by RS-pin to reduce EMI

and power consumption.

･PLL requires no external components.

･On chip jitter filtering.

･Spread Spectrum Clock input tolerant.

･Power down mode.

･Input clock triggering edge is selectable by R/F-pin.

･Operates from a Single 3.3V Supply and

110mW(typ.) at 75MHz.

Block Diagram

THC63LVDM83E_Rev.1.30_E

1234567

ATA6 TA5 TA4 TA3 TA2 TA1 TA0 A

BTB4 TD3 TD2 TD1 TD0 TA- TA+ B

CTB5 TB0 GND VCC RS TB- TB+ C

DTB6 TB1 GND LVDS

VCC

LVDS

VCC TC- TC+ D

ETC0 TB2 GND PLL

VCC R/F TCLK- TCLK+ E

FTC1 TB3 TD4 TD5 TD6 TD- TD+ F

GTC2TC3TC4TC5TC6CLKIN/PDWN

G

1234567

TOP VIEW

Ball Out

THC63LVDM83E_Rev.1.30_E

Pin Description

Pin Name Pin # Direction Type Description

TA+, TA- B7, B6

TB+, TB- C7, C6

TC+, TC- D7, D6

TD+, TD- F7, F6

LVDS Data Out

TCLK+,

TCLK-

E7, E6

Output LVDS

LVDS Clock Out

TA0 ~ TA6 A7,A6,A5,A4,A3,A2,A1

TB0 ~ TB6 C2,D2,E2,F2,B1,C1,D1

TC0 ~ TC6 E1,F1,G1,G2,G3,G4,G5

TD0 ~ TD6 B5,B4,B3,B2,F3,F4,F5

Pixel Data Input

/PDWN G7 H : Normal operation

L : Power down (all outputs are Hi-Z)

RS C5 LVDS swing mode, VREF select See Fig.5, 6

RS LVDS

Swing

Small Swing

Input Support

VCC 350mV N/A

0.6 ~ 1.4V 350mV RS=VREF

GND 200mV N/A

VREF is Input Reference Voltage

R/F E5 Input Clock Triggering Edge Select

H : Rising edge

L : Falling edge

CLKIN G6

Input LV-CMOS

/TTL

Input Clock

VCC C4 Power Supply Pin for CMOS input and digital

circuit.

GND C3,D3,E3 Ground Pins for Common.

LVDS VCC D4,D5 Power Supply Pins for LVDS Outputs.

PLL VCC E4

Power ---

Power Supply Pin for PLL circuit.

THC63LVDM83E_Rev.1.30_E

Absolute Maximum Ratings

Parameter Min Max Units

Supply Voltage -0.3 +4.0 V

LV-CMOS/TTL Input Voltage -0.3 VCC + 0.3 V

LVDS Transmitter Output Voltage -0.3 VCC + 0.3 V

Output Current -30 30 mA

Junction Temperature +125

°C

Storage Temperature -55 +125 °C

Reflow Peak Temperature +260

°C

Reflow Peak Temperature Time 10 sec

Maximum Power Dissipation @+25°C 1.2 W

Recommended Operating Conditions

Symbol Parameter Min Typ Max Units

All Supply Voltage 3.0 3.3 3.6 V

Ta Operating Ambient Temperature 0 25 +70 °C

Clock Frequency 8 160 MHz

THC63LVDM83E_Rev.1.30_E

CLKIN f

TA0, TB1, TC2 f/16

TA1, TB2, TC3 f/8

TA2, TB3, TC4 f/4

TA3, TB4, TC5 f/2

TA4-6, TB0,5,6

TC0

,

1

,

6

,

TD0-2 Steady State Low

TD3-6 Steady State High

CLKIN

Tx0-6

Power Consumption VCC = 3.0~3.6V, Ta= 0~+70ºC

Symbol Parameter Conditions Typ* Max Units

RL=100Ω, CL=5pF, f=85MHz

RS=VCC, (RS=GND)

42

(34) mA

LVDS Transmitter

Operating Current

Gray Scale Pattern 16

(Fig.1)

RL=100Ω, CL=5pF, f=160MHz

RS=VCC, (RS=GND)

58

(50) mA

RL=100Ω, CL=5pF, f=85MHz

RS=VCC, (RS=GND)

45

(36)

67

(56) mA

ITCCW LVDS Transmitter

Operating Current

Worst Case Pattern

(Fig.2)

RL=100Ω, CL=5pF, f=160MHz

RS=VCC, (RS=GND)

63

(55)

92

(80) mA

ITCCS LVDS Transmitter

Power Down Current 10 µA

*Typ values are at VCC=3.3V, Ta = +25ºC

16 Grayscale Pattern

Fig.1 16 Grayscale Pattern

Worst Case Pattern

x=A,B,C,D

Fig.2 Worst Case Pattern

THC63LVDM83E_Rev.1.30_E

Electrical Characteristics

LV-CMOS/TTL DC Specifications VCC = 3.0~3.6V, Ta= 0~+70ºC

Symbol Parameter Conditions Min Typ Max Units

VIH High Level Input Voltage RS=VCC or GND 2.0 VCC V

VIL Low Level Input Voltage RS=VCC or GND GND 0.8 V

VDDQ

1 Small Swing Voltage 1.2 2.8 V

VREF Input Reference Voltage Small Swing (RS=VDDQ/2) VDDQ/2

VSH

2 Small Swing High Level

Input Voltage VREF= VDDQ/2 VDDQ/2

+100mV V

VSL

2 Small Swing Low Level

Input Voltage VREF= VDDQ/2

VDDQ/2

-100mV V

IINC Input Current GND ≤ VIN ≤ VCC

±10 μA

*Typ values are at VCC=3.3V, Ta = +25ºC

Notes : 1 VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage.

2 Small swing signal is applied to TA0-6, TB0-6, TC0-6, TD0-6 and CLKIN.

LVDS Transmitter DC Specifications VCC = 3.0~3.6V, Ta= 0~+70ºC

Symbol Parameter Conditions Min Typ Max Units

Normal swing

RS=VCC 250 350 450 mV

VOD Differential Output Voltage RL=100ΩReduced swing

RS=GND 120 200 300 mV

∆VOD Change in VOD between

complementary output states 35 mV

VOC Common Mode Voltage 1.125 1.25 1.375 V

∆VOC Change in VOC between

complementary output states

RL=100Ω

35 mV

IOS Output Short Circuit Current VOUT=GND, RL=100Ω -24 mA

IOZ Output TRI-STATE Current /PDWN=GND,

VOUT=GND to VCC

±10 μA

*Typ values are at VCC=3.3V, Ta = +25ºC

THC63LVDM83E_Rev.1.30_E

CLK IN

90%

10%

90%

10%

tTCIT tTCIT

5pF 100Ω

TA+

TA-

20%

80%

20%

80%

tLVT tLVT

Vdiff

LV-CMOS/TTL & LVDS Transmitter AC Specifications VCC = 3.0~3.6V, Ta= 0~+70ºC

Symbol Parameter Min Typ Max Units

tTCIT CLK IN Transition Time 5.0 ns

tTCP CLK IN Period 6.25 T 125 ns

tTCH CLK IN High Time 0.35T 0.5T 0.65T ns

tTCL CLK IN Low Time 0.35T 0.5T 0.65T ns

tTCD CLK IN to TCLK+/- Delay 3T ns

tTS LV-CMOS/TTL Data Setup to CLK IN 2.0 ns

tTH LV-CMOS/TTL Data Hold from CLK IN 0.0 ns

tLVT LVDS Transition Time 0.6 1.5 ns

tTOP1 Output Data Position0 (T=6.25ns ~ 20ns) -0.15 0.0 +0.15 ns

tTop0 Output Data Position1 (T=6.25ns ~ 20ns) T/7-0.15 T/7 T/7+0.15 ns

tTop6 Output Data Position2 (T=6.25ns ~ 20ns) 2T/7-0.15 2T/7 2T/7+0.15 ns

tTop5 Output Data Position3 (T=6.25ns ~ 20ns) 3T/7-0.15 3T/7 3T/7+0.15 ns

tTop4 Output Data Position4 (T=6.25ns ~ 20ns) 4T/7-0.15 4T/7 4T/7+0.15 ns

tTop3 Output Data Position5 (T=6.25ns ~ 20ns) 5T/7-0.15 5T/7 5T/7+0.15 ns

tTop2 Output Data Position6 (T=6.25ns ~ 20ns) 6T/7-0.15 6T/7 6T/7+0.15 ns

tTPLL Phase Lock Loop Set 10.0 ms

*Typ values are at VCC=3.3V, Ta = +25ºC

LV-CMOS/TTL Input

Fig.3 CLKIN Transmission Time

LVDS Output

V

Diff = (TA+) – (TA-)

LVDS Output Load

Fig.4 LVDS Output Load and Transmission Time

THC63LVDM83E_Rev.1.30_E

RS VOD

VCC

0.6 ~ 1.4V

GND 200mV

350mV

tTC P

tTS tTH

tTCH

tTCL

CLK IN

Tx0-Tx6

tTCD

TCLK+

TCLK-

VDDQ

GND

VDDQ

VREF

VOC

VREF

VDDQ

/2 VDDQ /2

VDDQ/2 VDD Q/2 VDD Q/2

VOD

RS VREF

VCC ---

0.6 ~ 1.4V V

DDQ

/2

GND ---

tTCP

tTS tTH

tTC H

tTCL

CLK IN

Tx0-Tx6

tTCD

TCLK+

TCLK-

VOC

VCC

GND

VCC

VOD

AC Timing Diagrams

LV-CMOS/TTL Inputs

Note :

CLKIN : for R/F=GND, denote as solid line,

for R/F = VCC, denote as dashed line.

Fig.5 CLKIN Period, High/Low Time, Setup/Hold Timing

Small Swing Inputs

Note :

CLKIN : for R/F=GND, denote as solid line,

for R/F = VCC, denote as dashed line.

Fig.6 Small Swing Inputs

THC63LVDM83E_Rev.1.30_E

Vdiff = 0V Vdiff = 0V

TCLK+/-

tTOP1

tTO P0

tTO P6

tTO P5

tTO P4

tTO P3

tTO P2

TD6 TD5 TD4 TD 3 TD 2 TD1 TD 0

TD+/-

TC6 TC5 TC4 TC 3 TC 2 TC1 TC 0

TC+/-

TB6 TB5 TB4 TB3 TB2 TB1 TB0

TB+/-

TA6 TA5 TA4 TA3 TA2 TA1 TA0

TA+/-

(Differential)

Nex t Cycle

Previous Cycle

2.0V

CLKIN

/PDWN

TCLK+/-

3.0V

VCC tTPLL

Vdiff

= 0V

LVDS Output

Fig.7 LVDS Output Data Position

Phase Lock Loop Set Time

Fig.8 PLL Lock Set Time

THC63LVDM83E_Rev.1.30_E

TA- TA+

TB- TB+

TC- TC+

TCLK- TCLK+

TD- TD+

TA5TA6

TB4

TB6

TC0

TC1

TB5

TC2 TC3 TC4 TC5 TC6

VCC

LVDS

VCC

LVDS

VCC

PLL

VCC

GND

TA4 TA3 TA2 TA1

TB1

TB0

TA0

TB2

TB3

R/F

RS

TD0TD1TD2TD3

TD4 TD5 TD6

/PWDNCLKIN

R2

R3

R4

R5

R6

R7

G2

G3

G4

G5

G6

G7

B2

B3

B4

B5

B6

B7

R0

R1

G0

G1

B0

B1

1234567

A

TA6 TA5 TA4 TA3 TA2 TA1 TA0

A

B

TB4 TD3 TD2 TD1 TD0 TA- TA+

B

C

TB5 TB0 GND VCC RS TB- TB+

C

D

TB6 TB1 GND LVDS

VCC

LVDS

VCC TC- TC+

D

E

TC0 TB2 GND PLL

VCC R/F TCLK- TCLK+

E

F

TC1 TB3 TD4 TD5 TD6 TD- TD+

F

G

TC2 TC3 TC4 TC5 TC6 CLKIN /PDWN

G

1234567

TOP VIEW

Board Layout Example

THC63LVDM83E_Rev.1.30_E

LVDS-Rx

THC63LVDM83E LVDS-Rx

TCLK+

TCLK-

IC

CLKOUT

DATA

DATA LVDS-Rx

LVDS-Rx

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

THC63LVDM83E

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

IC

THC63LVDM83E

Note

1) Cable Connection and Disconnection

Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.

2) GND Connection

Connect the each GND of the PCB which THC63LVDM83E and LVDS-Rx on it. It is better for EMI

reduction to place GND cable as close to LVDS cable as possible.

3) Multi Drop Connection

Multi drop connection is not recommended.

4) Asynchronous use

Asynchronous using such as following systems are not recommended.

THC63LVDM83E_Rev.1.30_E

Package

1234567

A

B

C

D

E

F

G

PIN A1 CORNER

5.0

1234567

A

B

C

D

E

F

G

PIN A1 CORNER

3.90

Φ0.3

0.3

TOP VIEW

BOTTOM VIEW

SIDE VIEW

Unit : mm

THC63LVDM83E_Rev.1.30_E

Notices and Requests

1. The product specifications described in this material are subject to change without prior notice.

2. The circuit diagrams described in this material are examples of the application which may not always apply to

the customer's design. We are not responsible for possible errors and omissions in this material. Please note if

errors or omissions should be found in this material, we may not be able to correct them immediately.

3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties

the contents of this material without our prior permission is prohibited.

4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will

be exempted from the responsibility unless it directly relates to the production process or functions of the

product.

5. This product is presumed to be used for general electric equipment, not for the applications which require

very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or

nuclear control equipment). Also, when using this product for the equipment concerned with the control and

safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please

do it after applying appropriate measures to the product.

6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain

small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have

sufficiently redundant or error preventive design applied to the use of the product so as not to have our

product cause any social or public damage.

7. Please note that this product is not designed to be radiation-proof.

8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic

goods under the Foreign Exchange and Foreign Trade Control Law.

THine Electronics, Inc.

sales@thine.co.jp