THC63LVDM83E_Rev.1.30_E THC63LVDM83E SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER General Description Features The THC63LVDM83E transmitter is designed to support pixel data transmission between Host and Flat Panel Display up to 1080p/WUXGA resolutions. The THC63LVDM83E converts 28bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 160MHz, 24bits of RGB data and 4bits of timing and control data (HSYNC, VSYNC, DE, CONT1) are transmitted at an effective rate of 1120Mbps per LVDS channel. 49pin 0.65mm pitch VFBGA Package Wide dot clock range: 8-160MHz suited for TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz) PC Signal : QVGA(8MHz) - WUXGA(154MHz) 1.2V to 3.3V CMOS inputs are supported. LVDS swing is reducible by RS-pin to reduce EMI and power consumption. PLL requires no external components. On chip jitter filtering. Spread Spectrum Clock input tolerant. Power down mode. Input clock triggering edge is selectable by R/F-pin. Operates from a Single 3.3V Supply and 110mW(typ.) at 75MHz. Block Diagram TA0-6 TB0-6 TC0-6 TD0-6 TRANSMITTER CLKIN (8 to 160MHz) 7 7 7 7 CMOS/TTL PARALLEL TO SERIAL THC63LVDM83E CMOS/TTL INPUTS DATA (LVDS) TA +/TB +/TC +/TD +/(56-1120Mbit/On Each LVDS Channel) TCLK +/- PLL CLOCK (LVDS) 8-160MHz R/F /PDWN RS Copyright(c)2012 THine Electronics, Inc. 1 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Ball Out TOP VIEW 1 2 3 4 5 6 7 A TA6 TA5 TA4 TA3 TA2 TA1 TA0 A B TB4 TD3 TD2 TD1 TD0 TA- TA+ B C TB5 TB0 GND VCC RS TB- TB+ C D TB6 TB1 GND LVDS VCC LVDS VCC TC- TC+ D E TC0 TB2 GND PLL VCC R/F TCLK- TCLK+ E F TC1 TB3 TD4 TD5 TD6 TD- TD+ F G TC2 TC3 TC4 TC5 TC6 CLKIN /PDWN G 1 2 3 4 5 6 7 Copyright(c)2012 THine Electronics, Inc. 2 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Pin Description Pin Name TA+, TATB+, TBTC+, TCTD+, TDTCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 /PDWN Pin # B7, B6 C7, C6 D7, D6 F7, F6 E7, E6 A7,A6,A5,A4,A3,A2,A1 C2,D2,E2,F2,B1,C1,D1 E1,F1,G1,G2,G3,G4,G5 B5,B4,B3,B2,F3,F4,F5 G7 RS C5 R/F E5 CLKIN VCC G6 C4 GND LVDS VCC PLL VCC C3,D3,E3 D4,D5 E4 Copyright(c)2012 THine Electronics, Inc. Direction Type Output LVDS Description LVDS Data Out LVDS Clock Out Pixel Data Input H : Normal operation L : Power down (all outputs are Hi-Z) LVDS swing mode, VREF select See Fig.5, 6 Input LV-CMOS /TTL Power --- 3 LVDS Small Swing Swing Input Support VCC 350mV N/A 0.6 ~ 1.4V 350mV RS=VREF GND 200mV N/A VREF is Input Reference Voltage Input Clock Triggering Edge Select H : Rising edge L : Falling edge Input Clock Power Supply Pin for CMOS input and digital circuit. Ground Pins for Common. Power Supply Pins for LVDS Outputs. Power Supply Pin for PLL circuit. RS THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Absolute Maximum Ratings Parameter Supply Voltage LV-CMOS/TTL Input Voltage LVDS Transmitter Output Voltage Output Current Junction Temperature Storage Temperature Reflow Peak Temperature Reflow Peak Temperature Time Maximum Power Dissipation @+25C Min -0.3 -0.3 -0.3 -30 Max +4.0 VCC + 0.3 VCC + 0.3 30 +125 +125 +260 10 1.2 -55 Units V V V mA C C C sec W Recommended Operating Conditions Symbol Ta Parameter All Supply Voltage Operating Ambient Temperature Clock Frequency Copyright(c)2012 THine Electronics, Inc. Min 3.0 0 8 4 Typ 3.3 25 Max 3.6 +70 160 Units V C MHz THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Power Consumption Symbol Parameter Conditions LVDS Transmitter RL=100, CL=5pF, f=85MHz Operating Current RS=VCC, (RS=GND) Gray Scale Pattern 16 RL=100, CL=5pF, f=160MHz (Fig.1) RS=VCC, (RS=GND) ITCCW LVDS Transmitter RL=100, CL=5pF, f=85MHz Operating Current RS=VCC, (RS=GND) Worst Case Pattern RL=100, CL=5pF, f=160MHz (Fig.2) RS=VCC, (RS=GND) LVDS Transmitter ITCCS Power Down Current *Typ values are at VCC=3.3V, Ta = +25C VCC = 3.0~3.6V, Ta= 0~+70C Typ* Max Units 42 mA (34) 58 mA (50) 45 67 mA (36) (56) 63 92 mA (55) (80) 10 A 16 Grayscale Pattern CLKIN f TA0, TB1, TC2 f/16 TA1, TB2, TC3 f/8 TA2, TB3, TC4 f/4 TA3, TB4, TC5 f/2 TA4-6, TB0,5,6 TC0,1,6, TD0-2 Steady State Low TD3-6 Steady State High Fig.1 16 Grayscale Pattern Worst Case Pattern CLKIN Tx0-6 x=A,B,C,D Fig.2 Worst Case Pattern Copyright(c)2012 THine Electronics, Inc. 5 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Electrical Characteristics VCC = 3.0~3.6V, Ta= 0~+70C Parameter Conditions Min Typ Max Units High Level Input Voltage RS=VCC or GND 2.0 VCC V Low Level Input Voltage RS=VCC or GND GND 0.8 V Small Swing Voltage 1.2 2.8 V Input Reference Voltage Small Swing (RS=VDDQ/2) VDDQ/2 Small Swing High Level VDDQ/2 VREF= VDDQ/2 V Input Voltage +100mV VSL2 Small Swing Low Level VDDQ/2 VREF= VDDQ/2 V Input Voltage -100mV IINC Input Current 10 A GND VIN VCC *Typ values are at VCC=3.3V, Ta = +25C Notes : 1 VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage. 2 Small swing signal is applied to TA0-6, TB0-6, TC0-6, TD0-6 and CLKIN. LV-CMOS/TTL DC Specifications Symbol VIH VIL VDDQ1 VREF VSH2 LVDS Transmitter DC Specifications Symbol VOD VOD Parameter Differential Output Voltage IOS Change in VOD between complementary output states Common Mode Voltage Change in VOC between complementary output states Output Short Circuit Current IOZ Output TRI-STATE Current VOC VOC Conditions Normal swing RS=VCC RL=100 Reduced swing RS=GND RL=100 VCC = 3.0~3.6V, Ta= 0~+70C Min Typ Max Units 250 350 450 mV 120 200 300 mV 35 mV 1.375 V 35 mV -24 mA 10 A 1.125 VOUT=GND, RL=100 /PDWN=GND, VOUT=GND to VCC 1.25 *Typ values are at VCC=3.3V, Ta = +25C Copyright(c)2012 THine Electronics, Inc. 6 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E LV-CMOS/TTL & LVDS Transmitter AC Specifications Symbol Parameter tTCIT CLK IN Transition Time tTCP CLK IN Period tTCH CLK IN High Time tTCL CLK IN Low Time tTCD CLK IN to TCLK+/- Delay tTS LV-CMOS/TTL Data Setup to CLK IN tTH LV-CMOS/TTL Data Hold from CLK IN tLVT LVDS Transition Time tTOP1 Output Data Position0 (T=6.25ns ~ 20ns) tTop0 Output Data Position1 (T=6.25ns ~ 20ns) tTop6 Output Data Position2 (T=6.25ns ~ 20ns) tTop5 Output Data Position3 (T=6.25ns ~ 20ns) tTop4 Output Data Position4 (T=6.25ns ~ 20ns) tTop3 Output Data Position5 (T=6.25ns ~ 20ns) tTop2 Output Data Position6 (T=6.25ns ~ 20ns) tTPLL Phase Lock Loop Set *Typ values are at VCC=3.3V, Ta = +25C LV-CMOS/TTL Input Min 6.25 0.35T 0.35T 2.0 0.0 -0.15 T/7-0.15 2T/7-0.15 3T/7-0.15 4T/7-0.15 5T/7-0.15 6T/7-0.15 90% CLK IN VCC = 3.0~3.6V, Ta= 0~+70C Typ Max Units 5.0 ns T 125 ns 0.5T 0.65T ns 0.5T 0.65T ns 3T ns ns ns 0.6 1.5 ns 0.0 +0.15 ns T/7 T/7+0.15 ns 2T/7 2T/7+0.15 ns 3T/7 3T/7+0.15 ns 4T/7 4T/7+0.15 ns 5T/7 5T/7+0.15 ns 6T/7 6T/7+0.15 ns 10.0 ms 90% 10% 10% t TCIT t TCIT Fig.3 CLKIN Transmission Time LVDS Output VDiff = (TA+) - (TA-) 80% 80% TA+ 5pF 100 Vd if f 20% 20% TA- LVDS Output Load t LVT t LVT Fig.4 LVDS Output Load and Transmission Time Copyright(c)2012 THine Electronics, Inc. 7 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E AC Timing Diagrams LV-CMOS/TTL Inputs RS VCC 0.6 ~ 1.4V GND tTCP tTC H VOD 350mV 200mV VCC CLK IN GND t T CL tTS tTH VCC Tx0-Tx6 GND t TCD TCLK+ VOD VOC TCLK- Note : CLKIN : for R/F=GND, denote as solid line, for R/F = VCC, denote as dashed line. Fig.5 CLKIN Period, High/Low Time, Setup/Hold Timing Small Swing Inputs RS VREF VCC --0.6 ~ 1.4V VDDQ/2 GND --- tTC P t T CH VD DQ CLK IN VD DQ /2 V DD Q /2 VREF VDD Q /2 GND t TCL t TS t TH VDDQ Tx0-Tx6 V D D Q/2 VD DQ /2 VREF GND tTCD TCLK+ VOD VOC TCLK- Note : CLKIN : for R/F=GND, denote as solid line, for R/F = VCC, denote as dashed line. Fig.6 Small Swing Inputs Copyright(c)2012 THine Electronics, Inc. 8 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E LVDS Output TCLK+/(Differential) Vdiff = 0V Vdiff = 0V TA+/- TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB+/- TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC+/- TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD+/- TD6 TD5 TD4 TD3 TD2 TD1 TD0 Previous Cycle Next Cycle t TOP1 t TOP0 t TOP6 t TOP5 t TOP4 t TOP3 t TOP2 Fig.7 LVDS Output Data Position Phase Lock Loop Set Time /PDWN VCC 2.0V 3.0V tTPLL CLKIN Vdiff = 0V TCLK+/- Fig.8 PLL Lock Set Time Copyright(c)2012 THine Electronics, Inc. 9 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Board Layout Example TOP VIEW 1 2 3 4 5 6 7 A TA6 TA5 TA4 TA3 TA2 TA1 TA0 A B TB4 TD3 TD2 TD1 TD0 TA- TA+ B C TB5 TB0 GND VCC RS TB- TB+ C D TB6 TB1 GND LVDS VCC LVDS VCC TC- TC+ D E TC0 TB2 GND PLL VCC R/F TCLK- TCLK+ E F TC1 TB3 TD4 TD5 TD6 TD- TD+ F G TC2 TC3 TC4 TC5 TC6 CLKIN /PDWN G 1 2 3 4 5 6 7 R0 R1 R2 R3 R4 R5 R6 R7 B0 B1 G0 G1 G2 G3 G4 G5 G6 G7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB4 TD3 TD2 TD1 TD0 TA- TA+ TB5 TB0 GND VCC RS TB- TB+ TB6 TB1 GND LVDS VCC LVDS VCC TC- TC+ TC0 TB2 GND PLL VCC R/F TCLK- TCLK+ TC1 TC2 TB3 TC3 TD4 TC4 TD5 TC5 TD6 TC6 TDCLKIN TD+ /PWDN B2 B3 B4 B5 B6 B7 Copyright(c)2012 THine Electronics, Inc. 10 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Note 1) Cable Connection and Disconnection Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 2) GND Connection Connect the each GND of the PCB which THC63LVDM83E and LVDS-Rx on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 3) Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVDM83E LVDS-Rx TCLKLVDS-Rx 4) Asynchronous use Asynchronous using such as following systems are not recommended. CLKOUT DATA IC TCLK+ THC63LVDM83E CLKOUT DATA TCLK- CLKOUT LVDS-Rx IC TCLK+ THC63LVDM83E TCLK- CLKOUT DATA IC Copyright(c)2012 THine Electronics, Inc. LVDS-Rx DATA TCLK+ THC63LVDM83E CLKOUT DATA DATA TCLKTCLK+ THC63LVDM83E 11 IC TCLK- THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Package PIN A1 CORNER TOP VIEW 1 2 3 4 5 6 7 A B C D E F G 5.0 BOTTOM VIEW PIN A1 CORNER 0.3 7 6 5 4 3 2 1 A B C D E F G 3.90 SIDE VIEW Unit : mm 0.3 Copyright(c)2012 THine Electronics, Inc. 12 THine Electronics, Inc. THC63LVDM83E_Rev.1.30_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. sales@thine.co.jp Copyright(c)2012 THine Electronics, Inc. 13 THine Electronics, Inc.