©2009 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
November 2009
FAN7085_GF085 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
FAN7085_GF085
High Side Gate Driver with Recharge FET
Features
• Qualified to AEC Q100
• Floating channel designed for bootstrap operatio n fully oper-
ational up to 300V.
• Tolerance to negative transient voltage on VS pin
• dv/dt immune.
• Gate drive supply range from 4.5V to 20V
• Under-voltage lockout
• CMOS Schmitt-triggered inputs with pull-down and pull-up
• High side output out of phase with input (Inverted input)
• Reset input
• Internal recharge FET for bootstrap refresh
Typical Applications
• Diesel and gasoline injectors/valves
• MOSFET-and IGBT high side driver applications
For Fairchild’s definition of “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html
Description
The FAN7085_GF085 is a high-side gate drive IC with reset
input and built-in recharge FET. It is designed for high voltage
and high speed driving of MOSFET or IGBT, which operates up
to 300V. Fairchild's high-voltage process and common-mode
noise cancellation technique provide stable operation in the
high side driver under high-dV/dt noise circumstances. Logic
input is compatible with standard CMOS outputs. The UVLO cir-
cuits prevent from malfunction when VCC and VBS are lower
than the specified threshold voltage. It is available with space
saving SOIC-8 Package. Minimum source and sink current
capability of output driver is 250mA and 250mA. Built-in
recharge FET to refresh bootstrap circuit is very useful for circuit
topology requiring switches on low and high side of load.
Ordering Information
X : Tape & Reel type
Device Package Operating
Temp.
FAN7085M SOIC-8 -40 °C ~ 125 °C
FAN7085MX SOIC-8 -40 °C ~ 125 °C
SOIC-8
2www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Block Diagrams
Pin Assignments
Pin Definitions
Pine Number Pin Name I/O Pin Function Description
1 VCC P Driver supply voltage, typically 5V
2 IN- I Driver control signal input (Negative Logic)
3GNDPGround
4 RESET- I Driver enable input signal (Negative Logic)
5 VS P High side floating offset for MOSFET Source connection
6 NC - No connection (No Bond wire)
7 HO A High side drive output for MOSFET Gate connection
8 VB P Driver output stage supply
VCC Under Voltage
Reset VCC to GND
Logic
Pulse
Filter
Level Shifter
ON
Level Shifter
OFF
Delay
Under
Voltage Reset
VB to VS
Pulse Filter
Flip Flop
Brake before
make
RESET-
IN-
GND
VS
HO
VB
Recharge Path
1
2
3
45
6
7
8
VCC
IN-
GND
RESET- VS
NC
HO
VB
3www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are abso-
lute voltages referenced to GND.
Note: 1) The thermal resistance and power dissipation rating are measured bellow conditions;
JESD51-2: Integrated Circuit Thermal Test Method Environmental Conditions - Natural condition(StillAir)
JESD51-3: Low Effective Thermal Conductivi ty Test Board for Leaded Sur face Mount Package
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.-40°C <= Ta <= 125°C
Note: 1) Guaranteed by design.
2) Duty = 0.5, VBS >=7V
3) Guaranteed by design. Pulse widths below the specified values, may be ignored. Output will either follow the input signal or will ignore it.
No false output state is guaranteed when minimum input width is smaller than tin
4) Guaranteed by design
Parameter Symbol Min. Max. Unit
High side floating supply voltage VBS -0.3 25 V
High side driver output stage voltage
Neg. transient: 0.5 ms, external MOSFET off VB-5 325 V
High side floating supply offset voltage
Neg. transient 0.2 us Vs -25 300 V
High side floating output voltage VHO VS-0.3 VB+0.3 V
Supply voltage VCC -0.3 25 V
Input voltage for IN- VIN -0.3 Vcc+0.3 V
Input voltage for RESET- VRES -0.3 Vcc+0.3 V
Power Dissipation 1) Pd 0.625 W
Thermal resistance, junction to ambient 1) Rthja 200 °C/W
Electrostatic discharge voltage
(Human Body Model) VESD 1.5K V
Charge device model VCDM 500 V
Junction Temperature Tj 150 °C
Storage Temperature TS-55 150 °C
Parameter Symbol Min. Max. Unit
High side floating supply voltage(DC)
Transient:-10V@ 0.2 us VBVS+4.5 VS+20 V
High side floating supply offset voltage(DC)
@VBS=7V VS-3 300 V
High side floating supply offset voltage(Transient)
0.2us @VBS<25V VS-25 300 V
High side floating output voltage VHO Vs VB V
Allowable offset voltage Slew Rate 1) dv/dt - 50 V/ns
Supply voltage for logic part VCC 4.5 20 V
Input voltage for IN- VIN 0 Vcc V
Input voltage for RESET- VRESET 0 Vcc V
Switching frequency 2) Fs 200K Hz
Minimum low input width 3) tIN(low,min) 1000 - ns
Minimum high input width 3) tIN(high,min) 60 - ns
Minimum operating voltage of VB related to GND VB(MIN)4) 4- V
Ambient temperature Ta-40 125 °C
4www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Statics Electrical Chara cteristics
Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50Ω, CL = 2.5nF.
Note: The input parameter are referenced to GND. The VO and IO parameters are referenced to GND.
Parameter Symbol Conditions Min. Typ. Max. Unit
VCC and VBS Supply Characteristics
VCC and VBS supply under voltage
positive going threshold VCCUV+
VBSUV+ Vcc and VBS rising from 0V - 3.7 4.3 V
VCC and VBS supply under voltage
negative going thresho ld VCCUV-
VBSUV- Vcc and VBS dropping from 5V 2.8 3.4 - V
VCC and VBS under voltage hysteresis VCCUVH
VBSUVH - 0.02 0.3 - V
Under voltage lockout response time tduvcc
tduvbs VCC: 6.5V->2.4V or 2.4V->6.5V
VBS: 6.5V->2.4V or 2.4V->6.5V 0.5
0.5 20
20 us
us
Offset supply leakage current ILK VB=VS=300V - - 200 uA
Quiescent Vcc supply current IQCC Vcc=20V - - 500 uA
Quiescent VBS supply current IQBS1 Static mode,
VBS=7V, VIN=0 or 5V 100 uA
Quiescent VBS supply current IQBS2 Static mode,
VBS=16V, VIN=0 or 5V 200 uA
VBS drop due to output turn-on
(Design guaranty) ΔVBS VBS=7V, Cbs=1uF, tdIG-IN =3uS,
tTEST=100uS 210 mV
Input Characteristics
High logic level input voltage for IN- VIH 0.6VCC --V
Low logic level input voltage for IN- VIL --0.28VCC V
Low logic level input bias current for IN- IIN- VIN=0 5 25 60 uA
High logic level input bias current for IN- IIN+ VIN=5V - - 5 uA
Full up resistance at IN RIN 83 200 1000 ΚΩ
High logic level input voltage for RESET- VRH 0.6Vcc - - V
Low logic level input voltage for RESET- VRL 0.28Vcc V
High logic level input current for RESET- IRES+ VRESET=5V 5 25 60 uA
Low logic level input bias current for RESET- IRES- VRESET=0 5 uA
Full down resistance at RESET- RRES 83 200 1000 ΚΩ
Output characteristics
High level output voltage, VB - VHO VOH IO=0 - - 0.1 V
Low level output voltage, VHO-GND VOL IO=0 - - 0.1 V
Peak output source current IO+ VIN=5V 250 450 - mA
Peak output sink current IO- VIN=0 250 450 - mA
Equivalent output resistance ROP 15.5 28 Ω
RON 15.5 28 Ω
Recharge Characteristics
Recharge TR turn-on propagation delay Ton_rech 47.99.8us
Recharge TR turn-off propagation delay Toff_rech 0.2 0.4 us
Recharge TR on-state voltage drop VRECH Is=1mA, VIN=5V @125°C 1.2 V
Dead Time Characteristics
High side turn-off to recharge gate turn-on DTHOFF Vcc=5V, VS=7V 4 7.8 9.8 us
Recharge gate turn-off to high side turn-on DTHON Vcc=5V, VS=7V 0.1 0.4 0.7 us
5www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Dynamic Electrical Characteristics
Unless otherwise specified, -40°C <= Ta <= 125°C, VCC = 5V, VBS = 7V, VS = 0V, VRESET = 5V, RL = 50Ω, CL = 2.5nF.
Parameter Symbol Conditions Min. Typ. Max. Unit
Input-to-output turn-on propagation delay tplh 50% input level to 10% output level,
VS = 0V 0.56 1 us
Input-to-output turn -off propagation delay tphl 50% input level to 90% output level
VS = 0V - 0.15 0.5 us
RESET-to-output turn-off propagation delay tphl_res 50% input level to 90% output level - 0.17 0.5 us
RESET-to-output turn-on propagat ion del ay tplh_res 50% input level to 10% output level - 0.56 1 us
Output rising time tr1 Tj=25°C - 65 200 ns
tr2 - 400 ns
tr3 Tj=25°C,VBS=16V 65 200 ns
tr4 VBS=16V - 400 ns
Output falling time tf1 Tj=25°C - 25 200 ns
tf2 - 300 ns
tf3 Tj=25°C,VBS=16V 25 200 ns
tf4 VBS=16V - 300 ns
6www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Application Information
1. Logic Tables
Notes:
X means independent from signal
IN-=LOW indicates that the high side NMOS is ON
IN-=HIGH indicates th at the high side NMOS is OFF
RechFET =ON indicates that the recharge MOSFET is ON
RechFET =OFF indicates that the recharge MOSFET is OFF
VCC VBS RESET- IN- Ho RechFET
< VCCUVLO- X X X OFF ON
XXLOWXOFFON
X X X HIGH OFF ON
> VCCUVLO+ > VBSUVLO+ HIGH LOW ON OFF
> VCCUVLO+ < VBSUVLO- HIGH LOW OFF OFF
7www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Typical Application Circuit
1. Typical Application Circuit
2. Application Example
VCC
IN-
GND
RESET-
VB
HO
NC
VS
C1
R1
R2
C2
VCC
C3
D1 Up to 300V
Load
VCC
IN-
GND
RESET-
VB
HO
NC
VS
C2 C1
R1
R2
R3
R4
C3
5V
From Charge Pump Voltage Source
C4
Load
GND
From LS Driver
S1
S2
D3
D4
D5
8www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Input-Output Waveforms
1. Input/Output Timing Diagrams
2. Reset Timing Diagrams
Toff_rech Ton_rech
tphl
IN-
RESET-
VS
VHO
Recharge tplh
10%
90%90%
10%
tr tf
Figure.1 Input and Output Timing Diagram and Switching Time Waveform Definition
tphl_res
tplh_res
IN-
RESET-
VHO
Figure.2 Reset and Output Timing Diagram
9www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
3.VB Drop Voltage Diagram
VBdrop
IN-
RESET-
VB-VS
Ig
7V
Brake before make
VCC
IN-
GND
RESET-
VB
HO
NC
VS
1u
50R
2n5
Ig
Figure3.a VB Drop Voltage Diagram
Figure3.b VB Drop Volt age Test Circuit
10 www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Performance Graphs
This performance graphs based on ambient temperature -40°C ~125°C
4.4 4.7 5.0 5.3 5.6 5.9 6.2 6.5
2.2
2.4
2.6
2.8
3.0
3.2
Typ.
Vinth+ (V)
Vsupply (V)
Figure 4a. Positive IN and RESET Threshold vs VCC Supply Figure 4b. Negative IN and RESET Threshold vs VCC Supply
Figure5b. Output Source Current vs Temperature
Figure 6a. Turn-On Prop agation Delay T im e vs Temperature Figure 6b. Turn-Off Propagation Delay Time vs Temperature
Figure5a. Output Sink Current vs VBS Supply
VBS=7V, RL=50, CL=2.5nF
4.44.75.05.35.65.96.26.5
1.8
2.0
2.2
2.4
2.6
Typ.
Vinth- (V)
Vsupply (V)
5101520
0
400
800
1200
1600
2000
125oC
Output Sink Cureent (mA)
VBS(V)
-40oC
-50 0 50 100 150
300
350
400
450
500
Typ.
Output Source Cureent (mA)
Temperature (oC)
-50 0 50 100 150
500
530
560
590
620
650
Turn-on Propagation Delay (ns)
Temperature(oC)
Typ.
-50 0 50 100 150
100
150
200
250
Turn-off Propagation Delay (ns)
Temperature (oC)
Typ.
VBS=7V, RL=50, CL=2.5nF
VCC=5V, VBS=7VVCC=5V
VCC=5V,VBS=7V, RL=50, CL=2.5nFVCC=5V,VBS=7V, RL=50, CL=2.5nF
11 www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
-50 0 50 100 150
100
150
200
250
Typ.
RES-to-Output Turn-off Propagation Delay (ns)
Temperature (oC)
-50 0 50 100 150
500
550
600
650
700
Typ.
RES-to-Output Turn-on Propagation Delay (ns)
Temperature (oC)
Figure 7a. RES to Output Turn-On Propagation Delay vs Temperature Figure 7b. RES to Output Turn-Off Propagation Delay vs Temperatu
r
Figure 9. Logic “1” RESET Input Current vs Temperature
Figure 10a. VBS Under Vol tage Threshold(+) vs Temperature Figure 10b. VBS Under Voltage Threshold(-) vs Temperature
Figure 8. Logic “0” IN Input Current vs Temperature
VCC=5V, VBS=7V, RL=50, CL=2.5nF VCC=5V, VBS=7V, RL=50, CL=2.5nF
-50 0 50 100 150
0
10
20
30
40
50
Logic "0" Input Current (uA)
Temperature ( oC)
Typ.
-50 0 50 100 150
0
10
20
30
40
50
Typ.
Logic "1" RES I n put Current (uA)
Temperature (oC)
VCC=5V, RL=50, CL=2.5nF VCC=5V, RL=50, CL=2.5nF
-50 0 50 100 150
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Min.
Max.
Typ.
VBS Supply Voltage(V)
Temperature(oC)
-50 0 50 100 150
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VBS Supply Voltage(V)
Temperature(oC)
Max.
Typ.
Min.
12 www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Figure 11a. VCC Under Voltage Threshold(+) vs Temperature Figure 11b. VCC Under Voltage Threshold(-) vs Temperature
Figure 12. Recharge FET Turn-on Delay time
Figure 14. Recharge FET I-V curve
Figure 12. Recharge FET Turn-off Delay time
VBS=7V
-50 0 50 100 150
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCC Supply Voltage(V)
Temperature(oC)
Max.
Typ.
Min.
-50 0 50 100 150
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCC Supply Voltage(V)
Temperature(oC)
Max.
Typ.
Min.
-50 0 50 100 150
4
6
8
10
Typ.
Recharge Transistor Turn-on Propagation
Delay (us)
Temperature(oC) -50 0 50 100 150
140
180
220
260
300
Typ.
Recharge Gate Turn-off Propagation
Delay (ns)
Temperature (oC)
0.4 0.6 0.8 1.0 1.2
0.2
0.6
1.0
1.4
1.8
I (mA)
V (V)
Typ.
-50 0 50 100 150
4
6
8
10
Typ.
High Side Turn-off to Recharge Gate
Turn-on (us)
Temperature (oC)
Figure 15. High Side Turn-off to Recharge FET turn-on VS Temperature
VCC=5v, VBS=7, VRL=50, CL=2.5nF VCC=5v, VBS=7V, RL=50, CL=2.5nF
VCC=5v, VBS=7V, RL=50, CL=2.5nF VCC=5v, VBS=7V, RL=50, CL=2.5nF
13 www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
Package Dimensions
14 www.fairchildsemi.com
FAN7 085 _G F0 85 Rev. 1.0.0
FAN7085_GF085 High Side Gate Driver with Recharge FET
TRADEM ARKS
The following includes registered and unregistered t rademarks and service marks, owned by Fairchild Semiconductor and/ or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
AccuPower™
Auto-SPM™
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT™
CTL™
Curre nt Trans fer Lo gic ™
EcoSPARK®
EfficientMax™
EZSWITCH™*
™*
DEUXPEED™
®
Fairchild®
Fairchild Semiconductor®
FACT Quie t Series™
FACT®
FAST®
FastvCore™
FETBench™
FlashWriter®*
FPS™
F-PFS™
FRFET®
Gl obal P ower ResourceSM
Green FP S™
Green FP S™ e-Series™
Gmax™
GTO™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
MotionMa x™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
PDP SPM™
Power-SPM™
PowerTrench®
PowerXS™
Pr ogr a mm a ble A ctiv e Dr oop™
QFET®
QS™
Qu i e t Se r i es™
RapidConfigure™
™
Sav ing our w or ld, 1mW/W/ k W a t a ti me™
SignalWise™
SmartMax™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS™
SyncFET™
Sync-Lock™
®*
The Power Fr anc hise®
TinyBoost™
TinyBuck™
TinyCalc™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
TriFault Detect™
TRUECURRENT™*
μSerDes™
UHC®
Ult r a FRF ET™
UniFET™
VCX™
VisualMax™
XS™
* Trademar ks of Sy stem Gener al Corporation, used under lic ens e b y Fairchild Sem ic o nduc tor.
DISCLAIMER
FAIRCHILD SEM IC OND UCTOR RES ERV ES THE RIGHT TO MAKE CHANGES WI THOUT FU RTHER NOTI CE TO A NY PRODUCTS HEREIN TO IM PROVE
R ELIABILITY, FUNCT I O N, OR DESIGN . FAIRCHILD DOE S NOT ASSUME AN Y LIABI LIT Y ARISING O UT O F THE APPLICATIO N OR U SE OF ANY PR O DU CT
O R CIRC UIT DESCRIBED HEREIN; NEI THER DOE S IT CON VEY ANY LICENSE UNDER IT S P AT E NT RIGHT S , NO R THE RI GHT S OF OT HERS. T HE S E
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAI RCHILD’S WO RLDWI DE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN,
WHICH COVERS THESE PRODUCTS.
LIFE SUPP ORT PO LIC Y
FAI RCHI LD’S PRODU CTS ARE N O T AUTHORIZ ED FOR USE AS C RIT I CAL C O MPO NENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WIT HOUT THE
EXPRE SS W RIT T E N APPR O VAL OF F AI RC HILD SEMICONDUCTO R COR PORATI O N.
As used he r ei n:
1. Li fe sup por t de vice s or system s a re d evi ces or syst e ms which, (a ) are
intended for surgical implant into the body or (b) support or sustain
life, and (c) whose failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be
reasonably expected to res ult in a significant injury of the user.
2. A critical c omponent in any com ponent of a lif e s upport, dev ic e, or
system whose failure to perform can be reasonably expected to
cause the failure of the life support devic e or system , or to affect its
safety or effectiveness.
ANTI - CO U NTER FE I TIN G POLI C Y
Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our ex t er n al websi t e, w ww.fa ir c hilds em i.c om ,
under Sales Support.
Counter feiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing c ounterfeiting of their par ts.
Customers who inadvertently purchase counter feit parts experience many problems such as loss of brand reputation, substandard per for mance, failed applications,
and increased c ost of production and manufacturing delays. Fair child is taking str ong measures to protect ourselves and our customers from the proliferation of
counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fair child Distributors who are
li sted by country on our web page cited abo ve. Pr oduc ts customer s buy ei ther from Fairchild di rectly or from Authorized Fair child Distributors are genuine part s,
have fu ll tracea bilit y, m eet Fairchil d's quality st and ards for handlin g an d st orage and provide access t o Fai r c hil d's full r ang e of up-to- date technical and pr oduct
information. Fairchild and our Authorized Distributors will stand behind all war ranties and will appropriately address any warranty issues that may arise. Fairchild will
not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and
encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFI NI TI ONS
Def inition of Te rms
Datasheet
Id enti fication Product Sta tus Def inition
Adv anc e Information Form ative / I n Des ign Datasheet contains t he des ign s pec ifications f or produc t development. Spec ifications may change
in any manner without notice.
Preliminary First Production
Datas heet contains preliminary data; s upplementary dat a will be published at a later date. Fairchild
Sem ic onductor res er ves the right to mak e changes at any t im e without not ic e to impr ove design.
No I dentifi cation Needed Ful l Product ion Data shee t co ntains final spec ifications. F air c hild Sem ic ond uct or re se rves the right to mak e
changes a t any t im e without not ic e to impr ov e the des ign.
Ob so l e te N o t In Pr o d u cti o n D atasheet co ntains specifications on a product that is discontin ued b y F air c hild S em ic onduc tor.
T he datasheet i s for r eferenc e inform ation only. Rev. I43
