CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum Features Ability to synthesize nonstandard frequencies with Fractional-N capability Three clock outputs with Programmable drive strength Glitch-free outputs while frequency switching 8-pin SOIC package Reference Clock input voltage range 2.5 V, 3.0 V, and 3.3 V for CY25483 1.8 V for CY25403 and CY25423 Commercial and Industrial temperature ranges Wide operating output frequency range 3 to 166 MHz Multiple high performance PLLs allow synthesis of unrelated frequencies Programmable Spread Spectrum with Center and Down Spread option and Lexmark and Linear modulation profiles VDD supply voltage options: 2.5 V, 3.0 V, and 3.3 V for CY25403 and CY25483 1.8 V for CY25423 Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies Application specific Programmable EMI reduction using Spread Spectrum for clocks Programmable PLLs for system frequency margin tests Meets critical timing requirements in complex system designs Suitability for PC, consumer, portable, and networking applications Capable of Zero PPM frequency synthesis error Uninterrupted system operation during clock frequency switch Application compatibility in standard and low power systems Three fully integrated phase locked loops (PLLs) Input frequency range External crystal: 8 to 48 MHz External reference: 8 to 166 MHz clock Benefits Selectable output clock voltages independent of VDD supply: 2.5 V, 3.0 V, and 3.3 V for CY25403 and CY25483 1.8 V for CY25423 Frequency Select feature with option to select four different frequencies Power Down, Output Enable, and SS ON/OFF controls Low jitter, high accuracy outputs Block Diagram Crossbar Switch XIN/ EXCLKIN XOUT OSC PLL1 Dividers and MUX and FS0 FS1 CLK1 (SS) Output PLL 2 (SS) Control CLK2 (No SS) Drive Strength Logic Control PLL3 (SS) CLK3 (SS) SSON PD#/OE Cypress Semiconductor Corporation Document #: 001-12564 Rev. *E * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised June 02, 2010 [+] Feedback CY25403/CY25423/CY25483 Table 1. Device Selector Guide Device Crystal Input EXCKLKIN Input VDD CY25403 Yes 1.8 V LVCMOS 2.5 V, 3.0 V, 3.3 V CY25483 No 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V CY25423 Yes 1.8 V LVCMOS 1.8 V Figure 1. Pin Diagram - CY25403 8-Pin SOIC XIN/ EXCLKIN 1 VDD 2 CLK1 CLK2/FS0 8 XOUT 7 GND 3 6 CLK3/SSON 4 5 PD#/OE/FS1 CY25403 Table 2. Pin Definition - CY25403 (2.5 V, 3.0 V, or 3.3 V Supply) Pin Number Name IO Description 1 XIN/EXCLKIN Input Crystal Input or 1.8 V External Clock Input 2 VDD Power Power Supply: 2.5 V, 3.0 V, or 3.3 V 3 CLK1 Output Programmable Clock Output with Spread Spectrum 4 CLK2/FS0 Output/Input Multifunction Programmable pin: Programmable Clock Output with no Spread Spectrum or Frequency Select pin 5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin 6 CLK3/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin 7 GND Power Power Supply Ground 8 XOUT Output Crystal Output Document #: 001-12564 Rev. *E Page 2 of 12 [+] Feedback CY25403/CY25423/CY25483 Figure 2. Pin Diagram - CY25483 8-Pin SOIC 8 DNU 7 GND 3 6 CLK3/SSON 4 5 PD#/OE/FS1 EXCLKIN 1 VDD 2 CLK1 CLK2/FS0 CY25483 Table 3. Pin Definition - CY25483 (2.5 V, 3.0 V, or 3.3 V Supply) Pin Number 1 Name EXCLKIN IO Description Input 2.5 V, 3.0 V, or 3.3 V External Clock Input 2 VDD Power Power Supply: 2.5 V, 3.0 V, or 3.3 V 3 CLK1 Output Programmable Clock Output with Spread Spectrum 4 CLK2/FS0 Output/Input Multifunction Programmable pin: Programmable Clock Output with no Spread Spectrum or Frequency Select pin 5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin 6 CLK3/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin 7 GND Power Power Supply Ground 8 DNU Output Do not use this pin Figure 3. Pin Diagram - CY25423 8-Pin SOIC XIN/ EXCLKIN 1 VDD 2 CLK1 3 6 CLK3/SSON CLK2/FS0 4 5 PD#/OE/FS1 CY25423 8 XOUT 7 GND Table 4. Pin Definition - CY25423 (1.8 V Supply) Pin Number Name IO Description 1 XIN/EXCLKIN Input Crystal Input or 1.8 V External Clock Input 2 VDD Power Power Supply: 1.8 V 3 CLK1 Output Programmable Clock Output with Spread Spectrum 4 CLK2/FS0 Output/Input Multifunction Programmable pin: Programmable Clock Output with no Spread Spectrum or Frequency Select pin 5 PD#/OE/FS1 Input Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin 6 CLK3/SSON Output/Input Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin 7 GND Power Power Supply Ground 8 XOUT Output Crystal Output Document #: 001-12564 Rev. *E Page 3 of 12 [+] Feedback CY25403/CY25423/CY25483 General Description 3 Configurable PLLs The CY25403, CY25423, and CY25483 have three programmable PLLs that can be used to generate output frequencies ranging from 3 to 166 MHz. The advantage of having three PLLs is that a single device generates up to three independent frequencies from a single crystal. Input Reference Clocks The input reference clock can be either a crystal or a clock signal, for CY25403 and CY25423 while just a clock signal for CY25483. The input frequency range for crystal (XIN) is 8 MHz to 48 MHz and that for external reference clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the reference clock input for CY25483 is 2.5 V/3.0 V/3.3 V while that for CY25403 and CY25423 is 1.8 V. This gives user an option for this device to be compatible for different input clock voltage levels in the system. VDD Power Supply Options select inputs, can be used to select among these arbitrarily programmed frequency settings. Each output has programmable output divider options. Glitch-Free Frequency Switch When the frequency select pin, FS(1:0) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is being switched. PD#/OE Mode Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to operate as either frequency select (FS1), power down (PD#) or output enable (OE) mode. PD# is a low-true input. If activated it shuts off the entire chip, resulting in minimum power consumption for the device. Setting this signal high brings the device in the operational mode with default register settings. These devices have programmable power supply options. The CY25403/CY25483 is a high voltage part that can be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while CY25423 is a low voltage part that can operate at 1.8 V. When this pin is programmed as Output Enable (OE), clock outputs can be enabled or disabled using OE (pin 5). Individual clock outputs can be programmed to be sensitive to this OE pin. Output Source Selection The DC drive strength of the individual clock output can be programmed for different values. Table 5 shows the typical rise and fall times for different drive strength settings. These devices have programmable input sources for each of its clock outputs. There are four available clock sources and these clock sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3. Output clock source selection is done by using four out of four crossbar switch. Thus, any one of these four available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to three independent clock outputs. Spread Spectrum Control Two of the three PLLs (PLL2 and PLL3) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK3/SSON). It can be programmed to either center spread range from 0.125% to 2.50% or down spread range from -0.25% to -5.0% with Lexmark or Linear profile. Frequency Select Output Drive Strength Table 5. Output Drive Strength Output Drive Strength Rise/Fall Time (ns) (Typical Value) Low 6.8 Mid Low 3.4 Mid High 2.0 High 1.0 Generic Configuration and Custom Frequency There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The device, CY25403, CY25423, and CY25483 can be custom programmed to any desired frequencies and listed features. For customer specific programming, please contact local Cypress Field Application Engineer (FAE) or sales representative. Each PLL can be programmed for up to four different frequencies. There are two multifunction programmable pins, CLK2/FS0 and PD#/OE/FS1 which if programmed as frequency Document #: 001-12564 Rev. *E Page 4 of 12 [+] Feedback CY25403/CY25423/CY25483 Absolute Maximum Conditions Parameter Description Condition VDD Supply Voltage for CY25403/CY25483 VDD Supply Voltage for CY25423 VIN Input Voltage for CY25403/CY25483 VIN TS Min Max Unit -0.5 4.5 V -0.5 2.6 V Relative to VSS -0.5 VDD+0.5 V Input Voltage for CY25423 Relative to VSS -0.5 2.2 V Temperature, Storage Non Functional -65 +150 C 2000 ESDHBM ESD Protection (Human Body Model) JEDEC EIA/JESD22-A114-E UL-94 Flammability Rating V-0 at 1/8 in. MSL Moisture Sensitivity Level SOIC package Volts 10 ppm Max Unit 3 Recommended Operating Conditions Parameter Description Min Typ VDD VDD Operating Voltage for CY25403 2.25 - 3.60 V VDD VDD Operating Voltage for CY25423 1.65 1.8 1.95 V TAC Commercial Ambient Temperature TAI Industrial Ambient Temperature CLOAD Maximum Load Capacitance tPU Power up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Document #: 001-12564 Rev. *E 0 - +70 C -40 -- +85 C - - 15 pF 0.05 - 500 ms Page 5 of 12 [+] Feedback CY25403/CY25423/CY25483 DC Electrical Specifications Parameter VOL Description Output Low Voltage Conditions IOL = 2 mA, drive strength = [00] Min Typ Max Unit - - 0.4 V VDD - 0.4 - - V IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] Output High Voltage VOH IOH = -2 mA, drive strength = [00] IOH = -3 mA, drive strength = [01] IOH = -7 mA, drive strength = [10] IOH = -12 mA, drive strength = [11] VIL1 Input Low Voltage of PD#/OE, FS0, FS1 and SSON - - 0.2*VDD V VIL2 Input Low Voltage of EXCLKIN - - 0.18 V VIH1 Input High Voltage of PD#/OE, FS0, FS1 and SSON 0.8*VDD - - V VIH2 Input High Voltage of EXCLKIN for CY25403/CY25423 1.62 - 2.2 V VIH3 Input High Voltage of EXCLKIN for CY25483 0.8*VDD - - V IIL Input Low Current, PD#/OE/FS1 VIN = 0V - - 10 A IIH Input High Current, PD#/OE/FS1 VIN = VDD - - 10 A IILDN Input Low Current, SSON and FS0 pins VIN = 0V (Internal pull down resistor = 160k typ.) - - 10 A IIHDN Input High Current, SSON and FS0 pins 14 - 36 A RDN Pull Down Resistor of CLK1, CLK2/FS0 Output clocks in off state by setting and CLK3/SSON pins PD# = Low 100 160 250 k IDD[1, 2] Supply Current for CY25423 IDDS [1] CIN[1] VIN = VDD (Internal pull down resistor = 160k typ.) PD# = High, No load - 20 - mA Supply Current for CY25403/CY25483 PD# = High, No load - 22 - mA Standby Current PD# = Low - 3 - A Input Capacitance SSON, PD#/OE/FS1 and FS0 pins - - 7 pF 1. Guaranteed by design but not 100% tested. 2. Configuration dependent. Document #: 001-12564 Rev. *E Page 6 of 12 [+] Feedback CY25403/CY25423/CY25483 AC Electrical Specifications Parameter Description Conditions Min Typ Max Unit FIN (crystal) Crystal Frequency, XIN 8 - 48 MHz FIN (clock) Input Clock Frequency (EXCLKIN) 8 - 166 MHz FCLK Output Clock Frequency 3 - 166 MHz DC Output Duty Cycle, All Clocks except Duty Cycle is defined in Figure 5 on page 8; t1/t2, Ref Out measured at 50% of VDD 45 50 55 % DC Ref Out Duty Cycle Ref In Min 45%, Max 55% 40 - 60 % TRF1[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CL = 15 pF, drive strength [00] - 6.8 - ns TRF2[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CL = 15 pF, drive strength [01] - 3.4 - ns TRF3[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CL = 15 pF, drive strength [10] - 2.0 - ns TRF4[1] Output Rise/Fall Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CL = 15 pF, drive strength [11] - 1.0 - ns TCCJ[1,2] Cycle-to-cycle Jitter (peak) Configuration dependent. See Table 6 - 100 - ps TLOCK[1] PLL Lock Time Measured from 90% of the applied power supply level - 1 3 ms 1. Guaranteed by design but not 100% tested. 2. Configuration dependent. Table 6. Configuration Example for C-C Jitter CLK1 Output CLK2 Output CLK3 Output Ref. Frequency (MHz) Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) 14.3181 8.0 134 166 103 48 92 19.2 74.25 99 166 94 8 91 27 48 67 27 109 166 103 48 48 93 27 123 166 137 Recommended Crystal Specification for SMD Package Parameter Description Fmin Minimum Frequency Fmax R1 Range 1 Range 2 Range 3 Unit 8 14 28 MHz Maximum Frequency 14 28 48 MHz Motional Resistance (ESR) 135 50 30 C0 Shunt Capacitance 4 4 2 pF CL Parallel Load Capacitance 18 14 12 pF DL(max) Maximum Crystal Drive Level 300 300 300 W Recommended Crystal Specification for Thru-Hole Package Parameter Fmin Description Minimum Frequency Range 1 Range 2 Range 3 8 14 Unit 24 MHz Fmax Maximum Frequency 14 24 32 MHz R1 Motional Resistance (ESR) 90 50 30 C0 Shunt Capacitance 7 7 7 pF CL Parallel Load Capacitance 18 12 12 pF DL(max) Maximum Crystal Drive Level 1000 1000 1000 W Document #: 001-12564 Rev. *E Page 7 of 12 [+] Feedback CY25403/CY25423/CY25483 Test and Measurement Setup Figure 4. Test and Measurement Setup V DD 0.1 F Outputs C LOAD DUT GND Voltage and Timing Definitions Figure 5. Duty Cycle Definition t1 t2 V DD 50% of VDD Clock Output 0V Figure 6. Rise Time = TRF, Fall Time = TRF T RF T RF V DD 80% of V DD Clock Output Document #: 001-12564 Rev. *E 20% of VDD 0V Page 8 of 12 [+] Feedback CY25403/CY25423/CY25483 Ordering Information Part Number Type Package Supply Voltage Production Flow Pb-free CY25403SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C CY25403SXCT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C CY25423SXC Field Programmable 8-pin SOIC 1.8 V Commercial, 0C to 70C Commercial, 0C to 70C CY25423SXCT Field Programmable 8-pin SOIC -Tape and Reel 1.8 V CY25483SXC Field Programmable 8-pin SOIC CY25483SXCT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C CY25403SXI Field Programmable 8-pin SOIC CY25403SXIT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C CY25423SXI Field Programmable 8-pin SOIC CY25423SXIT CY25483SXI CY25483SXIT 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C 1.8 V Industrial, -40C to +85C Field Programmable 8-pin SOIC -Tape and Reel 1.8 V Industrial, -40C to +85C Field Programmable 8-pin SOIC Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C Programmer CY3675-CLKMAKER1 Programming Kit CY3675-SOIC8A Socket Adapter Board, for programming CY25402, CY25403, CY25422, CY25423, CY25482, and CY25483 Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for more information Possible Configurations Part Number[1] Type VDD(V) Production Flow Pb-free CY25403SXC-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C CY25403SXC-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C CY25403SXI-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C CY25403SXI-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C CY25423SXC-xxx 8-pin SOIC Supply Voltage: 1.8 V Commercial, 0C to 70C CY25423SXC-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 1.8 V Commercial, 0C to 70C CY25423SXI-xxx 8-pin SOIC Supply Voltage: 1.8 V Industrial, -40C to +85C CY25423SXI-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 1.8 V Industrial, -40C to +85C CY25483SXC-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C CY25483SXC-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0C to 70C CY25483SXI-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C CY25483SXI-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, -40C to +85C 1. xxx indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative. Document #: 001-12564 Rev. *E Page 9 of 12 [+] Feedback CY25403/CY25423/CY25483 Ordering Code Definitions CY254x3 SX C/I - xxx T Package Type: (T = Tape and Reel) Customer specific identification code Temperature code (C=Commercial or I=Industrial) 8-Pin SOIC package Marketing Code: CY25403/23/83 = Device Number Package Drawing and Dimensions Figure 7. 8-Pin (150-Mil) SOIC S8 51-85066 *D Document #: 001-12564 Rev. *E Page 10 of 12 [+] Feedback CY25403/CY25423/CY25483 Acronyms Acronym Description DL drive level DNU do not use DUT device under test EMI electromagnetic interference ESD electrostatic discharge FAE field application engineer FS frequency select JEDEC EIA joint electron devices engineering council electronic industries alliance LVCMOS low voltage complemetary metal oxide semiconductor OE output enable OSC oscillator PD power down PLL phase locked loop PPM parts per million SS spread spectrum SSC spread spectrum clock SSON spread spectrum on Document #: 001-12564 Rev. *E Page 11 of 12 [+] Feedback CY25403/CY25423/CY25483 Document History Page Document Title: CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12564 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 690296 See ECN RGL New Data Sheet *A 815788 See ECN RGL Minor Change: To post on web *B 1428744 See ECN *C 2748211 08/10/09 TSAI Posting to external web. *D 2899300 03/25/10 CXQ Updated Ordering Information. Added note regarding Possible Configurations in Ordering Information section. Added Possible Configurations table for "xxx' parts. Updated Package Drawing and Dimensions *E 2898568 06/02/10 CXQ Updated Ordering Information and template. RGL/AESA Changed data sheet format to match generic part, CY2544/46 Added new device and specification for high ref. input voltage part, CY25483 Removed Preliminary from Title page Replaced CLK2 with REFOUT Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC(R) Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-12564 Rev. *E Revised June 02, 2010 Page 12 of 12 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback