UXD20K
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Features
• Wide Operating Range: DC-26.5
GHz
• Low SSB Phase Noise: -153 dBc @
10 kHz
• Large Output Swings: 750 mV ppk/
side
• Single-Ended and/or Differential
Operation
• Low power consumption: 430 mW
• 4x4 ceramic leadless QFN package
• 3 Dividers-in-One with Pass Through
• DC-7 GHz Limit Amp
Description
The UXD20K is a low noise DC to 26.5
GHz programmable prescaler featuring
either divide by-1, divide-by-2,
divide-by-4, or divide-by-8 division ra-
tios. In the divide by 1 mode the UX-
D20K is also a limit amplifier. The
device features differential inputs and
outputs, adjustable output swing and
high input sensitivity. The control
inputs are CMOS and LVTTL compat-
ible. The UXD20K is packaged in a 24
pin, 4 mm x 4 mm ceramic leadless
surface mount package.
Key Specifications (T = 25˚C):
Vee = -3.3 V, Iee = 130 mA, Zo=50 Ω
Application
The UXD20K can be used as a general
purpose, fixed modulus prescaler in high
frequency PLLs. The low phase noise of the
divider makes it ideal for generating low jitter,
synchronous clocks in telecom applications.
Pad Metallization
The QFN package pad metallization consists
of a 500-1000 micro-inch Sn63 automated
solder dip process.
Parameter
Description
Min
Typ
Max
Fin (GHz)
Input Frequency
DC*
-
26.5
Pin (dBm)
Input Power
-10
0
10
Pout (dBm)
Output Power
-5
5
-
£ (dBc/Hz)
SSB Phase Noise @10 kHz Offset
-
-153
-
PDC (mW)
DC Power Dissipation
-
430
-
θjc (ºC/W)
Junction-Case Thermal Resistance
-
52
-
* Low frequency limit dependent on input edge speed
DC-26.5 GHz Programmable
1,2,4,8 Binary Prescaler
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Frequency Divider Application
Min/Max Single-Ended Input Power
Input Sensitivity Window
UXD20K: SSB Phase Noise for Binary
Divide-by-8 Configuration
Input Freq = 7.8 GHz Gain S21
Binary Divide-by-2 Output Power,
3rd Harmonic & Input Feedthru
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Limit Amplifier Application
S-parameters S21 Pout vs. Frequency
S-parameters S11, S22 S-parameters S12
Group Delay vs. Frequency Binary Divide-by-1 Configuration
Input Freq = 5 GHz, 150mV/div
-1V
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Table 1: Pin Description
Functional Block Diagram
Port Name
Description
Notes
INP
Prescaler Input, Positive Terminal
CML signal levels
INN
Prescaler Input, Negative Terminal
CML signal levels
OUTP
Prescaler Output, Positive Terminal
Requires DC return path to VCC
OUTN
Prescaler Output, Negative Terminal
Requires DC return path to VCC
VADJ
Output Amplitude Control
Tie to VCC via resistor, refer to text for value
SelA
Divider Select Control Line
Divider Select, See Table 1, defaults to logic 0
SelB
Divider Select Control Line
Divider Select, See Table 1, defaults to logic 0
Temp
Temperature Diode
Optional Temperature diode, refer to text
VCC
RF & DC Ground
-
VEE
-3.3 V @ 130 mA
Negative Supply Voltage
Table 2: Divider Mode Select Logic Simplified Control Logic Schematic
SelA
SelB
Mode
DC Current
0
0
Divide-by-1
105 mA
1
0
Divide-by-8
130 mA
0
1
Divide-by-4
125 mA
1
1
Divide-by-2
120 mA
Table 3: Control Voltages
State
Bias Condition
Comment
Low (logic 0)
VEE @ 0 mA
Default condition (in-
ternally pulled low)
High (logic 1)
VCC @ 1 mA
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Divider Mode: Application Notes
The UXD20K supports four division ratios controlled by two select lines which are compatible with
CMOS/LVTTL signaling levels. Table 1 lists the four states for the given logic levels on the SelA and
SelB select lines. For any of the four modes, circuitry which is not used is automatically powered
down to reduce power consumption.
Divider Outputs:
The equivalent circuit of the divider outputs is shown on the below. The outputs require a DC return
path capable of handling ~35 mA per side. If DC coupling is employed, the DC resistance of the
receiving circuits should be ~50 Ω (or less) to VCC to prevent excessive common mode voltage from
saturating the prescaler outputs. If AC coupling is used, the perfect embodiment is shown in figure 2.
The discrete R/L/C elements should be resonance free up to the maximum frequency of operation for
broadband applications.
The output amplitude can be adjusted over a 1.5:1 range by one of the two methods The Vadj pin
voltage can be set to VCC for maximum amplituded or VCC-1.3 V for an amplitude ~2/3 the max
swing. Voltages between these two values will produce a linear change in output swing. Alternatively,
users can use a 1k potentiometer or fixed resistor tied between Vadj and VCC. Resistor values
approaching 0 ohms will lead to the maximum swing, while values approaching 1k will lead to the
minimum output swing. Users who only need/want the maximum swing should simply tie Vadj to VCC.
Equivalent Circuit of Output Buffer Recommended Circuit for AC Coupled Outputs
Low Frequency Operation:
Low frequency operation is limited by external bypass capacitors and the slew rate of the input clock.
The next paragraph shows the calculations for the bypass capacitors. If DC coupled, the device
operates down to DC for square-wave inputs. Sine-wave inputs are limited to ~50 MHz due
to the 10 dBm max input power limitation.
The values of the coupling capacitors for the high-speed inputs and outputs (I/O’s) are determined
by the lowest frequency the IC will be operated at.
C>> 1
2•π•50Ω•flowest
For example to use the device below 30 kHz, coupling capacitors should be larger than 0.1uF.
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Temperature Diode:
An optional on chip temperature diode is provided for users
interested in evaluating the IC’s temperature. A single
resistor to VCC establishes a nominal current thru the
diode. The voltage developed across the temperature
pin (pin 8) referenced to VEE (pin 9) can then be used
to indicate the surface temperature of the IC. The plot below
was obtained by forcing a fixed current of 120uA thru the
diode for an unbiased device at multiple temperatures and
fitting a line to the data to allow extrapolation over a range
of temperatures.
Diode Voltage vs Temp
Diode Voltage vs Temp, 1d = 120 µA
T=(0.84-Vd)/0.00133
Package Heatsink:
The package backside provides the primary heat conduction path and should be attached to a
good heatsink on the PC board to maximize performance. User PC boards should maximize the
contact area to the package paddle and contain an array of vias to aid thermal conduction to either
a backside heatsink or internal copper planes.
IC Assembly:
The device is designed to operate with either single-ended or differential inputs. Figures 4, 5 & 6
show the IC assembly diagrams for positive and negative supply voltages. In either case the supply
should be capacitively bypassed to the ground to provide a good AC ground over the frequency range
of interest. The backside of the chip should be connected to a good thermal heat sink.
All RF I/O’s are connected to VCC through on-chip termination resistors. This implies that when VCC
is not DC grounded (as in the case of positive supply), the RF I/O’s should be AC coupled through
series capacitors unless the connecting circuit can generate the correct levels through level shifting.
CML Logic Levels for DC Coupling (T = 25˚C):
Assuming 50 Ω Terminations at Inputs and Outputs
Parameter
Minimum
Typical
Maximum
Input
Differential
{
Logic Inputhigh
Vcc
Vcc
Vcc
Logic Inputlow
Vcc - 0.05 V
Vcc - 0.3 V
Vcc - 1 V
Single
{
Logic Inputhigh
Vcc + 0.05 V
Vcc + 0.3 V
Vcc + 1 V
Logic Inputlow
Vcc - 0.05 V
Vcc - 0.3 V
Vcc - 1 V
Output
Differential & Single
{
Logic Inputhigh
Vcc - 0.9 V
Vcc – 0.6 V
Vcc – 0.5 V
Logic Inputlow
Vcc – 1.3 V
Vcc – 1.6 V
Vcc – 1.7 V
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Differential vs. Single-Ended:
The UXD20K is fully differential to maximize signal-to-noise ratios for high-speed operation. High
speed inputs are terminated to VCC with on-chip resistors (refer to functional block diagram for
specific resistor values). The maximum DC voltage on any terminal must be limited to V max
to prevent damaging the termination resistors with excessive current. Regardless of bias conditions,
the following equation should be satisfied when driving the inputs differentially:
I Vdm/2 + Vcm I < Vcc ≥ Vmax
where Vdm is the differential input signal and Vcm is the common-mode voltage.
In addition to the maximum input signal levels, single-ended operation imposes additional
restrictions: the average DC value of the waveform at IC should be equal to VCC for single-ended
operation. In practice, this is easily achieved with a single capacitor on the input acting as a DC block.
The value of the capacitor should be large enough to pass the lowest frequencies of interest.
Use the positive terminals for single-ended operation while terminating the negative terminal to VCC.
Note that a potential oscillation mechanism exists if both inputs are static and have identical DC
voltages; a small DC offset on either input is sufficient to prevent possible oscillations. Tying unused
inputs directly to VCC shorts out the internal 50 Ω bias resistor, imposing a DC offset sufficient to
prevent oscillations. Driving the differential inputs with DC blocks, or driving the single-ended inputs
without terminating unused inputs, is not recommended without taking additional steps to eliminate
the potential oscillation issues.
Positive Supply (AC Coupling)
Biasing recommendations for positive supply with AC coupling applications
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Negative Supply (DC Coupling)
Biasing recommendations for negative supply with DC coupling applications
Negative Supply (AC Coupling)
Biasing recommendations for negative supply with AC coupling applications
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UXD20K Physical Characteristics
Pkg size:
4.00 x 4.00 mm
Pkg size tolerance:
+/- 0.25 mm
Pkg thickness:
1.05 +/- 0.1 mm
Pad dimensions:
0.30 x 0.35 mm
Center paddle:
2.5 x 2.5 mm
JEDEC designator:
MO-220
Bottom View
Table 4: UXD20K Pin Definition
Function
Notes
1,3,5,6,7,13,15,17,19,20 (Vcc)
RF and DC Ground
0 V (+3.3 V when using positive supply)
9,23,24 (Vee)
Negative Supply Voltage
Nominally -3.3 V (0 V when using positive supply)
2 (INP)
Divider Input
Positive Terminal of differential output
4 (INN)
Divider Input
Negative Terminal of differential output
8 (Temp)
Temperature Diode
IC Surface temperature, Refer to text
12,11,10 (NC)
No Connect
-
14 (VADJ)
Output Amplitude Control
Tie to VCC for max swing. Refer to text
16 (OUTP)
Divider Output
Positive Terminal of differential output
18 (OUTN)
Divider Output
Negative Terminal of differential output
21 (SelB)
Divider Mode
Divider Select Line, Refer to Table 1
22 (SelA)
Divider Mode
Divider Select Line, Refer to Table 1
Paddle
Package Paddle
Tie to heatsink, Refer to text. Tie to +3.3 V for
positive supply and ground for negative supply.
Table 5: Absolute Maximum Ratings
The information contained herein is believed to be accurate
and is provided “AS IS, WHERE IS”, with all faults and the entire risk
associated with its use being entirely with the user. Microsemi makes
no representation with respect to the merchantability of the products
or their suitability or fitness for any particular purpose or use.
The information contained herein or any use of such information does
not grant, explicitly or implicitly, to any party any patent rights, licenses,
or any other intellectual property rights, whether with regard to such
information itself or anything described by such information.
19 20 21 22 23 24
18
17
16
15
14
13
12 11 10 9 8
7
1
2
3
4
5
6
Parameter
Value
Unit
Supply Voltage (VCC-VEE)
4
V
RF Input Power (INP, INN)
10
dBm
Operating Temperature
-40 to 85
ºC
Storage Temperature
-85 to 125
ºC
Junction Temperature
125
ºC
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Information contained in this document is proprietary to Microsem. This document may not be modified in any way without the express
written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to
change the configuration and performance of the product and to discontinue product at any time.
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