MB90F949PF - Fujitsu Limited

DS07-13741-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90945 Series

MB90F946A/947A/F947/F947A/F949/F949A/

V390HA/V390HB

■DESCRIPTION

The MB90945 series with one FULL-CAN* interface and FLASH ROM is especially designed for automotive HV AC

applications. Its main feature is the on board CAN* Interface, which conform to V2.0 Part A and Part B, while

supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN*

approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memor y

up to 384 K bytes. An internal voltage booster removes the necessity for a second prog ramming voltage.

An on board voltage regulator provides 3 V to the inter nal MCU core. This creates a major advantage in ter ms

of EMI and power consumption.

The internal PLL clock freque ncy multiplier provides an internal 42 ns instruction cycle time from an external

4 MHz clock.

The unit features a 4-chann el Output Comp are Unit a nd a 6-chann el Input Capt ure Unit with two sepa ra te 16-bit

free running timers. Up to 3 UARTs, one Serial I/O and one I2C constitute additional functionality for communication

purposes.

* : Controller Area Network (CAN) - License of Robert Bosch GmbH

■PACKAGE

100-pin Plastic QFP

(FPT-100P-M06)

MB90945 Series

■FEATURES

• 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instr. cycle time)

• New 0.35 µm CMOS Process Technology

• Internal volta ge regulator supports 3 V MCU core, offering low EMI and low power consumption figures

• One FULL-CAN interface; confor ming to Version 2.0 Par t A and Par t B, flexible message buffering (mailbox

and FIFO buffering can be mixed)

• Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)

•EI

2OS - Automatic transfer function independant of CPU; 16 ch anne ls of intellig e nt I/O Services

• 18-bit Time-b ase counter

• Watchdog Timer

• 1 full duplex UART; support 10.4 KBaud (USA standard)

• up to 2 full duplex UARTs (LIN/SCI/SPI)

• 1 Serial I/O (SPI)

•1 I

2C interface

• A/D Converter : 15 channels analog inputs (Resolution 10-bit or 8-bit)

• 16-bit reload timer × 1channel

• ICU (Input capture) 16-bit × 6 channels

• OCU (Output compare) 16-bit × 4 channels

• 16-bit free running timer × 2 channels (FRT0 : IC U 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5)

• 8/16-bit Programmable Pulse Generator 6 channels × 8/16-bit

• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different

addressing modes; barrel shift; variety of pointers)

• 4-byte instruction execution queue

• signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available

• Program Patch Function (3 add re ss ma tc h re gisters)

• Fast Interrupt processing

• Low Power Consumption mode

Sleep mode

Timebase timer mode

Stop mode

CPU inter mittent mode

• Automotive input levels

• Package : 100-pin plastic QFP

MB90945 Series

■PRODUCT LINEUP

(Continued)

Part Number

Parameter MB90947A MB90F946A MB90F947, MB90F947A

MB90F949, MB90F949A MB90V390HA

MB90V390HB

CPU F2MC-16LX CPU

System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/ 2 when PLL stops)

Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL clock

multiplied by 6)

ROM ROM memory

128 Kbytes

Boot-block

Flash memory

384 Kbytes

Boot-block

Flash memory

256 Kbytes: MB90F949

MB90F949A

128 Kbytes: MB90F947

MB90F947A

External

RAM 6 Kbytes 16 Kbytes

12 Kbytes: MB90F949

MB90F949A

6 Kbytes: MB90F947

MB90F947A

30 Kbytes

Emulator-specific

power supply*1 ⎯Yes

Technology

0.35 µm CMOS with

on-chip voltage

regulator for internal

power supply

0.35 µm CMOS with on-chip voltage regulator

for internal power su pp ly + Flash memory

with on-chip charge pump for programming

voltage

0.35 µm CMOS with

on-chip voltage

regulator for inte rn a l

power supply

Operating

voltage range

3.5 V to 5.5 V : other than conditions listed below

4.0 V to 5.5 V : when writing to Flash

4.5 V to 5.5 V : if A/D Converter is used 5 V ± 10%

Temperature range −40 °C to +105 °C⎯

Package QFP-100P PGA-299C

UART

1 channel 2 channels

Full duplex double buffer

Supports asynchronous/synchronous (with start/stop bit) transfer

Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous)

500 K/1 M/2 Mbps (synchronous) at System clock = 20 MHz

UART

(LIN/SCI/SPI) 1 channel 2 channels 1 channel 2 channels

Serial I/O

1 channel

Transfer can be started from MSB or LSB

Supports internal clock synchronized transfer and external clock synchronized transfer

Supports positive-edge and negative-edge clock synchronization

Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 20 MHz

I2C (400 Kbps) 1 channel

MB90945 Series

(Continued)

Part Number

Parameter MB90947A MB90F946A MB90F947, MB9 0F947A

MB90F949, MB90F949A MB90V390HA

MB90V390HB

A/D Converter

(15 input channels)

10-bit or 8-bit resolution

Conversion time : Min 4.9 µs includes sa mple time (per one channel, only at certain

machine clock frequencies)

16-bit Reload Timer 1 channel 2 channels

Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)

Supports External Event Count function

16-bit

I/O Timer

(2 channels)

Signals an interrupt when overflowing

Supports Timer Clear when a match with Output Compare (ch0)

Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27

(fsys = System clock freq.)

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3

I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5

16-bit

Input Capture

(6 channels)

Rising edge, falling edge or rising & falling edge sensitive

Six 16-bit Capture registers

Signals an interrupt upon external event

⎯ICU 3/5 inputs are

shared with OCU 6/7

outputs

16-bit

Output Compare

4 channels 8 channels

Signals an inte rrupt when a match with 16-bit I/O Timer

Eight 16-bit comp ar e re gis te rs.

A pair of compare registers can be used to generate an output signal.

⎯ICU 3/5 inputs are

shared with OCU 6/7

outputs

8/16-bit

Programmable

Pulse Generato r

(6 channels)

Supports 8-bit and 16-bit operation modes

Twelve 8-bi t reload counters

Twelve 8-bit reload registers for L pulse width

Twelve 8-bit reload registers for H pulse width

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler plus 8-bit reload counter

Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs (fosc = 5 MHz)

(fsys = System clock frequency, fosc = Oscillation clock frequency)

CAN Interface

1 channel 5 channels

Conforms to CAN Specification Ver sio n 2.0 Part A and B

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID’s

Supports multiple messages

Flexible configuration of acceptance filtering :

Full-bit compare/Full-bit mask/Two partial bit masks

Supports up to 1 Mbps

MB90F947/F949/V390HA: Do not use clock modulation and CAN at the same time

MB90945 Series

(Continued)

Part Number

Parameter MB90947A MB90F946A MB90F947, MB90F947A

MB90F949, MB90F949A MB90V390HA

MB90V390HB

External Interrupt

(8 channels) Can be programmed edge sensitive or level sensitive

Stepping motor

controller ⎯2 channels

Watch Timer ⎯1 channel

Sound gener ato r ⎯1 channel

Machine clock out-

put ⎯2 channels

(non-inverted and in-

verted)

Program patch

function 3 address match registers 5 address match

registers

I/O Ports

Virtually all external pins can be used as general purpose I/O

All push-pull outputs

Bit-wise programmable as input/output or peripheral signal

Automotive input level (P21/RX1, P42/SDA, P43/SCL have CMOS

Schmitt input level)

Port-wise program-

mable as Automotive

(default) or CMOS

Schmitt input level

I/O Ports with 4 mA

CMOS output All ports except P42, P43 All ports except P80,

P81, PA0 to PA7,

P42, P43

I/O Ports with 3 mA

CMOS output P42, P43 P42, P43

I/O Ports with 30 mA

CMOS output with

slewrate control ⎯P80, P81,

PA0 to PA7

Clock Modulator Phase modulation mode

Phase modulation mode Frequen cy an d

phase

modulation mode

MB90F947/F949/V390HA:

Do not use clock modulation and CAN at the

same time

Reduces EMI by modulating the PLL clock

Start-up time at

power-on reset 3 × 216 oscillation cycles (49.152 ms at 4 MHz oscillation) + oscilla-

tion time of oscillator*2

218 oscillation cycles

(65.536 ms at 4 MHz

oscillation) +

oscillation time o f os-

cillator*2

MB90945 Series

(Continued)

*1 : It is setting of Jumper switch SI when Emulation Pod (MB2147) is used.

Please refer to the Emulator hardware manual about details.

*2 : Oscillation time of the oscillator is the time that the amplitude reaches 90%.

*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

*4 : Data is based on reliability tests during process qualification (the value f or TA = + 85 °C is calculated via

the Arrenhius formula from data of accelerated measurements at elevated temperature) .

Part Number

Parameter MB90947A MB90F946A MB90F947, MB90F947A

MB90F949, MB90F949A MB90V390HA

MB90V390HB

Flash

Memory ⎯

Supports automatic programming, Embedded

AlgorithmTM*3

Write/Erase/Erase-Suspend/Resume com-

mands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Data retention time : 20 years*4

Hard-wired re se t vect or ava ilab le in or de r to

point to a fixed boot sector in Flash Memory

(address FFA000H, mode data 00H)

Boot block configura tion

Erase can be performed on each block

Block protection with external programming

voltage

Write and erase at Fmax = 20 MHz

⎯

MB90945 Series

■PIN ASSIGNMENTS

• MB90947A/F946A/F947/F947A/F949/F949A

(TOP VIEW)

(FPT-100P-M06)

B6/SOT4/AN14

AVcc

AVRH

AVRL

AVss

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

Vss

P51/PPG11

P52/PPG12

P53/PPG13

P54/PPG14

PB7/FRCK0

P97/FRCK1

100

P23/INT3

P22/INT2

P21/RX1

P20/TX1

P17

P16

P15/TOT

Vss

Vcc

P14/TIN0

P13

P12

P11/OUT

P10/OUT

P07/OUT

P06/OUT

P05/IN5

P04/IN4

P24/INT4

P25/INT5

P26/INT6

P27/INT7

P30

P31

P32

P33

P34/SOT0

P35/SCK0

P36/SIN0

P37

P44

P45/ADTG

Vcc

Vss

P40

P41

P42/SDA

P43/SCL

P46/INT0

P47/INT1

P50/PPG10

PB0/PPG02/AN8

PB1/PPG03/AN9

B2/PPG04/AN10

B3/PPG05/AN11

PB4/SIN4/AN12

PB5/SCK4/AN13

P03/IN3

P02/IN2

P01/IN1

P00/IN0

P81

P80

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Vss

Vcc

P96

P92

P91

P94/SCK3

P95/SOT3

P93/SIN3

P90

P57/PPG0

P56/PPG0

P55/PPG1

RST

MD0

MD1

MD2

MB90945 Series

• MB90V390HA/V390HB

(TOP VIEW)

(FPT-100P-M06)

As seen with QFP100 probe cable

PB6/SOT4/AN14

AVcc

AVRH

AVRL

AVss

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

Vss

P51/PPG11

P52/PPG12

P53/PPG13

P54/PPG14

PB7/FRCK0/HCLK

97/FRCK1/HCLKX

P23/INT3

P22/INT2

P21/RX1

P20/TX1

P17/SGA

P16/SGO

P15/TOT0

Vss

Vcc

P14/TIN0

P13/OUT5

P12/OUT4

P11/OUT3

P10/OUT2

P07/OUT1

P06/OUT0

P05/IN5/OUT

P04/IN4

100

P24/INT4

P25/INT5

P26/INT6

P27/INT7

P30/RX0

P31/TX0

P32/TIN1

P33/TOT1

P34/SOT0

P35/SCK0

P36/SIN0

P37/SIN1

P44

P45/ADTG

Vcc

Vss

P40/SCK1

P41/SOT1

P42/SDA

P43/SCL

P46/INT0

P47/INT1

P50/PPG10

PB0/PPG02/TX3/AN8

PB1/PPG03/RX3/AN9

B2/PPG04/TX4/AN10

B3/PPG05/RX4/AN11

PB4/SIN4/AN12

PB5/SCK4/AN13

P03/IN3/OUT6

P02/IN2

P01/IN1

P00/IN0

P81

P80

PA7/PWM2M5

PA6/PWM2P5

PA5/PWM1M5

PA4PWM1P5

PA3/PWM2M4

PA2/PWM2P4

PA1/PWM1M4

PA0/PWM1P4

DVss

DVcc

P96/WOT

P92/SOT2

P91/SCK2

P94/SCK3

P95/SOT3

P93/SIN3

P90/SIN2

P57/PPG01/TX

P56/PPG00/RX

P55/PPG15

RST

MD0

MD1

MD2

MB90945 Series

■PIN DESCRIPTION

(Continued)

Pin no. Pin name Circuit type Function

92 X1 APin for oscillation

93 X0 Pin for oscillation

54 RST B Reset input

77 to 82 P00 to P05 DGeneral purpose I /O

IN0 to IN5 Inputs for the Input Captures 0-5

83 to 86 P06, P07

P10, P11 DGeneral purpose I /O

OUT0 to OUT3 Outputs for the Output Compares

87, 88 P12, P13 D General purpose I/O

89 P14 DGeneral purpose I /O

TIN0 TIN0 input for the 16-bit Reload Timer 0

94 P15 DGeneral purpose I /O

TOT0 TOT0 output for the 16-bit Reload Timer 0

95, 96 P16, P17 D General purpose I/O

97 P20 DGeneral purpose I /O

TX1 TX output for CAN Interface 1

98 P21 FGeneral purpose I /O

RX1 RX input for CAN Interface 1

99, 100

1 to 4 P22 to P27 DGeneral purpose I /O

INT2 to INT7 External interrupt inputs for INT2 to INT7

5 to 8 P30 to P33 D General p urpose I/O

9P34 DGeneral purpose I /O

SOT0 SOT output for UART0

10 P35 DGeneral purpose I /O

SCK0 SCK input/output for UART0

11 P36 DGeneral purpose I /O

SIN0 SIN input for UART0

12 P37 D General purpose I/O

13 P44 D General purpose I/O

14 P45 DGeneral purpose I /O

ADTG External trigger input of the A/D Conver ter

18, 19 P40, P41 D General purpose I/O

20 P42 FGeneral purpose I /O

SDA Serial data for I2C interface

MB90945 Series

(Continued)

Pin no. Pin name Circuit type Function

21 P43 FGeneral purpose I /O

SCL Serial clock for I2C interfac e

22, 23 P46, P47 DGeneral purpose I /O

INT0, INT1 External interrupt inputs for INT0, INT1

24 P50 DGeneral purpose I /O

PPG10 Output for the PPG1

25 to 28

PB0 to PB3

General purpose I /O

PPG02 to PPG05 Outputs for th e PPG4, 6, 8, A

AN8 to AN11 Inputs for the A/D Conve r ter

PB4

General purpose I /O

SIN4 SIN input for Serial I/O

AN12 Input for the A/D Converter

PB5

General purpose I /O

SCK4 SCK input/output for Serial I/O

AN13 Input for the A/D Converter

PB6

General purpose I /O

SOT4 SOT output for Serial I/O

AN14 Input for the A/D Converter

36 to 43 P60 to P67 EGeneral purpose I /O

AN0 to AN7 Inputs for the A/D Converter

45 to 48 P51 to P54 DGeneral purpose I /O

PPG11 to PPG14 Outputs for th e PPG3, 5, 7, 9

49 PB7 DGeneral purpose I /O

FRCK0 FRCK0 input for the 16-bit I/O Timer 0

50 P97 DGeneral purpose I /O

FRCK1 FRCK1 input for the 16-bit I/O Timer 1

55 P55 DGeneral purpose I /O

PPG15 Outputs for the PPGB

56, 57 P56, P57 DGeneral purpose I /O

PPG00, PPG01 Outputs for the PPG0, PPG2

58 P90 DGeneral purpose I /O

SIN2 SIN input for UART 2 (LI N/SCI/SPI) (only MB90V390HA,

MB90V390HB and MB90F946A)

59 P93 DGeneral purpose I /O

SIN3 SIN input for UART3 (LIN/SCI/SPI)

MB90945 Series

(Continued)

Pin no. Pin name Circuit type Function

60 P95 DGeneral purpose I /O

SOT3 SOT output for UART3 (LIN/SCI/SPI)

61 P94 DGeneral purpose I /O

SCK3 SCK input/output for UART3 (LIN/SCI/SPI)

62 P91 DGeneral purpose I /O

SCK2 SCK input/output for UART 2 (LIN/SCI/SPI) (only MB90V390HA,

MB90V390HB and MB90F946A)

63 P92 DGeneral purpose I /O

SOT2 SOT output for UART 2 (LIN/SCI/SPI) (only MB90V390HA,

MB90V390HB and MB90F946A)

64 P96 D General purpose I/O

67 to 74 PA0 to PA7 H General purpose I/O. For the EVA device, these pins are high

current outp u ts.

75, 76 P80, P81 H General purpose I/O. For the EVA device, these pins are high

current outp u ts.

32 AVCC ⎯Dedicated power supply pin (5 V) for the A/D converter

33 AVRH ⎯Dedicated pos. refe rence voltage pin for the A/D converter

34 AVRL ⎯Dedicated neg. reference voltage pin for the A/D converter

35 AVss ⎯Dedicated power supply pin (0 V) for the A/D converter

52, 53 MD1, MD0 C These are input pins used to designate the operating mode. They

should be connec te d dir ec tly to V CC or VSS.

51 MD2 G This is an input pin used to designate the operating mode. It

should be connec te d dir ec tly to V CC or VSS.

90 Vcc ⎯These are power su pply (5 V) input pins. For the EVA de vice, pin

65 is the DVCC supply pin for the high current outputs.

Vss ⎯These are power su pply (0 V) input pins. For the EVA de vice, pin

66 is the DVSS supply pin for the high current outputs.

17 C ⎯This is the power supply stabilization capacitor pin. It should be

connected to higher than or equal to 0.1 µF ceramic capacitor.

MB90945 Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

• Oscillation feedback resistor :

1 MΩ approx.

• CMOS Hysteresis input with pull-up

resistor :

50 kΩ approx.

• EVA/ROM device :

CMOS Hysteresis input

• Flash device :

CMOS input.

• CMOS output (4 mA)

• Automotive Hysteresis input

Standby control signal

Pch Nch Clock inp

CMOS Hysteres

VCC

R (pull-up)

CMOS Hysteres

Automotive Hysteres

Pch

Nch

MB90945 Series

(Continued)

Type Circuit Remarks

• CMOS output (4 mA)

• Automotive Hysteresis input

• Analog input

• CMOS output

P42, P43 : 3mA

P21 : 4 mA

• CMOS Hysteresis input

• EVA/ROM device :

CMOS Hysteresis input with pull-

down resistor : 50 kΩ approx.

• Flash device :

CMOS input without pull-down.

• EVA/ROM device :

CMOS high current output (30 m A)

with slewrate control

• Flash device :

CMOS output (4 mA)

• Automotive Hysteresis input

Analog input

Automotive Hysteres

Pch

Nch

Pch

Nch

CMOS Hysteres

Pch

Nch

CMOS Hysteres

R (pull-down)

Automotive Hysteres

Pch

Nch

MB90945 Series

■HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Stabilization of supply voltage

• Treatment of unused pi ns

• Using external clock

• Power supply pins (VCC/VSS)

• Pull-up/pull-down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter if A/D Converter is unused.

• Caution on Operations during PLL Clock Mode

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the follo wing conditions :

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC and VSS.

• The AVCC power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

In using the devices, take sufficient care to avoid exceeding maximum ratings.

F or the same reason, also be careful no t to let the analog power -supply volta ge (A VCC, AVRH) e xceed the digital

power-supply voltage.

2. Stabilization of supply voltage

A sudden change in the supply voltage may cause the de vice to malfunction e ven within the specified VCC supply

voltage opera tion range. Therefore, the VCC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at

commercial freque ncies (50 Hz to 60 Hz) fall belo w 10 % of the standard VCC supply voltage and t he coeffi cient

of fluctuation does not exceed 0.1 V/ms at instantaneous power switching .

3. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefore they must be pulled up or pulled down throug h resistor s. In this case those resistors sho uld

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the abo ve

described connection.

4. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90945 Serie

MB90945 Series

5. Power supply pins (VCC/VSS)

• If there are multiple VCC and VSS pins, from the point o f vie w of de vice design, pins to be of the same pot ential

are connected the inside of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and observe the standa rd f or total output current, be sure to con nect the VCC and VSS pins to t he power sup ply

and ground externally.

• Connect VCC and VSS to the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between

VCC and VSS in the vicinity of VCC and VSS pins of the device.

6. Pull-up/pull-down resistors

The MB90945 series does not support internal pull-up/pull-down resistors option. Use external components

where needed.

7. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and

make sure, to the utmost eff ort, that lines of oscillation circuit not cross the lines of other circuits while you design

a printed circuit.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to tur n on the A/D conver ter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14)

after turning-on the digital power supply (VCC) .

Turn-off the digital power after tur ning off the A/D conver ter supply and analog inputs. In this case, make sure

that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultane ously

is acceptable) .

9. Connection of Unused Pins of A/D Converter if A/D Converter is unused

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.

10. Notes on During Operation of PLL Clock Mode

If the PLL cloc k mode is selected, the microcontroller attempt to be working with the self-oscillating circuit e ven

when there is no exter nal oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

VCC

VSS

MB90945

Series

MB90945 Series

■BLOCK DIAGRAMS

• MB90F946A

RAM

16 K bytes

Prescaler

Prescaler x2

10-bit A/D

Converter

15 input

channel

IO Timer 0

Input

Capture

6 channels

Output

Compare

4 channels

CAN

Interface 1

External

Interrupt

8/16-bit

PPG

6 channels

F2MC-16LX

CPU

Internal data bus

0, X1

OT0

CK0

IN0

OT2/3

CK2/3

IN2/3

VCC

VSS

N [14:0]

VRH

VRL

DTG

IN5 to IN0

OUT3 to OUT0

RX1

TX1

INT7 to INT0

Flash

384 K bytes

IO Timer 1 FRCK1

FRCK0

PPG15 to PPG1

UART0

UART2/3

(LIN/SCI/

SPI)

I2C

Interface SDA

SCL

TIN0

TOT0

16-bit

Reload Timer

1 channel

Prescaler

OT4

CK4

IN4

Serial I/O

PPG05 to PPG0

Clock

Controller

with Phase

Modulator

MB90945 Series

• MB90947A

RAM

6 K bytes

Prescaler

10-bit A/D

Converter

15 input

channel

IO Timer 0

Input

Capture

6 channels

Output

Compare

4 channels

CAN

Interface 1

External

Interrupt

8/16-bit

PPG

6 channels

F2MC-16LX

CPU

Internal data bus

0, X1

OT0

CK0

IN0

OT3

CK3

IN3

VCC

VSS

N [14:0]

VRH

VRL

DTG

IN5 to IN0

OUT3 to OUT0

RX1

TX1

INT7 to INT0

ROM

128 K bytes

IO Timer 1 FRCK1

FRCK0

PPG15 to PPG1

UART0

UART3

(LIN/SCI/

SPI)

I2C

Interface SDA

SCL

TIN0

TOT0

16-bit

Reload Timer

1 channel

Prescaler

OT4

CK4

IN4

Serial I/O

PPG05 to PPG0

Clock

Controller

with Phase

Modulator

MB90945 Series

• MB90F947, MB90F947A

RAM

6 K bytes

Prescaler

10-bit A/D

Converter

15 input

channel

IO Timer 0

Input

Capture

6 channels

Output

Compare

4 channels

CAN

Interface 1

External

Interrupt

8/16-bit

PPG

6 channels

F2MC-16LX

CPU

Internal data bus

0, X1

OT0

CK0

IN0

OT3

CK3

IN3

VCC

VSS

N14 to AN0

VRH

VRL

DTG

IN5 to IN0

OUT3 to OUT0

RX1

TX1

INT7 to INT0

Flash

128 K bytes

IO Timer 1 FRCK1

FRCK0

PPG15 to PPG1

UART0

UART3

(LIN/SCI/

SPI)

I2C

Interface SDA

SCL

TIN0

TOT0

16-bit

Reload Timer

1 channel

Prescaler

OT4

CK4

IN4

Serial I/O

PPG05 to PPG0

Clock

Controller

with Phase

Modulator

MB90945 Series

• MB90F949, MB90F949A

RAM

12 K bytes

Prescaler

10-bit A/D

Converter

15 input

channel

IO Timer 0

Input

Capture

6 channels

Output

Compare

4 channels

CAN

Interface 1

External

Interrupt

8/16-bit

PPG

6 channels

F2MC-16LX

CPU

Internal data bus

0, X1

OT0

CK0

IN0

OT3

CK3

IN3

VCC

VSS

N14 to AN0

VRH

VRL

DTG

IN5 to IN0

OUT3 to OUT0

RX1

TX1

INT7 to INT0

Flash

256 K bytes

IO Timer 1 FRCK1

FRCK0

PPG15 to PPG1

UART0

UART3

(LIN/SCI/

SPI)

I2C

Interface SDA

SCL

TIN0

TOT0

16-bit

Reload Timer

1 channel

Prescaler

OT4

CK4

IN4

Serial I/O

PPG05 to PPG0

Clock

Controller

with Phase

Modulator

MB90945 Series

■MEMORY MAP

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make th e small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without

using the far specification in the pointer declaration.

For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.

The R OM area in bank FF exceeds 32/48 K bytes, and its entire image cannot be shown in bank 00.

The image between FF4000H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H

and FF3FFFH/FF7FFFH is visible only in bank FF.

MB90947A

FFFFFFH

FF0000H

FEFFFFH

FE0000H

0018FFH

000100H

0000BFH

000000H

ROM (FF bank)

ROM (FE bank)

RAM 6 Kbytes

Peripheral

ROM (Image of

FF bank)

004000H/

003FFFH

003500H

00FFFFH

008000H

: No access

MB90F949

FFFFFFH

FF0000H

FEFFFFH

FE0000H

0030FFH

000100H

0000BFH

000000H

R OM (FF bank)

R OM (FE bank)

RAM 12 Kbytes

Peripheral

ROM (Image of

FF bank)

004000H/

003FFFH

003500H

00FFFFH

008000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

ROM (FD bank)

ROM (FC bank)

FFFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

008000H

0070FFH

003FFFH

003500H

0030FFH

000100H

0000BFH

000000H

MB90V390HA

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

Peripheral

RAM 12 Kbytes

Peripheral

R OM (FB bank)

FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

F90000HROM (F9 bank)

ROM (FA bank)

00FFFFH

004100H

RAM 12

Kbytes

R OM (Image of

FF bank)

8017FFH

800000HRAM 6 Kbytes

MB90F947 MB90F949A

MB90F947A

FFFFFFH

FF0000H

FEFFFFH

FE0000H

0030FFH

000100H

0000BFH

000000H

R OM (FF bank)

ROM (FE bank)

RAM 12 Kbytes

Peripheral

ROM (Image of

FF bank)

008000H

003FFFH

003500H

00FFFFH

FDFFFFH

FD0000H

FBFFFFH

FB0000H

ROM (FD bank)

ROM (FA bank)

MB90F946A

ROM (FB bank)

ROM (F9 bank)

FAFFFFH

FA0000H

F9FFFFH

F90000H

RAM 4 Kbytes

004100H

0050FFH

MB90V390HB

MB90945 Series

■I/O MAP

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

00HPort 0 data register PDR0 R/W Port 0 XXXXXXXX

01HPort 1 data register PDR1 R/W Port 1 XXXXXXXX

02HPort 2 data register PDR2 R/W Port 2 XXXXXXXX

03HPort 3 data register PDR3 R/W Port 3 XXXXXXXX

04HPort 4 data register PDR4 R/W Port 4 XXXXXXXX

05HPort 5 data register PDR5 R/W Port 5 XXXXXXXX

06HPort 6 data register PDR6 R/W Port 6 XXXXXXXX

07HReserved

08HPort 8 data register PDR8 R/W Port 8 XXXXXXXX

09HPort 9 data register PDR9 R/W Port 9 XXXXXXXX

0AHPort A data register PDRA R/W Port A XXXXXXXX

0BHPort B data register PDRB R/W Port B XXXXXXXX

0CHAnalog Input Enable 0 ADER0 R/W Port 6, A/D 11111111

0DHAnalog Input Enable 1/ ADC Select ADER1 R/W Port B, A/D 01111111

0EHInput Level Select Register

(MB90V390HA/MB90V3 90HB only) ILSR R/W Ports 00000000

0FHInput Level Select Register

(MB90V390HA/MB90V3 90HB only) ILSR R/W Ports 00000000

10HPort 0 direction register DDR0 R/W Port 0 00000000

11HPort 1 direction register DDR1 R/W Port 1 00000000

12HPort 2 direction register DDR2 R/W Port 2 00000000

13HPort 3 direction register DDR3 R/W Port 3 00000000

14HPort 4 direction register DDR4 R/W Port 4 00000000

15HPort 5 direction register DDR5 R/W Port 5 00000000

16HPort 6 direction register DDR6 R/W Port 6 00000000

17HReserved

18HPort 8 direction register DDR8 R/W Port 8 XXXXXX00

19HPort 9 direction register DDR9 R/W Port 9 00000000

1AHPort A direction register DDRA R/W Port A 00000000

1BHPort B direction register DDRB R/W Port B 00000000

1CH to 1FHReserved

MB90945 Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

20HSerial Mode Control 0 UMC0 R/W

UART0

00000100

21HStatus 0 USR0 R/W 00010000

22HInput/Out pu t Dat a 0 UIDR0/

UODR0 R/W XXXXXXXX

23HRate and Data 0 URD0 R/W 0000000X

24H to 2BHReserved

2CHSerial Mode Control 4 SMCS4 R/W

Serial I/O

Interface

XXXX0000

2DHSerial Mode Control 4 SMCS4 R/W 00000010

2EHSerial Data 4 SDR4 R/W XXXXXXXX

2FHSerial I/O Prescaler/Edge Selector 4 CDCR4 R/W 0 X 0 X 0000

30HExternal Interr up t Ena ble ENIR R/W

External Interrupt

00000000

31HExternal Interrupt Request EIRR R/W XXXXXXXX

32HExternal Interrupt Level ELVR R/W 00000000

33HExternal Interrupt Level ELVR R/W 00000000

34HA/D Control Status 0 ADCS0 R/W

A/D Converter

00000000

35HA/D Control Status 1 ADCS1 R/W 00000000

36HA/D Data 0 ADCR0 R XXXXXXXX

37HA/D Data 1 ADCR1 R/W 000000XX

38HPPG0 operation mode control register PPGC0 R/W 16-bit Programable

Pulse

Generator 0/1

0X000XX1

39HPPG1 operation mode control register PPGC1 R/W 0X000001

3AHPPG0 and PPG1 clock select register PPG01 R/W 000000XX

3BHReserved

3CHPPG2 operation mode control register PPGC2 R/W 16-bit Programable

Pulse

Generator 2/3

0X000XX1

3DHPPG3 operation mode control register PPGC3 R/W 0X000001

3EHPPG2 and PPG3 clock select register PPG23 R/W 000000XX

3FHReserved

40HPPG4 operation mode control register PPGC4 R/W 16-bit Programable

Pulse

Generator 4/5

0X000XX1

41HPPG5 operation mode control register PPGC5 R/W 0X000001

42HPPG4 and PPG5 clock select register PPG45 R/W 000000XX

43HReserved

44HPPG6 operation mode control register PPGC6 R/W 16-bit Programable

Pulse

Generator 6/7

0X000XX1

45HPPG7 operation mode control register PPGC7 R/W 0X000001

46HPPG6 and PPG7 clock select register PPG67 R/W 000000XX

47HReserved

MB90945 Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

48HPPG8 operation mode control register PPGC8 R/W 16-bit Programable

Pulse

Generator 8/9

0X000XX1

49HPPG9 operation mode control register PPGC9 R/W 0X000001

4AHPPG8 and PPG9 clock sele ct re gis te r PPG89 R/W 000000XX

4BHReserved

4CHPPGA operation mode control register PPGCA R/W 16-bit Programable

Pulse

Generator A/B

0X000XX1

4DHPPGB operation mode control register PPGCB R/W 0X000001

4EHPPGA and PPGB clock select register PPGAB R/W 000000XX

4FHReserved

50HTimer Control Status 0 TMCSR0 R/W 16-bit Reload Timer

000000000

51HTimer Control Status 0 TMCSR0 R/W XXXX0000

52H to 53H Reserved

54HInput Capture Control Status 0/1 ICS01 R/W Input Capture 0/1 00000000

55HInput Capture Control Status 2/3 ICS23 R/W Input Capture 2/3 00000000

56HInput Capture Control Status 4/5 ICS45 R/W Input Capture 4/5 00000000

57HReserved

58HOutput Compare Cont rol Status 0 OCS0 R/W Output Compare 0/1 0000XX00

59HOutput Compare Cont rol Status 1 OCS1 R/W 0XX00000

5AHOutput Compare Control Status 2 OCS2 R/W Output Compare 2/3 0000XX00

5BHOutput Compare Control Status 3 OCS3 R/W 0XX00000

5CH to

6EHReserved

6FHROM Mirror ROMM W ROM Mirror XXXXXXX1

70H to 7FHReserved

80H to 8FHReserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”

90H to 9DHReserved

9EHROM Correction Control Status 0 PACSR0 R/W ROM Correction 0 00000000

9FHDelayed Interrupt/release DIRR R/W Delayed Interrupt XXXXXXX0

A0HLow-power Mode LPMCR R/W Low Power

Controller 00011000

A1HClock Selector CKSCR R/W Low Power

Controller 11111100

A2H to A7HReserved

A8HWatchdog Control WDTC R/ W Watchdog Timer XXXXX111

A9HTimebase timer Control TBTC R/W Timebase timer 1XX00100

AAH to

ADHReserved

MB90945 Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

AEHFlash Control Status

(Flash devices only. Otherwise reserved) FMCS R/W Flash memory 000X0000

AFHReserved

B0HInterrupt control register 00 ICR00 R/W

Interrupt controller

00000111

B1HInterrupt control register 01 ICR01 R/W 000 00111

B2HInterrupt control register 02 ICR02 R/W 000 00111

B3HInterrupt control register 03 ICR03 R/W 000 00111

B4HInterrupt control register 04 ICR04 R/W 000 00111

B5HInterrupt control register 05 ICR05 R/W 000 00111

B6HInterrupt control register 06 ICR06 R/W 000 00111

B7HInterrupt control register 07 ICR07 R/W 000 00111

B8HInterrupt control register 08 ICR08 R/W 000 00111

B9HInterrupt control register 09 ICR09 R/W 000 00111

BAHInterrupt cont rol register 10 ICR10 R/W 00000111

BBHInterrupt cont rol register 11 ICR11 R/W 00000111

BCHInterrupt contr ol register 12 ICR12 R/W 00000111

BDHInterrupt contr ol register 13 ICR13 R/W 00000111

BEHInterrupt cont rol register 14 ICR14 R/W 00000111

BFHInterrupt control register 15 ICR15 R/W 00000111

C0H to

FFHReserved

MB90945 Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

3500HReload L PRLL0 R/W 16-bit Programable

Pulse

Generator 0/1

XXXXXXXX

3501HReload H PRLH0 R/W XXXXXXXX

3502HReload L PRLL1 R/W XXXXXXX X

3503HReload H PRLH1 R/W XXXXXXXX

3504HReload L PRLL2 R/W 16-bit Programable

Pulse

Generator 2/3

XXXXXXXX

3505HReload H PRLH2 R/W XXXXXXXX

3506HReload L PRLL3 R/W XXXXXXX X

3507HReload H PRLH3 R/W XXXXXXXX

3508HReload L PRLL4 R/W 16-bit Programable

Pulse

Generator 4/5

XXXXXXXX

3509HReload H PRLH4 R/W XXXXXXXX

350AHReload L PRLL5 R/W XXXXXXX X

350BHReload H PRLH5 R/W XXXXXXXX

350CHReload L PRLL6 R/W 16-bit Programable

Pulse

Generator 6/7

XXXXXXXX

350DHReload H PRLH6 R/W XXXXXXXX

350EHReload L PRLL7 R/W XXXXXXX X

350FHReload H PRLH7 R/W XXXXXXXX

3510HReload L PRLL8 R/W 16-bit Programable

Pulse

Generator 8/9

XXXXXXXX

3511HReload H PRLH8 R/W XXXXXXXX

3512HReload L PRLL9 R/W XXXXXXX X

3513HReload H PRLH9 R/W XXXXXXXX

3514HReload L PRLLA R/W 16-bit Programable

Pulse

Generator A/B

XXXXXXXX

3515HReload H PRLHA R/W XXXXXXXX

3516HReload L PRLLB R/W XXXXXXXX

3517HReload H PRLHB R/W XXXXXXXX

3518HSerial Mode Register SMR3 R/W

UART3

00000000

3519HSerial Control Register SCR3 R/W 00000000

351AHReception/Transmission Data Register RDR3/

TDR3 R/W 00000000

351BHSerial Status Register SSR3 R/W 00001000

351CHExtended Communication Control Reg. ECCR3 R/W 000000XX

351DHExtended Status/Control Register ESCR3 R/W 00000100

351EHBaud Rate Register 0 BGR03 R/W 00000000

351FHBaud Rate Regi ster 1 BGR13 R/W 00000000

MB90945 Series

(Continued)

Address Register Abbrevia-

tion Access Resource name Initial value

3520HInput Capture 0 IPCP0 R

Input Capture 0/1

XXXXXXXX

3521HInput Capture 0 IPCP0 R XXXXXXXX

3522HInput Capture 1 IPCP1 R XXXXXXXX

3523HInput Capture 1 IPCP1 R XXXXXXXX

3524HInput Capture 2 IPCP2 R

Input Capture 2/3

XXXXXXXX

3525HInput Capture 2 IPCP2 R XXXXXXXX

3526HInput Capture 3 IPCP3 R XXXXXXXX

3527HInput Capture 3 IPCP3 R XXXXXXXX

3528HInput Capture 4 IPCP4 R

Input Capture 4/5

XXXXXXXX

3529HInput Capture 4 IPCP4 R XXXXXXXX

352AHInput Capture 5 IPCP5 R XXXXXXXX

352BHInput Capture 5 IPCP5 R XXXXXXXX

352CHTimer Data 0 TCDT0 R/W

I/O Timer 0

00000000

352DHTimer Data 0 TCDT0 R/W 00000000

352EHTimer Control 0 TCCS0 R/W 00000000

352FHTimer Control 0 TCCS0 R/W 0XXXXXXX

3530HOutput Compare 0 OCCP0 R/W

Output Compare 0/1

XXXXXXXX

3531HOutput Compare 0 OCCP0 R/W XXXXXXXX

3532HOutput Compare 1 OCCP1 R/W XXXXXXXX

3533HOutput Compare 1 OCCP1 R/W XXXXXXXX

3534HOutput Compare 2 OCCP2 R/W

Output Compare 2/3

XXXXXXXX

3535HOutput Compare 2 OCCP2 R/W XXXXXXXX

3536HOutput Compare 3 OCCP3 R/W XXXXXXXX

3537HOutput Compare 3 OCCP3 R/W XXXXXXXX

3538H to

353BHReserved

353CHTimer Data 1 TCDT1 R/W

I/O Timer 1

00000000

353DHTimer Data 1 TCDT1 R/W 00000000

353EHTimer Control 1 TCCS1 R/W 00000000

353FHTimer Control 1 TCCS1 R/W 0XXXXXXX

3540HTimer 0/Reload 0 TMR0/

TMRLR0 R/W 16-bit Reload

Timer 0

XXXXXXXX

3541HTimer 0/Reload 0 TMR0/

TMRLR0 R/W XXXXXXXX

3542H to

356DHReserved

MB90945 Series

Address Register Abbrevia-

tion Access Resource name Initial value

356EHCAN Direct Mode Register CDMR R/W CAN clock sync XXXXXXX0

356FH to

359FHReserved

35A0HI2C bus status register IBSR R

I2C Interface

00000000

35A1HI2C bus control register IBCR R/W 00000000

35A2HI2C ten bit slave address register ITBAL R/W 00000000

35A3HITBAH R/W 00000000

35A4HI2C ten bit address ma sk register ITMKL R/W 11111111

35A5HITMKH R/W 00111111

35A6HI2C seven bit slave address register ISBA R/W 00000000

35A7HI2C seven bit address mask register ISMK R/W 01111111

35A8HI2C data register IDAR R/W 00000000

35A9H to

35AAHReserved

35ABHI2C clock control register ICCR R/W I2C Interface 00011111

35ACH to

35C8HReserved

35C9HInput Capture Edge 0/1 ICE01 R/W Input Capture 0/1 XXXXX0XX

35CAHInput Capture Edge 2/3 ICE23 R Input Capture 2/3 XXXXXXXX

35CBHInput Capture Edge 4/5 ICE45 R/W Input Capture 4/5 XXXXX0XX

35CCH to

35CEHReserved

35CFHPLL and Special Configuration Control

35D0H to

35D7HReserved

35D8HSerial Mode Register SMR2 R/W

UART2

(MB90V390HA,

MB90V390HB and

MB90F946A only)

00000000

35D9HSerial Control Register SCR2 R/W 00000000

35DAHReception/Transmission Data Register RDR2/

TDR2 R/W 00000000

35DBHSerial Status Register SSR2 R/W 00001000

35DCHExtended Communication Control Reg. ECCR2 R/W 000000XX

35DDHExtended Status/Control Register ESCR2 R/W 00000100

35DEHBaud Rate Register 0 BGR02 R/W 00000000

35DFHBaud Rate Register 1 BGR12 R/W

UART2

(MB90V390HA,

MB90V390HB and

MB90F946A only)

00000000

MB90945 Series

(Continued)

_ : Unused bit

X : Unknown value

Note : Any write access to reserved addresses in I/O map should not be performed.

A read access to reserved addr ess results in reading “X”.

35E0HROM Correction Address 0 PADR0 R/W

Address Matching

Detection Function 0

XXXXXXXX

35E1HROM Correction Address 0 PADR0 R/W XXXXXXXX

35E2HROM Correction Address 0 PADR0 R/W XXXXXXXX

35E3HROM Correction Address 1 PADR1 R/W XXXXXXXX

35E4HROM Correction Address 1 PADR1 R/W XXXXXXXX

35E5HROM Correction Address 1 PADR1 R/W XXXXXXXX

Address Register Abbrevia-

tion Access Resource name Initial value

35E6HROM Correction Address 2 PADR2 R/W Address Matching

Detection Function 0

XXXXXXXX

35E7HROM Correction Address 2 PADR2 R/W XXXXXXXX

35E8HROM Correction Address 2 PADR2 R/W XXXXXXXX

35E9H to

37FFHReserved

3800H to

38FFHReserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”

3900H to

39FFHReserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”

3A00H to

3FFFHReserved

Address Register Abbrevia-

tion Access Resource name Initial value

MB90945 Series

■CAN CONTROLLER

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

- Supports transmission/reception in standard frame an d extended frame formats

• Supports transmitting of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

- 29-bit ID and 8-byte data

- Multi-level message buffer configuration

• Provides full-bit compar ison, full-bit mask, acceptance mask register 0/acceptance mask register 1 for each

message buffer as ID acceptance mask

- Two acceptance mask registers in either standard frame format or extended frame formats

• Bit ra te programmable from 10 Kbps t o 2 Mbps (when input clock is at 16 MHz)

List of Control Registers (1)

Address Register Abbreviation Access Initial Value

CAN1

000080HMessage buffer

valid register BVALR R/W 00000000

00000000

000081H

000082HTransmit request

00000000

000083H

000084HTransmit cancel

00000000

000085H

000086HTransmit

complete regi ster TCR R/W 00000000

00000000

000087H

000088HReceive complete register RCR R/W 00000000

00000000

000089H

00008AHRemote request receiving

00000000

00008BH

00008CHReceive overru n

00000000

00008DH

00008EHReceive interrupt enable

00000000

00008FH

MB90945 Series

List of Control Registers (2)

Address Register Abbreviation Access Initial Value

CAN1

003900HControl status

0XXXX0X1

003901H

003902HLast event

indicator register LEIR R/W XXXXXXXX

000X0000

003903H

003904HReceive/transmit

error coun ter RTEC R 00000000

00000000

003905H

003906HBit timing

11111111

003907H

003908HIDE register IDER R/W XXXXXXXX

XXXXXXXX

003909H

00390AHTransmit RTR

00000000

00390BH

00390CHRemote frame

receive waiting

XXXXXXXX

00390DH

00390EHTransmit

interrupt enable register TIER R/W 00000000

00000000

00390FH

003910H

Acceptance mask select

XXXXXXXX

003911H

003912HXXXXXXXX

XXXXXXXX

003913H

003914H

Acceptance mask register 0 AMR0 R/W

XXXXXXXX

003915H

003916HXXXXXXXX

XXXXXXXX

003917H

003918H

Acceptance mask register 1 AMR1 R/W

XXXXXXXX

003919H

00391AHXXXXXXXX

XXXXXXXX

00391BH

MB90945 Series

List of Message Buffers (ID Registers) (1)

Address Register Abbreviation Access Initial Value

CAN1

003800H

00381FH

General-

purpose RAM ⎯R/W XXXXXXXX

XXXXXXXX

003820H

ID register 0 IDR0 R/W

XXXXXXXX

003821H

003822HXXXXXXXX

XXXXXXXX

003823H

003824H

ID register 1 IDR1 R/W

XXXXXXXX

003825H

003826HXXXXXXXX

XXXXXXXX

003827H

003828H

ID register 2 IDR2 R/W

XXXXXXXX

003829H

00382AHXXXXXXXX

XXXXXXXX

00382BH

00382CH

ID register 3 IDR3 R/W

XXXXXXXX

00382DH

00382EHXXXXXXXX

XXXXXXXX

00382FH

003830H

ID register 4 IDR4 R/W

XXXXXXXX

003831H

003832HXXXXXXXX

XXXXXXXX

003833H

003834H

ID register 5 IDR5 R/W

XXXXXXXX

003835H

003836HXXXXXXXX

XXXXXXXX

003837H

003838H

ID register 6 IDR6 R/W

XXXXXXXX

003839H

00383AHXXXXXXXX

XXXXXXXX

00383BH

00383CH

ID register 7 IDR7 R/W

XXXXXXXX

00383DH

00383EHXXXXXXXX

XXXXXXXX

00383FH

MB90945 Series

List of Message Buffers (ID Registers) (2)

Address Register Abbreviation Access Initial Value

CAN1

003840H

ID register 8 IDR8 R/W

XXXXXXXX

003841H

003842HXXXXXXXX

XXXXXXXX

003843H

003844H

ID register 9 IDR9 R/W

XXXXXXXX

003845H

003846HXXXXXXXX

XXXXXXXX

003847H

003848H

ID register 10 IDR10 R/W

XXXXXXXX

003849H

00384AHXXXXXXXX

XXXXXXXX

00384BH

00384CH

ID register 11 IDR11 R/W

XXXXXXXX

00384DH

00384EHXXXXXXXX

XXXXXXXX

00384FH

003850H

ID register 12 IDR12 R/W

XXXXXXXX

003851H

003852HXXXXXXXX

XXXXXXXX

003853H

003854H

ID register 13 IDR13 R/W

XXXXXXXX

003855H

003856HXXXXXXXX

XXXXXXXX

003857H

003858H

ID register 14 IDR14 R/W

XXXXXXXX

003859H

00385AHXXXXXXXX

XXXXXXXX

00385BH

00385CH

ID register 15 IDR15 R/W

XXXXXXXX

00385DH

00385EHXXXXXXXX

XXXXXXXX

00385FH

MB90945 Series

List of Message Buffers (DLC Regi sters and Data Registers) (1)

Address Register Abbreviation Access Initial Value

CAN1

003860HDLC register 0 DLCR0 R/W XXXXXXXX

003861H

003862HDLC register 1 DLCR1 R/W XXXXXXXX

003863H

003864HDLC register 2 DLCR2 R/W XXXXXXXX

003865H

003866HDLC register 3 DLCR3 R/W XXXXXXXX

003867H

003868HDLC register 4 DLCR4 R/W XXXXXXXX

003869H

00386AHDLC register 5 DLCR5 R/W XXXXXXXX

00386BH

00386CHDLC register 6 DLCR6 R/W XXXXXXXX

00386DH

00386EHDLC register 7 DLCR7 R/W XXXXXXXX

00386FH

003870HDLC register 8 DLCR8 R/W XXXXXXXX

003871H

003872HDLC register 9 DLCR9 R/W XXXXXXXX

003873H

003874HDLC register 10 DLCR10 R/W XXXXXXXX

003875H

003876HDLC register 11 DLCR11 R/W XXXXXXXX

003877H

003878HDLC register 12 DLCR12 R/W XXXXXXXX

003879H

00387AHDLC register 13 DLCR13 R/W XXXXXXXX

00387BH

00387CHDLC register 14 DLCR14 R/W XXXXXXXX

00387DH

00387EHDLC register 15 DLCR15 R/W XXXXXXXX

00387FH

MB90945 Series

List of Message Buffers (DLC Regi sters and Data Registers) (2)

Address Register Abbreviation Access Initial Value

CAN1

003880H

003887HData register 0 (8 bytes) DTR0 R/W XXXXXXXX

XXXXXXXX

003888H

00388FHData register 1 (8 bytes) DTR1 R/W XXXXXXXX

XXXXXXXX

003890H

003897HData register 2 (8 bytes) DTR2 R/W XXXXXXXX

XXXXXXXX

003898H

00389FHData register 3 (8 bytes) DTR3 R/W XXXXXXXX

XXXXXXXX

0038A0H

0038A7HData register 4 (8 bytes) DTR4 R/W XXXXXXXX

XXXXXXXX

0038A8H

0038AFHData register 5 (8 bytes) DTR5 R/W XXXXXXXX

XXXXXXXX

0038B0H

0038B7HData register 6 (8 bytes) DTR6 R/W XXXXXXXX

XXXXXXXX

0038B8H

0038BFHData register 7 (8 bytes) DTR7 R/W XXXXXXXX

XXXXXXXX

0038C0H

0038C7HData register 8 (8 bytes) DTR8 R/W XXXXXXXX

XXXXXXXX

0038C8H

0038CFHData register 9 (8 bytes) DTR9 R/W XXXXXXXX

XXXXXXXX

0038D0H

0038D7HData register 10 (8 bytes) DTR10 R/W XXXXXXXX

XXXXXXXX

0038D8H

0038DFHData register 11 (8 bytes) DTR11 R/W XXXXXXXX

XXXXXXXX

0038E0H

0038E7HData register 12 (8 bytes) DTR12 R/W XXXXXXXX

XXXXXXXX

0038E8H

0038EFHData register 13 (8 bytes) DTR13 R/W XXXXXXXX

XXXXXXXX

MB90945 Series

List of Message Buffers (DLC Regi sters and Data Registers) (3)

Address Register Abbreviation Access Initial Value

CAN1

0038F0H

0038F7HData register 14 (8 bytes) DTR14 R/W XXXXXXXX

XXXXXXXX

0038F8H

0038FFHData register 15 (8 bytes) DTR15 R/W XXXXXXXX

XXXXXXXX

MB90945 Series

■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

(Continued)

Interrupt cause EI2OS

clear Interrupt vector Interrupt control

Number Address Number Address

Reset N/A #08 FFFFDCH⎯⎯

INT9 instruction N/A #09 FFFFD8H⎯⎯

Exception N/A #10 FFFFD4H⎯⎯

Timebase timer N/A #11 FFFFD0HICR00 0000B0H

External Interrupt INT0 to INT7 #12 FFFFCCH

Reserved #13 FFFFC8HICR01 0000B1H

Reserved #14 FFFFC4H

CAN 1 RX N/A #15 FFFFC0HICR02 0000B2H

CAN 1 TX/NS N/A #16 FFFFBCH

PPG 0/1 N/A #17 FFF F B8HICR03 0000B3H

PPG 2/3 N/A #18 FFF F B4H

PPG 4/5 N/A #19 FFF F B0HICR04 0000B4H

PPG 6/7 N/A #20 FFFFACH

PPG 8/9 N/A #21 FFF F A8HICR05 0000B5H

PPG A/B N/A #22 FFFFA4H

16-bit Reload Timer 0 #23 FFFFA0HICR06 0000B6H

Reserved #24 FFFF9CH

Input Capture 0/1 #25 FFFF98HICR07 0000B7H

Output compare 0/1 #26 FFFF94H

Input Capture 2/3 #27 FFFF90HICR08 0000B8H

Output Compare 2/3 #28 FFFF8CH

Input Capture 4/5 #29 FFFF88HICR09 0000B9H

I2C #30 FFFF84H

A/D Converter #31 FFFF80HICR10 0000BAH

I/O Timer 0 / I/O Timer 1 N/A #32 FFFF7CH

Serial I/O #33 FFFF78HICR11 0000BBH

Reserved #34 FFFF74H

UART 0 RX #35 FFFF70HICR12 0000BCH

UART 0 TX #36 FFFF6CH

Reserved #37 FFFF68HICR13 0000BDH

Reserved #38 FFFF64H

MB90945 Series

(Continued)

: The interrupt request fl ag is cleared by the EI2OS interrupt clear signal.

: The interrupt request fl ag is cleared by the EI2OS interrupt clear signal. A stop request is available.

: Unavailable

N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.

Notes : •For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request

flags are cleared by the EI2OS interrupt clear signal.

•At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same

interr u pt number. If one interr u pt fla g sta rts the EI2OS and in the meantime an oth e r in te r rupt flag is set

b y hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused

by the first event. So it is recommended not to use t he EI2OS for this interrupt number.

•If EI2OS is enab led, EI2OS is initiated when one of the two interrupt signals in the same interrupt control

which should be unique for each interrupt source. For this reason, when one interrupt source uses the

EI2OS, the oth er interrupt should be disabled.

Interrupt cause EI2OS

clear Interrupt vector Interrupt control

Number Address Number Address

UART 2 RX / UART 3 RX #39 FFFF60HICR14 0000BEH

UART 2 TX / UART 3 TX #40 FFFF5CH

Flash memory N/A #41 FFFF58HICR15 0000BFH

Delayed interrupt N/A #42 FFFF54H

MB90945 Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

*1 : This paramet er is base d on V SS = AVSS = 0 V.

*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not ex ceed AVCC when the power is switched on.

*3 : VI and VO should not e xceed VCC + 0.3 V. VI should not e xceed the specified ratings. Ho wever if the maximum

current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the

VI rating.

*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P4 7, P50 to P57, P60 to P67,

P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7

*5 : •Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7

•Use within recommended operating conditions.

•Use at DC voltage (current)

•The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

•The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

•Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential ma y pass throug h the protectiv e diode and increase the potential at the VCC pin, and this ma y aff ect

other devices.

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage*1

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *2

AVRH,

AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH, AVCC ≥ AVRL,

AVRH ≥ AVRL

Input voltage*1VIVSS − 0.3 VSS + 6.0 V *3

Output voltage*1VOVSS − 0.3 VSS + 6.0 V *3

Maximum Clamp C urre nt ICLAMP −4.0 +4.0 mA *5

Total Maximum Clamp Current Σ|ICLAMP|⎯40 mA *5

“L” level maximum output cur rent IOL1 ⎯15 mA *4

“L” level average output current IOLAV1 ⎯4mA*4

“L” level maximum overa ll output curr ent ΣIOL1 ⎯100 mA *4

“L” level average overall output current ΣIOLAV1 ⎯50 mA *4

“H” level maximum output current IOH1 ⎯−15 mA *4

“H” level average output current IOHAV1 ⎯−4mA*4

“H” level maximum overall output current ΣIOH1 ⎯−100 mA *4

“H” level average overall output current ΣIOHAV ⎯−50 mA *4

Power consumption PD⎯500 mW MB90947A/F947/F947A/F949/

F949A

⎯525 MB90F946A

Operating temperature TA−40 +105 °C

Storage temperature TSTG −55 +150 °C

MB90945 Series

•Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the po wer

supply is prov ided from the pins, so that incomplete operation may result.

•Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

•Care must be taken not to leave the +B input pin open.

•Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

•Sample recommended circuits :

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Pch

Nch

VCC

• Input/output equivalent circuits

+B input (0 V to 16 V)

Limiting

resistance

Protective diode

MB90945 Series

2. Recommended Conditions (VSS = AVSS = 0 V)

* : Use a ceramic capa citor, or a capacitor of similar fr equency characteristics. On the VCC pin, use a bypass

capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of smoothing

capacitor CS.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within thes e ranges.

Always use semiconductor devices within their recommended ope rating condition ranges. Oper ation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Typ Max

Power supply voltage VCC,

AVCC

3.5 5.0 5.5 V Other than when writing to Flash

memory and when using the A/D

converter

4.0 5.0 5.5 V When writing to Flash memory

4.5 5.0 5.5 V When using the A/D converter

2.0 ⎯5.5 V Retain RAM data in stop mode

Smoothing capacitor CS0.1 ⎯1.0 µF*

Operating temperature TA−40 ⎯+105 °C

• C Pin Connection Diagram

MB90945 Series

3. DC Characteristics (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

(Continued)

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Typ Max

Input “H”

voltage

VIHA ⎯⎯0.8 VCC ⎯VCC + 0.3 V Port inputs except

ports P21/RX1,

P42/SDA, P43/SCL

VIHS ⎯⎯0.7 VCC ⎯VCC + 0.3 V Port inputs P21/

RX1, P42/SDA,

P43/SCL

VIHR ⎯⎯0.8 VCC ⎯VCC + 0.3 V RST input pin

(CMOS Hysteresis)

VIHM ⎯⎯VCC − 0.3 ⎯VCC + 0.3 V MD input pin

Input “L”

voltage

VILA ⎯⎯VSS − 0.3 ⎯0.5 VCC VPort inputs except

ports P21/RX1,

P42/SDA, P43/SCL

VILS ⎯⎯VSS − 0.3 ⎯0.3 VCC VPort inputs P21/

RX1, P42/SDA,

P43/SCL

VILR ⎯⎯VSS − 0.3 ⎯0.2 V CC VRST input pin

(CMOS Hysteresis)

VILM ⎯⎯VSS − 0.3 ⎯VSS + 0.3 V MD input pin

Output “H”

voltage VOH Normal

outputs VCC = 4.5 V,

IOH1 = −4.0 mA VCC − 0.5 ⎯⎯V

Output “H”

voltage VOHI I2C

outputs VCC = 4.5 V,

IOH1 = −3.0 mA VCC − 0.5 ⎯⎯V

Output “L”

voltage VOL Normal

outputs VCC = 4.5 V,

IOL1 = 4.0 mA ⎯⎯0.4 V

Output “L”

voltage VOLI I2C

outputs VCC = 4.5 V,

IOL1 = 3.0 mA ⎯⎯0.4 V

Input leak

current IIL ⎯VCC = 5.5 V,

VSS < VI < VCC −1⎯1µA

MB90945 Series

(Continued) (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

* : The power supply current is measured with an external clock.

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Typ Max

Pull-down

resistance RDOWN MD2 ⎯25 50 100 kOhm only ROM

devices

Power supply

current*

ICC

VCC

VCC = 5.0 V,

Internal frequency :

24 MHz,

At normal operat ion.

⎯60 75 mA MB90947A

MB90F947/A

MB90F949/A

⎯65 85 mA MB90F946A

VCC = 5.0 V,

Internal frequency :

20 MHz,

At normal operat ion.

⎯50 65 mA MB90947A

MB90F947/A

MB90F949/A

⎯55 75 mA MB90F946A

VCC = 5.0 V,

Internal frequency :

20 MHz,

At writing FLASH memory.

⎯65 80 mA MB90F947/A

MB90F949/A

⎯70 90 mA MB90F946A

VCC = 5.0 V,

Internal frequency :

20 MHz,

At erasing FLASH memory.

⎯70 85 mA MB90F947/A

MB90F949/A

⎯75 95 mA MB90F946A

ICCS

VCC = 5.0 V,

Internal frequency :

24 MHz,

At Sleep mode.

⎯25 35 mA MB90947A

MB90F947/A

MB90F949/A

⎯28 40 mA MB90F946A

ICTS

VCC = 5.0 V,

Internal frequency :

2 MHz,

At Main Timebase timer mode

⎯0.3 0.6 mA

MB90947A

MB90F946A

MB90F947/A

MB90F949/A

ICTSPLL6

VCC = 5.0 V,

Internal frequency :

24 MHz,

At PLL Timebase timer mode,

external frequency = 4 MHz

⎯57mA

MB90947A

MB90F946A

MB90F947/A

MB90F949/A

ICCH VCC = 5.0 V,

At Stop mode,

TA = +25°C⎯5 100 µA

MB90947A

MB90F946A

MB90F947/A

MB90F949/A

Input capacity CIN

Other than C,

AVCC, AVSS,

AVRH,

AVRL, VCC,

VSS

⎯⎯515pF

MB90945 Series

4. AC Characteristics

(1) Clock Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0 V)

Parameter Sym-

bol Pin Value Unit Remarks

Min Typ Max

CS2 = 0 CS2 = 1

Clock

frequency fC

X0, X1

3⎯88MHz

× 1/2 (When PLL stops)

When using an oscillation circuit

4⎯8⎯MHz PLL × 1 When using an oscillation circuit

4⎯8 8 MHz PLL × 2 When using an oscillation circuit

4⎯6.67 ⎯MHz PLL × 3 When using an oscillation circuit

4⎯5 6 MHz PLL × 4 When using an oscillation circuit

4⎯⎯ 4 MHz PLL × 6 When using an oscillation circuit

3⎯12 12 MHz × 1/2 (When PLL stops)

When using an ex te rn al circuit

4⎯12 ⎯MHz PLL × 1 When using an external circuit

4⎯10 12 MHz PLL × 2 When using an external circuit

4⎯6.67 ⎯MHz PLL × 3 When using an external circuit

4⎯5 6 MHz PLL × 4 When using an external circuit

4⎯⎯ 4 MHz PLL × 6 When using an external circuit

Clock

cycle time tCYL X0, X1 125 ⎯333 ns When using an oscillation circuit

X0, X1 83.33 ⎯333 n s When using an extern al cloc k

Input clock

pulse width PWH,

PWL X0 20 ⎯⎯ ns Duty ratio is about 30 % to 70%.

Input clock

rise and fall

time

tCR,

tCF X0 ⎯⎯ 5 ns When using external clock

Machine clock

frequency fCP

⎯1.5 ⎯24 MHz Except programming or erasing Flash memory.

⎯1.5 ⎯20 MHz When programming or erasing Flash memory.

Be sure that the maxim u m m om e nta r y

frequency Fmax does not exceed 20MHz.

Machine clock

cycle time tCP ⎯41.67 ⎯666 ns Except programming or erasing Flash memory.

⎯50 ⎯666 n s W hen programming or er asing Flash memory.

CYL

0.8 V

0.2 V

• Clock Timing

MB90945 Series

Guaranteed operation range of MB90F947/MB90F949

*1 : PLL × 1 guaranteed operation r ange is from 4.0 MHz to 12 MHz.

*2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz

External clock frequency and Machine clock frequency

5.5

3.5

41.5 24

Guaranteed operation range

Power supply voltage VCC (V)

Machine clock fCP (MHz)

4.5

Guaranteed A/D converte

operation range

820

Guaranteed PLL operation range (CS2=1)

Guaranteed PLL operation range (CS2=0)

1.5

34 8 12

×4 (CS=011)

Machine clock f

(MHz)

External clock fC (MHz)*2

Guaranteed oscilation frequency range

×3 (CS=010) ×2 (CS=001)

×1*1 (CS=000)

×1/2 (PLL off)

1.5

34 8 12

×6 (CS=110)

Machine clock f

(MHz)

External clock f

(MHz)*

Guaranteed oscilation frequency range

×4 (CS=101) ×2 (CS=100)

×1/2 (PLL off)

• CS2 (bit 0 in PSCCR register) = 1

• CS2 (bit 0 in PSCCR register) = 0

• Guaranteed PLL operation range

MB90945 Series

(2) Reset Standby Input (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V)

*1 : “tCP” represents one cycle time of the machine clock.

No reset can fully initialize the Flash memory if it is performing the automatic algorithm.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In F AR / ceramic oscillators,

the oscillation time is between hundreds of µs to several ms. With an e xternal clock, the oscillation time is 0 ms.

Parameter Symbol Pin Value Unit Remarks

Min Max

Reset input

time tRSTL RST

16 tCP*1⎯ns Under normal operation

Oscillation time of oscillator*2

+ 100 + 16 tCP*1⎯µs In Stop mode

100 ⎯µs In Timebase timer mode

0.2 VCC

tRSTL

0.2 VCC

tRSTL

0.2 VCC 0.2 VCC

16 tCP

RST

90% of

amplitude

Instruction execution

Oscillation stabilization

waiting time

Oscillation time

of oscillator

+100 µs

nternal operation

lock

Internal reset

Under normal operat ion :

In Stop mode :

MB90945 Series

(3) Power On Reset (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V)

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Power on rise time tRVCC ⎯0.05 30 ms

Power off time tOFF VCC 1⎯ms Due to repetitive operation

VCC

VSS

3 V

tOFF

2.7 V

0.2 V 0.2 V0.2 V

Holds RAM data

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you startup smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

We recommend a rise o

50 mV/ms maximum.

MB90945 Series

(4) UART0, SIO Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V)

Notes : • AC characteristics in CLK synchronized mode.

• CL is load capacity value of pins when testing.

• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP

Parameter Sym-

bol Pin Condition Value Unit Re-

marks

Min Max

Serial clock cycle time tSCYC SCK0, SCK4

Internal clock

operation output

pins are

CL = 80 pF + 1 TTL.

8 tCP ⎯ns

SCK ↓ → SOT delay time tSLOV SCK0, SCK4,

SOT0, SOT4 −80 +80 ns

Valid SIN → SCK ↑tIVSH SCK0, SCK4,

SIN0, SIN4 100 ⎯ns

SCK ↑ → Valid SIN hold time tSHIX SCK0, SCK4,

SIN0, SIN4 60 ⎯ns

Serial clock “H” pulse width tSHSL SCK0, SCK4

External clock

operation output

pins are

CL = 80 pF + 1 TTL.

4 tCP ⎯ns

Serial clock “L” pulse width t SLSH SCK0, SCK4 4 tCP ⎯ns

SCK ↓ → SOT delay time tSLOV SCK0, SCK4,

SOT0, SOT4 ⎯150 ns

Valid SIN → SCK ↑tIVSH SCK0, SCK4,

SIN0, SIN4 60 ⎯ns

SCK ↑ → Valid SIN hold time tSHIX SCK0, SCK4,

SIN0, SIN4 60 ⎯ns

MB90945 Series

CK 2.4 V

SCYC

0.8 V

OT 0.8 V

2.4 V

0.8 V

SLOV

IN V

IVSH

SHIX

• Internal Shift Clock Mode

CK V

SLSH

OT 0.8 V

2.4 V

SLOV

IN V

IVSH

SHIX

SHSL

• External Shift Clock Mode

MB90945 Series

(5) UART2/3 Timing

• Bit setting : ESCR : SCES = 0, ECCR : SCDE = 0

(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0V)

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK2,SCK3

Internal clock

operation output

pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↓ → SOT delay time tSLOVI SCK2,SCK3

SOT2,SOT3 −50 +50 ns

Valid SIN → SCK ↑tIVSHI SCK2,SCK3

SIN2,SIN3 tCP + 80 ⎯ns

SCK ↑ → Valid SIN hold time tSHIXI SCK2,SCK3

SIN2,SIN3 0⎯ns

Serial clock “H” pulse width tSHSL SCK2,SCK3

External clock

operation output

pins are

CL = 80 pF + 1 TTL.

tCP + 10 ⎯ns

Serial clock “L” pulse width tSLSH SCK2,SCK3 3 tCP − tR⎯ns

SCK ↓ → SOT delay time tSLOVE SCK2,SCK3

SOT2,SOT3 ⎯2 tCP + 60 ns

Valid SIN → SCK ↑tIVSHE SCK2,SCK3

SIN2,SIN3 30 ⎯ns

SCK ↑ → Valid SIN hold time tSHIXE SCK2,SCK3

SIN2,SIN3 tCP + 30 ⎯ns

SCK fall time tFSCK2,SCK3 ⎯10 ns

SCK rise time tRSCK2,SCK3 ⎯10 ns

2.4 V

0.8 V

2.4 V

0.8 V

SLOVI

SCYC

IVSHI

SHIXI

• Internal Shift Clock Mode

MB90945 Series

• Bit setting : ESCR : SCES = 1, ECCR : SCDE = 0

(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V)

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK2,SCK3

Internal clock

operation output

pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↑ → SOT delay time tSHOVI SCK2,SCK3

SOT2,SOT3 −50 +50 ns

Valid SIN → SCK ↓tIVSLI SCK2,SCK3

SIN2,SIN3 tCP + 80 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXI SCK2,SCK3

SIN2,SIN3 0⎯ns

Serial clock “H” pulse width tSHSL SCK2,SCK3

External clock

operation output

pins are

CL = 80 pF + 1 TTL.

3 tCP − tR⎯ns

Serial clock “L” pulse width tSLSH SCK2,SCK3 tCP + 10 ⎯ns

SCK ↑ → SOT delay time tSHOVE SCK2,SCK3

SOT2,SOT3 ⎯2 tCP + 60 ns

Valid SIN → SCK ↓tIVSLE SCK2,SCK3

SIN2,SIN3 30 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXE SCK2,SCK3

SIN2,SIN3 tCP + 30 ⎯ns

SCK fall time tFSCK2,SCK3 ⎯10 ns

SCK rise time tRSCK2,SCK3 ⎯10 ns

CK VIH

VIL

OT 0.8 V

2.4 V

tSLOVE

IN VIL

VIH

VIL

VIH

VIL

tSHSL

tSLSH

tIVSHE tSHIXE

• External Shift Clock Mode

MB90945 Series

2.4 V

SCYC

0.8 V

2.4 V

SHOVI

IVSLI

SLIXI

• Internal Shift Clock Mode

0.8 V

2.4 V

SHOVE

IVSLE

SLIXE

SHSL

SLSH

• External Shift Clock Mode

MB90945 Series

• Bit setting : ESCR : SCES = 0, ECCR : SCDE = 1

(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V)

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK2,SCK3

Internal clock

operation output

pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↑ → SOT delay time tSHOVI SCK2,SCK3

SOT2,SOT3 −50 +50 ns

Valid SIN → SCK ↓tIVSLI SCK2,SCK3

SIN2,SIN3 tCP + 80 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXI SCK2,SCK3

SIN2,SIN3 0⎯ns

SOT → SCK ↓ delay time tSOVLI SCK2,SCK3

SOT2,SOT3 3 tCP −

70 ⎯ns

CK 2.4 V

SCYC

0.8 V

OT 0.8 V

2.4 V

SOVLI

IN V

IVSLI

SLIXI

0.8 V

SHOVI

0.8 V

2.4 V

MB90945 Series

• Bit setting : ESCR : SCES = 1, ECCR : SCDE = 1

(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V)

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP

Parameter Sym-

bol Pin Condition Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK2,SCK3

Internal clock

operation output

pins are

CL = 80 pF + 1 TTL.

5 tCP ⎯ns

SCK ↓ → SOT delay time tSLOVI SCK2,SCK3

SOT2,SOT3 −50 +50 ns

Valid SIN → SCK ↑tIVSHI SCK2,SCK3

SIN2,SIN3 tCP + 80 ⎯ns

SCK ↑ → Valid SIN hold time tSHIXI SCK2,SCK3

SIN2,SIN3 0⎯ns

SOT → SCK ↑ delay time tSOVHI SCK2,SCK3

SOT2,SOT3 3 tCP −

70 ⎯ns

CK 2.4 V

tSCYC

2.4 V

OT 0.8 V

2.4 V

tSOVHI

IN VIL

VIH

tIVSHI

VIL

VIH

tSHIXI

0.8 V

tSLOVI

0.8 V

2.4 V

MB90945 Series

(6) Trigger Input Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V)

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP

(7) Timer Related Resource Input Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5. 5V, VSS = AVSS = 0.0 V)

Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Input pulse width tTRGH

tTRGL

INT0 to INT7 ⎯200 ⎯ns

ADTG tCP + 200 ⎯ns

Parameter Symbol Pin Condition Value Unit Remarks

Min Max

Input pulse width tTIWH TIN0,

IN0 to IN5 ⎯4 tCP ⎯ns

tTIWL

VIL

VIH

tTRGH

VIL

VIH

tTRGL

• Trigger Input Timin g

VIL

VIH

tTIWH

VIL

VIH

tTIWL

• Timer Input Timing

MB90945 Series

(8) I2C Timing (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0. 0 V)

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum tHDDAT only has to be met if the devie does not stret ch the “L” width (tLOW) of the SCL signal.

*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSUDAT ≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

Parameter Symbol Condition Standard-mode Fast-mode*4 Unit

Min Max Min Max

SCL clock frequency fSCL

R = 1.3 kΩ,

C = 50 pF*1

01000400kHz

Hold time (repeated) START condition

SDA ↓ → SCL ↓tHDSTA 4.0 ⎯0.6 ⎯µs

“L” width of SCL clock tLOW 4.7 ⎯1.3 ⎯µs

“H” width of SCL clock tHIGH 4.0 ⎯0.6 ⎯µs

Set-up ti me for a repeat ed START cond ition

SCL ↑ → SDA ↓tSUSTA 4.7 ⎯0.6 ⎯µs

Data hold time

SCL ↑ → SDA ↓↑ tHDDAT 03.45*

200.9*

3µs

Data set-up time

SDA ↓↑ → SCL ↑tSUDAT 250 ⎯100 ⎯ns

Set-up time for STOP condition

SCL ↑ → SDA ↑tSUSTO 4.0 ⎯0.6 ⎯µs

Bus free time between STOP and START

condition tBUS 4.7 ⎯1.3 ⎯µs

LOW

HIGH

HDDAT

HDSTA

SUDAT

SUSTA

HDSTA

SUSTO

BUS

• I2C Timing

MB90945 Series

5. A/D Converter

(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .

Terminology

Notes : •tCP is the machine clock cycle time (Unit : ns) . Refer to “4. AC Characteristics (1) Clock timing” rating

for tCP

•The accuracy gets worse as |AVRH − AVRL| becomes smaller.

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Resolution ⎯⎯ ⎯ 10 bit

Total error ⎯⎯ ⎯ ⎯±3.0 LSB

Nonlinearity error ⎯⎯ ⎯ ⎯±2.5 LSB

Differential

nonlinearity error ⎯⎯ ⎯ ⎯±1.9 LSB

Zero reading voltage VOT AN0 to AN14 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB

Full scale reading

voltage VFST AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB

Compare time ⎯⎯ 3.3 66 tCP 16500 µs

Sampling time ⎯⎯ 1.6 32 tCP ∞µs

Analog port input

current IAIN AN0 to AN14 −0.3 ⎯+0.3 µA

Analog input volta ge

range VAIN AN0 to AN14 AVRL ⎯AVRH V

Reference voltage

range ⎯AVRH AVRL + 2.7 ⎯AVCC V

AVRL 0 ⎯AVRH − 2.7 V

Power supply current IAAVCC ⎯3.5 7.5 mA

IAH AVCC ⎯⎯ 5µA*

Reference voltage

current IRAVRH ⎯165 250 µA

IRH AVRH ⎯⎯ 5µA*

Offset betw een input

channels ⎯AN0 to AN14 ⎯⎯ 4LSB

Conversion error : Absolute maximum conversion deviation with respect to the theoretical conversion

line.

Nonlinearity : Relat ive maximum conversion deviation with respect to the theoretical conversion

line conncecting to the device unigque zero reading voltage and full scale reading

voltage.

Differential nonlinearity : Max conversion deviation in any two adjacent reading voltages with respect to the

theoretical LSB conversion step.

Zero reading voltage : Input voltage which results in the minimum conversion value.

Full scale reading voltage : Input voltage which results in the maximum conversion value.

MB90945 Series

6. Definition of A/D Converter Terms

(Continued)

Resolution : Analog variation that is recognized by an A/D converter.

Linear error : De viation betw een a line across z ero -tra nsition line ( “0 0 0000 000 0” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differential linear

error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error : Differ en ce be tween an actual value and an ideal value. A total error includes zero tr ansition

error, full-scale transition error, and linear error.

3FFH

3FEH

3FDH

004H

003H

002H

001H

AVRL AVRH

VNT

1.5 LSB

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

Actual conversion

characteristics

(Actually-measured valu

Actual conversion

characteristics

Ideal characteristics

Digital output

Analog input

Total error

Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB [LSB]

1 LSB (Ideal value) = AVRH − AVRL

1024 [V]

VOT (Ideal value) = AVRL + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

VNT : A voltage at wh ich digital output tran sitions from (N − 1) to N.

MB90945 Series

(Continued)

3FFH

3FEH

3FDH

004H

003H

002H

001H

AVRL AVRH AVRL AVRH

N + 1

N − 1

N − 2

VOT (actual measurement value)

{1 LSB × (N − 1)

+ VOT }

Actual conversion

characteristics

VFST (actual

measurement

value)

VNT (actual

measurement value)

Actual conversion

characteristics

Ideal characteristics

Actual conversion

characteristics

Actual conversion

characteristics

Ideal

characteristics

Digital output

Analog inputAnalog input

VNT

(actual measurement valu

V (N + 1) T

(actual measurement

value)

Linear error Differential linear error

Linear error of digital output N =VNT − {1 LSB × (N − 1) + VOT}

1 LSB [LSB]

Differential linear error of digital output N =V (N+1) T − VNT

1 LSB −1 LSB [LSB]

VFST − VOT

1022 [V]

1 LSB =

VOT : Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

MB90945 Series

7. Notes on A/D Converter Section

• About the external impedance of the analog input and its sampling time

• A/D converter wit h samp le and hold circu it. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conver sio n precision.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so th at the sa mp lin g tim e is longe r tha n the mini mum value.

• If the samplin g time cannot be sufficient, connect a capacitor of about 0.1 µF to the an alog input pin.

• About the error

The accuracy gets worse as |AVRH − AVRL| becomes smaller.

MB90F946A/947A/

F947/F947A/F949/

F949A 2.4 kΩ (Max) 36.4 pF (Max)

• Analog input circuit model

Note : The values are reference values.

Analog input Comparator

During sampling : ON

0 5 10 15 20 25 30 35

100

MB90F947

MB90F949

0123 5678

MB90F947

MB90F949

(External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ)

External impedance [kΩ]

Minimum sampling time [µs]

External impedance [kΩ]

Minimum sampling time [µs]

• The relationsh ip between the external impedance and minimum sampling time

MB90945 Series

8. Flash Memory Program/Erase Characteristics

* : This v alue comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into nor m alized value at +85 °C) .

Parameter Conditions Value Unit Remarks

Min Typ Max

Sector erase tim e

TA = +25 °C

VCC = 5.0 V

⎯115s

Excludes programmin g

prior to erasure

Chip erase time ⎯5⎯sMB90F947, Excludes pro-

gramming prior t o erasur e

⎯7⎯sMB90F949, Excludes pro-

gramming prior t o erasur e

Word (16-bit width)

programming time ⎯16 3,600 µsExcept for the overhead

time of the system

Program/Erase cycle ⎯10,000 ⎯⎯cycle

Flash Data Retention

Time Average

TA = +85 °C20 ⎯⎯Year *

MB90945 Series

■EXAMPLE CHARACTERISTICS

•MB90F947

(Continued)

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICC - VCC

ICC [mA]

VCC [V]

f = 24 MH

f = 20 MH

f = 16 MH

f = 12 MH

f = 10 MH

f = 8 MHz

f = 4 MHz

f = 2 MHz

02.0 3.0 4.0 5.0 6.0 7.0

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICCS - VCC

ICCS [mA]

VCC [V]

f = 24 MHz

f = 20 MHz

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

02.0 3.0 4.0 5.0 6.0 7.0

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICTS - VCC

ICTS [µA]

VCC [V]

f = 2 MHz

500

450

400

350

300

250

200

150

100

02.0 3.0 4.0 5.0 6.0 7.0

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICTSPLL6 - VCC

ICTSPLL6 [mA]

VCC [V]

f = 24 MHz

02.0 3.0 4.0 5.0 6.0 7.0

MB90945 Series

(Continued)

TA = +25 ˚C, at stop

ICCH - VCC

ICCH [µA]

VCC [V]

02.0 3.0 4.0 5.0 6.0 7

MB90945 Series

•MB90F949

(Continued)

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICC - VCC

ICC [mA]

VCC [V]

f = 24 MH

f = 20 MH

f = 16 MH

f = 12 MH

f = 10 MH

f = 8 MHz

f = 4 MHz

f = 2 MHz

02.0 3.0 4.0 5.0 6.0 7.0

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICCS - VCC

ICCS [mA]

VCC [V]

f = 24 MHz

f = 20 MHz

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

02.0 3.0 4.0 5.0 6.0 7.0

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICTS - VCC

ICTS [µA]

VCC [V]

f = 2 MHz

500

450

400

350

300

250

200

150

100

02.0 3.0 4.0 5.0 6.0 7.0

TA = +25 ˚C, at external clock operating

f = Internal operation frequency

ICTSPLL6 - VCC

ICTSPLL6 [mA]

VCC [V]

f = 24 MHz

02.0 3.0 4.0 5.0 6.0 7.0

MB90945 Series

(Continued)

TA = +25 ˚C, at stop

ICCH - VCC

ICCH [µA]

VCC [V]

02.0 3.0 4.0 5.0 6.0 7

MB90945 Series

•I/O Characteristic

(VCC−VOH) − IOH VOL − IOL

TA = +25 °C, VCC = 4.5 V TA = +25 °C, VCC = 4.5 V

Automotive VIN − VCC CMOS VIN − VCC

TA = +25 °CCAN RX pin, I2C pin

TA = +25 °C

900

800

700

600

500

400

300

200

100

VCC-VOH (mV)

0128

43567910

IOH (mA)

1000

900

800

700

600

500

400

300

200

100

010325

IOL (mA)

VOL (mV)

47691

VIN (V)

5.0

1.5

0.5

1.0

VCC (V)

0.0

2.0

3.0

3.5

2.5

2.5 3.5 4.5 5.5 6.53.0 4.0 5.0 6.0 7.0

4.0

4.5 VIHA

VILA

(V)

5.0

2.5

0.5

1.0

(V)

0.0

3.0

4.0

4.5

3.5

1.5

2.0

2.5 3.5 4.5 5.5 6.53.0 4.0 5.0 6.0 7.0

IHS

ILS

MB90945 Series

■ORDERING IN FORMATION

Part number Package Remarks

MB90F946APF 100-pin Plastic QFP

(FPT-100P-M06)

MB90947APF 100-pin Plastic QFP

(FPT-100P-M06)

MB90F947PF 100-pin Plastic QFP

(FPT-100P-M0 6 )

It is recommended to use MB90F947A,

because MB90F947 does not support

clock modulation and CAN at the same

time

MB90F947APF 100-pin Plastic QFP

(FPT-100P-M0 6 )

MB90F949PF 100-pin Plastic QFP

(FPT-100P-M0 6 )

It is recommended to use MB90F949A,

because MB90F949 does not support

clock modulation and CAN at the same

time

MB90F949APF 100-pin Plastic QFP

(FPT-100P-M0 6 )

MB90V390HACR 299-pin Ceramic PGA

(PGA-299C-A01) For evalua tion

It is recommended to use MB90V390HB

MB90V390HBCR 299-pin Ceramic PGA

(PGA-299C-A01) For evalua tion

MB90945 Series

■PACKAGE DIMENSIONS

100-pin Plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include t ie bar cutting remainder.

Dimensions in mm (inches) .

Note : The values in pa re nt he se s ar e re fe re nce values.

2002 FUJITSU LIMITED F100008S-c-5-5

1 30

5180

100

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20

(.551±.008)

17.90±0.40

(.705±.016)

INDEX

0.65(.026) 0.32±0.05

(.013±.002) M

0.13(.005)

"A"

0.17±0.06

(.007±.002)

0.10(.004)

Details of "A" part

(.035±.006)

0.88±0.15

(.031±.008)

0.80±0.20

0.25(.010)

3.00 +0.35

–0.20

+.014

–.008

.118

(Mounting height)

0.25±0.20

(.010±.008)

(Stand off)

0~8˚

MB90945 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infr ingement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infri ngement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nu clear faci lit y, ai rcr aft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0507