FUJITSU SEMICONDUCTOR DATA SHEET DS07-13741-2E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90945 Series MB90F946A/947A/F947/F947A/F949/F949A/ V390HA/V390HB DESCRIPTION The MB90945 series with one FULL-CAN* interface and FLASH ROM is especially designed for automotive HVAC applications. Its main feature is the on board CAN* Interface, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN* approach. With the new 0.35 m CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 384 K bytes. An internal voltage booster removes the necessity for a second programming voltage. An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features a 4-channel Output Compare Unit and a 6-channel Input Capture Unit with two separate 16-bit free running timers. Up to 3 UARTs, one Serial I/O and one I2C constitute additional functionality for communication purposes. * : Controller Area Network (CAN) - License of Robert Bosch GmbH PACKAGE 100-pin Plastic QFP (FPT-100P-M06) MB90945 Series FEATURES * * * * * * * * * * * * * * * * * * * * * * * * * * 2 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instr. cycle time) New 0.35 m CMOS Process Technology Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures One FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) Powerful interrupt functions (8 progr. priority levels; 8 external interrupts) EI2OS - Automatic transfer function independant of CPU; 16 channels of intelligent I/O Services 18-bit Time-base counter Watchdog Timer 1 full duplex UART; support 10.4 KBaud (USA standard) up to 2 full duplex UARTs (LIN/SCI/SPI) 1 Serial I/O (SPI) 1 I2C interface A/D Converter : 15 channels analog inputs (Resolution 10-bit or 8-bit) 16-bit reload timer x 1channel ICU (Input capture) 16-bit x 6 channels OCU (Output compare) 16-bit x 4 channels 16-bit free running timer x 2 channels (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5) 8/16-bit Programmable Pulse Generator 6 channels x 8/16-bit Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 4-byte instruction execution queue signed multiply (16-bit x 16-bit) and divide (32-bit/16-bit) instructions available Program Patch Function (3 address match registers) Fast Interrupt processing Low Power Consumption mode Sleep mode Timebase timer mode Stop mode CPU intermittent mode Automotive input levels Package : 100-pin plastic QFP MB90945 Series PRODUCT LINEUP Part Number MB90947A MB90F946A Parameter ROM RAM On-chip PLL clock multiplier (x1, x2, x3, x4, x6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL clock multiplied by 6) ROM memory 128 Kbytes 6 Kbytes Emulator-specific power supply*1 Boot-block Flash memory 384 Kbytes Boot-block Flash memory 256 Kbytes: MB90F949 MB90F949A 128 Kbytes: MB90F947 MB90F947A External 16 Kbytes 12 Kbytes: MB90F949 MB90F949A 6 Kbytes: MB90F947 MB90F947A 30 Kbytes Yes 0.35 m CMOS with on-chip voltage regulator for internal power supply + Flash memory with on-chip charge pump for programming voltage Technology 0.35 m CMOS with on-chip voltage regulator for internal power supply Operating voltage range 3.5 V to 5.5 V : other than conditions listed below 4.0 V to 5.5 V : when writing to Flash 4.5 V to 5.5 V : if A/D Converter is used Temperature range Package UART UART (LIN/SCI/SPI) Serial I/O I2C (400 Kbps) MB90V390HA MB90V390HB F2MC-16LX CPU CPU System clock MB90F947, MB90F947A MB90F949, MB90F949A 0.35 m CMOS with on-chip voltage regulator for internal power supply 5 V 10% -40 C to +105 C QFP-100P PGA-299C 1 channel 2 channels Full duplex double buffer Supports asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock = 20 MHz 1 channel 2 channels 1 channel 2 channels 1 channel Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 20 MHz 1 channel (Continued) 3 MB90945 Series Part Number MB90947A MB90F946A Parameter MB90F947, MB90F947A MB90F949, MB90F949A MB90V390HA MB90V390HB 10-bit or 8-bit resolution A/D Converter Conversion time : Min 4.9 s includes sample time (per one channel, only at certain (15 input channels) machine clock frequencies) 1 channel 2 channels 16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function 16-bit I/O Timer (2 channels) 16-bit Input Capture (6 channels) 16-bit Output Compare Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (ch0) Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = System clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5 Rising edge, falling edge or rising & falling edge sensitive Six 16-bit Capture registers Signals an interrupt upon external event ICU 3/5 inputs are shared with OCU 6/7 outputs 4 channels 8 channels Signals an interrupt when a match with 16-bit I/O Timer Eight 16-bit compare registers. A pair of compare registers can be used to generate an output signal. 8/16-bit Programmable Pulse Generator (6 channels) Supports 8-bit and 16-bit operation modes Twelve 8-bit reload counters Twelve 8-bit reload registers for L pulse width Twelve 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 s (fosc = 5 MHz) (fsys = System clock frequency, fosc = Oscillation clock frequency) 1 channel CAN Interface ICU 3/5 inputs are shared with OCU 6/7 outputs 5 channels Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering : Full-bit compare/Full-bit mask/Two partial bit masks Supports up to 1 Mbps MB90F947/F949/V390HA: Do not use clock modulation and CAN at the same time (Continued) 4 MB90945 Series Part Number MB90947A MB90F946A Parameter External Interrupt (8 channels) MB90F947, MB90F947A MB90F949, MB90F949A MB90V390HA MB90V390HB Can be programmed edge sensitive or level sensitive Stepping motor controller 2 channels Watch Timer 1 channel Sound generator 1 channel Machine clock output 2 channels (non-inverted and inverted) 3 address match registers 5 address match registers Program patch function Virtually all external pins can be used as general purpose I/O All push-pull outputs Bit-wise programmable as input/output or peripheral signal I/O Ports Port-wise programAutomotive input level (P21/RX1, P42/SDA, P43/SCL have CMOS mable as Automotive Schmitt input level) (default) or CMOS Schmitt input level I/O Ports with 4 mA CMOS output All ports except P42, P43 All ports except P80, P81, PA0 to PA7, P42, P43 I/O Ports with 3 mA CMOS output P42, P43 P42, P43 I/O Ports with 30 mA CMOS output with slewrate control P80, P81, PA0 to PA7 Phase modulation mode Clock Modulator Phase modulation mode Frequency and phase modulation mode MB90F947/F949/V390HA: Do not use clock modulation and CAN at the same time Reduces EMI by modulating the PLL clock Start-up time at power-on reset 218 oscillation cycles (65.536 ms at 4 MHz 3 x 216 oscillation cycles (49.152 ms at 4 MHz oscillation) + oscillaoscillation) + tion time of oscillator*2 oscillation time of oscillator*2 (Continued) 5 MB90945 Series (Continued) Part Number MB90947A Parameter Flash Memory MB90F946A MB90F947, MB90F947A MB90F949, MB90F949A Supports automatic programming, Embedded AlgorithmTM*3 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 20 years*4 Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory (address FFA000H, mode data 00H) Boot block configuration Erase can be performed on each block Block protection with external programming voltage Write and erase at Fmax = 20 MHz MB90V390HA MB90V390HB *1 : It is setting of Jumper switch SI when Emulation Pod (MB2147) is used. Please refer to the Emulator hardware manual about details. *2 : Oscillation time of the oscillator is the time that the amplitude reaches 90%. *3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. *4 : Data is based on reliability tests during process qualification (the value for TA = + 85 C is calculated via the Arrenhius formula from data of accelerated measurements at elevated temperature) . 6 MB90945 Series PIN ASSIGNMENTS * MB90947A/F946A/F947/F947A/F949/F949A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P03/IN3 P02/IN2 P01/IN1 P00/IN0 P81 P80 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Vss Vcc P96 P92 P91 P94/SCK3 P95/SOT3 P93/SIN3 P90 P57/PPG01 P56/PPG00 P55/PPG15 RST MD0 MD1 MD2 PB6/SOT4/AN14 AVcc AVRH AVRL AVss P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Vss P51/PPG11 P52/PPG12 P53/PPG13 P54/PPG14 PB7/FRCK0 P97/FRCK1 P24/INT4 P25/INT5 P26/INT6 P27/INT7 P30 P31 P32 P33 P34/SOT0 P35/SCK0 P36/SIN0 P37 P44 P45/ADTG Vcc Vss C P40 P41 P42/SDA P43/SCL P46/INT0 P47/INT1 P50/PPG10 PB0/PPG02/AN8 PB1/PPG03/AN9 PB2/PPG04/AN10 PB3/PPG05/AN11 PB4/SIN4/AN12 PB5/SCK4/AN13 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P23/INT3 P22/INT2 P21/RX1 P20/TX1 P17 P16 P15/TOT0 X0 X1 Vss Vcc P14/TIN0 P13 P12 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P05/IN5 P04/IN4 (TOP VIEW) (FPT-100P-M06) 7 MB90945 Series * MB90V390HA/V390HB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PB6/SOT4/AN14 AVcc AVRH AVRL AVss P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Vss P51/PPG11 P52/PPG12 P53/PPG13 P54/PPG14 PB7/FRCK0/HCLK P97/FRCK1/HCLKX P24/INT4 P25/INT5 P26/INT6 P27/INT7 P30/RX0 P31/TX0 P32/TIN1 P33/TOT1 P34/SOT0 P35/SCK0 P36/SIN0 P37/SIN1 P44 P45/ADTG Vcc Vss C P40/SCK1 P41/SOT1 P42/SDA P43/SCL P46/INT0 P47/INT1 P50/PPG10 PB0/PPG02/TX3/AN8 PB1/PPG03/RX3/AN9 PB2/PPG04/TX4/AN10 PB3/PPG05/RX4/AN11 PB4/SIN4/AN12 PB5/SCK4/AN13 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P23/INT3 P22/INT2 P21/RX1 P20/TX1 P17/SGA P16/SGO P15/TOT0 X0 X1 Vss Vcc P14/TIN0 P13/OUT5 P12/OUT4 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P05/IN5/OUT7 P04/IN4 (TOP VIEW) (FPT-100P-M06) As seen with QFP100 probe cable 8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P03/IN3/OUT6 P02/IN2 P01/IN1 P00/IN0 P81 P80 PA7/PWM2M5 PA6/PWM2P5 PA5/PWM1M5 PA4PWM1P5 PA3/PWM2M4 PA2/PWM2P4 PA1/PWM1M4 PA0/PWM1P4 DVss DVcc P96/WOT P92/SOT2 P91/SCK2 P94/SCK3 P95/SOT3 P93/SIN3 P90/SIN2 P57/PPG01/TX2 P56/PPG00/RX2 P55/PPG15 RST MD0 MD1 MD2 MB90945 Series PIN DESCRIPTION Pin no. Pin name 92 X1 93 X0 54 RST 77 to 82 83 to 86 P00 to P05 IN0 to IN5 P06, P07 P10, P11 Circuit type A B D D OUT0 to OUT3 87, 88 89 94 95, 96 97 98 P12, P13 P14 TIN0 P15 TOT0 P16, P17 P20 TX1 P21 RX1 P22 to P27 99, 100 1 to 4 INT2 to INT7 5 to 8 P30 to P33 9 10 11 P34 SOT0 P35 SCK0 P36 SIN0 Function Pin for oscillation Pin for oscillation Reset input General purpose I/O Inputs for the Input Captures 0-5 General purpose I/O Outputs for the Output Compares D D D D D F D D D D D General purpose I/O General purpose I/O TIN0 input for the 16-bit Reload Timer 0 General purpose I/O TOT0 output for the 16-bit Reload Timer 0 General purpose I/O General purpose I/O TX output for CAN Interface 1 General purpose I/O RX input for CAN Interface 1 General purpose I/O External interrupt inputs for INT2 to INT7 General purpose I/O General purpose I/O SOT output for UART0 General purpose I/O SCK input/output for UART0 General purpose I/O SIN input for UART0 12 P37 D General purpose I/O 13 P44 D General purpose I/O 14 18, 19 20 P45 ADTG P40, P41 P42 SDA D D F General purpose I/O External trigger input of the A/D Converter General purpose I/O General purpose I/O Serial data for I2C interface (Continued) 9 MB90945 Series Pin no. 21 22, 23 24 Pin name P43 SCL P46, P47 INT0, INT1 P50 PPG10 Circuit type F D D PB0 to PB3 25 to 28 PPG02 to PPG05 E E E 45 to 48 49 50 55 56, 57 P60 to P67 AN0 to AN7 P51 to P54 PPG11 to PPG14 PB7 FRCK0 P97 FRCK1 P55 PPG15 P56, P57 PPG00, PPG01 E 59 SIN2 P93 SIN3 SIN input for Serial I/O SCK input/output for Serial I/O SOT output for Serial I/O Input for the A/D Converter E D D D D D P90 58 Outputs for the PPG4, 6, 8, A General purpose I/O AN14 36 to 43 Output for the PPG1 Input for the A/D Converter PB6 SOT4 General purpose I/O General purpose I/O AN13 31 External interrupt inputs for INT0, INT1 Input for the A/D Converter PB5 SCK4 General purpose I/O General purpose I/O AN12 30 Serial clock for I2C interface Inputs for the A/D Converter PB4 SIN4 General purpose I/O General purpose I/O AN8 to AN11 29 Function General purpose I/O Inputs for the A/D Converter General purpose I/O Outputs for the PPG3, 5, 7, 9 General purpose I/O FRCK0 input for the 16-bit I/O Timer 0 General purpose I/O FRCK1 input for the 16-bit I/O Timer 1 General purpose I/O Outputs for the PPGB General purpose I/O Outputs for the PPG0, PPG2 General purpose I/O D D SIN input for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A) General purpose I/O SIN input for UART3 (LIN/SCI/SPI) (Continued) 10 MB90945 Series (Continued) Pin no. 60 61 Pin name P95 SOT3 P94 SCK3 Circuit type D D P91 62 SCK2 SOT2 General purpose I/O SOT output for UART3 (LIN/SCI/SPI) General purpose I/O SCK input/output for UART3 (LIN/SCI/SPI) General purpose I/O D P92 63 Function SCK input/output for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A) General purpose I/O D SOT output for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A) 64 P96 D General purpose I/O 67 to 74 PA0 to PA7 H General purpose I/O. For the EVA device, these pins are high current outputs. 75, 76 P80, P81 H General purpose I/O. For the EVA device, these pins are high current outputs. 32 AVCC Dedicated power supply pin (5 V) for the A/D converter 33 AVRH Dedicated pos. reference voltage pin for the A/D converter 34 AVRL Dedicated neg. reference voltage pin for the A/D converter 35 AVss Dedicated power supply pin (0 V) for the A/D converter 52, 53 MD1, MD0 C These are input pins used to designate the operating mode. They should be connected directly to VCC or VSS. 51 MD2 G This is an input pin used to designate the operating mode. It should be connected directly to VCC or VSS. 15 65 90 Vcc These are power supply (5 V) input pins. For the EVA device, pin 65 is the DVCC supply pin for the high current outputs. 16 44 66 91 Vss These are power supply (0 V) input pins. For the EVA device, pin 66 is the DVSS supply pin for the high current outputs. 17 C This is the power supply stabilization capacitor pin. It should be connected to higher than or equal to 0.1 F ceramic capacitor. 11 MB90945 Series I/O CIRCUIT TYPE Type Circuit Remarks X1 Clock input Pch * Oscillation feedback resistor : 1 M approx. Nch X0 A Standby control signal * CMOS Hysteresis input with pull-up resistor : 50 k approx. VCC B R (pull-up) R C R CMOS Hysteresis CMOS Hysteresis * EVA/ROM device : CMOS Hysteresis input * Flash device : CMOS input. * CMOS output (4 mA) * Automotive Hysteresis input VCC Pch D Nch R Automotive Hysteresis (Continued) 12 MB90945 Series (Continued) Type Circuit Remarks * CMOS output (4 mA) * Automotive Hysteresis input * Analog input VCC Pch Nch E Pch Analog input Nch Automotive Hysteresis R VCC Pch F Nch CMOS Hysteresis R R G * CMOS output P42, P43 : 3mA P21 : 4 mA * CMOS Hysteresis input CMOS Hysteresis R (pull-down) VCC Pch H Nch R * EVA/ROM device : CMOS Hysteresis input with pulldown resistor : 50 k approx. * Flash device : CMOS input without pull-down. * EVA/ROM device : CMOS high current output (30 mA) with slewrate control * Flash device : CMOS output (4 mA) * Automotive Hysteresis input Automotive Hysteresis 13 MB90945 Series HANDLING DEVICES Special care is required for the following when handling the device : * Preventing latch-up * Stabilization of supply voltage * Treatment of unused pins * Using external clock * Power supply pins (VCC/VSS) * Pull-up/pull-down resistors * Crystal Oscillator Circuit * Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs * Connection of Unused Pins of A/D Converter if A/D Converter is unused. * Caution on Operations during PLL Clock Mode 1. Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than VCC or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VCC and VSS. * The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. In using the devices, take sufficient care to avoid exceeding maximum ratings. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 2. Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operation range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 Hz to 60 Hz) fall below 10 % of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 3. Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 4. Using external clock To use external clock, drive the X0 pin and leave X1 pin open. MB90945 Series X0 X1 14 MB90945 Series 5. Power supply pins (VCC/VSS) * If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. * Connect VCC and VSS to the device from the current supply source at a low impedance. * As a measure against power supply noise, connect a capacitor of about 0.1 F as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device. VCC VSS VCC VSS VSS VCC MB90945 Series VCC VSS VSS VCC 6. Pull-up/pull-down resistors The MB90945 series does not support internal pull-up/pull-down resistors option. Use external components where needed. 7. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits while you design a printed circuit. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. 8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 9. Connection of Unused Pins of A/D Converter if A/D Converter is unused Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on During Operation of PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 15 MB90945 Series BLOCK DIAGRAMS * MB90F946A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 Input Capture 6 channels IN5 to IN0 Output Compare 4 channels OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 UART0 8/16-bit PPG 6 channels PPG05 to PPG00 RAM 16 K bytes Flash 384 K bytes SOT0 SCK0 Prescaler x2 SOT2/3 SCK2/3 SIN2/3 UART2/3 (LIN/SCI/ SPI) Internal data bus SIN0 CAN Interface 1 External Interrupt PPG15 to PPG10 RX1 TX1 INT7 to INT0 Prescaler SOT4 SCK4 Serial I/O I2 C Interface SDA 16-bit Reload Timer 1 channel TIN0 SIN4 AVCC AVSS AN [14:0] AVRH AVRL ADTG 16 10-bit A/D Converter 15 input channel SCL TOT0 MB90945 Series * MB90947A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 Input Capture 6 channels IN5 to IN0 Output Compare 4 channels OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 UART0 8/16-bit PPG 6 channels PPG05 to PPG00 RAM 6 K bytes ROM 128 K bytes SOT0 SCK0 Prescaler SOT3 SCK3 SIN3 UART3 (LIN/SCI/ SPI) Internal data bus SIN0 CAN Interface 1 External Interrupt PPG15 to PPG10 RX1 TX1 INT7 to INT0 Prescaler SOT4 SCK4 Serial I/O I2 C Interface SIN4 AVCC AVSS AN [14:0] AVRH 10-bit A/D Converter 15 input channel 16-bit Reload Timer 1 channel SDA SCL TIN0 TOT0 AVRL ADTG 17 MB90945 Series * MB90F947, MB90F947A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 Input Capture 6 channels IN5 to IN0 Output Compare 4 channels OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 UART0 8/16-bit PPG 6 channels PPG15 to PPG10 RAM 6 K bytes Flash 128 K bytes SOT0 SCK0 Prescaler SOT3 SCK3 SIN3 UART3 (LIN/SCI/ SPI) Internal data bus SIN0 CAN Interface 1 External Interrupt PPG05 to PPG00 RX1 TX1 INT7 to INT0 Prescaler SOT4 SCK4 Serial I/O I2 C Interface SIN4 AVCC AVSS AN14 to AN0 AVRH AVRL ADTG 18 10-bit A/D Converter 15 input channel 16-bit Reload Timer 1 channel SDA SCL TIN0 TOT0 MB90945 Series * MB90F949, MB90F949A X0, X1 RST Clock Controller with Phase Modulator F2MC-16LX CPU IO Timer 0 FRCK0 Input Capture 6 channels IN5 to IN0 Output Compare 4 channels OUT3 to OUT0 Prescaler IO Timer 1 FRCK1 UART0 8/16-bit PPG 6 channels PPG15 to PPG10 RAM 12 K bytes Flash 256 K bytes SOT0 SCK0 Prescaler SOT3 SCK3 SIN3 UART3 (LIN/SCI/ SPI) Internal data bus SIN0 CAN Interface 1 External Interrupt PPG05 to PPG00 RX1 TX1 INT7 to INT0 Prescaler SOT4 SCK4 Serial I/O I2C Interface SDA 16-bit Reload Timer 1 channel TIN0 SIN4 AVCC AVSS AN14 to AN0 AVRH 10-bit A/D Converter 15 input channel SCL TOT0 AVRL ADTG 19 MB90945 Series MEMORY MAP MB90947A MB90F947 MB90F947A MB90F946A FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FFFFFFH FFFFFFH FFFFFFH ROM (FF bank) ROM (FE bank) FF0000H FEFFFFH FE0000H MB90F949 MB90F949A ROM (FF bank) ROM (FE bank) ROM (FD bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FFFFFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H MB90V390HA MB90V390HB ROM (FB bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (FA bank) FA0000H F9FFFFH ROM (F9 bank) F90000H 8017FFH ROM (F9 bank) RAM 6 Kbytes 800000H 00FFFFH 008000H 0050FFH 004100H ROM (Image of FF bank) ROM (Image of FF bank) 004000H/ 008000H 00FFFFH ROM (Image of FF bank) 004000H/ 008000H 00FFFFH 008000H ROM (Image of FF bank) 0070FFH RAM 12 Kbytes RAM 4 Kbytes Peripheral 003500H 0030FFH RAM 12 Kbytes 003500H Peripheral Peripheral Peripheral 003500H 0030FFH 0000BFH 000000H Peripheral 003500H 0030FFH RAM 12 Kbytes 0018FFH 000100H 000100H 004100H 003FFFH 003FFFH 003FFFH 003FFFH 0000BFH 000000H 00FFFFH RAM 6 Kbytes Peripheral 000100H 0000BFH 000000H RAM 12 Kbytes 000100H Peripheral 0000BFH 000000H Peripheral : No access Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32/48 K bytes, and its entire image cannot be shown in bank 00. The image between FF4000H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH/FF7FFFH is visible only in bank FF. 20 MB90945 Series I/O MAP Address Register AbbreviaAccess tion Resource name Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Reserved 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXX 0AH Port A data register PDRA R/W Port A XXXXXXXX 0BH Port B data register PDRB R/W Port B XXXXXXXX 0CH Analog Input Enable 0 ADER0 R/W Port 6, A/D 11111111 0DH Analog Input Enable 1/ ADC Select ADER1 R/W Port B, A/D 01111111 0EH Input Level Select Register (MB90V390HA/MB90V390HB only) ILSR R/W Ports 00000000 0FH Input Level Select Register (MB90V390HA/MB90V390HB only) ILSR R/W Ports 00000000 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 00000000 12H Port 2 direction register DDR2 R/W Port 2 00000000 13H Port 3 direction register DDR3 R/W Port 3 00000000 14H Port 4 direction register DDR4 R/W Port 4 00000000 15H Port 5 direction register DDR5 R/W Port 5 00000000 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Reserved 18H Port 8 direction register DDR8 R/W Port 8 XXXXXX00 19H Port 9 direction register DDR9 R/W Port 9 00000000 1AH Port A direction register DDRA R/W Port A 00000000 1BH Port B direction register DDRB R/W Port B 00000000 1CH to 1FH Reserved (Continued) 21 MB90945 Series Address Register AbbreviaAccess tion Resource name Initial value 20H Serial Mode Control 0 UMC0 R/W 00000100 21H Status 0 USR0 R/W 00010000 22H Input/Output Data 0 UIDR0/ UODR0 R/W 23H Rate and Data 0 URD0 R/W 0000000X XXXX0000 24H to 2BH UART0 XXXXXXXX Reserved 2CH Serial Mode Control 4 SMCS4 R/W 2DH Serial Mode Control 4 SMCS4 R/W 2EH Serial Data 4 SDR4 R/W 2FH Serial I/O Prescaler/Edge Selector 4 CDCR4 R/W 0 X 0 X 0000 30H External Interrupt Enable ENIR R/W 00000000 31H External Interrupt Request EIRR R/W 32H External Interrupt Level ELVR R/W 33H External Interrupt Level ELVR R/W 00000000 34H A/D Control Status 0 ADCS0 R/W 00000000 35H A/D Control Status 1 ADCS1 R/W 36H A/D Data 0 ADCR0 R 37H A/D Data 1 ADCR1 R/W 38H PPG0 operation mode control register PPGC0 R/W 39H PPG1 operation mode control register PPGC1 R/W 3AH PPG0 and PPG1 clock select register PPG01 R/W 3BH External Interrupt A/D Converter 00000010 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX 000000XX 16-bit Programable Pulse Generator 0/1 0X000XX1 0X000001 000000XX Reserved 3CH PPG2 operation mode control register PPGC2 R/W 3DH PPG3 operation mode control register PPGC3 R/W 3EH PPG2 and PPG3 clock select register PPG23 R/W 3FH 16-bit Programable Pulse Generator 2/3 0X000XX1 0X000001 000000XX Reserved 40H PPG4 operation mode control register PPGC4 R/W 41H PPG5 operation mode control register PPGC5 R/W 42H PPG4 and PPG5 clock select register PPG45 R/W 43H 16-bit Programable Pulse Generator 4/5 0X000XX1 0X000001 000000XX Reserved 44H PPG6 operation mode control register PPGC6 R/W 45H PPG7 operation mode control register PPGC7 R/W 46H PPG6 and PPG7 clock select register PPG67 R/W 47H Serial I/O Interface 16-bit Programable Pulse Generator 6/7 0X000XX1 0X000001 000000XX Reserved (Continued) 22 MB90945 Series Address Register AbbreviaAccess tion 48H PPG8 operation mode control register PPGC8 R/W 49H PPG9 operation mode control register PPGC9 R/W 4AH PPG8 and PPG9 clock select register PPG89 R/W 4BH Resource name 16-bit Programable Pulse Generator 8/9 Initial value 0X000XX1 0X000001 000000XX Reserved 4CH PPGA operation mode control register PPGCA R/W 4DH PPGB operation mode control register PPGCB R/W 4EH PPGA and PPGB clock select register PPGAB R/W 4FH 16-bit Programable Pulse Generator A/B 0X000XX1 0X000001 000000XX Reserved 50H Timer Control Status 0 TMCSR0 R/W 51H Timer Control Status 0 TMCSR0 52H to 53H 00000000 R/W 16-bit Reload Timer 0 XXXX0000 Reserved 54H Input Capture Control Status 0/1 ICS01 R/W Input Capture 0/1 00000000 55H Input Capture Control Status 2/3 ICS23 R/W Input Capture 2/3 00000000 56H Input Capture Control Status 4/5 ICS45 R/W Input Capture 4/5 00000000 57H Reserved 58H Output Compare Control Status 0 OCS0 R/W 59H Output Compare Control Status 1 OCS1 R/W 5AH Output Compare Control Status 2 OCS2 R/W 5BH Output Compare Control Status 3 OCS3 R/W 5CH to 6EH 6FH Output Compare 0/1 Output Compare 2/3 0000XX00 0XX00000 0000XX00 0XX00000 Reserved ROM Mirror 70H to 7FH ROMM W ROM Mirror XXXXXXX1 Reserved 80H to 8FH Reserved for CAN Interface 1. Refer to " CAN CONTROLLER" 90H to 9DH Reserved 9EH ROM Correction Control Status 0 9FH Delayed Interrupt/release A0H A1H PACSR0 R/W ROM Correction 0 00000000 DIRR R/W Delayed Interrupt XXXXXXX0 Low-power Mode LPMCR R/W Low Power Controller 00011000 Clock Selector CKSCR R/W Low Power Controller 11111100 A2H to A7H Reserved A8H Watchdog Control WDTC R/W Watchdog Timer XXXXX111 A9H Timebase timer Control TBTC R/W Timebase timer 1XX00100 AAH to ADH Reserved (Continued) 23 MB90945 Series Address Register AEH Flash Control Status (Flash devices only. Otherwise reserved) AbbreviaAccess tion FMCS R/W Resource name Initial value Flash memory 000X0000 Reserved AFH B0H Interrupt control register 00 ICR00 R/W 00000111 B1H Interrupt control register 01 ICR01 R/W 00000111 B2H Interrupt control register 02 ICR02 R/W 00000111 B3H Interrupt control register 03 ICR03 R/W 00000111 B4H Interrupt control register 04 ICR04 R/W 00000111 B5H Interrupt control register 05 ICR05 R/W 00000111 B6H Interrupt control register 06 ICR06 R/W 00000111 B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 00000111 BAH Interrupt control register 10 ICR10 R/W 00000111 BBH Interrupt control register 11 ICR11 R/W 00000111 BCH Interrupt control register 12 ICR12 R/W 00000111 BDH Interrupt control register 13 ICR13 R/W 00000111 BEH Interrupt control register 14 ICR14 R/W 00000111 BFH Interrupt control register 15 ICR15 R/W 00000111 C0H to FFH Interrupt controller 00000111 00000111 Reserved (Continued) 24 MB90945 Series Address Register AbbreviaAccess tion Resource name Initial value XXXXXXXX 3500H Reload L PRLL0 R/W 3501H Reload H PRLH0 R/W 3502H Reload L PRLL1 R/W 3503H Reload H PRLH1 R/W XXXXXXXX 3504H Reload L PRLL2 R/W XXXXXXXX 3505H Reload H PRLH2 R/W 3506H Reload L PRLL3 R/W 3507H Reload H PRLH3 R/W XXXXXXXX 3508H Reload L PRLL4 R/W XXXXXXXX 3509H Reload H PRLH4 R/W 350AH Reload L PRLL5 R/W 350BH Reload H PRLH5 R/W XXXXXXXX 350CH Reload L PRLL6 R/W XXXXXXXX 350DH Reload H PRLH6 R/W 350EH Reload L PRLL7 R/W 350FH Reload H PRLH7 R/W XXXXXXXX 3510H Reload L PRLL8 R/W XXXXXXXX 3511H Reload H PRLH8 R/W 3512H Reload L PRLL9 R/W 3513H Reload H PRLH9 R/W XXXXXXXX 3514H Reload L PRLLA R/W XXXXXXXX 3515H Reload H PRLHA R/W 3516H Reload L PRLLB R/W 3517H Reload H PRLHB R/W XXXXXXXX 3518H Serial Mode Register SMR3 R/W 00000000 3519H Serial Control Register SCR3 R/W 00000000 351AH Reception/Transmission Data Register RDR3/ TDR3 R/W 00000000 351BH Serial Status Register SSR3 R/W 351CH Extended Communication Control Reg. ECCR3 R/W 000000XX 351DH Extended Status/Control Register ESCR3 R/W 00000100 351EH Baud Rate Register 0 BGR03 R/W 00000000 351FH Baud Rate Register 1 BGR13 R/W 00000000 16-bit Programable Pulse Generator 0/1 16-bit Programable Pulse Generator 2/3 16-bit Programable Pulse Generator 4/5 16-bit Programable Pulse Generator 6/7 16-bit Programable Pulse Generator 8/9 16-bit Programable Pulse Generator A/B UART3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001000 (Continued) 25 MB90945 Series Address Register AbbreviaAccess tion Resource name Initial value 3520H Input Capture 0 IPCP0 R 3521H Input Capture 0 IPCP0 R 3522H Input Capture 1 IPCP1 R 3523H Input Capture 1 IPCP1 R XXXXXXXX 3524H Input Capture 2 IPCP2 R XXXXXXXX 3525H Input Capture 2 IPCP2 R 3526H Input Capture 3 IPCP3 R 3527H Input Capture 3 IPCP3 R XXXXXXXX 3528H Input Capture 4 IPCP4 R XXXXXXXX 3529H Input Capture 4 IPCP4 R 352AH Input Capture 5 IPCP5 R 352BH Input Capture 5 IPCP5 R XXXXXXXX 352CH Timer Data 0 TCDT0 R/W 00000000 352DH Timer Data 0 TCDT0 R/W 352EH Timer Control 0 TCCS0 R/W 352FH Timer Control 0 TCCS0 R/W 0XXXXXXX 3530H Output Compare 0 OCCP0 R/W XXXXXXXX 3531H Output Compare 0 OCCP0 R/W 3532H Output Compare 1 OCCP1 R/W 3533H Output Compare 1 OCCP1 R/W XXXXXXXX 3534H Output Compare 2 OCCP2 R/W XXXXXXXX 3535H Output Compare 2 OCCP2 R/W 3536H Output Compare 3 OCCP3 R/W 3537H Output Compare 3 OCCP3 R/W XXXXXXXX 00000000 3538H to 353BH Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 I/O Timer 0 Output Compare 0/1 Output Compare 2/3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved 353CH Timer Data 1 TCDT1 R/W 353DH Timer Data 1 TCDT1 R/W 353EH Timer Control 1 TCCS1 R/W 353FH Timer Control 1 TCCS1 R/W 3540H Timer 0/Reload 0 TMR0/ TMRLR0 R/W 3541H Timer 0/Reload 0 TMR0/ TMRLR0 R/W 3542H to 356DH XXXXXXXX I/O Timer 1 00000000 00000000 0XXXXXXX 16-bit Reload Timer 0 XXXXXXXX XXXXXXXX Reserved (Continued) 26 MB90945 Series Address 356EH Register CAN Direct Mode Register 356FH to 359FH AbbreviaAccess tion CDMR R/W Resource name Initial value CAN clock sync XXXXXXX0 Reserved 35A0H I2C bus status register IBSR R 00000000 35A1H I2C bus control register IBCR R/W 00000000 ITBAL R/W 00000000 ITBAH R/W 00000000 ITMKL R/W 35A2H 35A3H 35A4H 35A5H 35A6H I2C ten bit slave address register I2C ten bit address mask register I2C Interface 11111111 ITMKH R/W 00111111 2 ISBA R/W 00000000 2 I C seven bit slave address register 35A7H I C seven bit address mask register ISMK R/W 01111111 35A8H I2C data register IDAR R/W 00000000 35A9H to 35AAH 35ABH Reserved I2C clock control register 35ACH to 35C8H ICCR R/W I2C Interface 00011111 Reserved 35C9H Input Capture Edge 0/1 ICE01 R/W Input Capture 0/1 XXXXX0XX 35CAH Input Capture Edge 2/3 ICE23 R Input Capture 2/3 XXXXXXXX 35CBH Input Capture Edge 4/5 ICE45 R/W Input Capture 4/5 XXXXX0XX W PLL XXXX0000 35CCH to 35CEH 35CFH Reserved PLL and Special Configuration Control Register 35D0H to 35D7H PSCCR Reserved 35D8H Serial Mode Register SMR2 R/W 00000000 35D9H Serial Control Register SCR2 R/W 00000000 35DAH Reception/Transmission Data Register RDR2/ TDR2 R/W 35DBH Serial Status Register SSR2 R/W 35DCH Extended Communication Control Reg. ECCR2 R/W 35DDH Extended Status/Control Register ESCR2 R/W 00000100 35DEH Baud Rate Register 0 BGR02 R/W 00000000 35DFH Baud Rate Register 1 BGR12 R/W UART2 (MB90V390HA, MB90V390HB and MB90F946A only) UART2 (MB90V390HA, MB90V390HB and MB90F946A only) 00000000 00001000 000000XX 00000000 27 MB90945 Series Address Register AbbreviaAccess tion Resource name Initial value 35E0H ROM Correction Address 0 PADR0 R/W XXXXXXXX 35E1H ROM Correction Address 0 PADR0 R/W XXXXXXXX 35E2H ROM Correction Address 0 PADR0 R/W 35E3H ROM Correction Address 1 PADR1 R/W Address Matching XXXXXXXX Detection Function 0 XXXXXXXX 35E4H ROM Correction Address 1 PADR1 R/W XXXXXXXX 35E5H ROM Correction Address 1 PADR1 R/W XXXXXXXX (Continued) (Continued) Address Register AbbreviaAccess tion 35E6H ROM Correction Address 2 PADR2 R/W 35E7H ROM Correction Address 2 PADR2 R/W 35E8H ROM Correction Address 2 PADR2 R/W Resource name XXXXXXXX Address Matching XXXXXXXX Detection Function 0 XXXXXXXX 35E9H to 37FFH Reserved 3800H to 38FFH Reserved for CAN Interface 1. Refer to " CAN CONTROLLER" 3900H to 39FFH Reserved for CAN Interface 1. Refer to " CAN CONTROLLER" 3A00H to 3FFFH Reserved _ : Unused bit X : Unknown value Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved address results in reading "X". 28 Initial value MB90945 Series CAN CONTROLLER The CAN controller has the following features : * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmitting of data frames by receiving remote frames * 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance mask register 0/acceptance mask register 1 for each message buffer as ID acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz) List of Control Registers (1) Address CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Abbreviation Access Initial Value Message buffer valid register BVALR R/W 00000000 00000000 Transmit request register TREQR R/W 00000000 00000000 Transmit cancel register TCANR W 00000000 00000000 Transmit complete register TCR R/W 00000000 00000000 Receive complete register RCR R/W 00000000 00000000 Remote request receiving register RRTRR R/W 00000000 00000000 Receive overrun register ROVRR R/W 00000000 00000000 Receive interrupt enable register RIER R/W 00000000 00000000 29 MB90945 Series List of Control Registers (2) Address CAN1 003900H 003901H 003902H 003903H 003904H 003905H 003906H 003907H 003908H 003909H 00390AH 00390BH 00390CH 00390DH 00390EH 00390FH Register Abbreviation Access Initial Value Control status register CSR R/W, R 00XXX000 0XXXX0X1 Last event indicator register LEIR R/W XXXXXXXX 000X0000 Receive/transmit error counter RTEC R 00000000 00000000 Bit timing register BTR R/W X1111111 11111111 IDE register IDER R/W XXXXXXXX XXXXXXXX Transmit RTR register TRTRR R/W 00000000 00000000 Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXX Transmit interrupt enable register TIER R/W 00000000 00000000 003910H 003911H 003912H Acceptance mask select register XXXXXXXX XXXXXXXX AMSR R/W XXXXXXXX XXXXXXXX 003913H 003914H 003915H 003916H XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX 003917H 003918H 003919H 00391AH 00391BH 30 XXXXXXXX XXXXXXXX Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX MB90945 Series List of Message Buffers (ID Registers) (1) Address CAN1 003800H to 00381FH Register Abbreviation Access Initial Value Generalpurpose RAM R/W XXXXXXXX to XXXXXXXX 003820H 003821H 003822H XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX 003823H 003824H 003825H 003826H XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX 003827H 003828H 003829H 00382AH XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX 00382BH 00382CH 00382DH 00382EH XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX 00382FH 003830H 003831H 003832H XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX 003833H 003834H 003835H 003836H XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX 003837H 003838H 003839H 00383AH XXXXXXXX XXXXXXXX ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX 00383BH 00383CH 00383DH 00383EH 00383FH XXXXXXXX XXXXXXXX ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX 31 MB90945 Series List of Message Buffers (ID Registers) (2) Address CAN1 Register Abbreviation Access 003840H 003841H 003842H XXXXXXXX XXXXXXXX ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX 003843H 003844H 003845H 003846H XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX 003847H 003848H 003849H 00384AH XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX 00384BH 00384CH 00384DH 00384EH XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX 00384FH 003850H 003851H 003852H XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX 003853H 003854H 003855H 003856H XXXXXXXX XXXXXXXX ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX 003857H 003858H 003859H 00385AH XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX 00385BH 00385CH 00385DH 00385EH 00385FH 32 Initial Value XXXXXXXX XXXXXXXX ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX MB90945 Series List of Message Buffers (DLC Registers and Data Registers) (1) Address CAN1 003860H 003861H 003862H 003863H 003864H 003865H 003866H 003867H 003868H 003869H 00386AH 00386BH 00386CH 00386DH 00386EH 00386FH 003870H 003871H 003872H 003873H 003874H 003875H 003876H 003877H 003878H 003879H 00387AH 00387BH 00387CH 00387DH 00387EH 00387FH Register Abbreviation Access Initial Value DLC register 0 DLCR0 R/W XXXXXXXX DLC register 1 DLCR1 R/W XXXXXXXX DLC register 2 DLCR2 R/W XXXXXXXX DLC register 3 DLCR3 R/W XXXXXXXX DLC register 4 DLCR4 R/W XXXXXXXX DLC register 5 DLCR5 R/W XXXXXXXX DLC register 6 DLCR6 R/W XXXXXXXX DLC register 7 DLCR7 R/W XXXXXXXX DLC register 8 DLCR8 R/W XXXXXXXX DLC register 9 DLCR9 R/W XXXXXXXX DLC register 10 DLCR10 R/W XXXXXXXX DLC register 11 DLCR11 R/W XXXXXXXX DLC register 12 DLCR12 R/W XXXXXXXX DLC register 13 DLCR13 R/W XXXXXXXX DLC register 14 DLCR14 R/W XXXXXXXX DLC register 15 DLCR15 R/W XXXXXXXX 33 MB90945 Series List of Message Buffers (DLC Registers and Data Registers) (2) Address Register Abbreviation Access Initial Value 003880H to 003887H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX to XXXXXXXX 003888H to 00388FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXX to XXXXXXXX 003890H to 003897H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX to XXXXXXXX 003898H to 00389FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXX to XXXXXXXX 0038A0H to 0038A7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX to XXXXXXXX 0038A8H to 0038AFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXX to XXXXXXXX 0038B0H to 0038B7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX to XXXXXXXX 0038B8H to 0038BFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXX to XXXXXXXX 0038C0H to 0038C7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXX to XXXXXXXX 0038C8H to 0038CFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXX to XXXXXXXX 0038D0H to 0038D7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXX to XXXXXXXX 0038D8H to 0038DFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXX to XXXXXXXX 0038E0H to 0038E7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXX to XXXXXXXX 0038E8H to 0038EFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXX to XXXXXXXX CAN1 34 MB90945 Series List of Message Buffers (DLC Registers and Data Registers) (3) Address Register Abbreviation Access Initial Value 0038F0H to 0038F7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXX to XXXXXXXX 0038F8H to 0038FFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXX to XXXXXXXX CAN1 35 MB90945 Series INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause EI2OS clear Interrupt vector Interrupt control register Number Address Number Address Reset N/A #08 FFFFDCH INT9 instruction N/A #09 FFFFD8H Exception N/A #10 FFFFD4H Timebase timer N/A #11 FFFFD0H External Interrupt INT0 to INT7 #12 FFFFCCH ICR00 0000B0H Reserved #13 FFFFC8H Reserved #14 FFFFC4H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH CAN 1 RX N/A #15 FFFFC0H CAN 1 TX/NS N/A #16 FFFFBCH PPG 0/1 N/A #17 FFFFB8H PPG 2/3 N/A #18 FFFFB4H PPG 4/5 N/A #19 FFFFB0H PPG 6/7 N/A #20 FFFFACH PPG 8/9 N/A #21 FFFFA8H PPG A/B N/A #22 FFFFA4H 16-bit Reload Timer 0 #23 FFFFA0H Reserved #24 FFFF9CH Input Capture 0/1 #25 FFFF98H Output compare 0/1 #26 FFFF94H Input Capture 2/3 #27 FFFF90H Output Compare 2/3 #28 FFFF8CH Input Capture 4/5 #29 FFFF88H IC #30 FFFF84H A/D Converter #31 FFFF80H #32 FFFF7CH Serial I/O #33 FFFF78H Reserved #34 FFFF74H UART 0 RX #35 FFFF70H UART 0 TX #36 FFFF6CH Reserved #37 FFFF68H Reserved #38 FFFF64H 2 I/O Timer 0 / I/O Timer 1 N/A (Continued) 36 MB90945 Series (Continued) Interrupt cause EI2OS clear Interrupt vector Number Address UART 2 RX / UART 3 RX #39 FFFF60H UART 2 TX / UART 3 TX #40 FFFF5CH Flash memory N/A #41 FFFF58H Delayed interrupt N/A #42 FFFF54H Interrupt control register Number Address ICR14 0000BEH ICR15 0000BFH : The interrupt request flag is cleared by the EI2OS interrupt clear signal. : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. : Unavailable N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. Notes : * For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. * At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. * If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. 37 MB90945 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC *2 AVRH, AVRL VSS - 0.3 VSS + 6.0 V AVCC AVRH, AVCC AVRL, AVRH AVRL VI VSS - 0.3 VSS + 6.0 V *3 VO VSS - 0.3 VSS + 6.0 V *3 ICLAMP -4.0 +4.0 mA *5 |ICLAMP| 40 mA *5 IOL1 15 mA *4 "L" level average output current IOLAV1 4 mA *4 "L" level maximum overall output current IOL1 100 mA *4 "L" level average overall output current IOLAV1 50 mA *4 IOH1 -15 mA *4 "H" level average output current IOHAV1 -4 mA *4 "H" level maximum overall output current IOH1 -100 mA *4 "H" level average overall output current IOHAV -50 mA *4 500 525 TA -40 +105 C TSTG -55 +150 C Power supply voltage*1 Input voltage*1 Output voltage* 1 Maximum Clamp Current Total Maximum Clamp Current "L" level maximum output current "H" level maximum output current Power consumption Operating temperature Storage temperature PD MB90947A/F947/F947A/F949/ mW F949A MB90F946A *1 : This parameter is based on VSS = AVSS = 0 V. *2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7 *5 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7 * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. 38 MB90945 Series * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits : * Input/output equivalent circuits Protective diode VCC Limiting resistance Pch +B input (0 V to 16 V) Nch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 39 MB90945 Series 2. Recommended Conditions (VSS = AVSS = 0 V) Parameter Power supply voltage Symbol VCC, AVCC Value Unit Remarks Min Typ Max 3.5 5.0 5.5 V Other than when writing to Flash memory and when using the A/D converter 4.0 5.0 5.5 V When writing to Flash memory 4.5 5.0 5.5 V When using the A/D converter 2.0 5.5 V Retain RAM data in stop mode * Smoothing capacitor CS 0.1 1.0 F Operating temperature TA -40 +105 C * : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the VCC pin, use a bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of smoothing capacitor CS. * C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 40 MB90945 Series 3. DC Characteristics (TA = -40 C to +105 C, VCC = 5.0 V 10%, VSS = AVSS = 0 V) Parameter Input "H" voltage Input "L" voltage Symbol Pin Condition VIHA VIHS Value Unit Remarks VCC + 0.3 V Port inputs except ports P21/RX1, P42/SDA, P43/SCL VCC + 0.3 V Port inputs P21/ RX1, P42/SDA, P43/SCL 0.8 VCC VCC + 0.3 V RST input pin (CMOS Hysteresis) VCC - 0.3 VCC + 0.3 V MD input pin VSS - 0.3 0.5 VCC V Port inputs except ports P21/RX1, P42/SDA, P43/SCL VILS VSS - 0.3 0.3 VCC V Port inputs P21/ RX1, P42/SDA, P43/SCL VILR VSS - 0.3 0.2 VCC V RST input pin (CMOS Hysteresis) VILM VSS - 0.3 VSS + 0.3 V MD input pin Min Typ Max 0.8 VCC 0.7 VCC VIHR VIHM VILA Output "H" voltage VOH Normal outputs VCC = 4.5 V, IOH1 = -4.0 mA VCC - 0.5 V Output "H" voltage VOHI I2C outputs VCC = 4.5 V, IOH1 = -3.0 mA VCC - 0.5 V Output "L" voltage VOL Normal outputs VCC = 4.5 V, IOL1 = 4.0 mA 0.4 V Output "L" voltage VOLI I2C outputs VCC = 4.5 V, IOL1 = 3.0 mA 0.4 V Input leak current IIL VCC = 5.5 V, VSS < VI < VCC -1 1 A (Continued) 41 MB90945 Series (Continued) Parameter Pull-down resistance (TA = -40 C to +105 C, VCC = 5.0 V 10%, VSS = AVSS = 0 V) Symbol Pin Condition RDOWN MD2 VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation. VCC = 5.0 V, Internal frequency : 20 MHz, At normal operation. ICC VCC = 5.0 V, Internal frequency : 20 MHz, At writing FLASH memory. VCC = 5.0 V, Internal frequency : 20 MHz, At erasing FLASH memory. Power supply current* VCC ICCS ICTS VCC = 5.0 V, Internal frequency : 2 MHz, At Main Timebase timer mode ICTSPLL6 VCC = 5.0 V, Internal frequency : 24 MHz, At PLL Timebase timer mode, external frequency = 4 MHz ICCH Input capacity VCC = 5.0 V, Internal frequency : 24 MHz, At Sleep mode. CIN Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS Unit Remarks Min Typ Max 25 50 100 kOhm 60 75 mA MB90947A MB90F947/A MB90F949/A 65 85 mA MB90F946A 50 65 mA MB90947A MB90F947/A MB90F949/A 55 75 mA MB90F946A 65 80 mA MB90F947/A MB90F949/A 70 90 mA MB90F946A 70 85 mA MB90F947/A MB90F949/A 75 95 mA MB90F946A 25 35 mA MB90947A MB90F947/A MB90F949/A 28 40 mA MB90F946A mA MB90947A MB90F946A MB90F947/A MB90F949/A mA MB90947A MB90F946A MB90F947/A MB90F949/A MB90947A MB90F946A MB90F947/A MB90F949/A 0.3 5 0.6 7 VCC = 5.0 V, At Stop mode, TA = +25C 5 100 A 5 15 pF * : The power supply current is measured with an external clock. 42 Value only ROM devices MB90945 Series 4. AC Characteristics (1) Clock Timing (TA = -40 C to +105 C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0 V) Value Parameter Symbol Pin X0, X1 Clock frequency fC X0 8 8 MHz 4 8 MHz PLL x 1 When using an oscillation circuit 4 8 8 MHz PLL x 2 When using an oscillation circuit 4 6.67 MHz PLL x 3 When using an oscillation circuit x 1/2 (When PLL stops) When using an oscillation circuit 4 5 6 MHz PLL x 4 When using an oscillation circuit 4 MHz PLL x 6 When using an oscillation circuit 3 12 12 MHz 4 12 MHz PLL x 1 When using an external circuit 4 10 12 MHz PLL x 2 When using an external circuit 4 6.67 MHz PLL x 3 When using an external circuit 4 5 6 MHz PLL x 4 When using an external circuit 4 4 MHz PLL x 6 When using an external circuit x 1/2 (When PLL stops) When using an external circuit 333 ns When using an oscillation circuit X0, X1 83.33 333 ns When using an external clock ns Duty ratio is about 30% to 70%. 5 ns When using external clock 1.5 24 MHz Except programming or erasing Flash memory. 1.5 20 When programming or erasing Flash memory. MHz Be sure that the maximum momentary frequency Fmax does not exceed 20MHz. 41.67 666 ns Except programming or erasing Flash memory. 666 ns When programming or erasing Flash memory. X0, X1 125 PWH, PWL X0 20 Input clock rise and fall time tCR, tCF X0 tCP CS2 = 0 CS2 = 1 4 Input clock pulse width Machine clock cycle time Remarks 3 tCYL fCP Unit Typ Clock cycle time Machine clock frequency Max Min 50 * Clock Timing tCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF tCR 43 MB90945 Series * Guaranteed PLL operation range Guaranteed operation range Guaranteed PLL operation range (CS2=1) Power supply voltage VCC (V) 5.5 Guaranteed A/D converter operation range 4.5 3.5 Guaranteed PLL operation range (CS2=0) 1.5 4 8 20 24 Machine clock fCP (MHz) Guaranteed operation range of MB90F947/MB90F949 * CS2 (bit 0 in PSCCR register) = 0 Machine clock fCP (MHz) Guaranteed oscilation frequency range x4 (CS=011) x3 (CS=010) 20 x2 (CS=001) 16 x1*1 (CS=000) 12 8 6 4 1.5 x1/2 (PLL off) 3 4 6 8 10 12 External clock fC (MHz)*2 * CS2 (bit 0 in PSCCR register) = 1 Guaranteed oscilation frequency range x6 (CS=110) x4 (CS=101) x2 (CS=100) Machine clock fCP (MHz) 24 16 8 6 x1/2 (PLL off) 1.5 3 4 6 8 10 12 External clock fC (MHz)*2 *1 : PLL x 1 guaranteed operation range is from 4.0 MHz to 12 MHz. *2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz External clock frequency and Machine clock frequency 44 MB90945 Series (2) Reset Standby Input (TA = -40 C to +105 C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V) Parameter Reset input time Symbol tRSTL Pin RST Value Unit Remarks Min Max 16 tCP*1 ns Under normal operation Oscillation time of oscillator*2 + 100 + 16 tCP*1 s In Stop mode 100 s In Timebase timer mode *1 : "tCP" represents one cycle time of the machine clock. No reset can fully initialize the Flash memory if it is performing the automatic algorithm. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators, the oscillation time is between hundreds of s to several ms. With an external clock, the oscillation time is 0 ms. Under normal operation : tRSTL RST 0.2 VCC 0.2 VCC In Stop mode : tRSTL RST 0.2 VCC X0 0.2 VCC 90% of amplitude Internal operation clock 16 tCP Oscillation time of oscillator +100 s Oscillation stabilization waiting time Instruction execution Internal reset 45 MB90945 Series (3) Power On Reset (TA = -40 C to +105 C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Power on rise time tR VCC tOFF VCC Power off time Condition Value Unit Min Max 0.05 30 ms 1 ms Remarks Due to repetitive operation tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. VCC We recommend a rise of 50 mV/ms maximum. 3V VSS 46 Holds RAM data MB90945 Series (4) UART0, SIO Timing (TA = -40 C to +105 C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V) Symbol Pin Serial clock cycle time tSCYC SCK0, SCK4 SCK SOT delay time tSLOV SCK0, SCK4, SOT0, SOT4 Valid SIN SCK tIVSH SCK0, SCK4, SIN0, SIN4 SCK Valid SIN hold time tSHIX Serial clock "H" pulse width Parameter Condition Value Unit Min Max 8 tCP ns -80 +80 ns 100 ns SCK0, SCK4, SIN0, SIN4 60 ns tSHSL SCK0, SCK4 4 tCP ns Serial clock "L" pulse width tSLSH SCK0, SCK4 4 tCP ns SCK SOT delay time tSLOV SCK0, SCK4, SOT0, SOT4 150 ns Valid SIN SCK tIVSH SCK0, SCK4, SIN0, SIN4 60 ns SCK Valid SIN hold time tSHIX SCK0, SCK4, SIN0, SIN4 60 ns Internal clock operation output pins are CL = 80 pF + 1 TTL. External clock operation output pins are CL = 80 pF + 1 TTL. Remarks Notes : * AC characteristics in CLK synchronized mode. * CL is load capacity value of pins when testing. * tCP is the machine clock cycle time (Unit : ns) . Refer to " (1) Clock timing" rating for tCP. 47 MB90945 Series * Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX VIH VIH VIL VIL * External Shift Clock Mode tSLSH tSHSL VIH VIH SCK VIL VIL tSLOV SOT 2.4 V 0.8 V tIVSH SIN 48 tSHIX VIH VIH VIL VIL MB90945 Series (5) UART2/3 Timing * Bit setting : ESCR : SCES = 0, ECCR : SCDE = 0 (TA = -40 C to +105 C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0V) Symbol Pin Serial clock cycle time tSCYC SCK2,SCK3 SCK SOT delay time tSLOVI Valid SIN SCK tIVSHI SCK Valid SIN hold time tSHIXI Serial clock "H" pulse width tSHSL SCK2,SCK3 Serial clock "L" pulse width tSLSH SCK2,SCK3 SCK SOT delay time tSLOVE Valid SIN SCK tIVSHE SCK Valid SIN hold time tSHIXE Parameter Condition Value Unit Remarks Min Max 5 tCP ns +50 ns ns ns tCP + 10 ns 3 tCP - tR ns 2 tCP + 60 ns 30 ns SIN2,SIN3 tCP + 30 ns SCK2,SCK3 -50 SOT2,SOT3 Internal clock operation output SCK2,SCK3 pins are tCP + 80 SIN2,SIN3 CL = 80 pF + 1 TTL. SCK2,SCK3 0 SIN2,SIN3 SCK2,SCK3 SOT2,SOT3 External clock SCK2,SCK3 operation output SIN2,SIN3 pins are SCK2,SCK3 CL = 80 pF + 1 TTL. SCK fall time tF SCK2,SCK3 10 ns SCK rise time tR SCK2,SCK3 10 ns Note : tCP is the machine clock cycle time (Unit : ns) . Refer to " (1) Clock timing" rating for tCP. * Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOVI SOT 2.4 V 0.8 V tIVSHI SIN tSHIXI VIH VIH VIL VIL 49 MB90945 Series * External Shift Clock Mode tSLSH tSHSL VIH VIH SCK VIL VIL tF tSLOVE tR 2.4 V SOT 0.8 V tIVSHE SIN tSHIXE VIH VIH VIL VIL * Bit setting : ESCR : SCES = 1, ECCR : SCDE = 0 (TA = -40 C to +105 C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V) Symbol Pin Serial clock cycle time tSCYC SCK2,SCK3 SCK SOT delay time tSHOVI Valid SIN SCK tIVSLI SCK Valid SIN hold time tSLIXI Serial clock "H" pulse width tSHSL SCK2,SCK3 Serial clock "L" pulse width tSLSH SCK2,SCK3 SCK SOT delay time tSHOVE SCK2,SCK3 SOT2,SOT3 Valid SIN SCK tIVSLE SCK Valid SIN hold time tSLIXE Parameter Condition Value Max 5 tCP ns +50 ns ns ns 3 tCP - tR ns tCP + 10 ns SCK2,SCK3 -50 SOT2,SOT3 Internal clock operation output SCK2,SCK3 pins are tCP + 80 SIN2,SIN3 CL = 80 pF + 1 TTL. SCK2,SCK3 0 SIN2,SIN3 2 tCP + 60 External clock SCK2,SCK3 operation output 30 SIN2,SIN3 pins are C SCK2,SCK3 L = 80 pF + 1 TTL. tCP + 30 SIN2,SIN3 ns ns ns SCK fall time tF SCK2,SCK3 10 ns SCK rise time tR SCK2,SCK3 10 ns Note : tCP is the machine clock cycle time (Unit : ns) . Refer to " (1) Clock timing" rating for tCP. 50 Unit Remarks Min MB90945 Series * Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSHOVI 2.4 V SOT 0.8 V tIVSLI SIN tSLIXI VIH VIH VIL VIL * External Shift Clock Mode tSHSL VIL tR SOT VIH VIH SCK tSLSH tSHOVE VIL tF 2.4 V 0.8 V tIVSLE SIN tSLIXE VIH VIH VIL VIL 51 MB90945 Series * Bit setting : ESCR : SCES = 0, ECCR : SCDE = 1 (TA = -40 C to +105 C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V) Symbol Pin Serial clock cycle time tSCYC SCK SOT delay time tSHOVI Valid SIN SCK tIVSLI SCK Valid SIN hold time tSLIXI SOT SCK delay time tSOVLI Parameter Value Condition Max SCK2,SCK3 5 tCP ns SCK2,SCK3 SOT2,SOT3 -50 +50 ns Internal clock SCK2,SCK3 tCP + 80 operation output SIN2,SIN3 pins are SCK2,SCK3 CL = 80 pF + 1 TTL. 0 SIN2,SIN3 ns ns 3 tCP - 70 ns SCK2,SCK3 SOT2,SOT3 Note : tCP is the machine clock cycle time (Unit : ns) . Refer to " (1) Clock timing" rating for tCP. tSCYC 2.4 V SCK 0.8 V 0.8 V tSHOVI tSOVLI SOT 2.4 V 2.4 V 0.8 V 0.8 V tIVSLI SIN 52 VIH VIL Unit Min tSLIXI VIH VIL Remarks MB90945 Series * Bit setting : ESCR : SCES = 1, ECCR : SCDE = 1 (TA = -40 C to +105 C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V) Symbol Pin Serial clock cycle time tSCYC SCK SOT delay time tSLOVI Valid SIN SCK tIVSHI SCK Valid SIN hold time tSHIXI SOT SCK delay time tSOVHI Parameter Value Condition Unit Min Max SCK2,SCK3 5 tCP ns SCK2,SCK3 SOT2,SOT3 -50 +50 ns Internal clock SCK2,SCK3 tCP + 80 operation output SIN2,SIN3 pins are SCK2,SCK3 CL = 80 pF + 1 TTL. 0 SIN2,SIN3 ns ns 3 tCP - 70 ns SCK2,SCK3 SOT2,SOT3 Remarks Note : tCP is the machine clock cycle time (Unit : ns) . Refer to " (1) Clock timing" rating for tCP. tSCYC 2.4 V 2.4 V SCK 0.8 V tSLOVI tSOVHI SOT 2.4 V 2.4 V 0.8 V 0.8 V tIVSHI SIN tSHIXI VIH VIH VIL VIL 53 MB90945 Series (6) Trigger Input Timing (TA = -40 C to +105 C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol Pin Condition tTRGH tTRGL INT0 to INT7 ADTG Value Unit Min Max 200 ns tCP + 200 ns Remarks Note : tCP is the machine clock cycle time (Unit : ns) . Refer to " (1) Clock timing" rating for tCP. * Trigger Input Timing VIH VIH VIL VIL tTRGH tTRGL (7) Timer Related Resource Input Timing (TA = -40 C to +105 C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol Pin Condition tTIWH TIN0, IN0 to IN5 tTIWL Value Min Max 4 tCP Unit ns Note : tCP is the machine clock cycle time (Unit : ns) . Refer to " (1) Clock timing" rating for tCP. * Timer Input Timing VIH VIH VIL VIL tTIWH 54 tTIWL Remarks MB90945 Series (8) I2C Timing (TA = -40 C to +105 C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V) Standard-mode Fast-mode*4 Unit Symbol Condition Min Max Min Max Parameter fSCL 0 100 0 400 kHz tHDSTA 4.0 0.6 s "L" width of SCL clock tLOW 4.7 1.3 s "H" width of SCL clock tHIGH 4.0 0.6 s Set-up time for a repeated START condition SCL SDA tSUSTA 4.7 0.6 s Data hold time SCL SDA tHDDAT 0 3.45*2 0 0.9*3 s Data set-up time SDA SCL tSUDAT 250 100 ns Set-up time for STOP condition SCL SDA tSUSTO 4.0 0.6 s tBUS 4.7 1.3 s SCL clock frequency Hold time (repeated) START condition SDA SCL Bus free time between STOP and START condition R = 1.3 k, C = 50 pF*1 *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT only has to be met if the devie does not stretch the "L" width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz. * I2C Timing SDA tBUS tSUDAT tLOW tHDSTA SCL tHDSTA tHDDAT tHIGH tSUSTA tSUSTO 55 MB90945 Series 5. A/D Converter (TA = -40 C to +105 C, 3.0 V AVRH - AVRL, VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0 V) Parameter Value Symbol Pin Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage VOT AN0 to AN14 AVRL - 1.5 AVRL + 0.5 AVRL + 2.5 LSB Full scale reading voltage VFST AN0 to AN14 AVRH - 3.5 AVRH - 1.5 AVRH + 0.5 LSB Min Typ Max Unit 10 bit 3.0 LSB 2.5 LSB 1.9 LSB Compare time 3.3 66 tCP 16500 s Sampling time 1.6 32 tCP s Analog port input current IAIN AN0 to AN14 -0.3 +0.3 A Analog input voltage range VAIN AN0 to AN14 AVRL AVRH V AVRH AVRL + 2.7 AVCC V AVRL 0 AVRH - 2.7 V IA AVCC 3.5 7.5 mA IAH AVCC 5 Reference voltage range Power supply current Reference voltage current IR AVRH 165 250 IRH AVRH 5 Offset between input channels AN0 to AN14 4 Remarks A * A A * LSB * : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) . Terminology Conversion error : Absolute maximum conversion deviation with respect to the theoretical conversion line. Nonlinearity : Relative maximum conversion deviation with respect to the theoretical conversion line conncecting to the device unigque zero reading voltage and full scale reading voltage. Differential nonlinearity : Max conversion deviation in any two adjacent reading voltages with respect to the theoretical LSB conversion step. Zero reading voltage : Input voltage which results in the minimum conversion value. Full scale reading voltage : Input voltage which results in the maximum conversion value. Notes : * tCP is the machine clock cycle time (Unit : ns) . Refer to "4. AC Characteristics (1) Clock timing" rating for tCP. * The accuracy gets worse as |AVRH - AVRL| becomes smaller. 56 MB90945 Series 6. Definition of A/D Converter Terms Resolution Linear error Differential linear error Total error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( "00 0000 0000" "00 0000 0001" ) and full-scale transition line ( "11 1111 1110" "11 1111 1111" ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FFH 3FEH Actual conversion characteristics 1.5 LSB Digital output 3FDH {1 LSB x (N - 1) + 0.5 LSB} 004H VNT (Actually-measured value) 003H 002H Actual conversion characteristics Ideal characteristics 001H 0.5 LSB AVRL AVRH Analog input VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVRH - AVRL 1 LSB (Ideal value) = [V] 1024 VOT (Ideal value) = AVRL + 0.5 LSB [V] Total error of digital output "N" = [LSB] VFST (Ideal value) = AVRH - 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N - 1) to N. (Continued) 57 MB90945 Series (Continued) Linear error Differential linear error Ideal characteristics 3FFH Actual conversion characteristics {1 LSB x (N - 1) + VOT } Digital output 3FDH N+1 VFST (actual measurement value) VNT (actual measurement value) 004H Actual conversion characteristics 003H Digital output 3FEH Actual conversion characteristics N V (N + 1) T (actual measurement value) VNT (actual measurement value) N-1 002H Ideal characteristics Actual conversion characteristics N-2 001H VOT (actual measurement value) AVRL AVRH AVRL AVRH Analog input Analog input Linear error of digital output N = Differential linear error of digital output N = 1 LSB = VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N+1) T - VNT 1 LSB VFST - VOT 1022 -1 LSB [LSB] [V] VOT : Voltage at which digital output transits from "000H" to "001H." VFST : Voltage at which digital output transits from "3FEH" to "3FFH." 58 [LSB] MB90945 Series 7. Notes on A/D Converter Section * About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model R Analog input Comparator C During sampling : ON R MB90F946A/947A/ F947/F947A/F949/ F949A Note : The values are reference values. C 2.4 k (Max) 36.4 pF (Max) * To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 20 k) (External impedance = 0 k to 100 k) MB90F947 MB90F949 20 90 External impedance [k] External impedance [k] 100 MB90F947 MB90F949 80 70 60 50 40 30 20 10 0 18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 0 Minimum sampling time [s] 1 2 3 4 5 6 7 8 Minimum sampling time [s] * If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * About the error The accuracy gets worse as |AVRH - AVRL| becomes smaller. 59 MB90945 Series 8. Flash Memory Program/Erase Characteristics Parameter Conditions Sector erase time Chip erase time TA = +25 C VCC = 5.0 V Word (16-bit width) programming time Value Unit Remarks Min Typ Max 1 15 s Excludes programming prior to erasure 5 s MB90F947, Excludes programming prior to erasure 7 s MB90F949, Excludes programming prior to erasure 16 3,600 s Except for the overhead time of the system Program/Erase cycle 10,000 cycle Flash Data Retention Time Average TA = +85 C 20 Year * * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) . 60 MB90945 Series EXAMPLE CHARACTERISTICS *MB90F947 ICC - VCC ICCS - VCC TA = +25 C, at external clock operating f = Internal operation frequency TA = +25 C, at external clock operating f = Internal operation frequency 60 30 50 f = 20 MHz f = 16 MHz 30 f = 12 MHz 20 f = 10 MHz 10 f = 4 MHz 20 ICCS [mA] 40 ICC [mA] 25 f = 24 MHz f = 24 MHz 15 f = 20 MHz f = 16 MHz 10 f = 12 MHz f = 10 MHz f = 8 MHz f = 8 MHz 5 f = 4 MHz f = 2 MHz f = 2 MHz 0 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 2.0 7.0 3.0 6.0 7.0 ICTSPLL6 - VCC ICTS - VCC TA = +25 C, at external clock operating f = Internal operation frequency TA = +25 C, at external clock operating f = Internal operation frequency 500 10 450 9 400 8 350 7 300 250 f = 2 MHz 200 ICTSPLL6 [mA] ICTS [A] 4.0 5.0 VCC [V] 6 5 4 150 3 100 2 50 1 f = 24 MHz 0 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 (Continued) 61 MB90945 Series (Continued) ICCH - VCC TA = +25 C, at stop 10 9 8 ICCH [A] 7 6 5 4 3 2 1 0 2.0 62 3.0 4.0 5.0 VCC [V] 6.0 7.0 MB90945 Series *MB90F949 ICC - VCC ICCS - VCC TA = +25 C, at external clock operating f = Internal operation frequency TA = +25 C, at external clock operating f = Internal operation frequency 60 30 f = 24 MHz 50 f = 20 MHz 40 20 f = 16 MHz 30 f = 12 MHz 20 f = 10 MHz 10 f = 4 MHz ICCS [mA] ICC [mA] 25 f = 24 MHz f = 20 MHz 15 f = 16 MHz 10 f = 8 MHz f = 12 MHz f = 10 MHz f = 8 MHz f = 4 MHz f = 2 MHz 5 f = 2 MHz 0 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 2.0 7.0 3.0 ICTS - VCC 9 400 8 350 7 300 250 f = 2 MHz ICTSPLL6 [mA] ICTS [A] 10 450 6 5 4 150 3 100 2 50 1 0 3.0 4.0 5.0 VCC [V] 6.0 7.0 TA = +25 C, at external clock operating f = Internal operation frequency 500 2.0 6.0 ICTSPLL6 - VCC TA = +25 C, at external clock operating f = Internal operation frequency 200 4.0 5.0 VCC [V] 7.0 f = 24 MHz 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 (Continued) 63 MB90945 Series (Continued) ICCH - VCC TA = +25 C, at stop 10 9 8 ICCH [A] 7 6 5 4 3 2 1 0 2.0 64 3.0 4.0 5.0 VCC [V] 6.0 7.0 MB90945 Series *I/O Characteristic (VCC-VOH) - IOH VOL - IOL TA = +25 C, VCC = 4.5 V TA = +25 C, VCC = 4.5 V 900 700 VOL (mV) VCC-VOH (mV) 800 600 500 400 300 200 100 0 0 1 2 3 4 5 6 IOH (mA) 8 7 9 1000 900 800 700 600 500 400 300 200 100 0 0 10 1 2 3 5 4 6 Automotive VIN - VCC VIN (V) VIN (V) 3.0 3.5 4.0 4.5 5.0 VCC (V) 9 10 CAN RX pin, I2C pin TA = +25 C VIHA VILA 2.5 8 CMOS VIN - VCC TA = +25 C 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 7 IOL (mA) 5.5 6.0 6.5 7.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VIHS VILS 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VCC (V) 65 MB90945 Series ORDERING INFORMATION Part number 66 Package MB90F946APF 100-pin Plastic QFP (FPT-100P-M06) MB90947APF 100-pin Plastic QFP (FPT-100P-M06) MB90F947PF 100-pin Plastic QFP (FPT-100P-M06) MB90F947APF 100-pin Plastic QFP (FPT-100P-M06) MB90F949PF 100-pin Plastic QFP (FPT-100P-M06) MB90F949APF 100-pin Plastic QFP (FPT-100P-M06) Remarks It is recommended to use MB90F947A, because MB90F947 does not support clock modulation and CAN at the same time It is recommended to use MB90F949A, because MB90F949 does not support clock modulation and CAN at the same time MB90V390HACR 299-pin Ceramic PGA (PGA-299C-A01) For evaluation It is recommended to use MB90V390HB MB90V390HBCR 299-pin Ceramic PGA (PGA-299C-A01) For evaluation MB90945 Series PACKAGE DIMENSIONS Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 100-pin Plastic QFP (FPT-100P-M06) 23.900.40(.941.016) * 20.000.20(.787.008) 80 51 50 81 0.10(.004) 17.900.40 (.705.016) *14.000.20 (.551.008) INDEX Details of "A" part 1 30 0.65(.026) "A" C 0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 31 100 0.320.05 (.013.002) 0.13(.005) M 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off) 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 67 MB90945 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0507 (c) 2005 FUJITSU LIMITED Printed in Japan