1
®
FN8130.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5168, X5169
(Replaces X25268, X25169)
CPU Supervisor with 16Kbit SPI EEPROM
These devices comb ine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Blo ck Lock
Protect Serial EEPROM Memory in one p ackag e. This
combination lowers system cost, reduces boa rd sp ace
requirement s, and increa ses reliab ility.
Applying power to the device acti vates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions by holding
RESET/RESET active when VCC falls below a minimum VCC
trip point. RESET/RESET remains asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold in
applications requiring higher precision.
Features
•Low V
CC Detection and Reset Assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock™ protection
- In circuit programmable ROM mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply
Operation
• Available Packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Block Diagram
Data
Register
Command
Decode &
Control
Logic
SI
SO
SCK
CS
V
CC
Reset
Timebase
Power-on and
Generation
V
TRIP
+
-
RESET/RESET
Reset
Low Voltage
Status
Register
Protect Logic
4Kbits
4Kbits
8Kbits
EEPROM Array
WP
X5168 = RESET
X5169 = RESET
Data Sheet June 15, 2006
2FN8130.2
June 15, 2006
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW) PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH) PART
MARKING VCC RANGE
(V) VTRIP RANGE
(V) TEMP
RANGE (°C) PACKAGE PKG.
DWG #
X5168P-4.5A X5168P AL X5169P-4.5A X5169P AL 4.5-5.5 4.5-4.75 0 to 70 8 Ld PDIP MDP0031
X5168PZ-4.5A
(Note) X5168P Z AL X5169PZ-4.5A
(Note) X5169P Z AL 0 to 70 8 Ld PDIP**
(Pb-free) MDP0031
X5168PI-4.5A X5168P AM X5169PI-4.5A X5169P AM -40 to 85 8 Ld PDIP MDP0031
X5168PIZ-4.5A
(Note) X5168P Z AM X5169PIZ-4.5A
(Note) X5169P Z AM -40 to 85 8 Ld PDIP**
(Pb-free) MDP0031
X5168S8-4.5A X5168 AL X5169S8-4.5A X5169 AL 0 to 70 8 Ld SOIC MDP0027
X5168S8Z-4.5A
(Note) X5168 Z AL X5169S8Z-4.5A
(Note) X5169 Z AL 0 to 70 8 Ld SOIC
(Pb-free) MDP0027
X5168S8I-4.5A* X5168 AM X5169S8I-4.5A X5169 AM -40 to 85 8 Ld SOIC MDP0027
X5168S8IZ-4.5A*
(Note) X5168 Z AM X5169S8IZ-4.5A
(Note) X5169 Z AM -40 to 85 8 Ld SOIC
(Pb-free) MDP0027
X5168V14-4.5A X5168V AL X5169V14-4.5A X5169V AL 0 to 70 14 Ld TSSOP M14.173
X5168V14Z-4.5A
(Note) X5168V Z AL X5169V14Z-4.5A
(Note) X5169V Z AL 0 to 70 14 Ld TSSOP
(Pb-free) M14.173
X5168V14I-4.5A X5168V AM X5169V14I-4.5A X5169V AM -40 to 85 14 Ld TSSOP M14.173
X5168V14IZ-4.5A
(Note) X5168V Z AM X5169V14IZ-4.5A
(Note) X5169V Z AM -40 to 85 14 Ld TSSOP
(Pb-free) M14.173
X5168P X5168P X5169P X5169P 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP MDP0031
X5168PZ (Note) X5168P Z X5169PZ (Note) X5169P Z 0 to 70 8 Ld PDIP**
(Pb-free) MDP0031
X5168PI X5168P I X5169PI X5169P I -40 to 85 8 Ld PDIP MDP0031
X5168PIZ (Note) X5168P Z I X5169PIZ (Note) X5169P Z I -40 to 85 8 Ld PDIP**
(Pb-free) MDP0031
X5168S8* X5168 X5169S8* X5169 0 to 70 8 Ld SOIC MDP0027
X5168S8Z*
(Note) X5168 Z X5169S8Z*
(Note) X5169 Z 0 to 70 8 Ld SOIC
(Pb-free) MDP0027
X5168S8I* X5168 I X5169S8I* X5169 I -40 to 85 8 Ld SOIC MDP0027
X5168S8IZ*
(Note) X5168 Z I X5169S8IZ*
(Note) X5169 Z I -40 to 85 8 Ld SOIC
(Pb-free) MDP0027
X5168V14* X5168V X5169V14* X5169V 0 to 70 14 Ld TSSOP M14.173
X5168V14Z*
(Note) X5168V Z X5169V14Z*
(Note) X5169V Z 0 to 70 14 Ld TSSOP
(Pb-free) M14.173
X5168V14I* X5168V I X5169V14I* X5169V I -40 to 85 14 Ld TSSOP M14.173
X5168V14IZ*
(Note) X5168V Z I X5169V14IZ*
(Note) X5169V Z I -40 to 85 14 Ld TSSOP
(Pb-free) M14.173
X5168P-2.7A X5168P AN X5169P-2.7A X5169P AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld PDIP MDP0031
X5168PZ-2.7A
(Note) X5168P Z AN X5169PZ-2.7A
(Note) X5169P Z AN 0 to 70 8 Ld PDIP**
(Pb-free) MDP0031
X5168PI-2.7A X5168P AP X5169PI-2.7A X5169P AP -40 to 85 8 Ld PDIP MDP0031
X5168PIZ-2.7A
(Note) X5168P Z AP X5169PIZ-2.7A
(Note) X5169P Z AP -40 to 85 8 Ld PDIP**
(Pb-free) MDP0031
X5168S8-2.7A* X5168 AN X5169S8-2.7A X5169 AN 0 to 70 8 Ld SOIC MDP0027
X5168S8Z-2.7A*
(Note) X5168 Z AN X5169S8Z-2.7A
(Note) X5169 Z AN 0 to 70 8 Ld SOIC
(Pb-free) MDP0027
X5168S8I-2.7A* X5168 AP X5169S8I-2.7A X5169 AP -40 to 85 8 Ld SOIC MDP0027
X5168S8IZ-2.7A
(Note) X5168 Z AP X5169S8IZ-2.7A
(Note) X5169 Z AP -40 to 85 8 Ld SOIC
(Pb-free) MDP0027
X5168, X5169
3FN8130.2
June 15, 2006
Pin Configuration
X5168V14-2.7A X5168V AN X5169V14-2.7A X5168V AN 2.7-5.5 2.85-3.0 0 to 70 14 Ld TSSOP M14.173
X5168V14Z-2.7A
(Note) X5168V Z AN X5169V14Z-2.7A
(Note) X5169V Z AN 0 to 70 14 Ld TSSOP
(Pb-free) M14.173
X5168V14I-2.7A X5168V AP X5169V14I-2.7A X5169V AP -40 to 85 14 Ld TSSOP M14.173
X5168V14IZ-2.7A
(Note) X5168V Z AP X5169V14IZ-2.7A
(Note) X5169V Z AP -40 to 85 14 Ld TSSOP
(Pb-free) M14.173
X5168P-2.7 X5168P F X5169P-2.7 X5169P F 2.7-5.5 2.55-2.7 0 to 70 8 Ld PDIP MDP0031
X5168PZ-2.7
(Note) X5168P Z F X5169PZ-2.7
(Note) X5169P Z F 8 Ld PDIP**
(Pb-free) MDP0031
X5168PI-2.7 X5168P G X5169PI-2.7 X5169P G -40 to 85 8 Ld PDIP MDP0031
X5168PIZ-2.7
(Note) X5168P Z G X5169PIZ-2.7
(Note) X5169P Z G 8 Ld PDIP**
(Pb-free) MDP0031
X5168S8-2.7* X5168 F X5169S8-2.7* X5169 F 0 to 70 8 Ld SOIC MDP0027
X5168S8Z-2.7*
(Note) X5168 Z F X5169S8Z-2.7*
(Note) X5169 Z F 8 Ld SOIC
(Pb-free) MDP0027
X5168S8I-2.7* X5168 G X5169S8I-2.7* X5169 G -40 to 85 8 Ld SOIC MDP0027
X5168S8IZ-2.7*
(Note) X5168 Z G X5169S8IZ-2.7*
(Note) X5169 Z G 8 Ld SOIC
(Pb-free) MDP0027
X5168V14-2.7* X5168V F X5169V14-2.7* X5169V F 0 to 70 14 Ld TSSOP M14.173
X5168V14Z-2.7*
(Note) X5168V Z F X5169V14Z-2.7*
(Note) X5169V Z F 0 to 70 14 Ld TSSOP
(Pb-free) M14.173
X5168V14I-2.7* X5168V G X5169V14I-2.7* X5168V G -40 to 85 14 Ld TSSOP M14.173
X5168V14IZ-2.7*
(Note) X5168V Z G X5169V14IZ-2.7*
(Note) X5168V Z G -40 to 85 14 Ld TSSOP
(Pb-free) M14.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "-T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only . They are not intended for use in Reflow solder processing applications.
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW) PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH) PART
MARKING VCC RANGE
(V) VTRIP RANGE
(V) TEMP
RANGE (°C) PACKAGE PKG.
DWG #
8 LD SOIC/PDIP
CS
WP
SO
1
2
3
4
RESET/RESET
8
7
6
5
VCC
14 LD TSSOP
SO
WP
VSS
1
2
3
4
5
6
7
RESET/RESET
SCK
SI
14
13
12
11
10
9
8
NC
VCC
NC
X5168/X5169
VSS
SCK
SI
CS
NC
NC
NC
NC
X5168/X5169
X5168, X5169
4FN8130.2
June 15, 2006
Pin Description
PIN
(SOIC/PDIP) PIN TSSOP NAME FUNCTION
11CSChip Select Input. CS HIGH, deselects the device and the SO output
pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be
in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior
to the start of any operation after power-up, a HIGH to LOW transition on CS is required.
22SOSerial Out put. SO is a push/pull serial data output pin. A read cycle shift s data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
58SISerial Input. SI is a serial dat a input pin. Input all op codes, byte addresses, a nd memory data on th is
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
69SCKSerial Clock. The serial clock controls the seria l bus timing for dat a input and output. Th e rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
36WPWrite Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
47V
SS Ground
814V
CC Supply Voltage
7 13 RESET/
RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
3-5,10-12 NC No internal connections
X5168, X5169
5FN8130.2
June 15, 2006
Principles of Operation
Power-on Reset
Application of power to the X5168, X5169 activates a power-
on reset circuit. This circuit goes active at about 1V and pulls
the RESET/RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insuf ficient volt ag e or prio r to st abili zati on of the oscillator.
When VCC exceeds the devi ce VTRIP value for 200ms
(nominal) the circuit releases RESET/RESET, allowin g th e
processor to begin executing code.
Low Voltage Monitoring
During operation, the X5168, X5169 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
VCC Threshold Reset Procedure
The X5168, X5169 has a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in
the VTRIP value, the X5168, X5169 threshold may be
adjusted.
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessa ry
to reset the trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS pin and the WP pin
HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage VP to both SCK and SI
and pulse CS LOW then HIGH. Remove VP and the
sequence is complete.
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset,
the new VTRIP is something le ss than 1.7V. This procedure
must be used to set the voltage to a lower value.
To reset the VTRIP volt age, apply a voltage between 2.7 and
5.5V to the VCC pin. Tie the CS pin, the WP pi n, and the SC K
pin HIGH. RESET/RESET and SO pins are left uncon nected.
Then apply the programming voltage VP to the SI pin ONLY
and pulse CS LOW then HIGH. Remove VP and the
sequence is complete.
SCK
SI
VP
VP
CS
FIGURE 1. SET VTRIP VOLTAGE
SCK
SI
VCC
VP
CS
FIGURE 2. RESET VTRIP VOLTAGE
X5168, X5169
6FN8130.2
June 15, 2006
VTRIP Programming
Apply 5V to VCC
Decrement VCC
RESET pin
goes active?
Measured VTRIP -
Desired VTRIP
DONE
Execute
Sequence
Reset VTRIP
Set VCC = VCC Applied =
Desired VTRIP
Execute
Sequence
Set VTRIP
New VCC Applied =
Old VCC Applied + Error
(VCC = VCC - 10mV)
Execute
Sequence
Reset VTRIP
New VCC Applied =
Old VCC Applied - Error
Error ≥ Emax
Error = 0
YES
NO
Error > Emax
Emax = Maximum Desired Error
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
X5168/
1
2
3
4
8
7
6
5
VTRIP
Adj.
Program
NC
NC
VP
Reset VTRIP
Test VTRIP
Set VTRIP
NC
RESET
4.7K
4.7K
10K 10K
+
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
X5169
X5168, X5169
7FN8130.2
June 15, 2006
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device feature s a
Serial Peripheral Interface (SPI) and soft ware protocol
allowing operation on a simple fou r-wire bus.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directl y wi th the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller fami lies. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW . Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condi tion and after the completion of a
valid write cycle.
Status Register
The RDSR instruction provides access to the status register .
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
7 6543210
WPEN FLB 0 0 BL1 BL0 WEL WIP
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION
WREN 0000 0110 Set the write enable latch (enable write operations)
SFLB 0000 0000 Set flag bit
WRDI/RFLB 0000 0100 Reset the write enable latch/reset flag bit
RDSR 0000 0101 Read status register
WRSR 0000 0001 Write status register (watchdog, block lock, WPEN and flag bits)
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER
WEL WPEN WP# PROTECTED BLOCK UNPROTECTED BLOCK WPEN, BL0, BL1 WD0,
WD1
0 X X Protected Protected Protected
1 1 0 Protected Writable Protected
1 0 X Protected Writable Writable
1 X 1 Protected Writable Writable
X5168, X5169
8FN8130.2
June 15, 2006
The Write Enable Latch (WEL) bit indicates the status of the
write enable latch. When WEL = 1, the latch is set HIG H and
when WEL = 0 the latch is reset LOW. The WEL bit is a
volatile, read only bit. It can be set by the WREN instruction
and can be reset by the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to prote ct one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock pro tected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instruction s . Th e fl ag bi t is automatically reset upon
power-up.
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an in-circuit programmable ROM function (Table 2).
WP is LOW and WPEN bit programmed HIGH disables all
status re gi ster write operatio ns.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog bits
from inadvertent corruption.
In the locked state (programmable ROM mode) the WP pin
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s status register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the status register.
When WP is HIGH, all functions, including nonvolatile writes
to the status register operate normally. Setting the WPEN bit
in the status register to “0” blocks the WP pin function,
allowing writes to the status register when WP is HIGH or
LOW. Setting the WPEN bit to “1 ” while the WP pin is LOW
activates the programmable ROM mode, thus requiring a
change in the WP pin prior to subsequent status register
changes. This allows manufacturing to install the device in a
system with WP pin grounded and still be able to program
the status register. Manufacturing can then load
configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to be
protected by setting the block lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.
STATUS
REGISTER BITS ARRAY ADDRESSES PROTECTED
BL1 BL0 X5168/X5169
0 0 None
0 1 $0600-$07FF
1 0 $0400-$07FF
1 1 $0000-$07FF
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
7 654321 0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction 16 Bit Address
15 14 13 3 2 1 0
FIGURE 5. READ EEPROM ARRAY SEQUENCE
X5168, X5169
9FN8130.2
June 15, 2006
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by conti nuing to provide
clock pulses. The address is automatically incremen ted to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS high. Refer to the read EEPROM array sequence
(Figure 1).
To read the status register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read status
register sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 3). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last dat a byte to be written i s clocked in. If it is brough t HIGH
at any other time, the write operation will not be completed
(Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0 and
1 must be “0”.
While the write is in progress following a status register or
EEPROM sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
•CS
must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
X5168, X5169
10 FN8130.2
June 15, 2006
01234567891011121314
76543210
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
FIGURE 6. READ STATUS REGISTER SEQUENCE
01234567
CS
SI
SCK
High Impedance
SO
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
32 33 34 35 36 37 38 39
SCK
SI
CS
012345678910
SCK
SI
Instruction 16 Bit Address Data Byte 1
76543210
CS
40 41 42 43 44 45 46 47
Data Byte 2
76543210
Data Byte 3
76543210
Data Byte N
15 14 13 3 2 1 0
20 21 22 23 24 25 26 27 28 29 30 31
654 321 0
FIGURE 8. WRITE SEQUENCE
X5168, X5169
11 FN8130.2
June 15, 2006
Symbol Table
0123456789
CS
SCK
SI
SO High Impedance
Instruction Data Byte
765432 10
10 11 12 13 14 15
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X5168, X5169
12 FN8130.2
June 15, 2006
Absolute Maximum Ratings Recommended Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . .-1.0V to +7V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Limits
-2.7 or -2.7A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank or -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V-5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
UNITMIN TYP MAX
ICC1 VCC write current (active) SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open 5mA
ICC2 VCC read current (active) SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open 0.4 mA
ISB VCC standby current WDT = OFF CS = VCC, VIN = VSS or VCC,
VCC = 5.5V 1µA
ILI Input leakage current VIN = VSS to VCC 0.1 10 µA
ILO Output leakage current VOUT = VSS to VCC 0.1 10 µA
VIL
(NOTE 1) Input LOW voltage -0.5 VCC x 0.3 V
VIH
(NOTE 1) Input HIGH voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output LOW voltage VCC > 3.3V, IOL = 2.1mA 0.4 V
VOL2 Output LOW voltage 2V < VCC ≤ 3.3V, IOL = 1mA 0.4 V
VOL3 Output LOW voltage VCC ≤ 2V, IOL = 0.5mA 0.4 V
VOH1 Output HIGH voltage VCC > 3.3V, IOH = -1.0mA VCC - 0.8 V
VOH2 Output HIGH voltage 2V < VCC ≤ 3.3V, IOH = -0.4mA VCC - 0.4 V
VOH3 Output HIGH voltage VCC ≤ 2V, IOH = -0.25mA VCC - 0.2 V
VOLS Reset output LOW voltage IOL = 1mA 0.4 V
Capacitance TA = +25°C, f = 1MHz, VCC = 5V.
SYMBOL TEST CONDITIONS MAX. UNIT
COUT
(NOTE 2) Output capacitance (SO, RESET/RESET) VOUT = 0V 8 pF
CIN (NOTE 2) Input capacitance (SCK, SI, CS, WP)V
IN = 0V 6 pF
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
X5168, X5169
13 FN8130.2
June 15, 2006
Equivalent A.C. Load Circuit at 5V VCC
5V
Output
100pF
5V
4.6kΩ
RESET/RESET
30pF
2.06kΩ
3.03kΩ
A.C. Test Conditions
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified.)
SYMBOL PARAMETER
2.7-5.5V
UNITMIN MAX
SERIAL INPUT TIMING
fSCK Clock frequency 0 2 MHz
tCYC Cycle time 500 ns
tLEAD CS lead time 250 ns
tLAG CS lag time 250 ns
tWH Clock HIGH time 200 ns
tWL Clock LOW time 200 ns
tSU Data setup time 50 ns
tHData hold time 50 ns
tRI(3) Input rise time 100 ns
tFI(3) Input fall time 100 ns
tCS CS deselect time 500 ns
tWC(4) Write cycle time 10 ms
X5168, X5169
14 FN8130.2
June 15, 2006
Serial Input Timing
Serial Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
SCK
CS
SI
SO
MSB IN
tSU tRI
tLAG
tLEAD
tH
LSB IN
tCS
tFI
High Impedance
SYMBOL PARAMETER
2.7-5.5V
UNITMIN MAX
fSCK Clock frequency 0 2 MHz
tDIS Output disable time 250 ns
tVOutput valid from clock low 200 ns
tHO Output hold time 0 ns
tRO(3) Output rise time 100 ns
tFO(3) Output fall time 100 ns
SCK
CS
SO
SI
MSB Out MSB–1 Out LSB Out
ADDR
LSB IN
tCYC
tVtHO tWL
tWH
tDIS
tLAG
X5168, X5169
15 FN8130.2
June 15, 2006
Power-Up and Power-Down Timing
RESET Output Timing
Note: (5) This parameter is periodically sampled and not 100% tested.
VTRIP Set Conditions
VCC
tPURST
tPURST
tR
tF
tRPD
RESET (X5168)
0 Volts
VTRIP VTRIP
RESET (X5169)
SYMBOL PARAMETER MIN TYP MAX UNIT
VTRIP Reset trip point voltage, X5168-4.5A, X5168-4.5A
Reset trip point voltage, X5168, X5169
Reset trip point voltage, X5168-2.7A, X5169-2.7A
Reset trip point voltage, X5168-2.7, X5169-2.7
4.5
4.25
2.85
2.55
4.63
4.38
2.93
2.63
4.75
4.5
3.0
2.7
V
VTH VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 20 mV
tPURST Power-up reset time out 100 200 280 ms
tRPD(5) VCC detect to reset/output 500 ns
tF(5) VCC fall time 100 µs
tR(5) VCC rise time 100 µs
VRVALID Reset valid VCC 1V
SCK
SI
VP
VP
CS tVPS tVPH
tP
tVPS tVPH
tRP
tVPO
tVPO
tTSU
tTHD
VTRIP
VCC
X5168, X5169
16 FN8130.2
June 15, 2006
VTRIP Reset Conditions
SCK
SI
VCC
VP
CS tVPS tVPH
tP
tVPS tVP1
tRP
tVPO
tVPO
VCC*
*VCC > Programmed VTRIP
VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C
PARAMETER DESCRIPTION MIN MAX UNIT
tVPS SCK VTRIP program voltage setup time 1 µs
tVPH SCK VTRIP program voltage hold time 1 µ s
tPVTRIP program pulse width 1µs
tTSU VTRIP level setup time 10 µs
tTHD VTRIP level hold (stable) time 10 ms
tWC VTRIP write cycle time 10 ms
tRP VTRIP program cycle recovery period (between successive programming cycles) 10 ms
tVPO SCK VTRIP program voltage off time before next cycle 0 ms
VPProgramming voltage 15 18 V
VTRAN VTRIP programmed voltage range 1.7 5.0 V
Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V
Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) -25 +25 mV
Vtr VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV
Vtv VTRIP Program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
X5168, X5169
17 FN8130.2
June 15, 2006
Typical Performance
18
16
14
12
10
8
6
4
2
0
Watchdog Timer On (VCC = 5V)
Watchdog Timer On (VCC = 5V)
Watchdog Timer Off (VCC = 3V, 5V)
-40C 25C 90C
Temp (°C)
Isb (µA)
VCC Supply Current vs. Temperature (ISB)
VTRIP vs. Temperature (programmed at 25°C)
tPURST vs. Temperature
5.025
5.000
4.975
3.525
3.500
3.475
2.525
2.500
2.475
025 85
Voltage
Temperature
VTRIP = 5V
VTRIP = 3.5V
VTRIP = 2.5V
200
195
190
185
180
175
170
165
160
-40 25 90
Degrees °C
205
Time (ms)
X5168, X5169
18 FN8130.2
June 15, 2006
X5168, X5169
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X 4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL SO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28) TOLERANCE NOTES
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
19 FN8130.2
June 15, 2006
X5168, X5169
Plastic Dual-In-Line Packages (PDIP)
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES
A 0.210 0.210 0.210 0.210 0.210 MAX
A1 0.015 0.015 0.015 0.015 0.015 MIN
A2 0.130 0.130 0.130 0.130 0.130 ±0.005
b 0.018 0.018 0.018 0.018 0.018 ±0.002
b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015
c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002
D 0.375 0.750 0.750 0.890 1.020 ±0.010 1
E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010
E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2
e 0.100 0.100 0.100 0.100 0.100 Basic
eA 0.300 0.300 0.300 0.300 0.300 Basic
eB 0.345 0.345 0.345 0.345 0.345 ±0.025
L 0.125 0.125 0.125 0.125 0.125 ±0.010
N 8 14 16 18 20 Reference
Rev. B 2/99
D
L
A
eb
A1
NOTE 5
A2
SEATING
PLANE
L
N
PIN #1
INDEX
E1
12 N/2
b2
E
eB
eA
c
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8130.2
June 15, 2006
X5168, X5169
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α0o8o0o8o-
Rev. 2 4/06
