GVT73128A16J-10I - Cypress Semiconductor

ASYNCHRONOUS

SRAM 128K x 16 SRAM

+3.3V SUPPLY, SINGLE CHIP ENABLE

REVOLUTIONARY PINOUT

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

Galvantech, Inc. reserves the right to change

products or specifications without notice.

Rev. 12/97

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688 Fax (408) 566-0699

FEATURES

•Fast access times: 10, 12, 15and 20ns

•Fast OE# access times: 5, 6, 7 and 8ns

•Single +3.3V +0.3V power supply

•Fully static -- no clock or timing strobes necessary

•All inputs and outputs are TTL-compatible

•Three state outputs

•Center power and ground pins for greater noise immunity

•Easy memory expansion with CE# and OE# options

•Automatic CE# power down

•High-performance, low-power consumption, CMOS

triple-poly, double-metal process

•Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil

TSOP

OPTIONSMARKING

•Timing

10ns access -10

12ns access -12

15ns access -15

20ns access -20

•Packages

44-pin SOJ (400 mil) J

44-pin TSOP (400 mil) TS

•Power consumption

Standard None

Low L

•Temperature

Commercial None (0°C to 70°C)

Industrial I (-40°C to 85°C)

GENERAL DESCRIPTION

The GVT73128A16 is organized as a 131,072 x 16

SRAM using a four-transistor memory cell with a high

performance, silicon gate, low-power CMOS process.

Galvantech SRAMs are fabricated using triple-layer

polysilicon, double-layer metal technology.

This device offers center power and ground pins for

improved performance and noise immunity. Static design

eliminates the need for external clocks or timing strobes. For

increased system flexibility and eliminating bus contention

problems, this device offers chip enable (CE#), separate byte

enable controls (BLE# and BHE#) and output enable (OE#)

with this organization.

The device offers a low power standby mode when chip

is not selected. This allows system designers to meet low

standby power requirements.

DQ12

DQ11

A10

A11

OE#

BHE#

DQ16

DQ15

VSS

VCC

DQ3

DQ4

WE#

A15

A14

A13

A12

CE#

DQ1

DQ2

VCC

VSS

PIN ASSIGNMENT

44-Pin SOJ

44-Pin TSOP

BLE#

DQ7

DQ8

DQ5

DQ6 DQ10

DQ9

DQ14

DQ13

A16

December 11, 199 72Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

CE#

ADDRESS BUFFER

ROW DECODER

COLUMN DECODER

MEMORY ARRAY

512 ROWS X 256 X 16

COLUMNS

I/O CONTROL

WE#

OE#

DQ8

DQ1

POWER

DOWN

A16

DQ16

DQ9

BHE#

BLE#

VCC

VSS

December 11, 199 73Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

TRUTH TABLE

PIN DESCRIPTIONS

MODECE#WE#OE#BLE#BHE#DQ1-

DQ8DQ9-

DQ16POWER

LOW BYTE READ (DQ1-DQ8)LHL L HQHIGH-ZACTIVE

HIGH BYTE READ (DQ9-DQ16)LHLHLHIGH-ZQACTIVE

WORD READ (DQ1-DQ16)LHLLLQ Q ACTIVE

LOW BYTE WRITE (DQ1-DQ8)L L XLH D HIGH-ZACTIVE

HIGH BYTE WRITE (DQ9-DQ16)L L XHLHIGH-ZDACTIVE

WORD WRITE (DQ1-DQ16)L L XL L D D ACTIVE

OUTPUT DISABLE

LX X H H HIGH-ZHIGH-ZACTIVE

LH H X X HIGH-ZHIGH-ZACTIVE

STANDBYHX X X X HIGH-ZHIGH-ZSTANDBY

SOJ & TSOP

Pin NumbersSYMBOLTYPEDESCRIPTION

5, 4, 3, 2, 1, 44, 43,

42, 27, 26, 25, 24,

22, 21, 20, 19, 18

A0-A16InputAddresses Inputs: These inputs determine which cell is addressed.

17 WE#InputWrite Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW

for a WRITE cycle and HIGH for a READ cycle.

6CE#InputChip Enable: This active LOW input is used to enable the device. When CE# is LOW, the

chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into

standby power mode.

39, 40BLE#, BHE#InputByte Enable: These active LOW inputs allow individual bytes to be written or read. When

BLE# is LOW, the data is written to or read from the lower byte (DQ1-DQ8). When BHE# is

LOW, the data is written to or read from the higher byte (DQ9-DQ16).

41 OE#InputOutput Enable: This active LOW input enables the output drivers.

7, 8, 9, 10, 13, 14,

15, 16, 29, 30, 31,

32, 35, 36, 37, 38

DQ1-DQ16Input/OutputSRAM Data I/O: Data inputs and data outputs. Lower byte is DQ1-DQ8 and upper byte is

DQ9-DQ16.

11, 33VCCSupplyPower Supply: 3.3V +0.3V

12, 34VSS SupplyGround

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V

VIN ..........................................................-0.5V to VCC+1.0V

Storage Temperature (plastic) ..........................-55oC to +125o

Junction Temperature .....................................................+125o

Power Dissipation ...........................................................1.0W

Short Circuit Output Current .......................................50mA

*Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.This is a stress

rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

December 11, 199 74Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)

CAPACITANCE

DESCRIPTIONCONDITIONSSYMBOLMINMAXUNITSNOTES

Input High (Logic 1) voltageVIH2.2VCC+0.5V1, 2

Input Low (Logic 0) VoltageVIl-0.50.8V1, 2

Input Leakage Current0V < VIN < VCCILI-5 5 uA

Output Leakage CurrentOutput(s) disabled,

0V < VOUT < VCCILO-5 5 uA

Output High VoltageIOH = -4.0mA VOH2.4V1

Output Low VoltageIOL = 8.0mA VOL0.4V1

Supply VoltageVCC3.03.6V1

DESCRIPTIONCONDITIONS SYMTYPPOWER-10-12-15-20UNITSNOTES

Power Supply

Current: OperatingDevice selected; CE# < VIL; VCC =MAX;

f=fMAX; outputs openIcc70 standard190 160 130 100 mA3, 14

low180 150 120 90

TTL StandbyCE# >VIH; VCC = MAX; f=fMAXISB110 standard35 30 25 20 mA14

low30 25 20 15

CMOS StandbyCE1# >VCC -0.2; VCC = MAX;

all other inputs < VSS +0.2 or >VCC -0.2;

all inputs static; f= 0

ISB20.02standard3333mA14

low0.30.30.30.3

DESCRIPTIONCONDITIONSSYMBOLMAXUNITSNOTES

Input CapacitanceTA = 25oC; f = 1 MHz

VCC = 3.3VCI6 pF4

Input/Output Capacitance (DQ)CI/O8 pF4

December 11, 199 75Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

AC ELECTRICAL CHARACTERISTICS

(Note 5) (All Temperature Ranges; VCC = 3.3V +0.3V)

DESCRIPTION- 10- 12- 15- 20

SYMMINMAXMINMAXMINMAXMINMANUNITSNOTES

READ Cycle

READ cycle timetRC 10 12 15 20 ns

Address access timetAA 10 12 15 20 ns

Chip Enable access timetACE10 12 15 20 ns

Output hold from address changetOH3 4 4 4 ns

Chip Enable to output in Low-ZtLZCE3 4 4 4 ns4, 7

Chip disable to output in High-ZtHZCE5 6 7 8 ns4, 6, 7

Output Enable access timetAOE5 6 7 8 ns

Output Enable to output in Low-ZtLZOE0 0 0 0 ns

Output Enable to output in High-ZtHZOE5 6 7 8 ns4, 6

Byte Enable access timetABE 6 7 8 9 ns

Byte Enable to output in Low-ZtLZBE0 0 0 0 ns4, 7

Byte disable to output in High-ZtHZBE5 6 7 8 ns4, 6, 7

Chip Enable to power-up timetPU0 0 0 0 ns4

Chip disable to power-down timetPD10 12 15 20 ns4

WRITE Cycle

WRITE cycle timetWC10 12 15 20 ns

Chip Enable to end of writetCW8 8 9 10 ns

Address valid to end of write, with OE#

HIGHtAW8 8 9 10 ns

Address setup timetAS 0 0 0 0 ns

Address hold from end of writetAH0 0 0 0 ns

WRITE pulse widthtWP2 10 10 11 12 ns

WRITE pulse width, with OE# HIGHtWP1 8 8 9 10 ns

Data setup timetDS5 6 7 8 ns

Data hold timetDH 0 0 0 0 ns

Write disable to output in Low-ZtLZWE3 4 5 5 ns4, 7

Write Enable to output in High-ZtHZWE5 6 7 8 ns4, 6, 7

Byte Enable to end of writetBW8 8 9 10 ns

AC TEST CONDITIONS

Input pulse levels0V to 3.0V

Input rise and fall times1.5ns

Input timing reference levels1.5V

Output reference levels1.5V

Output loadSee Figures 1 and 2

OUTPUT LOADS

Vt = 1.5V

30 pF

Z0 = 50

Ω

Fig. 1 OUTPUT LOAD EQUIVALENT

Ω

3.3v

317

Ω

351

Ω

Fig. 2 OUTPUT LOAD EQUIVALENT

5 pF

December 11, 199 76Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

NOTES

1. All voltages referenced to VSS (GND).

2. Overshoot: VIH ≤ +6.0V for t ≤ tRC /2.

Undershoot: VIL ≤ -2.0V for t ≤ tRC /2

3. Icc is given with no output current. Icc increases with greater

output loading and faster cycle times.

4. This parameter is sampled.

5. Test conditions as specified with the output loading as shown in

Fig. 1 unless otherwise noted.

6. Output loading is specified with CL=5pF as in Fig. 2. Transition

is measured +500mV from steady state voltage.

7. At any given temperature and voltage condition, tHZCE is less

than tLZCE and tHZWE is less than tLZWE.

8. WE# is HIGH for READ cycle.

9. Device is continuously selected. Chip enable and output enables

are held in their active state.

10. Address valid prior to, or coincident with, latest occurring chip

enable.

11. tRC = Read Cycle Time.

12. Chip Enable and Write Enable can initiate and terminate a

WRITE cycle.

13. Capacitance derating applies to capacitance different from the

load capacitance shown in Fig. 1.

14. Typical values are measured at 3.3V, 25oC and 20ns cycle time.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

DESCRIPTIONCONDITIONSSYMBOLMINTYPMAXUNITSNOTES

Vcc for Retention DataVDR2V

Data Retention CurrentCE# >VCC -0.2;

all other inputs < VSS +0.2

or >VCC -0.2;

all inputs static; f= 0

Vcc = 2VICCDR2 100 uA13

Vcc = 3VICCDR3 150 uA13

Chip Deselect to

Data Retention TimetCDR0 ns4

Operation Recovery TimetRtRC ns4, 11

December 11, 199 77Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

LOW VCC DATA RETENTION WAVEFORM

READ CYCLE NO. 1(8, 9)

READ CYCLE NO. 2(7, 8, 10, 12)

VCC

CE#

DATA RETENTION MODE

VDR

VIH

VIL

tRC

tCDR

ADDR VALID

tRC

DATA VALID

tOH

tAA

PREVIOUS DATA VALID

CE#

tRC

DATA VALID

tLZCE

tACE

OE#

HIGH Z

tAOE

tLZOE

tHZCE

tHZOE

UNDEFINED

DON'T CARE

December 11, 199 78Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

WRITE CYCLE NO. 1(7, 12, 13)

(Write Enable Controlled with Output Enable OE# active LOW))

WRITE CYCLE NO. 2(12, 13)

(Write Enable Controlled with Output Enable OE# inactive HIGH)

ADDR

DATA VALID

CE#

WE#

WP2

HIGH Z

HZWE

LZWE

ADDR

tWC

tAH

tDS

DATA VALID

HIGH Z

CE#

WE#

tDH

tWP1

tAS

tAW

tCW

UNDEFINED

DON'T CARE

December 11, 199 79Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

WRITE CYCLE NO. 3(12, 13)

(Chip Enable Controlled)

WRITE CYCLE NO. 4(12, 13)

(Byte Enable Controlled)

ADDR

DON'T CARE

DATA VALID

CE#

WE#

WP1

HIGH Z

ADDR

tWC

tAH

tDS

DON'T CARE

DATA VALID

CE#

WE#

tDH

tWP1

tAW tBW

HIGH Z

BLE#

BHE# tCW

tAS

December 11, 199 710 Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

Package Dimensions

Note: All dimensions in inches (millimeters)

1.129 (28.68)

1.123 (28.52)

.405 (10.29)

.395 (10.03)

PIN #1 INDEX .050 (1.27) TYP

.020 (0.51)

.015 (0.38)

MAX

MIN or typical, min where noted.

SEATING

PLANE

.380 (9.65)

.360 (9.14)

.095 (2.41)

.080 (2.03)

.148 (3.76)

.138 (3.51) .030 (0.76)

MIN

.445 (11.30)

.435 (11.05)

44-pin 400 Mil Plastic SOJ (J)

Note: All dimensions in inches (millimeters)

.741 (18.81)

.721 (18.31)

.402 (10.21)

.398 (10.11)

PIN #1 INDEX .0315 (0.80) TYP

.018 (0.45)

.010 (0.25)

MAX

MIN or typical, max where noted.

SEATING

PLANE

.008 (0.20)

.002 (0.05)

.007 (0.18)

.005 (0.12)

.467 (11.86)

.459 (11.66)

44-pin 400 Mil Plastic TSOP (TS)

.047 (1.20)

MAX

.032 (0.80) .024 (0.60)

.016 (0.40)

December 11, 199 711 Galvantech, Inc. reserves the right to change products or specifications without notice.

Rev. 12/97

GVT73128A16

REVOLUTIONARY PINOUT 128K X 16

GALVANTECH, INC.

ADVANCE INFORMATION

Ordering Information

GVT 73128A16X XX-XX X X

Galvantech Prefix

Part Number

Package (J = 400 mil SOJ,

15 = 15ns, 20 = 20ns)

Speed ( 10 = 10ns, 12 = 12ns

TS = TSOP TYPE II)

Temperature (Blank = Commercial

I = Industrial)

Power (Blank= Standard,

L= Low Power)

Revision Differentiator

(Blank for Original Revision)