HIGH-SPEED IDT7024S/L 4K x 16 DUAL-PORT STATIC RAM Integrated Device Technology, Inc. FEATURES: more than one device * True Dual-Ported memory ceils which allow simulta- * M/S=H for BUSY output flag on Master neous reads of the same memory location M/S = L for BUSY input on Slave + High-speed access * Interrupt Flag Military: 35/45/55/70ns (max.) * On-chip port arbitration logic Commercial: 25/35/45/55ns (max.) * Full on-chip hardware support of semaphore signaling + Low-power operation between ports IDT7024S + Fully asynchronous operation from either port Active: 750mW (typ.) * Battery backup operation2V data retention Standby: 5mW (typ.) + TTL-compatible, single 5V (10%) power supply IDT7024L + Available in 84-pin PGA, quad flatpack, PLCC, and 100- Active: 750mW (typ.) pin Thin Quad Plastic Flatpack Standby: 1mW (typ.) + Industrial temperature range (40C to +85C) is avail- * Separate upper-byte and lower-byte control for able, tested to military electrical specifications multiplexed bus compatibility * 1DT7024 easily expands data bus width to 32 bits or DESCRIPTION: more using the Master/Slave select when cascading The IDT7024 is a high-speed 4K x 16 Dual-Port Static FUNCTIONAL BLOCK DIAGRAM AW R/WR UBL UBR TBt [Ba CEL CER OEL OER Att AllR A10L A10R vost -VO15L VOR -/O15R COLUMN COLUMN vo vo WOOL -WO7L VOoR-VO7R Busy" Busye'?) As MEMORY ASA Ao ARRAY Aon NOTES: 1. (MASTER): BUSY i put; (SLAVE): BUSY ARBITRATION is input. CE INTERRUPT 2. BUSY outputs SEMAPHORE and INT outputs LOGIC are non-tri-stated push-pull. RAWL BWR SEMB, INT INTR 2740 drw 01 MILITARY AND COMMERCIAL TEMPERATURE RANGES NOVEMBER 1993 {1996 Integrated Denice Technology, Inc 6.10 DSC-1045/2 1IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM RAM. The iDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. PIN CONFIGURATIONS 2 Q 0 4 MILITARY AND COMMERCIAL TEMPERATURE RANGES Fabricated using IDTs CMOS high-performance technol- ogy, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of SOOUW from a2V battery. The IDT7024 is packaged in a ceramic 84-pin PGA, an 84- pin quad flatpack, and PLCC, and a 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. vor Chra past vous pMe vor is a vOrst (17 2 GNDE/i8 AIL vOraeCf19 Oe Aol, vost E20 Fa4-2 66 NTL BUSY: vee(a1 84-PIN PLCC / 85 A . ea FLATPACK 64 [GND TOP VIEW DMs NCeah Sf NIC NCooe 74 NIC NC mE=AIN/C NC 7a NIC VO10l es TIN ASL VOLES 70p=d Aa (O12. =r eg Aa O13 Is ogo Aa GND ee 67 AIL O1aLEhi0 IDT7024 oid Aol, Osean PN100-1 ea INTL Voc maqi2 6d BUSYL GND Eas 641 GND VOoR aia 100-PIN TQFP oa M/S VOIR As TOP VIEW si BUSYR VOzR ie INTE Voc esqi7 sda ton VOasrR emia SaAAIR Osnesis S73 Azar VOsR eo 5a=9 ASR lOcsrm=p1 sod AAR NC jez Sa NC NiCr anc NC mon Nic NC ees SANC g 9 2740 drw 03 6.10IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES 63 61 60 58 55 54 51 48 46 45 42 " VOr. | VOst VOaL Oa | Oo OE. | SEML TB. AL AOL A7L 66 64 62 59 86 4g 50 7 44 43 40 10 | vor | von | vO | vou | von | UB. | Ge | Ne | Aw | A | Ast 6? 65 Ss? 53 52 41 39 09) vor | vost GND | Vcc | RW Ae. | Aat 69 68 38 7 08 | Vora VO1aL ABL Aak 72 71 73 33 35 34 07 | vorst VWO1aL | Voc BUSYL | AoL INTL IDT7024 cs 70 74 G84-3 32 31 36 6 | Voor | GND | GND 84-PIN PGA GND | MS | an TOP VIEW 76 7 78 28 29 30 95 | voir | Oar | Voc Aor | INTa |BUSYR 79 80 26 27 4 | yOaR | 04a Aon | AIR a 83 7 " 12 23 25 31 vosr | Orn GND | GND | SEMr AsR | sr 82 1 2 8 10 14 17 20 22 24 62 | oer | voor | Voter | vOrsR | VOrsR | RANA | UBa | Aria | Aen | Asa | Aan 84 3 4 6 g 1S 13 16 18 19 21 01 | VWOsR | YO11R | VO12R | VOR | OER | CBR | CER Nc Aion | ASR A7R A B c D E F G H J K L Index PIN NAMES Left Port Right Port Names CEL CER Chip Enable RW R/We Read/Write Enable OE OER Output Enable Aot AtiL Aon A1iR Address VOot VO15L VOor I/O15R Data Input/Output SEML SEMA Semaphore Enable UBL UBR Upper Byte Select LBL LBr Lower Byte Select INTt INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select Vec Power GND Ground 2740 tol 18 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 2740 drw 04 6.10IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL 1. TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL Aol Arit # Aon AriR Inputs! Outputs CE RW cE | UB iB SEM | WOs1s | 00-7 Mode H xX x Xx X H High-Z | High-Z | Deselected: Power Down X X xX H H H High-Z | High-Z | Both Bytes Deselected: Power Down L L X L H H DATAIN | High-Z | Write to Upper Byte Only L L X H L H High-Z | DATAIN | Write to Lower Byte Only L L X L L H DATAIN | DATAIN | Write to Both Bytes L H L L H H DATAouT| High-Z | Read Upper Byte Only L H L H L H High-Z |DATAouT| Read Lower Byte Only L H L L L H DATAouT|DATAouT| Read Both Bytes x Xx H X Xx xX High-Z | High-Z | Outputs Disabled NOTE: 2740 tbl 01 CE RAW OE 10)=] iB SEM VOa-15 VOo-7 Mode H H L X xX L DATAoutT |DAT: Read Data in Semaphore Flag H L H H DATAouT |DAT, Read Data in Semaphore Flag ft x x X DATAIN | DATAIN | Write Dino into Semaphore Flag INO xX X L Not Allowed X Xx X Not Aliowed 2740 tol 02 ABSOLUTE MAXIMUM RATINGS") RECOMMENDED OPERATING Symbol Rating Commercial] Military | Unit) TEMPERATURE AND SUPPLY VOLTAGE VteRM?) | Terminal Voltage] -0.5 to +7.0] -0.5to47.0] V Ambient with Respect Grade Temperature GND Vec to GND Military -55C to +125C ov 5.0V + 10% TA Operating Oto+70 | -55to+125) C Commercial 0C to +70C ov 5.0V + 10% Temperature 2740 thi 04 TBIAS. Temperature 55 to +125 | -6510+135|] C RECOMMENDED DC OPERATING Under Bias T Ss ; 55 125 5 150} C CONDITIONS STG torage -55 to+ -65 to+ r ; Temperature Symbol Parameter Min. | Typ. | Max. | Unit lout DC Output 50 50 mA Vcc Supply Voltage 45 5.0 5.5 Vv Current GND Supply Voltage 0 0 0 V NOTE: 2740 tbl 03 VIH Input High Voltage 22 | | 608] Vv 1. Stresses greater than those listed under ABSOLUTE MAXIMUM (1) RATINGS may cause permanent damage to the device. This is a stress Vit Input Low Voltage | 0.5 08] Vv rating only and functional operation of the device at these or any other ogg. 2740 tol 0S conditions above those indicated in the operational sections of this , Vie -3.0V for pulse width less than 20ns. specification is not implied. Exposure to absolute maximum rating 2. VTERM must me exceed Vcc + 0.5V , conditions for extended periods may affect reliability. , 2. VTERM must not exceed Vec + 0.5V. CAPACITANCE (TA = +25C, f = 1.0MHz) Symbol Parameter! Conditions | Max. | Unit CIN Input Capacitance Vin = OV an] pF Cout Output VouT = OV 1 pF Capacitance NOTE: 2740 to! 06 1. production tested. This parameter is determined by device characterization but is not 6.10IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V + 10%) IDT7024S (DT7024L Symbol Parameter Test Conditions Min. Max. Min. Max. | Unit [tu Input Leakage Current Vcc = 5.5V, VIN = OV to Vcc _ 10 _ 5 pA [ILo} Output Leakage Current CE = Vin, VouT = OV to Voc _ 10 5 pA VOL Output Low Voltage lo. = 4mA - 0.4 _ 0.4 Vv VoH Output High Voltage OH = -4mMA 2.4 _- 24 _ Vv 2740 tol 07 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE"? (vcc = 5.0V + 10%) 7024X25 7024X35 Test COML ONLY Symbol Parameter Condition Version Typ. Max. [Typ.2 Max. [unit Icc Dynamic Operating CE < Vi, Outputs Open MIL. Ss _ _ 160 | 400 |mA Current SEM 2 VIH L _ _ 160 | 340 (Both Ports Active) f = fax!) COML.| S$ 170 | 360 | 160 | 340 L 170 310 160 290 Isa1 | Standby Current CER = CEL> VIH MIL. S |]- 20 85 |mA (Both Ports TTL SEMar = SEML2 VIH L _ ee 20 65 Level Inputs) f = fax) COM'L.] Ss 25 | 70 | 20 | 70 L 25 50 20 50 Iss2___| Standby Current CEL or CERz Vin MIL. S ~ 95 | 290 ImA (One Port TTL Active Port Outputs Open L _ _ 95 250 Level Inputs) f = fmax() COML.| $ 105 | 250 | 95 | 240 SEMR = SEML2 VIH L 105 | 220 95 210 Issa | Full Standby Current Both Ports CEL and MIL. 8 ~ | 1.0 | 30 |mA (Both Ports All CEr > Vcc - 0.2V L | | 02] 10 CMOS Level Inputs) VIN 2 Vcc - 0.2V or COM'L.| S$ 1.0 15 1.0 15 Vins 0.2V,f=04 L 0.2 5 0.2 5 SEMR = SEML2 Vcc - 0.2V \sBa Full Standby Current One Port CE. or MIL. $s _ _ 90 260 [mA (One Port All CER 2 Vcc - 0.2V L _ _ 90 215 CMOS Level Inputs) SEMA = SEML2 Vcc - 0.2V Vin 2 Vcc - 0.2V or COM'L.| S 100 230 90 220 Vin s 0.2V Active Port Outputs Open, L 100 |] 190 90 180 f = fMax) NOTES: 2740 tbl 08 1. 2. 3. 4. 5. of input levels of GND to 3V. X in part numbers indicates pawer rating (S or L) Vcc = 5V, TA = +25C. Atf = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/trc, and using AC Test Conditions f = 0 means no address or control lines change. . At Vcc < 2.0V input leakages are undefined.IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(Continued) (Vcc = 5.0V + 10%) MILITARY AND COMMERCIAL TEMPERATURE RANGES 7024X45 7024X55 7024X70 Test MIL ONLY Symbol Parameter Condition Version |Typ.@) Max. | Typ.(2) Max. |Typ.) Max. junit Icc Dynamic Operating CE VIL, Outputs Open MIL. S | 155 400 150 | 395 | 140 | 390 |mA Current SEM VIH L 165 340 150 | 335 | 140 | 330 (Both Ports Active) f = fuax@ CoML. S| 155 | 340 [ 150] 335 | [| L 155 290 150 285 _ _ IsBi Standby Current CEL = CER VIH MIL. Ss 16 85 13 85 10 85 [mA (Both Ports TTL SEMR = SEML VIH L 16 65 13 65 10 65 Level Inputs) f = fMax) COML. S| 16 70 13 7o | J[ L 16 50 13 50 _ Ispe_ | Standby Current CER or CEL VIH MIL. S | 90 290 85 | 290 | 80 | 290 |mA (One Port TTL Active Port Outputs Open L 90 250 85 250 80 250 Level Inputs) f = fmax? COML. S| 90 | 240 85 | 240 [| SEMR = SEML_VIH L 90 210 85 210 _ _ \sBg Full Standby Current Both Ports CEL and MIL. $s 1.0 30 1.0 30 1.0 30 [mA (Both Ports Alt CER VCC -0.2V L 0.2 10 0.2 10 0.2 10 CMOS Level Inputs) VIN Vcc - 0.2V or COM'L. S$ 1.0 15 1.0 15 _ _ Vin 0.2V, f= 0) L 2 5 02] 5 |- SEMR = SEML Vcc - 0.2V Ispq | Full Standby Current One Port CEL or MIL. Ss 85 260 80 260 75 260 [mA (One Port All CER Vcc - 0.2V CMOS Level Inputs) SEMR = SEML Vcc - 0.2V L 85 215 80 215 75 215 VIN Vcc - 0.2V or COM'L. S$ 85 220 80 220 _ - VIN 0.2V Active Port Outputs Open, L 85 180 80 180 _ _ f= fax NOTES: 2740 tbl 0B 1. Xin part numbers indicates power rating (S or L) 2. Voc = 5V, TA= 425C. 3. Atf=fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditions of input levels of GND to 3V. 4, f= 0 means no address or control lines change. DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) (VLC = 0.2V, VHC = Vcc - 0.2V) Symbol Parameter Test Condition Min. Typ. Max. Unit VDR Vcc for Data Retention Vcc = 2V 2.0 _ _ Vv IccoR Data Retention Current CE Vic MIL. 100 4000 | pA VIN VHC or VLC COM'L. _ 100 1500 tcpr) Chip Deselect to Data Retention Time SEM Vic 0 _ ns tA@) Operation Recovery Time tac!) ns NOTES: 2740 tol 09 1. TA = 425C, Voc = 2V 2. tac = Read Cycle Time 3. This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Voc tcDR Vor 2 2V VIH 6.10 DATA RETENTION MODE 2740 drw 05IDT7024S/L HIGH-SPEED 4Kx 16 DUAL-PORT STATIC RAM AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figures 1 & 2 2740 tbl 10 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE) 775Q 5V 12500 30pF* 2740 drw 06 Figure 1. Output Load {5pF tor tiz, tuz, twz, tow) * Including scope and jig. MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT7024X25 IDT7024X35 COML ONLY Symbol Parameter Min. | Max. | Min. | Max. | Unit READ CYCLE tRC Read Cycle Time 25 _ 35 _ ns tAA Address Access Time _ 25 _ 35 ns tACE Chip Enable Access Time) 25 _ 35 ns tABE Byte Enable Access Time) _ 25 35 ns tAOE Output Enable Access Time _ 13 _ 20 ns tOH Output Hold from Address Change 3 _ 3 _ ns tz Output Low-Z Time" @) 3 3 |ns tHz Output High-Z Time'!: 15 15 ns tPU Chip Enable to Power Up Time 0 _ 0 _ ns tPD Chip Disable to Power Down Timel*? 50 _ 50 ns tsop Semaphore Flag Update Pulse (OE or SEM) 12 _ 15 _ ns tSAA Semaphore Address Access _ 30 _ 40 ns IDT7024X45 1DT7024X55 IDT?7024X70 MIL ONLY Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Unit READ CYCLE tRC Read Cycle Time 45 _ 55 _ 70 _ ns TAA Address Access Time 45 _ 55 _ 70 ns TACE Chip Enable Access Time?) _ 45 _ 55 _ 70 ns ABE Byte Enable Access Time) _ 45 _ 55 _ 70 ns TAOE Output Enable Access Time _ 25 _ 30 35 ns 1OH Output Hold from Address Change 3 _ 3 _ 3 _ ns tz Output Low-Z Timel! 2) 3 _ 3 _ 3 _ ns tHZ Output High-Z Time! ) 20 25 30 ns tPU Chip Enable to Power Up Time?) 0 _ 0 _ 0 _ ns tPD Chip Disable to Power Down Time! 50 _ 50 50 ns tsoP Semaphore Flag Update Pulse (OE or SEM) 15 _ 15 = 15 _ ns 1SAA Semaphore Address Access _ 50 60 ~ 75 ns NOTES: 2740 tht 11 1. Transition is measured 500mV from low or high impedance voltage with load (figures 1 and 2). 2. This parameter is guaranteed but not tested. 3. To access RAM, CE = L, UB or LB = L, SEM =H. 4. Xin part numbers indicates power rating (S or L). 6.10 7IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF READ CYCLES) ADDR DATAout VALID DATA BUSYout 2740 drw 07 NOTES: 1. 2. 3. 4. 5. Timing depends on which signal is asserted last, CE, OE, LB, or UB. Timing depends on which signal is de-asserted firs CE, OE, LB, or UB. tapp delay is required only in cases where oppasite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. Start of valid data depends on which timing becomes effective last tase, tace, tAce, taa or teop. SEM = H. TIMING OF POWER-UP POWER-DOWN CE tPU tPD Icc IsB 2740 drw 08IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE ) iT7024x25 | IDT7024x35 Write Time to Address Valid to End-of-Write Address Time!) Write Pulse Width Write Time Data Valid to End-of-Write Z Time": 2) Data Hold Time") Write Enable to in Zit} Active from End-of-Writel" 2: SEM Write to Read Time 10 10 SEM Flag Contention Window 10 10 IDT7024X45 IDT7024X55 IDT7024X70 MIL. ONLY Symbol Parameter Min. | Max. Min. | Max. Min. | Max. | Unit WRITE CYCLE two Write Cycle Time 45 _ 55 _ 70 _ ns tew Chip Enable to End-of-Write) 40 ~ 45 ~ 50 ~~ ns TAW Address Valid to End-of-Write 40 _ 45 _ 50 _ ns tas Address Set-up Time! 0 ~ 0 ~ 0 ~ |ns twp Write Pulse Width 35 _ 40 _ 50 _ ns twR Write Recovery Time 0 0 _ 0 _ ns {DW Data Valid to End-of-Write 25 ~ 30 _ 40 _ ns tHz Output High-2 Time! 2) 20 25 30 ns tH Data Hold Time") 0 _ 0 ~_ 0 _ ns twz Write Enable to Output in High-2'". 2! = 20 25 = 30 | ns tow Output Active from End-of-Writel: *: 4) 0 ~_ 0 ~_ 0 _ ns tswap SEM Flag Write to Read Time 10 ~ 10 ~_ 10 ns ISPS SEM Flag Contention Window 10 _ 10 10 _ ns NOTES: 2740 tbl 12 1. Transition is measured +500mV from low or high impedance valtage with load (Figures 1 and 2). 2. This parameter is guaranteed but not tested. 3. To access RAM, CE = L, UB or [B = L, SEM=H. To access semaphore, GE = H and SEM = L. Either condition must be valid for the entire tew time. 4. The specification for toH must be met by the device supplying write data to the RAM under all operating conditions. Although tbH and tow values will vary over valtage and temperature, the actual toH will always be smaller than the actual tow. . Xin part numbers indicates power rating (S or L). w 6.10 9IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, RW CONTROLLED TIMING 35) two _ ADDRESS tHZ OE taw CE \ i UBorLB \ kh +t tas () tote wwe! iar] twr RW x t DATAout { ia ) $$ DW *\|_ tDH DATAIN 2740 drw 09 TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING35.) two ADDRESS x x tAw CE r je acl) mle tew?) = twel? be aa Ta V UB or LB / RAW \\\ / t 1DW ot DH > DATAIN 2740 crw 10 NOTES: 1. R/Wor CE or UB & LB must be high during all address transitions. 2. Awrita occurs during the overlap (tew or twr) of a low UB or LB and a low CE and a low RW for memory array writing cycle. 3. twr is measured from the earlier of CE or R/W (or SEM or RAW) going high to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM [ow transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W or or byte control. 7. Timing depends on which enable signal is de-asserted first, CE, R/W ar byte control. 8. If OE is low during R/W controlled write cycle, the write pulse width must be the larger of twr or (twz + tpw) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twe. 6.10 10IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE") ft tsaa-> 1OH Ao - Aa OK VALID ADDRESS > VALID ADDRESS taAw > tWR | tACE be tew SEM SELLE NL a) TDW tsoPp DATAo DATAIN VALID batt h tAS twP {DH Rw NY OO LLNSLLLLLL LE LLL L OY ee ON Write Cyde = > *__ Read Cycle }| 2740 drw 11 NOTE: 1. CE =H for UB & LB = H for the duration of the above timing (both write and read cycle). TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION) - Aoa-A2A MATCH x SIDE? ay 4 RAW tsPS Aop-A2B MATCH 4 a SIDE Br 4 RiWs } SEMB v 4 2740 drw 12 NOTES: 1, Dor = Dot = L, CER = CEL = H, or both UB & LB = H, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. A may be either left or right port. B" is the opposite port from "A". 3. This parameter is measured from R/Wa or SEMa going high to R/We or SEMs going high. 4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 6.10 HiIDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (IDT7024X25 IDT7024X35 COML ONLY Symbol Parameter Min. | Max. Min. | Max. | Unit BUSY TIMING (M/S = H) {BAA BUSY Access Time from Address Match 25 _ 35 ns tBDA BUSY Disable Time from Address Not Matched = 20 30 ns {BAC BUSY Access Time from Chip Enable LOW _ 20 - 30 ns tBpc BUSY Disable Time from Chip Enable HIGH 17 _ 25 ns tAPS Arbitration Priority Set-up Time) 5 _ 5 _ ns {BDO BUSY Disable to Valid Data? |Note3 | | Note3 | ns BUSY TIMING (M/3 = L) twB BUSY Input to Write) 0 0 ns twH Write Hold After BUSY 17 = 25 ns PORT-TO-PORT DELAY TIMING twoo Write Pulse to Data Delay! _ 50 _ 60 ns tooo Write Data Valid to Read Data Delay) _ 35 45 ns IDT7024X45 IDT7024X55 1DT7024X70 Symbol Parameter Min. | Max. Min. | Max. Min. Max. [Unit BUSY TIMING (mS =H) tBAA BUSY Access Time from Address Match _ 35 _ 45 _ 45 ns tBDA BUSY Disable Time trom Address Not Matched _ 30 _ 40 40 ns tBAC BUSY Access Time from Chip Enable LOW 30 40 40 ns tepc BUSY Disable Time from Chip Enable HIGH 25 _ 35 35 ns taps Arbitration Priority Set-up Time(?) 5 _ 5 5 | ns teoD BUSY Disable to Valid Data) _|Note3 | _|Note3 | _|Note3 | ns BUSY TIMING (MS = L) twa BUSY Input to Write 0 0 0 = ns twH Write Hold After BUSY) 25 25 25 | ns PORT-TO-PORT DELAY TIMING twoo Write Pulse to Data Delay! _ 70 _ 80 _ 95 ns to0D Write Data Valid to Read Data Delay!) _ 55 65 - 80 | ns NOTES: 2740 tbl 13 1. Om bh wh Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (MS = H)" or "Timing Waveform of Write With Port-To-Port Delay (M/S=L)". . To ensure that the earlier of the two ports wins. . tBDOD is a calculated parameter and is the greater of 0, tWDD tWP (actual) or tDDD tDW (actual). . To ensure that the write cycle is inhibited during contention. . To ensure that a write cycle is completed after contention. . "x" is part numbers indicates power rating (S or L). 6.10 12IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ WITH BUSY (M/S = H) two ADDRA MATCH DATAINA taps ADDRL BUSY L DATAOUTL NOTES: 2740 drw 13 1. To ensure that the earlier of the two ports wins. 2. CEL = CER=L 3. OE = L for the reading port. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY") (M/S =L) twe ADDAA MATCH RAWA DATAIN R ADDRt DATAOUTL NOTES: BUSY input equals H for the writing port. 2, CEL = CER=L 2740 drw 14 = TIMING WAVEFORM OF SLAVE WRITE (MS = L) twe _] RW Y tWB tWH BUSY 2740 drw 15 6.10 13(DT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = H) ADDR a > ADDRESSES MATCH ax and "B" CEa" KH taps?) re. ~~ CEs XN ti t BAC ht t BDC BUSY's" 2740 drw 16 WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING(M/5 = H) ADDR's ADDRESS "N" aK taps!) ADDR's" MATCHING ADDRESS "N" TBAA tBDA BUSY s { 1 2740 drw 17 NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Part B" is the port opposite from A. 2. If tars is not satisfied, the busy signal will be asserted on one side or anather but there is no guarantee on which side busy will be asserted. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE") IDT7024X25 IDT7024X35 CONL ONLY Symbol Parameter Min. | Max. {| Min. | Max. | Unit INTERRUPT TIMING TAS Address Set-up Time 0 _- 0 ns twa Write Recovery Time 0 _ 0 _ ns TINS Interrupt Set Time _ 20 _ 30 ns tINR Interrupt Reset Time _ 20 _ 30 ns IDT7024X45 IDT7024X55 IDT7024X70 MIL, ONLY Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Unit INTERRUPT TIMING TAS Address Set-up Time 0 _ _ _ ns twR Write Recovery Time 0 _ 0 _ 0 _ ns tINS Interrupt Set Time 35 _ 40 _ 50 ns tiNR Interrupt Reset Time _ 35 _ 40 _ 50 ns NOTE: 2740 tol 14 1. "x" in part numbers indicates power rating (S or L). 6.10 14IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES WAVEFORM OF INTERRUPT TIMING j* TWwC ~ ADDR YA" INTERRUPT SET ADDRESS) KKK XK 2740 drw 18 a tRC | ADDR 8" KK INTERRUPT CLEAR ADDRESS) KK a m a al m 3 ting &) Z| fi a 2740 drw 19 NOTES: 1. All timing is tha same for ieft and right ports. Port A may be either the left or right port. Port B is the port opposite from A. 2. See Interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first. TRUTH TABLES TRUTH TABLE | INTERRUPT FLAG Left Port Port RM | CE | OE -Art| INTL | RW GEr 11R] INTr Function x L x x L L X FFF X x X xX X X L Set Left INTL Flag Xx FFE Reset Left INTL Flag NOTES: 2740 thi 15 1. Assumes BUSYL = BUSYR = H. 2. If BUSYL = L, then no change. 3. If BUSYR = L, then no change. X L Set INTR Flag Reset Right INTA Flag 6.10 15IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM TRUTH TABLE If ADDRESS BUSY ARBITRATION Inputs Outputs AoL-A11L CE | CER | Aor-Aiin | BUSY | BUSa | = Function Xx X |NO MATCH H H Normal H x MATCH H H Normal x H MATCH H H Normal L L MATCH (2) (2) Write inhibit NOTES: 2740 tol 16 1 MILITARY AND COMMERCIAL TEMPERATURE RANGES . Pins BUSY. and BUSYna are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the IDT7024 are push pull, nat open drain outputs. On slaves the BUSYx input internally inhibits writes. 2. simultaneously. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable inputs of this port. If tars is not met, either BUSY. or BUSYR = Low will result. BUSYL and BUSYs outputs cannot be low Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYr outputs are driving low regardless of actual logic level on the pin. TRUTH TABLE ill EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE") Functions Do - 015 Left Do - Dis Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphor: Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Left port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "O" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTE: 2740 thi 17 1. This table denotes a sequence of events for only ane of the eight semaphores on the IDT7024. FUNCTIONAL DESCRIPTION The IDT7024 provides two ports with separate control, message (16 bits) at FFE or FFF is user-defined. if the address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7024 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE high). When a port is enabled, access to the entire memory array is permitted. INTERRUPTS if the user chooses to use the interrupt function, a memory location (mailbox or message center) is assigned to each port. The left port interrupt flag (INTL) is set when the right port writes to memory location FFE (HEX). The left port clears the interrupt by reading address location FFE. Likewise, the right port interrupt flag (INTR) is set when the left port writes to memory location FFF (HEX) and to clear the interrupt flag (NTR), the right port must read the memory location FFF. The interrupt function is not used, address locations FFE and FFF are not used as mail boxes, but as part of the random access memory. Refer to Table | for the interrupt operation. BUSY LOGIC Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side thatthe RAM is busy. The busy pin can thenbe used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write trom proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical 6.10IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES MASTER E Dual Port RAM ___ BUSY (L} BUSY _ R) + or I Ww SLAVE CE 5 Dual Port e RAM W T ] ] | 1 MASTER CE SLAVE CE Dual Port Dual Port RAM RAM BUSY Busy (1) BUSY BUSY (R BUSY (L)| LBUSY (L) ye) BUSY (L) BUSY (R) P- | 2740 drw 20 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7024 RAMs. operation. If the write inhibit function of busy logic is not desirable, the busy logic can be disabied by placing the part in slave mode with the M/Spin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. The busy outputs on the IDT 7024 RAM in master made, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the busy indication for the resulting array requires the use of an external AND gate. WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS When expanding an IDT7024 RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7024 RAM the busy pin is an output if the part is used as a master (M/Spin =H), and the busy pin is an input if the part used as a slave (M/Spin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The busy arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable mustbe valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. SEMAPHORES The IDT7024 is an extremely fast Dual-Port 4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time ofthe right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, anon-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective part to go into standby mode when not selected. This is the condition which is shown in Truth Table where CE and SEM are both high. Systems which can best use the IDT7024 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the 1DT7024's hardware semaphores, which pro- vide a lockout mechanism without requiring complex pro- gramming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7024 does not use its semaphore flags to control any resources through 6.10 17IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for ause assignment method called Token Passing Allocation. In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. Ifitwas not successful in setting the latch, it determines that the right side processor has set the latch first, has the token andis using the shared resource. The left processor can then either repeatedly request that semaphore's status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A tokenis requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7024 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins AO A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin Do is used. If a low level is written into an unused semaphore location, that flag willbe set to a zero on that side and a one on the other side (see Table Ill). That semaphore can now only be madified by the side showing the zero. Whena one is written into the same location from the same side, the flag willbe set to a one forboth sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interpracessor communica- tions. (A thorough discussing on the use of this feature follows shorlly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side's output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore ina test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the sema- phore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. Ifthe semaphoreis already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. Ona subsequent read, the processor will verify that it has written successfuily to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a sema- phore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue untila one is written to the same semaphore request latch. Should the other sides semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side's request latch. The second sides flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphare logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If ane side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powertul programming tech- nique. if semaphores are misused or misinterpreted, a soft- ware error can easily happen. 6.10 18IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORESSOME EXAMPLES Perhaps the simplest application of semaphores is their application as resource markers for the |DT7024s Dual-Port RAM. Say the 4K x 16 RAM was to be divided into two 2K x 16 blacks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 2K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were success- fully completed (a zero was read back rather than a one), the left processor would assume control of the lower 2K. Mean- while the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. Atthis point, the software could choose to try and gain control of the second 2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. lf Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the twa LPORT SEMAPHORE REQUEST FLIP FLOP Do 7D a WRITE -> SEMAPHORE 4 READ MILITARY AND COMMERCIAL TEMPERATURE RANGES processors to swap 2K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be as- signed different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the /O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was off-limits to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory WAIT state is available on one or both sides. Once a semaphore handshake has been performed, both proces- sors can access their assigned RAM segments at full speed. Another application is in the area of complex data struc- tures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefare, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data Structure. R PORT SEMAPHORE REQUEST FLIP FLOP Qa D- Do r WRITE SEMAPHORE READ 2740 drw 21 Figure 4. 1IDT7024 Semaphore Logie 6.10 19IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX A 999 A A Device Power Speed Package Process/ Type Temperature Range Biank Commercial (0 C to +70 C) Military (-55 C to +125 C) Compliant to MIL-STD-883, Class B 100-pin TQFP (PN100-1) 84-pin PGA (G84-3) 84-pin PLCC (J84-1) 84-pin Flatpack (F84-2) Commercial Only Speed in Nanoseconds Military Only Standard Power Low Power 64K (4K x 16) Dual-Port RAM 2740 drw 22 20