RFM products are now
Murata products.
©2010-2015 by Murata Electronics N.A., Inc.
SC3046B-5 (R) 2/12/15 Page 1 of 2 www.murata.com
Electrical Characteristics
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
Characteristic Sym Notes Minimum Typical Maximum Units
Output Frequency Absolute Frequency fO1, 2 932.725 933.300 MHz
Variation over Temperture 70 ppm
Q and Q Output Power into 50Ω (VSWR ≤ 1.2) VO1, 3 0.5 3.0 6.0 dBm
Operating Load VSWR 2:1 VP-P
Symmetry 3, 4, 5 49 51 %
Harmonic Spurious 3, 4, 6 -30 dBc
Nonharmonic Spurious -60 dBc
Start Up Time 1, 10 30 µs
Q and Q Period Jitter No Noise on VCC 3, 4, 6, 7 15 30 psP-P
200 mVP-P from 1 MHz to ½ fO on 3, 4, 7, 8 35 psP-P
Output (Disabled) Amplitude into 50 Ω3, 9 75 mVP-P
Output DC Resistance (between Q & Q)350 KΩ
ENABLE (Terminal 14) Input HIGH Voltage VIH
3, 9
VCC-0.1 VCC VCC+0.1 V
Input LOW Voltage VIL 0.0 0.20 V
Input HIGH Current IIH 35mA
Input LOW Current IIL -1 mA
Propagation Delay tPD 1ms
DC Power Supply Operating Voltage VCC 1, 3 +3.13 +3.30 +3.47 VDC
Operating Current ICC 25 45 mA
Operating Ambient Temperature TA1, 3 10 +60 °C
Lid Symbolization (YY = Year, WW = Week) RFM SC3046B-5 933.12 MHz YYWW
• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Very Low Jitter and Power Consumption
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use in high-speed communications timing systems. Fundamental-mode
oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter,
compact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving
50 Ω loads.
Absolute Maximum Ratings
Rating Value Units
Power Supply Voltage (VCC at Terminal 1) 0 to +4.0 VDC
Input Voltage (ENABLE at Terminal 8) 0 to +4.0 VDC
Case Temperature (Powered or Storage) -40 to +85 °C
933.12 MHz
Differential
Sine-Wave Clock
SC3046B-5
SMC-8B Case
1. Unless otherwise noted, all specifications are at 25 ± 3°C and include any combi-
nation of load VSWR and VCC. In addition, Q and Q are terminated into 50 Ω
loads to ground. (See: Typical Test Circuit.)
2. One or more of the following United States patents apply: 4,616,197; 4,670,681;
4,760,352.
3. The design, manufacturing process, and specifications of this device are subject
to change without notice.
4. Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and
nominal power supply voltage.
5. Symmetry is defined as the pulse width (in percent of total period) measured at
the 50% points of Q or Q. (See: Timing Definitions.)
6. Jitter and other spurious outputs induced by externally generated electrical noise
on VCC or mechanical vibration are not included. Dedicated external voltage
regulation and careful PCB layout are recommended for optimum performance.
7. Applies to period jitter of Q and Q. Measurements are made with the Tektronix
CSA803 signal analyzer with at least 1000 samples.
8. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half
of fO at the VCC power supply terminal.
9. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
point on the rising edge of the output amplitude or as the fall time from the 50%
point to the 10% point. (SEE: Timing Definitions.)
10. The start up time is definded as the time from when power is applied to terminals
1 and 8 (90% of 3.3V) until power out from Q and Qbar reaches 90% of Qout
level.
©2010-2015 by Murata Electronics N.A., Inc.
SC3046B-5 (R) 2/12/15 Page 2 of 2 www.murata.com
Electrical Connections
Case Design
All pads consist of 30 microinches (min) electroless gold on 50 microinches
(min) electroless nickel over base metal. The metallic center pad was
designed for mechanical support. Grounding of this pad is critical to the
performance of this high frequency Clock.
Lid symbolization, including terminal 1 locator dot, are in contrasting ink.
Symbolization varies by model number. For purposes of illustration, only
terminal 1 dot is shown.
Electrical Characteristics
Footprint
Actual size footprint:
Typical Printed Circuit Board Land Pattern
A typical land pattern for a circuit board is shown below. Grounding of the
metallic center pad is critical to the performance of this high frequency
Clock.
.
Typical Test Circuit
Timing Definitions
Terminal
Number Connection
1V
CC
2 Ground
3 NC or Ground
4 Q Output
5Q
Output
6 Ground
7
8 ENABLE
LID Ground
Dimensions Millimeters Inches
Min Max Min Max
A 13.46 13.97 0.530 0.550
B 9.14 9.66 0.360 0.380
C 2.05 Nominal 0.081 Nominal
D 3.56 Nominal 0.141 Nominal
E 2.24 Nominal 0.088 Nominal
F 1.27 Nominal 0.050 Nominal
G 2.54 Nominal 0.100 Nominal
H 3.05 Nominal 0.120 Nominal
J 1.93 Nominal 0.076 Nominal
K 5.54 Nominal 0.218 Nominal
L 4.32 Nominal 0.170 Nominal
M 4.83 Nominal 0.190 Nominal
N 0.50 Nominal 0.020 Nominal
A
B
N
J
L(X2)
D
(X8)
K
(X8)
C
H
G
M
(X3)
E
F
Typically 0.01" to 0.05" or 0.25 mm to
1.25 mm (8 Places)
(The optimum value of this dimension is
dependent on the PCB assembly process
employed.)
Clock
Under Test Q
Tektronix
CSA 803
Digitizing
Oscilloscope
Ch 2
ENABLE
Vcc
QCh 1
50 Ω
Trigger
*
*
*Power Splitter, Mini-Circuits ZFSC2-4
0.1 μF
Sine-Wave
Signal Generator
4.7 μH
50 Ω
50 Ω
Vcc
t
PD
Propagation Delay:
50%
ENABLE
Q or Q Output
Amplitude
Envelope
50%
90%
10%
Symmetry:
50% 50%
Q or Q Output
50%
Symmetry as
% of Period
Period
Symmetry as
% of Period
t
PD
1
2
3
4
8
7
6
5
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