M25P40-VMN6P - STMicroelectronics

1/40August 2004

M25P40

4 Mbit, Low Voltage, Serial Flash Memory

With 40MHz SPI Bus Interface

FEATURES SUMMARY

■4 Mb it of Fl ash Memory

■Page Program ( up to 256 Bytes) i n 1.5ms

(typical)

■Sector Erase (512 Kb it) in 1s (ty pical)

■Bulk Erase (4 Mbit) in 4.5s (typical)

■2.7 to 3.6V Single Supply Voltage

■SPI Bus Compatible Serial Interface

■40MH z Clock Rate (maximum)

■Deep Power-down Mode 1µA (typical)

■Ele ctronic Signature (12h)

Figure 1. Packages

SO8 (MN)

150 mil width

VDFPN8 (MP)

(MLP8)

M25P40

2/40

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. SO and VDFPN Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNA L DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Se lect (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Bus M aster an d Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. SPI Modes Supp orted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Page Pr ogrammin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Sec tor Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Po lling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Active Power, Stand-by Power a nd Deep Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Prote cted Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Write Enable (WR EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3/40

M25P40

Figure 8. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.Read S tatus Register (RDSR) Instruction Sequence and Data-O ut Sequen ce . . . . . . . 15

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11.Write Status Registe r (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. P rote ction Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.Read Dat a Bytes (READ) Instruction Sequen ce and Data-Out Sequence . . . . . . . . . . . 18

Read Data Bytes at High er Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13.Read Data Bytes at Higher Speed (FAST_READ ) Instruction Sequenc e and Data-Out Se-

quence 19

Page Pr ogram (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Figure 14.P age Pro gram (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Sec tor Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15.S ector Eras e (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 16.B ulk Erase (BE) Instruction Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3

Figure 17.Deep P ower-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Releas e from D e e p Power-do w n and R e a d El e c t r onic S ignatur e ( R ES) . . . . . . . . . . . . . . . . . 24

Figure 18.Release from Deep Power-down and Read Electronic Signature (RES) Instruction Se-

quenc e and Data-Out Seque nce24

Figure 19.Release from Deep Power-down (RES) Instruction Sequence. . . . . . . . . . . . . . . . . . . . 25

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 20.Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7. Power-Up Timin g and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

INITIAL DELIVERY STAT E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Operati ng Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 10. Data Retentio n and Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 12. DC Characteristics (Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. DC Characteristics (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

M25P40

4/40

Table 14. Instruction Times (Dev ice Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. Instruction Times (Dev ice Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. AC Measurement Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 21.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17. AC Characteristics (25MHz Operation , Device Grade 6 or 3). . . . . . . . . . . . . . . . . . . . . 32

Table 18. AC Characteristics (40MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 22.S erial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 23.Write Protect Setup and Hold Timing during WRSR when SRW D=1 . . . . . . . . . . . . . . . 34

Figure 24.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 25.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5

PACKAGE M ECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 26.S O8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 36

Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Figure 27.M LP 8, 8-lead Very thin Dual Flat P ac kage No lead, 6x 5mm, Package Outli ne . . . . . . . 37

Table 20. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm , Package Mechanical Data37

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. Orde ring Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 22. Document Re vision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5/40

M25P40

S UM MARY DESCR IPTION

The M25P40 is a 4 Mbit (512K x 8) Serial Flash

Memory, with advanced write protection mecha-

nisms, acces sed by a high speed SPI- compatible

bus.

The memory can be programmed 1 to 256 bytes at

a time, using the Page Progr am instruction.

The memory is organi zed as 8 sec tors, each c on-

taining 256 p ages. Each page is 256 bytes wide.

Thus, the whole memory can be viewed as con-

sisting of 2048 pages, or 524,288 bytes.

The whole mem ory can b e erased usi ng the Bulk

Erase instruction, or a sector at a time, using the

Sector Erase instruction.

Figure 2. Logic Diagram

Figu re 3. S O and VD FP N C onnec tio ns

Note : 1. There is an exposed di e paddle on the underside of the

MLP8 package. This is pulled, internally, to VSS, and

must not be allowed to be connected to any other voltage

or si gnal line on the PCB.

2. See PACKAGE MECHANICAL section for package di-

mens i ons, and how to ident i fy pi n-1.

Table 1. Signal Names

AI04090

VCC

M25P40

HOLD

VSS

AI04091B

5DVSS C

HOLDQ

M25P40

C Serial Clock

D Serial Data Input

Q Serial Data Outp ut

SChip Select

W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

M25P40

6/40

SIGNAL DESCRIPTION

Serial Data O utp ut (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data In put (D). This input signal i s used to

transfer data seriall y into t he devi ce. It receives in-

structions, addresses, and the data to be pro-

grammed. Values are latched on the rising edge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the s erial interface. Instructions, address-

es, or data present at Serial Data Input (D) are

latched on the ris ing edge of Serial Clock (C) . Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at high imped ance. Unless an intern al Pro-

gram, Erase or Write Status Register cycle is in

progress, the devi ce will be in the Standby mode

(this is not the Deep Power-down mode). Driving

Chip S ele c t ( S ) Low enabl es the device, placing it

in the active power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Hold (HOLD). The Hold (HOLD) signal is used to

pause any serial communications with the device

without deselecti ng the device.

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

To start the Hol d condit ion, the device must be se-

lected, wit h C h ip S e lec t (S) driven Low.

Write Protect (W). The main purpose of this in-

put signal is to freeze the size of the area of m em-

ory that is protected against program or erase

instructions (as specified by the values in t he BP2,

BP1 and BP0 bits of the S t atus Regis ter).

7/40

M25P40

SPI MODES

These dev ices can be drive n by a microcont roller

with its SPI peripheral running in either of the two

following modes:

– CP OL=0, CP HA=0

– CP OL=1, CP HA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 5., is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remains at 0 for (CPOL=0, CPHA =0)

– C remains at 1 for (CPOL=1, CPHA =1)

Figure 4. Bus Master and Memo ry Devices on the SPI Bus

Note: The Write Protect (W) and Hold ( HOLD) signal s should be dri ven, High or Low as appropriate.

Figure 5 . SPI Modes Suppor te d

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others) SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

AI01438B

MSB

CPHA

CPOL

MSB

M25P40

8/40

OPERAT ING FEA TURES

Page P rogramming

To program one dat a byte, t wo i ns tructions are re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is followed by the

internal Program cycle (of duration tPP).

To spread this overhead, the Page P rogram (PP)

instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bulk Eras e

The Page Program (PP) instruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of memo ry need to hav e been erased to a ll

1s (FFh). This can be achieved either a s ector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction. This starts an internal

Erase cycle (of duration tSE or tBE).

The Erase instruction must be preceded by a Write

Enable (WREN) instruction.

Polling Duri ng a Write, Program or Erase Cycle

A further improveme nt in the time to Write Status

BE) can be achieved by not waiting for the worst

case delay (tW, tPP, tSE, or tBE). The Write In

Progress (WIP) bit is provi ded in the S tatus Regis-

ter so that the application program can monitor its

value, polling it to establish when the previous

Write cycle, Pro gram cycle or Erase cycle is com-

plete.

Active Power, St a nd - by Po wer an d De ep

Power-Down Modes

When Chip Select (S) is Low, the device is en-

abled, and in the Active Power mode.

When Chip Select (S) is High, the device is dis-

abled, but could rema in in t he Active Powe r mode

until all internal cycles have com pleted (Program,

Erase, Write Status Register). The device then

goes in t o the Stand-by Power m ode. T he device

consumption drops to ICC1.

The Deep Power-down mode is entered when the

specific instruction (the Enter Deep Power-down

Mode (DP) instruction) is executed. The device

consump tion drops further to ICC2. T he de vic e re-

mains in this mode until another specific instruc-

tion (the Release from Deep Power-down Mode

and Read Elect ro nic Sig nature (RES) i nstruction)

is executed.

All other instructions are igno red while the device

is in the Deep Power-down mode. This can be

used as an ext ra software protec tio n mecha nism,

when the device is not in active use, to protect the

device from inadvertent Write, Program or Erase

instructions.

Status Reg ister

The Status Register contains a number of status

and control bits that can be read or set (as appro-

priate) by specific instructions.

WIP bit. The Write In Progress (WI P) bit indicates

whether the memory is busy with a Write Status

WE L bi t. The W rite Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Eras e instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in th e Hardware

Protected mode. In this mode, the non-volatile bits

of the Status Register (SRWD, BP2, BP1, BP0)

become read-only bits.

9/40

M25P40

P rotec tion Modes

The environments where non-vol atile memory de-

vices are used can be very noisy. No SPI device

can operate correct ly in the presence of excessive

noise. To help combat t his, the M25P40 boasts the

following dat a protection mechanisms:

■Powe r-On Reset and an internal timer (tPUW)

can provide protecti on against inadvertant

changes while the power supply is outside the

operat ing specificatio n.

■Program , Erase and Write Status Regis ter

instructions are checked that they c onsi st of a

numb er of clock pulses that is a multiple of

eight, before they are accepted for execution.

■All instructions that modify data must be

prece ded by a Write Enable (WREN)

instruction to set the Write Enable Latch

(WE L) bit . This bit is returned to its reset s tate

by the following events:

– Power-up

– Write Disable (WRDI) instruction

completion

– Write Status Register (WRSR) i nstr uction

completion

– Page Progr am (PP) instruction completion

– Sector Erase (SE) instruction comple tion

– Bulk Erase (BE) i nstruction completion

■The Bl oc k Pr o te ct (BP2, BP 1, BP0 ) b i ts a llow

part of the memory to be configured as read-

only. This is the Software Protected Mode

(SPM).

■The Write Protect (W) si gnal allows the Bl ock

Protec t (BP2, BP1, BP0) bits and Status

Regi st er Write Di sable (SRWD) bit to be

protected. This is the Hardware Protected

Mode (HPM).

■In addition to the low power consumption

feature, the Deep Power-down mode offers

extra software protection from inad vertant

Wri t e, Program and Erase instructions, as all

instructions are ignored ex cept one part icular

instruction (t he Release from Deep Power-

down instruction).

Table 2. Protected Area Sizes

Note: 1. The device is ready to accept a Bul k E rase in st ruction i f , and onl y i f , all Block Protect (BP2, BP1, BP0) are 0.

Status Register

Content Memory Content

BP2

Bit BP1

Bit BP0

Bit Protected Area Unprotected Area

0 0 0 none All sectors1 (eight sectors: 0 to 7)

0 0 1 Upper eighth (Sector 7) Lower seven-eighths (seven sectors: 0 to 6)

0 1 0 Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5)

0 1 1 Upper half (four sectors: 4 to 7) Lower half (four sectors: 0 to 3)

1 0 0 All sectors (eight sectors: 0 to 7) none

1 0 1 All sectors (eight sectors: 0 to 7) none

1 1 0 All sectors (eight sectors: 0 to 7) none

1 1 1 All sectors (eight sectors: 0 to 7) none

M25P40

10/40

Hold Condition

The Hold (HOLD) signal is used to pause any se-

rial communications with the device wi thou t rese t-

ting the clocking sequence. However, taking this

signal Low does not terminate any Write Status

in progress.

To enter the Hold condition, the device must be

sele c te d , wit h C hip Select (S) Low.

The Hold condit ion start s on t he f alling edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) bei ng L ow (as shown in Fig-

ure 6.).

The Hold condition ends on the ris ing edge of t he

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial

Clock (C) being Low, the Hold condition s tarts af-

ter Serial Clock (C) nex t goes Low. Similarly, if the

rising edge does not coi ncide with Seri al Clock (C)

being Low, the Hold condition ends after Serial

Clock (C) next goes Low. (T his is shown i n Figure

6.).

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip

Select (S) driven Low, for the whole duration of the

Hold condition. This is to ensure that the state of

the internal logic remains unchanged f rom the mo-

ment of entering the Hold condition.

If Chi p Select (S) goes High whil e t he d evice is in

the Hold c ondition, this has the effect of resett ing

the internal logic of the device. To restart commu-

nication with the device, it is necessary to drive

Hold (HOLD) High, and then to drive Chip Select

(S) Low. This prevent s t he device from going back

to the Hold condition.

Figure 6. Hold Condition Activation

AI02029D

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

11/40

M25P40

ME M ORY OR GANIZAT ION

The memory is organized as:

■524, 288 bytes (8 bits each)

■8 sectors (512 Kbits, 65536 bytes each)

■2048 pages (256 bytes each).

Each page can be individually programmed (bits

are programmed from 1 to 0). The device is S ec tor

or Bulk Erasable (bi ts are erased from 0 to 1) but

not Page Erasable.

Table 3. Memory Organization

Sector Address Range

7 70000h 7FFFFh

6 60000h 6FFFFh

5 50000h 5FFFFh

4 40000h 4FFFFh

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

M25P40

12/40

Figu re 7. Blo ck Diagram

AI04986

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Size of the

read-only

memory area

Status

00000h

7FFFFh

000FFh

13/40

M25P40

INSTRUCTIONS

All instructions, addresses and data are shifted in

and out of the device, most significant bit f irst.

Serial Data Input (D) is sampled on the first rising

edge of Serial Clock (C) after Chip Select (S) is

driven Low. Then, the one-byte instruction code

must be shifted in t o the device, most signif icant bit

first, on Serial Data Input (D), each bit being

latched on the rising edges of Serial Clock (C).

The instruct i on set is listed in Tab le 4..

Every instruction sequence s tarts with a one-byte

instruction code. Depending on the instruction,

this might be f ollowed by address bytes, or by data

bytes, or by both or none. Chip Select (S) must be

driven High after the last bit of the instruction se-

quence has been shifted in.

In the case of a Read Data Bytes (READ), Read

Data Bytes at Higher Speed (Fast_Read), Read

Status Register (RDSR) or Release from Deep

Power-down, and Read Electronic Signature

(RES) instruction, the shifted-in instruction se-

quence is followed by a data-out sequence. Chip

Select (S) can be driven High afte r any bit of the

data-out sequen ce is being shifted out.

In the case of a Page Program (PP), Sector Erase

(SE), Bulk Erase (BE), Write Status Register

(WRSR), Write Enable (WREN), Write Disable

(WRDI) or Deep Power-down (DP) instruction,

Chip Select (S) must be driven High exactly at a

byte bounda ry, otherwise the instruction is reject-

ed, and is not executed. That is, Chip Select (S)

must driven High when the number of clock pulses

after Chip Select ( S) being driven Low is an ex act

multiple of eight.

All attempts to access t he memory array du ri ng a

Write Status Register cycle, Program cycle or

Erase cycle are ignored, and the internal Write

Status Register cycle, P rogram cycle or Erase cy-

cle cont i nues unaf fected.

Table 4. Instruction Set

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RES Release from Deep Power-down,

and Read Electronic Signature 1010 1011 ABh 0 3 1 to

∞

Release from Deep Power-down 0 0 0

M25P40

14/40

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8.)

sets the Write Enable Latc h (WEL) bit.

The Write Enabl e Latch (WEL) bi t must be set pri-

or to every Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register

(WRSR) instruction.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 8. Write Enable (WREN) Instruction Sequen ce

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9.)

resets the Write Enable Latch (WEL ) bit.

The Write Disable (WRDI) inst ruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

–Power-up

– Write Disable (WRDI) instruction completion

– Write Stat us Register (WRSR) instruction

completion

– Page Program ( PP) instruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completion

Figure 9. Write Disable (WRDI) Instruction Sequence

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

15/40

M25P40

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Program, Eras e or Write Status Register cycle is in

progress. When one of these cycl es i s in pr ogress,

it is rec ommended to check the Write In P rogress

(WIP) bit before sending a new instruction to the

device. It is also possibl e to read the Status Reg-

ister continuously, as shown in Figure 10..

Table 5. Status Regi ster Format

The status and cont rol bits of t he Status Register

are as fol l ows:

WIP bit. The Write In Progress (WI P) bit indicates

whether the memory is busy with a Write Status

such a cycle is in progress, when reset to 0 no

suc h cycle is in pro gress.

WE L bi t. The W rite Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, when s et to 0 the inte rnal W r ite Enabl e Latch

is reset and no Write Status Reg ister, P rogram or

Erase instruction is accepted.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Erase instructions. These bits are

written with the Write Status Register (WRSR) in-

struction. When one or both of the Block Protect

(B P2, BP1, BP0) bit s i s set t o 1, the rel evan t me m-

ory area (as defi ned in Table 2.) becomes protect-

ed against Page Progra m (PP) and Sector Erase

(SE) instructions. The Block Protect (BP2, BP1,

BP0) bits can be written provided that the Hard-

ware Protected m ode has not been set. T he Bulk

Erase (BE) instruction is executed if, and only if,

both Block Protect (BP2, BP1, BP0) bits are 0.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in th e Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1 , and W rite Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP2, BP1,

BP0) bec ome read-on ly bits and t he Write S tatus

for execution.

Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

b7 b0

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Regis ter

Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

M25P40

16/40

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction al-

lows new val ues to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been d ecoded and ex ecuted, the de vice se ts

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (S) Low, followed

by the instruction code and the dat a byt e on Serial

Data Input (D).

The instruct i on sequence is shown in Figure 11..

The Write Stat us Regi ster (WRSR) i nstruction has

no effect on b6, b5, b1 and b0 of the Status Reg-

ister. b6 and b5 are always read as 0.

Chip Select (S) must be driven High after the

eighth bit of the data byte has been latched in. If

not, the W rite Status Regi ster (WRSR) i nstruction

is not executed. As soon as Chip Select (S) is driv-

en Hi gh, th e self -timed Write Status Regist er cycl e

(whose du ration is t W) is initia ted. Wh ile the W rite

Status Register cycle is in progress, the Status

Write In P rogress (WIP) bi t. T he Write In Progress

(WIP) bit is 1 during the self-timed Write Status

When the cycle is completed, the Write Enable

Latch (WEL) is reset.

The Write Status Register (WRSR) instruction al-

lows the user to change the values of the Block

Protect (BP2, BP1, BP0) bits, to define the size of

the area that is to be trea ted as read-only, as de-

fined in Table 2.. The Write Status Register

(WRSR) instruction also allows the user to set or

reset the Status Register Write Disable (SRWD)

bit in accordance with the Write Protect (W) signal.

The Status Register Wri te Disable (SRWD) bit and

Write Protect (W) signal allow the device to be put

in the Hardware Pr otected Mode (HPM). The Write

Status Register (WRSR) in struction is n ot execu t-

ed once the Hardware Protected Mode (HPM) is

entered.

Figure 11. Write Status Register (WRSR) Instruction Seq uence

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

17/40

M25P40

Table 6. Protection Mode s

Note: 1. As def i ned by th e values in the Block Protect (BP2, B P 1, B P0) bits of the S tatus Regi ster, as shown in T able 2..

The prot ection f eatures of t he device are su mma-

rized in Table 6..

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possible to write to the Status Regi ster

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, rega rd less o f the wh ether W ri te Protect

(W) is driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be considered , depending on t he state of

Write Protect (W):

– If Wr ite Protect (W) is driven High, i t is

pos sible to write to the Status Register

provided that the Write Enable Latch (WEL) bit

has previously been set by a Write E nable

(WREN ) instruction.

– If Wr ite Protect (W) is driven Low, it is not

poss ible to write to the Status Regist er even if

the Write Enable Latch (WEL) bit has

previously been set by a Write Enable

(WREN ) instruction. (Attempts to write to the

Stat us Register are rejected, and are not

accept ed for execution). As a consequence,

all the data bytes in the memory area t hat are

software protected (SPM) by the Block Protect

(BP2, BP1, BP0) bits of th e Status Register,

are also hardware protected agai nst data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered:

– by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

– or by driving Write Protect (W) Low aft er

setting th e Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protect ed Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected M ode

(SPM), using the Block Protect (BP2, BP1, BP0)

bits of the Status Register, can be used.

Signal SRWD

Bit Mode Write Protection of the

Status Register

Memory Content

Protected Area1Unprotected Area1

Software

Protected

(SPM)

Status Register is Writable

(if the WREN instruction

has set the WEL bit)

The values in the SRWD,

BP2, BP1 and BP0 bits

can be changed

Protected against Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector Erase

instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the SRWD,

BP2, BP1 and BP0 bits

cannot be changed

Protected against Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector Erase

instructions

M25P40

18/40

Read Data Bytes (READ)

The device is first selected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte

address (A23-A0), each bit being latched-in dur ing

the rising edge of Serial Cl ock (C). Then the mem-

ory contents , at that address, is shifted out on Se-

rial Data Output (Q), eac h b it bein g s hifted out, at

a maximum frequency fR, during the falling edge of

Serial Clock (C).

The instruct i on sequence is shown in Figure 12..

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, ther efore, be read

with a singl e Read Data Byt es (REA D) i nst ruction.

When the highes t address is reached, the address

counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruct ion is termi-

nated by driving Chi p Select (S) High. Chip Select

(S) can be driven High at any time during data out-

put. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in

progress, is rej ected without having any ef fects on

th e cycle tha t is in pro gr es s.

Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

Note : 1. Address bits A23 to A19 are Don’t Care.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

19/40

M25P40

Read Data Bytes at Higher Speed

(FAST_READ)

The device is first selected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the

rising edge of S erial Clock (C). Then the me mory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, durin g the falling edg e of

Serial Clock (C).

The instruct i on sequence is shown in Figure 13..

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, ther efore, be read

with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to

000000h, allowing the read sequence to be contin-

ued indefinitely.

The Read Data Bytes at Higher Speed

(FAST_READ) instruction is terminated by driving

Chip Select ( S) Hi gh. Chip Select (S) can be driv-

en High at any time during data output. Any Read

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an Erase, Program or W rite cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 13. Read Data Bytes at Higher Speed (FAST_RE AD) Instruction Sequence and Data-Out

Sequence

Note : 1. Address bits A23 to A19 are Don’t Care.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

M25P40

20/40

Page Program (PP)

The Page Pr ogram (PP) instruction allows bytes to

be programmed in the memory (changing bits from

1 to 0). Before i t can be acc epted, a Wri te Enab le

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been decoded , the device se ts the W rite En-

able Latch (WEL).

The Page Pro gram (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted dat a that goes beyond the end

of the current page are programmed from the st ar t

address of the same page (from the address

whose 8 l east si gnificant bits (A7-A0) are all zero).

Chip Select (S) must be driven Low for the entire

duration of the seq uence.

The instruct i on sequence is shown in Figure 14..

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be programmed cor-

rectly within the sam e page. If less than 2 56 Dat a

bytes are sent to device, they are correctly pro-

grammed at the request ed addres ses without hav-

ing any effects on the other bytes of the same

page.

Chip Select (S) must be driven High after the

eighth bi t of the last data byte has been l atched in,

otherwise the Page Program (PP) instr uction is not

executed.

As soon as Chip Select (S ) is dr iv en Hi gh , t he s elf -

time d Page Prog ram cycle (whose dura ti o n i s tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enabl e Latch (WEL)

bit is re set.

A Page Program (PP) instruction applied to a page

which is protected by the Block Protect (BP2, BP1,

BP0) bits (see Table 3. and Tabl e 2.) is no t ex ecut -

ed.

Figu re 14 . P age Program ( P P) In st ruction Sequence

Note : 1. Address bits A23 to A19 are Don’t Care.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

21/40

M25P40

Se ctor Erase (SE)

The Sector E rase (SE) instruction sets t o 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Writ e Enable Latch (WEL) .

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address by tes on Serial

Data Input (D). Any address inside the Sector (see

Table 3.) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the s equence.

The instruct i on sequence is shown in Figure 15..

Chip Select (S) must be driven High after the

eighth bit of the last address byt e has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Sel ect (S) is driven

High, the self -timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Stat us Register may be read

to check the value of the Write In Progress (WIP)

bit. The Wri t e In Progress (WIP) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enabl e Latch (WEL)

bit is re set.

A Sector Erase (SE) in st ruction applied to a page

which is protected by the Block Protect (BP2, BP1,

BP0) bits (see Table 3. and Tabl e 2.) is no t ex ecut -

ed.

Figure 15. Sector Erase (SE) Instruction Sequ ence

Note : 1. Address bits A23 to A19 are Don’t Care.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M25P40

22/40

Bulk Eras e ( BE)

The Bulk Erase (BE) instruction sets all bits to 1

(FFh). Before it can be acce pted , a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been decoded , the device se ts the W rite En-

able Latch (WEL).

The Bulk Erase (BE) instruction is entered by driv-

ing Chip Select (S) Low, followed by the instruction

code on Serial Data Input (D). Chip Select (S)

must be driven Low for the entire duration of the

sequence.

The instruct i on sequence is shown in Figure 16..

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise the Bulk Erase instruction is not exe-

cuted. As soon as Chip Select (S) is driven High,

th e self-timed Bul k Erase cycl e (wh ose duratio n is

tBE) is initiated. While the Bulk Erase cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Bulk Erase cycle, and is 0 when it is com-

pleted. At some unspeci fied time before the cycle

is completed, the Write Enable Latch (WEL) bit is

reset.

The Bulk Erase (BE) instruction is executed only if

all Block Prote ct (BP2, BP1, BP0) bits are 0. The

Bulk Erase (BE) instruction is ignored if one, or

more, sectors are protected.

Figure 16. Bulk E rase (BE) Instruction Sequence

AI03752D

21 345670

Instruction

23/40

M25P40

Deep Pow er-do wn (DP)

Executing the Deep Power-down (DP) instruction

is the only way to put the device in t he lowest con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism, while the device is not in active use,

since in this mode, the device ignores all Write,

Program and Eras e instructions.

Driving Chip Select (S) High deselects the device,

and puts the device in the Sta ndby m ode (if there

is no internal cycle currently in progress). But this

mode is not the Deep Power-down mode. The

Deep Power-down mode can only be entered by

executing the Deep Power-down (DP) instru ction,

to reduce the standby current (from ICC1 to ICC2,

as specified in Table 12.).

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. This releases

the device from this mode. The Release from

Deep Power-down and Read Electronic Signature

(RES) instruction al so allows the Electronic Signa-

ture of the device to be output on Serial Data Out-

put (Q).

The Deep P ower-down m ode automaticall y stops

at Power-down, and the device always Powers-up

in the St andby mode.

The Deep Power-down (DP) instructi on is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Inp ut (D). Chip Se-

lect (S) m ust be d riven Low for the entire durat ion

of the seq uence.

The instruct i on sequence is shown in Figure 17..

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise t he Deep Power-down (DP) instruc -

tion is not executed. As soon as Chip Select (S) is

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected wi th o ut havi ng any effects on th e cycle that

is in progr ess.

Figure 17. Deep Power-down ( DP) Instru ction Sequence

AI03753D

21 345670tDP

Deep Power-down Mode

Stand-by Mode

Instruction

M25P40

24/40

Release from Deep Power-down and Read

Electronic Signature (RES)

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. Executing this

instruction takes the device out of the Deep Pow-

er-down mode.

The instruction can also be used to read, on Ser ial

Data Output (Q), the 8-bit Electronic Signature,

whose value for the M25P40 is 12h.

Except while an Erase, Program or Write Status

Deep Power-down and Read Electronic Signature

(RES) instruction always provides access to the 8-

bit Electronic Signa ture of the dev ice, and c an be

applied even if the Deep Power-down mode has

not been entered.

Any Release from Deep Power-down and Read

Electronic Signature (RES) instruction while an

Erase, Program or Write Status Register cycle is in

progress, is not decoded, and has no effect on the

cycle that i s in progress.

The device is first selected by driving Chip Sele ct

(S) Low. The instruction code is followed by 3

dummy bytes, each bit being latched-in on Se rial

Data Input (D) during the rising edge of Serial

Clock (C). Then, the 8-bit Electronic Signature,

stored in the memory, is shift ed out on Serial Data

Output (Q), each bit being shifted out during the

falling edge of Serial Clock (C).

The instruct i on sequence is shown in Figure 18..

The Release from Deep Power-down and Read

Electronic Si gnature (RES) instruction is terminat-

ed by driving Chip Select (S) High after the Elec-

tronic Signature has been read at least once.

Sending additional clock cycles on Serial Clock

(C), while Chip Select (S) is dr iven Low, cause the

Electronic Signature to be output repeatedly.

When Chip Select (S) i s dr i ven High, t he devi ce is

put in the Stand-by Power mode. If the device was

not previously in the Deep Power-down mode, the

transition to t he St and-by Pow er m ode is immedi-

ate. If the device was previously in t he Deep Pow-

er-down mode, though, the transition to the Stand-

by Power mode i s delayed by tRES2, and Chip Se-

lect ( S ) must remain High for at least tRES2(max),

as specified in Table 17.. Once in the Stand-by

Power mode, the device waits to be selected, so

that it can receive, decode and execute instruc-

tions.

Figure 18. Rel ease from Deep Po wer-d ow n and Read Electro nic Signatur e (RES) Instruction

Sequence and Dat a- Out Seque nce

Note: Th e value of th e 8-bit Elec tronic S i gnature, for the M2 5P40, is 12h.

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic Signature Out

Instruction 3 Dummy Bytes

MSB

Stand-by Mode

Deep Power-down Mode

MSB

tRES2

25/40

M25P40

Figure 19. Rel ease from Deep Power-down (RES) Instruction Sequen ce

Driving Chip Select (S) High after the 8-bi t instruc-

tion byte has been received by the device, but be-

fore the whole of the 8-bit Electronic Signature has

been transmit ted for the first time (as shown in Fig-

ure 19.), still insures that the device is put into

Stand-by P ower mode. I f the d evice was not pre-

viously in the Deep Power-down mode, the transi-

tion to the Stand-by Power mode is immediate . If

the device was previously in the Deep Power-

down mode, though, the t ransition to the Stand-by

Power mode is delayed by tRES1, and Chip Select

(S) must remain High for at least tRES1(max), as

specified in Table 17.. Once in t he Stand-by Power

mode, the device waits to be selected, so that it

can receive, decode and execut e instructions.

AI04078B

21 345670tRES1

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

M25P40

26/40

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selected (that is Chip Select (S ) must follow

the volt age appl ied on VCC) u nt il VCC reache s the

correct value:

–V

CC(min) at Power-up, and then for a f urther

delay of tVSL

–V

SS at P o wer-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to insure safe and proper Power-up

and Power-down.

To avoid data corruption and inadvertent write op-

erations during power up, a Power On Reset

(POR) circuit i s included. Th e logic i nsi de the de-

vice is held reset w hile V CC is less than the POR

threshold value, VWI – a ll operations are disabled,

and the device does not respond to any instruc-

tion.

Moreover, the device ignores all Write Enable

(WREN), Page Program (PP), Sector Erase (SE),

Bulk Erase (BE) and Write Status Register

(WRSR) instructions until a time delay of tPUW has

elapsed after the moment that VCC rises above the

VWI threshold. However, the correct operation of

the device is not guaranteed if, by t his time, VCC is

still below VCC(min). No Write Status Register,

Program or Erase inst ructions should be sent until

the later of:

–t

PUW after VCC passed the VWI threshold

–t

VSL afterVCC passed the VCC(min ) le v e l

These values are specified in Table 7..

If the delay, tVSL, has elapsed, after VCC has risen

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not yet

fully elapsed.

At Po wer-up, the device is in the following state:

– The dev ice is in the Standby mode (not the

D eep Power-down mod e).

– The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail

decoupling, to stabilize the VCC f eed. Each device

in a syst em should have t he VCC r ail decoupled by

a suitable capacitor close to the package pins.

(Generally, this capacitor is of the order of 0.1µF).

At Power-down, when VCC drops from the operat-

ing voltage, to below the POR threshold value,

VWI, all operations are disabled and the device

does not respond to any instruct ion. (The designer

needs to be aware that if a Power-down occurs

while a Write, Program or Erase cycle is in

progress, some data corruption can result.)

27/40

M25P40

Figure 20. Power-up Timing

Table 7. Power-Up Timing and VWI Thresh ol d

Note: 1. These parameters are characterize d onl y.

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains FFh). The Status Regi ster cont ains 00h (all Status

Symbol Parameter Min. Max. Unit

tVSL1VCC(min) to S low 10 µs

tPUW1Time delay to Write instruction 1 10 ms

VWI1Write Inhibit Voltage 1 2 V

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

M25P40

28/40

MAXI MUM RAT IN G

Stressing the device ab ove t he rating listed in t he

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at t hese or

any other con ditions ab ove those i ndicated in t he

Operating sections of this specification is not im-

plied. Exposure to Absolute Max imum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Note : 1. Comp liant wit h JED EC Std J- STD- 020 B (for s mal l bod y, Sn-P b or P b asse mbl y), the ST ECOP ACK ® 7191395 s pecificat i on, and

the Eu ropean di rectiv e on Restr i ct i ons on Haz ardous S ubstan ces (RoHS) 2002/ 95/EU

2. JED EC St d J ESD22 -A 114A (C 1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note 1°C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V

29/40

M25P40

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement condition s, and the DC and AC charac-

teristics o f the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions in t heir circuit matc h the measurem ent

conditions when relying on the quoted parame-

ters.

Table 9. Operating Conditions

Tab le 10. Dat a Re te nt io n and Endu ra nce

Note: 1. This is preliminary data

Table 11. C apacitanc e

Note: Sampled o nl y, not 100% tested, at TA= 25°C and a f requency of 20MH z.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmbient Operating Temperature (Device Grade 6) –40 85 °C

Ambient Operating Temperature (Device Grade 3) –40 125

Parameter Condition Min. Max. Unit

Erase/Program Cycles Device Grade 6 100 000 cycles per

sector

Device Grade 3 1 10 000

Data Retention Device Grade 6 20 years

Device Grade 3 1 (at 85°C) 20

Symbol Parameter Test Condition Min.Max.Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

M25P40

30/40

Table 12. DC Characteristics (Device Grad e 6)

Table 13. D C Character istics (Device Grad e 3)

Note: 1. This is preliminary data

Symbol Parameter Test Condition

(in addition to those in Table 9.)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 10 µA

ICC3 Operating Current (READ)

C=0.1V

CC / 0.9.VCC at 40MHz,

Q = open 8mA

C=0.1V

CC / 0.9.VCC at 20MHz,

Q = open 4mA

ICC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operating Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Vol tage –0.5 0.3VCC V

VIH Input High Volta ge 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6mA 0.4 V

VOH Output High Voltage IOH = –100µAV

CC–0.2 V

Symbol Parameter Test Condition

(in addition to those in Table 9.)Min.1Max.1Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 100 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 50 µA

ICC3 Operating Current (READ)

C=0.1V

CC / 0.9.VCC at 40MHz,

Q = open 8mA

C=0.1V

CC / 0.9.VCC at 20MHz,

Q = open 4mA

ICC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operating Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Volta ge 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6mA 0.4 V

VOH Output High Voltage IOH = –100µAV

CC–0.2 V

31/40

M25P40

Table 14. Ins tructi on Times (Device Gra de 6)

Table 15. Ins tructi on Times (Device Gra de 3)

No te : 1. At 85°C

2. This is preli minary dat a

Table 16. A C Measu rement Cond itions

Note: Output Hi-Z is defined as the point where data ou t is no longer driven.

Figu re 21. A C Measure m ent I/O W av eform

Test conditions specified in Table 9. and T able 16.

Symbol Alt. Parameter Min. Typ. Max. Unit

tWWrite Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 1.4 5 ms

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 4.5 10 s

Test conditions specified in Table 9. and T able 16.

Symbol Alt. Parameter Min. Typ.1,2 Max.2Unit

tWWrite Status Register Cycle Time 8 15 ms

tPP Page Program Cycle Time 1.5 5 ms

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 4.5 10 s

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Refer ence Volta ges VCC / 2 V

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

0.5VCC

M25P40

32/40

Table 17. AC Character istics (25MHz Operati on, Device Grad e 6 or 3)

Note: 1. tCH + tCL must be gr eater than or e qual to 1/ fC

2. Value guaranteed by characterization, not 100% tested i n product i on.

3. Expressed as a slew-rate.

4. Only applicab l e as a const raint fo r a WRSR instruction when S RWD is set at 1.

5. For de vi ce grade 3, this i s P rel i m i nary Data

Test conditions specified in Table 9. and T able 16.

Symbol Alt. Parameter Min.5Typ. Max.5Unit

fCfCClock Frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES,

WREN, WRDI, RDSR, WRSR D.C. 25 MHz

fRClock Fre quen cy for READ instruc tions D.C. 20 MH z

tCH 1tCLH Clock High Time 18 ns

tCL 1tCLL Cl ock Low Tim e 18 ns

tCLCH 2Cl ock Rise Time3 (peak to peak) 0.1 V/ns

tCHCL 2Cl ock Fall Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 10 ns

tSHCH S Not Active Setup Time (relative to C) 10 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ 2tDIS Output Disable Time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO O utput Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 10 ns

tCHHH HOLD Hold Time (relative to C) 10 ns

tHHCH HOLD Setup Time (relative to C) 10 ns

tCHHL HOLD Hold Time (relative to C) 10 ns

tHHQX 2tLZ HOLD to Output Low-Z 15 ns

tHLQZ 2tHZ HOLD to Output High-Z 20 ns

tWHSL 4Write Protect Setup Time 20 ns

tSHWL 4Write Protect Hold Time 100 ns

tDP 2S High to Deep Power-down Mode 3 µs

tRES1 2S High to Standby Mode without Electronic

Signature Read 3µs

tRES2 2S High to Standby Mode with Electronic

Signature Read 1.8 µs

33/40

M25P40

Table 18. AC Characteristics (40MHz Operati on , Device Grade 6)

Note: 1. tCH + tCL must be gr eater than or e qual to 1/ fC

2. Value guaranteed by characterization, not 100% tested i n product i on.

3. Expressed as a slew-rate.

4. Only applicab l e as a const raint fo r a WRSR instruction when S RWD is set at 1.

5. Detail s of how to f i nd the dat e of m arki ng are given in Applica tion Note, AN1995.

40MHz available for products marked since week 20 of 2004, only5

Test conditions specified in Table 9. and T able 16.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES,

WREN, WRDI, RDSR, WRSR D.C. 40 MHz

fRClock Fre quen cy for READ instruc tions D.C. 20 MH z

tCH 1tCLH Clock High Time 11 ns

tCL 1tCLL Cl ock Low Tim e 11 ns

tCLCH 2Cl ock Rise Time3 (peak to peak) 0.1 V/ns

tCHCL 2Cl ock Fall Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ 2tDIS Output Disable Time 9 ns

tCLQV tVClock Low to Output Valid 9 ns

tCLQX tHO O utput Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX 2tLZ HOLD to Output Low-Z 9 ns

tHLQZ 2tHZ HOLD to Output High-Z 9 ns

tWHSL 4Write Protect Setup Time 20 ns

tSHWL 4Write Protect Hold Time 100 ns

tDP 2S High to Deep Power-down Mode 3 µs

tRES1 2S High to Standby Mode without Electronic

Signature Read 3µs

tRES2 2S High to Standby Mode with Electronic

Signature Read 1.8 µs

M25P40

34/40

Figure 22. Serial Input Timing

Figu re 23. W ri t e Pr ot ect Setup an d Hol d Ti m in g during WRS R when SRW D =1

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

35/40

M25P40

Figu re 24 . Hol d T im i ng

Figu re 25. Ou t pu t Tim i ng

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

AI01449D

LSB OUT

ADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

M25P40

36/40

P ACKAGE MECHANI CAL

Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outline

No te : Drawing is not to scal e.

Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27––0.050––

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

SO-a

LA1 α

h x 45˚

37/40

M25P40

Figure 27. M LP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm , Packa ge Ou tline

No te : Drawing is not to scal e.

Table 20. ML P8 , 8-lead Very thin Dual Flat Package No lead, 6x5m m, Packag e Mech anical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.20 0.1575 0.1496 0.1654

e 1.27 0.0500

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

θ12° 12°

VDFPN-01

eE2

M25P40

38/40

PART NUMBERING

Table 21. Ordering Information Scheme

Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-

tified F l ow (HRCF) is described i n the quality note QNEE9801. Please ask your nearest ST sales off i ce for a co py.

2. Available fo r S O8 package only

3. Available for MLP package only

4. Devi ce grade 3 a vailable i n SO8 Lead-fre e and RoHS compl i ant package

For a list of available opt ions (speed, package, etc.) or for further inf ormation on any aspect of this devic e,

please contact your nearest ST Sales Office .

Example: M25P40 – V MN 6 T P

Device Type

M25P = Serial Flash Memory for Code Storage

Device Function

40 = 4 Mbit (512K x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MN = SO8 (150 mil width)

MP = VDFPN8 6x5mm (MLP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3 4 = Device tested with High Reliability Certified Flow1.

Automotive temperature range (–40 to 125 °C)

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating

P2 = Lead-Free and RoHS compliant

G3 = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

39/40

M25P40

REVISION HISTORY

Table 22. Document Revi sion History

Date Rev. Description of Revision

12-Apr-2001 1.0 Document written

25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory

11-Sep-2001 1.2

Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes;

Release from Power-down and Read Electronic Signature (RES); Power-up

Repositioning of several tables and illustrations without changing their contents

Power-up timing illustration; SO8W package removed

Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL

16-Jan-2002 1.3 FAST_READ instruction added. Document revised with new timings, VWI, ICC3 and clock slew

rate. Descriptions of Polling, Hold Condition, Page Programming, Release for Deep Power-

down made more precise. Value of tW(max) modified.

12-Sep-2002 1.4 Clarification of descriptions of entering Stand-by Power mode from Deep Power-down mode,

and of terminating an instruction sequence or data-out sequence.

VFQFPN8 package (MLP8) added. Document promoted to Preliminary Data.

13-Dec-2002 1.5

Typical Page Prog ram time improved. Deep P ow er-down current changed. Write Protect setup

and hold times specified, for applications that switch Write Protect to exit the Hardware

Protection mode immediately before a WRSR, and to enter the Hardware Protection mode

again immediately after.

12-Jun-2003 1.6 Document promoted from Preliminary Data to full Datasheet

24-Nov-2003 2.0 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.

40MHz AC Characteristics table included as well as 25MHz. ICC3(max), tSE(typ) and tBE(typ)

values improved. Change of naming for VDFPN8 package

12-Mar-2004 3.0 Automotive range added. Soldering temperature information clarified for RoHS compliant

devices

05-Aug-2004 4.0 Device Grade information clarified. Data-retention measurement temperature corrected.

Details of how to find the date of marking added.

M25P40

40/40

Information furnished is believed to b e accurate and reliable. However, S TMicroelectronics assumes no re sponsibility for the conseq

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication ar e

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronic s products

authorized for us e as critical com ponents in life support devices or sys te m s without express written approval of STMi croelect ron

The ST l ogo i s a regi st ered tra dem ark of STMi croelectron ics.

All other names are th e property of their respective o wners

STM i croelectron ics group of compan i es

Aus tralia - B el gium - Brazil - Canad a - China - Czech Rep ubl i c - Finland - Fra nce - Germ any - Hong K ong - India - Israel - Italy - J

Malaysia - M a l t a - Moroc co - Singapore - Sp ai n - Sweden - Swit zerlan d - United Kingdom - Unite d States of Americ a