M29W320EB70N6F - STMicroelectronics

1/46March 2005

M29W320ET

M29W320EB

32 Mbit (4Mb x8 or 2Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■SUPPLY VOLTA GE

–V

CC = 2.7V to 3.6V for Program, Erase

and Read

–V

PP =12V for Fast Program (optional)

■ACCESS TIMES: 70, 90ns

■PROGRAMMING TIME

– 10µs per Byte/Word typical

– Double Word/ Quadruple Byte Program

■MEMORY BLOCKS

– Memory Array: 63 Main Blocks

– 8 Parameter Blocks (Top or Bottom

Location)

■ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Susp e nd

■UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■VPP/WP PIN for FAST PROGRAM and

WRITE PROTECT

■TEMPORARY BLOCK UNPROTECTION

MODE

■COMMON FLASH INTERFACE

– 64 bit Security Code

■EXTENDED MEMORY BLOCK

– Extra block used as security block or to

store additional information

■LOW POWER CONSUMPTION

– Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufactu rer Code : 0020h

– Top Device Code M29W320ET: 2256h

– Bottom Device Code M29W320EB: 2257h

Figure 1. Packages

TSOP48 (N)

12 x 20mm

FBGA

TFBGA4 8 (Z E )

6 x 8mm

M29W320ET, M29W320EB

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TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write En abl e (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

VPP/Write Pr ote ct (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3/46

M29W320ET, M29W320EB

Fast Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Enter Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Commands, 8-b it mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 12.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled. . . . . . . . . . . . 27

Figure 15.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . 27

Table 15. Toggle and Alternative Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M29W320ET, M29W320EB

4/46

Table 16. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . . 29

Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 29

Figure 19.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 30

Table 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 30

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 20. Top Boot Block Addresses, M29W320ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 21. Bottom Boot Block Addresses, M29W320EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 23. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 24. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 25. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 26. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 27. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 28. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 29. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 22.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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M29W320ET, M29W320EB

SUMMARY D ESCRIPTION

The M29W320E is a 32 Mbit (4Mb x8 or 2Mb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode.

The device fe atures an asymme trical block arc hi-

tecture. The M29W320E has an array of 8 param-

eter and 63 main blocks. M29W320ET locates the

Parameter Blocks at the top of the memory ad-

dress space while the M29W320EB locates the

Parameter Blocks starting from the bottom.

M29W320E has an extra 32 KWord (x16 mode) or

64 KByte (x8 mode) block, the Extended Block,

that can be accessed using a dedicated com-

mand. The E xtended Block c an be protected and

so is useful fo r storing security in formation. How-

ever the protection is irreversible, once protected

the protection cannot be undone.

Each block can be erased independently so it is

possible to preserve valid data while old data is

erased. The blocks can be protected to prevent

accidental Program or Erase commands from

modifying the memory. Program and Erase com-

mands are written to the Command Interface of

the memory. An on-chip Program/Erase Controller

simplifies the process of programming or erasing

the memory by taking care of all of the special op-

erations that are required to update the memory

contents. The end of a program or erase operation

can be detected and any error conditions identi-

fied. The command set required to control the

memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is of fered i n TSOP48 (1 2x20mm), a nd

TFBGA48 (6x8mm, 0.8mm pitch) packages. The

memory is supplied with all the bits erased (set to

’1’).

Figure 2. Logic Diagram Table 1. Signal Names

AI09346

A0-A20

DQ0-DQ14

VCC

M29W320ET

M29W320EB

VSS

DQ15A–1

BYTE

VPP/WP

A0-A20 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/B lo ck Tempora ry Unpr ote ct

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply Voltage

VPP/WP VPP/Write Protect

VSS Ground

NC Not Conn ect ed Inter na lly

M29W320ET, M29W320EB

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Figure 3. TSOP Connections

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

VPP/WP

AI09347

M29W320ET

M29W320EB

24 25

DQ8

A20

A19

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

7/46

M29W320ET, M29W320EB

Figure 4. TFBGA48 Connections (Top view through package)

654321

VSS

A15

A14

A12

A13

DQ3

DQ11

DQ10

A18

VPP

DQ1

DQ9

DQ8

DQ0

A17

DQ2

DQ6

DQ13

DQ14

A10

DQ4

VCC

DQ12

DQ5

A19

A11

DQ7

VSS

A5 A20

A16

BYTE

DQ15

A–1

AI08084

M29W320ET, M29W320EB

8/46

Figure 5. Block Addresses (x8)

Note: Also see APPENDIX A., Table 20. and Table 21 . for a full listing of the Block Addresses.

AI09348

64 KByte or

32 KWord

000000h

00FFFFh

64 KByte or

32 KWord

3E0000h

3EFFFFh

Top Boot Block (x8)

Address lines A20-A0, DQ15A-1

64 KByte or

32 KWord

2F0000h

2FFFFFh

64 KByte or

32 KWord

300000h

30FFFFh

8 KByte or

4 KWord

3FE000h

3FFFFFh

8 KByte or

4 KWord

3F0000h

3F1FFFh

Total of 63

Main Blocks

Total of 8

Parameter

Blocks

(1)

8 KByte or

4 KWord

000000h

001FFFh

64 KByte or

32 KWord

0F0000h

0FFFFFh

Bottom Boot Block (x8)

Address lines A20-A0, DQ15A-1

8 KByte or

4 KWord

00E000h

00FFFFh

Total of 8

Parameter

Blocks

(1)

64 KByte or

32 KWord

010000h

01FFFFh

64 KByte or

32 KWord

3F0000h

3FFFFFh

64 KByte or

32 KWord

100000h

10FFFFh

Total of 63

Main Blocks

Note 1. Used as Extended Block Addresses in Extended Block mode.

9/46

M29W320ET, M29W320EB

Figure 6. Block Addresses (x16)

Note: Also see APPENDIX A., Table 20. and Table 21 . for a full listing of the Block Addresses.

AI09349

64 KByte or

32 KWord

000000h

007FFFh

64 KByte or

32 KWord

1F0000h

1F7FFFh

Top Boot Block (x16)

Address lines A20-A0

64 KByte or

32 KWord

178000h

17FFFFh

64 KByte or

32 KWord

180000h

187FFFh

8 KByte or

4 KWord

1FF000h

1FFFFFh

8 KByte or

4 KWord

1F8000h

1F8FFFh

Total of 63

Main Blocks

Total of 8

Parameter

Blocks

(1)

8 KByte or

4 KWord

000000h

000FFFh

64 KByte or

32 KWord

078000h

07FFFFh

Bottom Boot Block (x16)

Address lines A20-A0

8 KByte or

4 KWord

007000h

007FFFh

Total of 8

Parameter

Blocks

(1)

64 KByte or

32 KWord

008000h

00FFFFh

64 KByte or

32 KWord

1F8000h

1FFFFFh

64 KByte or

32 KWord

080000h

087FFFh

Total of 63

Main Blocks

Note 1. Used as Extended Block Addresses in Extended Block mode.

M29W320ET, M29W320EB

10/46

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table

1., Signal Names, for a brief overview of the sig-

nals connected to this device.

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the Program/Erase

Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O

outputs the data stored at the selected address

during a B us Rea d operation wh en B YTE is Hi gh,

VIH. When BYTE is Low, VIL, these pins are not

used and are high impedance. During Bus Write

operations the Command Register does not use

these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A–1).

When BYTE is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the ad-

dressed Word, DQ15A–1 High will select the MSB.

Throughout the text consider references to the

Data Input/Output to include this pin when BYTE is

High and references to the Address Inputs to in-

clude this pin when BYTE is Low except when

stated expli citl y otherwi s e.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Writ e En a bl e, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

VPP/Write Protect (VPP/WP). The VPP/Write

Protect pi n provides two functi ons. The VPP fu nc-

tion allows the memory to use an external high

voltage powe r supply to reduce the time required

for Program operations. This is achieved by by-

passing the unlock cycles and/or using the Double

Word or Quadruple Byte Program commands.

The Write Protect function provides a hardware

method of protecting the two outermost boot

blocks. When VPP/Write Protect is Low, VIL, the

memory protects the two outermost boot blocks;

Program and Erase operations in these blocks are

ignored while VPP/Write Protect is Low, even when

RP is at VID.

When VPP/Write Protect is High, VIH, the memory

reverts to the previous protection status of the two

outermost b oot blo cks. Program and Erase oper-

ati ons can n ow modi fy the d ata in these blocks un-

less the blocks are protected using Block

Protection.

When VPP/Write Protect is raised to VPP the mem-

ory automatically enters the Unlock Bypass mode.

When VPP/Write Prot ect returns to VIH or VIL nor-

mal operation resumes. During Unlock Bypass

Program operations the memory draws IPP from

the pin to supply the programming circuits. See the

descripti on o f the Unlock Bypas s c omm and in the

Command Interface section. The transitions from

VIH to VPP and from VPP to VIH must be slower

than tVHVPP, see Figure 17.

Never raise VPP/Write Protect to VPP from any

mode except Read mode, otherwise the memory

may be left in an indeterminate state.

The VPP/Write Protect pin must not be left floating

or u nconnected or t he device may become unreli-

able. A 0.1µF cap acitor should be connec ted be-

tween the VPP/Write Protect pin and the VSS

Ground pin to decouple the current surges from

the power supply. The PCB track widths mus t be

sufficient to carry the currents required during

Unlock Bypass P rogram, IPP.

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to tempora rily un prote ct all Bl ock s t hat h av e be en

protected.

Note that if VPP/WP is at VIL, then the two outer-

most boot blocks will remain protected even if RP

is at VID.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High , VIH, the memory will be re ady for Bu s

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy

Output section, Table 16. and Figure 16., Reset/

Block Temporary Unprotect AC Waveforms, for

more details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

11/46

M29W320ET, M29W320EB

Ready/Busy is Low, VOL. Ready/Busy is high-im -

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 16. and Figure

16., Res et/Block Temporar y Unprotec t AC Wave -

forms.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte/Wor d Organiza tion Selec t (BYTE). The

Byte/Word Organization Select pin is used to

switch betwe en the x8 and x1 6 Bus modes of the

memory. When Byte/ Word Organi zation Sel ect is

Low, VIL, the memory is in x8 mode, when it is

High, VIH, the memory is in x16 mode.

VCC Supply Voltage (2.7V to 3.6V). VCC pro-

vides the power supply for all operations (Read,

Program and Erase).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the VCC Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during Program and

Erase operations, ICC3.

VSS Ground. VSS is the reference for all voltage

measure men ts. The d ev ice fe atur es tw o V SS pin s

which must be both connected to the system

ground.

M29W320ET, M29W320EB

12/46

BUS OPERATIONS

There are five standard bus operations that control

the device. Thes e are Bus Read, Bus Writ e, Out-

put Disable, Standby and Automatic Standby.

See Table 2. and Table 3., Bus Operations, for a

summary. Typically glitches of less than 5ns on

Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, ap plyi ng a Low signal , V IL, to Chip Enable

and Output Enable and keeping Write Enable

High, VIH. The Data Inputs /Outp uts wil l outpu t the

value, see Figure 11., Read Mode AC Waveforms,

and Table 12., Read AC Characteristics, for de-

tails of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inpu ts/Ou tputs are l atched by the Com -

mand Interfa ce on the rising ed ge of Chip Enab le

or Write Enable, whichever occurs first. Output En-

able must rema in High , VIH, duri ng the whol e Bu s

Write operation. See Figure 12. and Figure 13.,

Write AC Waveforms, and Table 13. and Table

14., Write AC Characteristics, for details of the tim-

ing requirements.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For the Standby current

level see Table 11., DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til the operation completes.

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to drive the bus and the bus is inactive for

300ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intende d for use by program ming eq uip-

ment and are not usually used in applications.

They require VID to be applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These cod es can b e read b y apply ing the s ignals

listed in Table 2. and Ta ble 3., Bus Operations.

Block Protect and

Chip Unprotect.

Groups of

blocks can be protected against accidental Pro-

gram or Era se. Th e Protect ion Groups are shown

in APPENDIX A., Table 20. and Table 21., Block

Addresses . T he whol e ch ip ca n be unp ro tect ed to

allow the data inside the blocks to be changed.

The V PP/Wr ite Pr otect pin can be us ed to protect

the two outermost boot blocks. When VPP/Write

Protect is at VIL the two outermost boot blocks are

protected and remain protected regardless of the

Block Protection Status or the Reset/Block Tem-

porary Unprotect pin status.

Block Protect and Chip Unprotect operations are

described in APPENDIX D.

13/46

M29W320ET, M29W320EB

Table 2. Bus Operations, BYTE = VIL

Note: X = VIL or VIH.

Table 3. Bus Operations, BYTE = VIH

Note: X = VIL or VIH.

Operation E G W Address Inputs

DQ15 A– 1, A0 -A2 0 Data I nputs/ Out puts

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Comman d Ad dre ss Hi-Z Data Input

Output Dis ab le X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL,

A9 = VID, Others VIL or VIH Hi-Z 56h (M29W320ET)

57h (M29W320EB)

Extende d Me mo ry

Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL,

A9 = VID, Others VIL or VIH Hi-Z 81h (factory locked)

01h (not factory locked)

Operation E G W Address Inputs

A0-A20 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Dis ab le X VIH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or VIH 2256h (M29W320ET)

2257h (M29W320EB)

Extende d Me mo ry

Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL,

A9 = VID, Others VIL or VIH 81h (factory locked)

01h (not factory locked)

M29W320ET, M29W320EB

14/46

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. See either Table 4., or Tabl e 5., depend-

ing on the configuration that is being used, for a

summary of the commands.

Read/Reset Command

The Read/Reset command returns the memory to

its Read mode. It also resets the errors in the Sta-

tus Register. Ei the r one or three Bu s Wr i te ope ra-

tions can be used to issue the Read/Reset

command.

The Read/Reset command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. If the Read /Res et c omm and is issu ed

during the time-out of a Block erase operation then

the memory will take up to 10µs to abort. During

the abort period no valid data can be read from the

memory. The Read/Reset command will not abort

an Erase operation when issued while in Erase

Suspend.

Auto Select Command

The Auto Select command is used to read the

Manufacturer Code, the Device Code, the Block

Protection Status and the Extended Memory Block

Verify Cod e. Three consecuti ve Bus Write opera -

tions are required to issue the Auto Select com-

mand. The memory remai ns in Auto S elect mode

until a Read/Reset or CFI Query command is is-

sued.

In Auto Select mode the Manufacturer Code can

be read using a Bus Read operation with A0 = VIL

and A1 = VIL. The other address bits may be set to

either VIL or VIH.

The Device Code can be read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either VIL or VIH.

The Blo ck Pro tectio n Statu s of ea ch bl ock c an be

read using a Bus Read operation with A0 = VIL,

A1 = VIH and A12-A20 specifying the block ad-

dress. The other address bits may be set to either

VIL or VIH. If the addressed block is protected then

01h is output on Data Inputs/Outputs DQ0-DQ7,

otherwise 00h is output.

Read CFI Query Command

The Read CFI Query Command is used to read

data from the Common Flash Interface (CFI)

Memory Area. This command is valid when the de-

vice is in the Read Array mode, or when the device

is in Auto Select mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subs equent Bus Read operatio ns read fr om

the Common Flash Interface Memory Area.

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Auto Select mode). A second Read/

Reset com mand wo uld be needed if the d evice i s

to be put in the Read Array mode from Auto Select

mode.

See APPEND IX B., Tables 22, 23, 24, 25, 26 and

27 for details on the information contained in the

Common Flash Interface (CFI) memory area.

Program Command

The Program command can be used to program a

value to one address in the memory array at a

time. The co mma nd re quir es four Bus Write op er -

ations, the final write operation latches the ad-

dress and data, and starts the Program/Erase

Controller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the p rogram op eration the memor y will ig-

nore all com mands . It is no t possib le to iss ue any

command to abort or pause the operation. After

programming has started, Bus Read operations

output the Status Register content. See the sec-

tion on the STATUS REGISTER for more d etails.

Typical program times are given in Table 6.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs Bus

Read operations will continue to output the Status

to reset the error condition and return to Read

mode.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

15/46

M29W320ET, M29W320EB

Fast Program Commands

There are two F as t P rogr am c omm and s av ailable

to improve the programming throughput, by writing

several adjacent words or bytes in parallel. The

Quadruple Byte Program command is available for

x8 operations, while the Double Word Program

command is available for x16 operations.

Fast Program commands should not be attempted

when VPP/WP is not at VPP. Care must be taken

because applying a 12V VPP voltage to the VPP/

WP pin will temporarily unprotect any protected

block.

After programming has started, Bus Read opera-

tions output the Status Register content.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs Bus

Read operations will continue to output the Status

to reset the error condition and return to Read

mode.

Note that the Fast Program commands cannot

change a bit set at ’0’ back to ’1’. One of the Erase

Commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

Typical Program times are given in Table

6., Program, Erase Times and Program, Erase

Endurance Cycles

Quadruple Byte Program Command. The Qua-

druple Byte Program comma nd is used to wri te a

page of four adjacent Bytes in parallel. The four

bytes must differ only for addresses A0, DQ15A-1.

Five bus write cycles are necessary to issue the

Quadruple Byte Program command.

■The first bus cycle sets up the Quadruple Byte

Program Command.

■The second bus cycle latches the Address and

the Data of the first byte to be written.

■The third bus cycle latches the Address and

the Data of the second byte to be written.

■The fourth bus cycle latches the Address and

the Data of the third byte to be written.

■The fifth bus cycle latches the Address and the

Data of the fourth byte to be written and starts

the Program/Erase Controller.

Double Word Program Command. The Double

Word Program com mand is used to write a page

of two adjacent words in parallel. The two words

must differ only for the address A0.

Three bu s w ri te c ycl es are necessar y to i ssue the

Double Word Program command.

■The first bus cycle sets up the Double Word

Program Command.

■The second bus cycle latches the Address and

the Data of the first word to be written.

■The third bus cycle latches the Address and

the Data of the second word to be written and

starts the Program/Erase Controller.

Unlock Bypass Command

The Unloc k Bypas s com mand is used in conju nc-

tion with the Unlock Bypass Program command to

program the memory faster than with the standard

program commands. When the cycle time to the

device is long, considerable time saving can be

made by using these commands. Three Bus Write

operations are required to issue the Unlock By-

pass comma nd.

Once the Unlock Bypass command has been is-

sued the memory enters Unlock Bypass mode.

The Unlock Bypass Program command can then

be issued to program addresses or the Unlock By-

pass Reset command can be issued to return to

Read mode. In Unlock Bypass mod e the memor y

can be read as if in Read mode.

When V PP is applie d to the VPP/Write Protect pin

the memory automatically enters the Unlock By-

pass mode and the Unlock Bypass Program com-

mand can be issued immediately. Care must be

taken bec ause apply ing a 12V VPP voltage to the

VPP/WP pin will temporarily unprotect any protect-

ed block.

Unlock Bypass Program Command

The Unlock Bypass Program command can be

used to program one address in the memory array

at a time. The command requires two Bus Write

operations, the final write operation latches the ad-

dress and data, and starts the Program/Erase

Controller.

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. The

operation cannot be aborted, a Bus Read opera-

tion outputs the Status Register. See the Program

command for details on the behavior.

Unlock Bypass Reset Command

The Unloc k Bypa ss Re set comm and ca n be us ed

to return to Read/Reset mode from Unlock Bypass

Mode. Two Bus Write operations are required to

issue th e Unlock B ypass Reset command. Re ad/

Reset command does not exit from Unlock Bypass

Mode.

Chip Erase Command

The Chip Erase command can be used to erase

the entire chip. Six Bus Write operations are re-

quired to issue the Chip Erase Command and start

the Program/Erase Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100µs,

M29W320ET, M29W320EB

16/46

leaving the da ta unc hanged . No err or con dition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all comman ds , inc lud in g the Eras e S usp end com -

mand. I t is not po ssible to iss ue any command to

abort the operation. Typical chip erase times are

given in Table 6.. All Bus Read ope rations du ring

the Chip Erase operation will output the Status

tion on the Status Register for more details.

After the C hip Erase o peration has c om pleted the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command

The Block Erase c ommand can be u sed to erase

a list of one or more blocks. It sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

Six Bus Write operations are required to select the

first block in the list. Each additional block in the

list can be selected by repeating the sixth Bus

Write operation using the address of the additional

block. The Block Erase operation starts the Pro-

gram/Erase Controller after a time-out period of

50µs after the last Bus Wr ite operatio n. Once the

Program/Erase Controller starts it is not possible

to select any more blocks. Each additional block

must ther efor e be selec ted wi thin 50µs o f t he la st

block. Th e 50 µ s tim er rest arts when an add ition al

block is s elected . After the six th Bus W rite ope ra-

tion a Bus Read operation will output the Status

tails on how to identify if the Program/ Erase Con-

troller has started the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are prot ected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Bl ock Er ase o per at ion the memory wil l

ignore all commands except the Erase Suspend

command and the Read/Reset command which is

only accepted during the 50µs time-out period.

Typical block erase times are given in Table 6.

After the Erase operation has started all Bus Read

operations will output the Status Register on the

Data Inputs/Outputs. See the section on the Sta-

tus Register for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs Bus

Read operations will continue to output the Status

to reset the error condition and return to Read

mode.

Erase Suspe nd C ommand

The Erase Suspend Command may be used to

temporar ily sus pend a Bloc k Eras e oper ation a nd

return the mem ory to Read mode. The co mmand

require s one Bu s Write operatio n.

The Progra m/Erase Controlle r will suspen d with in

the Erase Suspend Latency time of the Erase Sus-

pend Command being issued. Once the Program/

Erase Controller has stopped the memory will be

set to Read mode and the Erase wil l be susp end-

ed. If the Er as e S usp end co mma nd i s is su ed d ur -

ing the p eriod when the memory is waiting for an

additional block (before the Program/Erase Con-

troller starts) then the Erase is suspended immedi-

ately and will start immediately when the Erase

Resume Comm and is issu ed. It is not pos sible to

select any further blocks to erase after the Erase

Resume.

During Erase Suspend it is possible to Re ad and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these b locks. I f any atte mpt is mad e to

program in a protected bl ock or in the s uspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not r ead and no error condit ion is given. Read-

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass comman ds during

an Erase Suspend. The Read/Reset command

must be issued to return the device to Read Array

mode before the Resume command will be ac-

cepted.

During Erase Suspend a Bus Read operation to

the Extended Block will output the Extended Block

data.

Erase Resume Command

The Erase Resume command must be used to re-

start the P rogram/Er ase Contr oller after a n Erase

Suspend. The device must be in Read Array mode

before the Resume command will be accepted. An

erase ca n be suspen ded and r esumed mor e than

once.

Enter Extended Block Command

The M29W32 0E has an extra 64K Byte block (E x-

tended Block) that can only be accessed using the

Enter Ex tended Bloc k com mand. Th ree B us wri te

cycles are required to issue the Extended Block

command. Once the command has been issued

17/46

M29W320ET, M29W320EB

the device enters Exte nded Bl oc k mod e wh ere al l

Bus Read or Program operations to the Boot Block

addresses access the Extended Block. The Ex-

tended Bloc k (with the same address as the b oot

block) cannot be erased, and can be treated as

one-time programmable (OTP) memory. In Ex-

tended Block mode the Boot Blocks are not acces-

sible.

To exit from the Extended Block mode the Exit Ex-

tended Block command must be issued.

The Extended Block can be protected, however

once protected the protection cannot be undone.

Exit Extended Block Command

The Exit Extended Block command is used to exit

from the Ex te nded Bl ock mode and retur n th e de -

vice to Read mode. Four Bus Write operations are

required to issue the command.

Block Protect and Chip Unprotect Commands

Groups of blocks can be protected against acci-

dental Program or Erase. The Protection Groups

are show n in APPENDIX A., T able 20. and Table

21., Block Ad dresses. The whol e chip can be un-

protected to allo w the d ata i ns id e the block s to be

changed.

Block Protect and Chip Unprotect operations are

described in APPENDIX D.

Table 4. Commands, 16-bit mode, BYTE = VIH

Note: X Don’t Care, PA Progr am Address, PD Program Data, BA Any address in th e Block. All values in the table are in hex adecimal .

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BY TE is VIL or DQ15 when BYTE is VIH.

Command

Length

Bus Write Operati ons

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3555 AA2AA 55 X F0

Auto Select 3 555 AA 2AA 55 (BA)

555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Double Word Pro gr am 3 555 50 PA0 PD0 PA 1 PD 1

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 55 5 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 BA B0

Erase Resume 1 BA 30

Read CFI Query 1 55 98

Enter Extended Block 3 555 AA 2AA 55 555 88

Exit Extended Block 4 555 AA 2AA 55 555 90 X 00

M29W320ET, M29W320EB

18/46

Table 5. Commands, 8-bit mode, BYTE = VIL

Note: X Don’t Care, PA Progr am Address, PD Program Data, BA Any address in th e Block. All values in the table are in hex adecimal .

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BY TE is VIL or DQ15 when BYTE is VIH.

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sam pl e d , but not 100% tested .

3. Maximum value measured at worst case co nditions for both tempera ture and VCC after 100,00 program/erase cycles .

4. Maximum value measured at worst case co nditions for both tempera ture and VCC.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Add Data Add Data Add Data Add Data Add Data Add Data

Read/Reset 1X F0

3AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 (BA)

AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Quadruple Byte Program 5 AAA 55 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 A AA 80 A AA A A 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 BA B0

Erase Resume 1 BA 30

Read CFI Query 1 AA 98

Enter Extended Block 3 AAA AA 555 55 AAA 88

Exit Extended Block 4 AAA AA 555 55 AAA 90 X 00

Parameter Min Typ (1, 2) Max(2) Unit

Chip Erase 40 200(3) s

Block Erase (64 KBytes) 0.8 6(3) s

Erase Suspend Latency Time 50(4) µs

Program (Byte or Word) 10 200(4) µs

Double Word Program (Byte or Word) 10 200(3) µs

Chip Program (Byte by Byte) 40 200(3) s

Chip Program (Word by Word) 20 100(3) s

Chip Program (Quadruple Byte or Double Word) 10 100(3) s

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

19/46

M29W320ET, M29W320EB

STATUS REGISTER

The M29W320E has one Status Register. It pro-

vides information on the current or previous Pro-

gram or Erase operations. The various bits convey

information and errors on the operation. Bus Read

operations from any address, always read the Sta-

tus Register during Program and Erase opera-

tions. It is also read during Erase Suspend when

an address within a block being erased is access-

ed.

The bits in the S t atu s R egi st er ar e s umm ariz ed in

Table 7., Status Register Bits.

Data Polling Bit (DQ7). T he Data Poll ing B it can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Afte r succe ssfu l com pleti on o f th e Era se op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Rea d operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 7., Data P olling Flowcha rt, give s an ex am-

ple of how to use the Dat a Polling Bit . A Valid Ad -

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend . The Toggle Bit is

output on DQ6 when the Status Register is read.

During Prog ram a nd Eras e oper ations the Togg le

Bit change s from ’0’ to ’1’ to ’ 0’, etc. , with suc ces-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 8., Toggle Flowchart, gives an example of

how to use the Data Toggle Bit. Figure 14. and

Figure 15. describe Toggle Bit timing waveform.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Res et comm and mus t be issu ed

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress w il l show the bit is s ti ll ‘0 ’. On e of the Er ase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

Erase Ti m er B it (D Q3). The Erase T imer B it can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is s et to ’0’ a nd additiona l block s to be eras ed

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase con troller d uring Erase o perations. T he Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the bl ocks being eras ed. A protected bl ock

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks be ing erased . Bus Read ope rations to ad -

dresses wi thi n b lock s not b eing e ra se d will out put

the memory cell data as if in Read mode.

After an E r ase o peration th at ca us es the Err or B it

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

Figure 14. and Figure 15. describe Alternative

Toggle Bit timing waveform.

M29W320ET, M29W320EB

20/46

Table 7. Status Register Bits

Note: Unspecified data bits should be ignored.

Figure 7. Data Polling Flowchart Figure 8. Toggle Flowchart

Note: BA = Address of Block being Programmed or Erased.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 – – 0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – Hi-Z

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle Hi-Z

Non-Erasing Block Data read as normal Hi-Z

Erase Error Good Block Address 0 Toggle 1 1 No Toggle Hi-Z

Faulty Blo ck Addr ess 0 Toggle 1 1 Tog gle H i-Z

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI90194

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

READ DQ6

ADDRESS = BA

START

READ DQ6

TWICE

ADDRESS = BA

FAIL PASS

AI08929b

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

ADDRESS = BA

21/46

M29W320ET, M29W320EB

MAXIMUM RATING

Stressing the dev ice above the ratin g lis ted in the

Absolute Maximum Ratin gs table ma y cause pe r-

manent damage to the device. Expos ur e to Ab so -

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operat ion of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Note: 1. Compliant with the ECOPACK® 7191395 specification for Lead-free soldering processes.

2. Not exceeding 250° C for more than 30s, and peaking at 260°C.

3. Minimum voltage may unders hoot to –2V du ring transition and for less than 20ns during transitions.

4. Maximum voltage may overshoot to VCC +2V during transition and for less t han 20ns during transitio ns.

5. VPP must not remain at 12V for more than a total of 80hrs.

Symbol Parameter Min Max Unit

TBIAS Temperature Under Bias –50 125 °C

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering(1) 260(2) °C

VIO Input or Output Voltage (3,4) –0.6 VCC +0.6 V

VCC Supply Voltage –0.6 4 V

VID Identification Voltage –0.6 13.5 V

VPP(5) Program Voltage –0.6 13.5 V

M29W320ET, M29W320EB

22/46

DC AND AC PARA METERS

This section summarizes the operating measure-

ment condi tions, an d the DC and AC characteri s-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 9., Operating and

AC Measurement Conditions. Designers should

check that the operating conditions in their circuit

match the operating conditions when relying on

the quoted parameters.

Table 9. Operating and AC Measurement Conditions

Figure 9. AC Measurement I/O Waveform Figure 10. AC Measurement Load Circuit

Table 10. Device Capacitance

Note: Sampled only, no t 100% tested.

Parameter

M29W320E

Unit70 90

Min Max Min Max

VCC Supply Voltage 2.7 3.6 2.7 3.6 V

Ambient Operating Temperature –40 85 –40 85 °C

Load Capacitance (CL)30 30 pF

Input Rise and Fall Times 10 10 ns

Input Pulse Voltages 0 to VCC 0 to VCC V

Input and Output Timing Ref. Voltages VCC/2 VCC/2 V

AI05557

VCC

VCC/2

AI05558

CL includes JIG capacitance

DEVICE

UNDER

TEST

25kΩ

VCC

25kΩ

VCC

0.1µF

VPP

0.1µF

Symb ol Parame te r Test Cond itio n Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

COUT Output Capacitance VOUT = 0V 12 pF

23/46

M29W320ET, M29W320EB

Table 11. DC Characteristics

Note: 1. Sampled only, not 100% test ed.

2. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1(2) Supply Current (Read) E = VIL, G = VIH,

f = 6MHz 10 mA

ICC2 Supply Current (Standby) E = VCC ±0.2V,

RP = VCC ±0.2V 100 µA

ICC3 (1,2) Supply Current (Program/

Erase) Program/Erase

Controller active

VPP/WP =

VIL or VIH 20 mA

VPP/WP = VPP 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC +0 .3 V

VPP Voltage for VPP/WP Program

Acceleration VCC = 2.7V ±10% 11.5 12.5 V

IPP Current for VPP/WP Program

Acceleration VCC = 2.7V ±10% 15 mA

VOL Output Low Voltage IOL = 1.8mA 0.45 V

VOH Output High Voltage IOH = –100µAVCC –0.4 V

VID Identification Voltage 11.5 12.5 V

VLKO Program/Erase Lockout Supply

Voltage 1.8 2.3 V

M29W320ET, M29W320EB

24/46

Figure 11. Read Mode AC Waveforms

Table 12. Read AC Characteristics

Note: 1. Sampled only, not 100% test ed.

Symbol Alt Parameter Test Condition M29W320E Unit

70 90

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min 70 90 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 70 90 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 ns

tGLQX (1) tOLZ Output Enable Low to Output

Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 ns

tEHQZ (1) tHZ Chip Enab le Hig h to Ou tpu t Hi-Z G = VIL Max 25 30 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 30 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or

Address Transition to Output Transition Min 0 0 ns

tELBL

tELBH tELFL

tELFH Chip Enab le to BY TE Low or High Max 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns

AI05559

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

25/46

M29W320ET, M29W320EB

Figure 12. Write AC Waveforms, Write Enable Controlled

Table 13. Write AC Characteristics, Write Enable Controlled

Note: 1. Sampled only, not 100% test ed.

Symbol Alt Parameter M29W320E Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 50 ns

tDVWH tDS Input V alid to Write Enable High Min 45 50 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 50 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

AI05560

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

M29W320ET, M29W320EB

26/46

Figure 13. Write AC Waveforms, Chip Enable Controlled

Table 14. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% test ed.

Symbol Alt Parameter M29W320E Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tWLEL tWS Write Enable Low to Ch ip En ab le Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 50 ns

tDVEH tDS Input V alid to Chip Enable High Min 45 50 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 50 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI05561

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

27/46

M29W320ET, M29W320EB

Figure 14. Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled

Note: 1. The Toggle bit is output on DQ6.

2. The Alternative Toggle bit is ou tput on DQ2.

Figure 15. Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled

Note: 1. The Toggle bit is output on DQ6.

2. The Alternative Toggle bit is ou tput on DQ2.

Table 15. Toggle and Alternative Toggle Bits AC Characteristics

Note: tELQV and tGLQV values are presented in Table 12., Read AC Characteristics.

Symbol Alt Parameter M29W320E Unit

70 90

tAXEL Addre ss Transition to Chip En ab le Low Min 10 10 ns

tAXGL Addre ss Transition to Outp ut En ab le Low Min 10 10 ns

AI09350

A0-A20

DQ2

(1)

/DQ6

(2)

tAXEL

tELQV

Data Data

Alternative Toggle/

Toggle Bit

tELQV

Alternative Toggle/

Toggle Bit

VALID ADDRESS VALID ADDRESSVALID ADDRESS

AI09351

A0-A20

DQ2

(1)

/DQ6

(2)

tAXGL

tGLQV

Data Data

Alternative Toggle/

Toggle Bit

tGLQV

Alternative Toggle/

Toggle Bit

VALID ADDRESS VALID ADDRESSVALID ADDRESS

M29W320ET, M29W320EB

28/46

Figure 16. Reset/Block Temporary Unprotect AC Waveforms

Table 16. Reset/Block Temporary Unprotect AC Characteristics

Note: 1. Sampled only, not 100% test ed.

Figure 17. Accelerated Program Timing Waveforms

Symbol Alt Parameter M29W320E Unit

70 90

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH tREADY RP Low to Read Mode Max 50 50 µs

tPHPHH (1) tVIDR RP Ris e Time to VID Min 500 500 ns

tVHVPP (1) VPP Rise and Fall Time Min 250 250 ns

AI02931B

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

AI05563

VPP/WP

VPP

VIL or VIH tVHVPP tVHVPP

29/46

M29W320ET, M29W320EB

PACKAGE MECHANICAL

Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline

Note: Drawing not to scale.

Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.080 0.0031

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α305305

TSOP-G

DIE

LA1 α

M29W320ET, M29W320EB

30/46

Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline

Note: Drawing not to scale.

Table 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.260 0.0102

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189

E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.000 – – 0.0394 – –

FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

E1E

BGA-Z32

ddd

FE SD

BALL "A1"

31/46

M29W320ET, M29W320EB

PART NUMBERING

Table 19. Ordering Information Scheme

Note: This product is also available with the Extended Block factory locked. For further details and ordering

information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

Example: M29W320EB 70 N 1 T

Device Type

M29

Operatin g Voltage

W = VCC = 2.7 to 3.6V

Device Function

320E = 32 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

ZE = TFBGA48: 6 x 8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

M29W320ET, M29W320EB

32/46

APPENDIX A. BLOCK ADDRESSES

Table 20. Top Boot Block Addresses, M29W320ET

Block (Kbytes/Kwords) Protection Block Group (x8) (x16)

0 64/32

Protection Group

000000h–00FFFFh 000000h–07FFFh

1 64/32 010000h–01FFFFh 008000h–0FFFFh

2 64/32 020000h–02FFFFh 010000h–17FFFh

3 64/32 030000h–03FFFFh 018000h–01FFFFh

4 64/32

Protection Group

040000h–04FFFFh 020000h–027FFFh

5 64/32 050000h–05FFFFh 028000h–02FFFFh

6 64/32 060000h–06FFFFh 030000h–037FFFh

7 64/32 070000h–07FFFFh 038000h–03FFFFh

8 64/32

Protection Group

080000h–08FFFFh 040000h–047FFFh

9 64/32 090000h–09FFFFh 048000h–04FFFFh

10 64/32 0A0000h–0AFFFFh 050000h–057FFFh

11 64/32 0B0000h–0BFFFFh 058000h–05FFFFh

12 64/32

Protection Group

0C0000h–0CFFFFh 060000h–067FFFh

13 64/32 0D0000h–0DFFFFh 068000h–06FFFFh

14 64/32 0E0000h–0EFFFFh 070000h–077FFFh

15 64/32 0F0000h–0FFFFFh 078000h–07FFFFh

16 64/32

Protection Group

100000h–10FFFFh 080000h–087FFFh

17 64/32 110000h–11FFFFh 088000h–08FFFFh

18 64/32 120000h–12FFFFh 090000h–097FFFh

19 64/32 130000h–13FFFFh 098000h–09FFFFh

20 64/32

Protection Group

140000h–14FFFFh 0A0000h–0A7FFFh

21 64/32 150000h–15FFFFh 0A8000h–0AFFFFh

22 64/32 160000h–16FFFFh 0B0000h–0B7FFFh

23 64/32 170000h–17FFFFh 0B8000h–0BFFFFh

24 64/32

Protection Group

180000h–18FFFFh 0C0000h–0C7FFFh

25 64/32 190000h–19FFFFh 0C8000h–0CFFFFh

26 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh

27 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh

28 64/32

Protection Group

1C0000h–1CFFFFh 0E0000h–0E7FFFh

29 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh

30 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh

31 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh

32 64/32

Protection Group

200000h–20FFFFh 100000h–107FFFh

33 64/32 210000h–21FFFFh 108000h–10FFFFh

34 64/32 220000h–22FFFFh 110000h–117FFFh

35 64/32 230000h–23FFFFh 118000h–11FFFFh

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M29W320ET, M29W320EB

Note: 1. Used as the Extended Block Addresses in Ext ended Block mode.

36 64/32

Protection Group

240000h–24FFFFh 120000h–127FFFh

37 64/32 250000h–25FFFFh 128000h–12FFFFh

38 64/32 260000h–26FFFFh 130000h–137FFFh

39 64/32 270000h–27FFFFh 138000h–13FFFFh

40 64/32

Protection Group

280000h–28FFFFh 140000h–147FFFh

41 64/32 290000h–29FFFFh 148000h–14FFFFh

42 64/32 2A0000h–2AFFFFh 150000h–157FFFh

43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

44 64/32

Protection Group

2C0000h–2CFFFFh 160000h–167FFFh

45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh

46 64/32 2E0000h–2EFFFFh 170000h–177FFFh

47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

48 64/32

Protection Group

300000h–30FFFFh 180000h–187FFFh

49 64/32 310000h–31FFFFh 188000h–18FFFFh

50 64/32 320000h–32FFFFh 190000h–197FFFh

51 64/32 330000h–33FFFFh 198000h–19FFFFh

52 64/32

Protection Group

340000h–34FFFFh 1A0000h–1A7FFFh

53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh

54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh

55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh

56 64/32

Protection Group

380000h–38FFFFh 1C0000h–1C7FFFh

57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh

58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh

59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh

60 64/32

Protection Group

3C0000h–3CFFFFh 1E0000h–1E7FFFh

61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh

63 8/4 Protection Group 3F0000h–3F1FFFh(1) 1F8000h–1F8FFFh(1)

64 8/4 Protection Group 3F2000h–3F3FFFh(1) 1F9000h–1F9FFFh(1)

65 8/4 Protection Group 3F4000h–3F5FFFh(1) 1FA000h–1FAFFFh(1)

66 8/4 Protection Group 3F6000h–3F7FFFh(1) 1FB000h–1FBFFFh(1)

67 8/4 Protection Group 3F8000h–3F9FFFh(1) 1FC000h–1FCFFFh(1)

68 8/4 Protection Group 3FA000h–3FBFFFh(1) 1FD000h–1FDFFFh(1)

69 8/4 Protection Group 3FC000h–3FDFFFh(1) 1FE000h–1FEFFFh(1)

70 8/4 Protection Group 3FE000h–3FFFFFh(1) 1FF000h–1FFFFFh(1)

Block (Kbytes/Kwords) Protection Block Group (x8) (x16)

M29W320ET, M29W320EB

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Table 21. Bottom Boot Block Addresses, M29W320EB

Block (Kbytes/Kwords) Protection Block Group (x8) (x16)

0 8/4 Protection Group 000000h-001FFFh(1) 000000h–000FFFh(1)

1 8/4 Protection Group 002000h-003FFFh(1) 001000h–001FFFh(1)

2 8/4 Protection Group 004000h-005FFFh(1) 002000h–002FFFh(1)

3 8/4 Protection Group 006000h-007FFFh(1) 003000h–003FFFh(1)

4 8/4 Protection Group 008000h-009FFFh(1) 004000h–004FFFh(1)

5 8/4 Protection Group 00A000h-00BFFFh(1) 005000h–005FFFh(1)

6 8/4 Protection Group 00C000h-00DFFFh(1) 006000h–006FFFh(1)

7 8/4 Protection Group 00E000h-00FFFFh(1) 007000h–007FFFh(1)

8 64/32

Protection Group

010000h-01FFFFh 008000h–00FFFFh

9 64/32 020000h-02FFFFh 010000h–017FFFh

10 64/32 030000h-03FFFFh 018000h–01FFFFh

11 64/32

Protection Group

040000h-04FFFFh 020000h–027FFFh

12 64/32 050000h-05FFFFh 028000h–02FFFFh

13 64/32 060000h-06FFFFh 030000h–037FFFh

14 64/32 070000h-07FFFFh 038000h–03FFFFh

15 64/32

Protection Group