ispLSI® 2192VE
3.3V In-System Programmable
SuperFAST™ High Density PLD
2192ve_10 1
Features
•SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
—8000 PLD Gates
— 96 I/O Pins, Nine or Twelve Dedicated Inputs
—192 Registers
—High Speed Global Interconnect
—Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
—Small Logic Block Size for Random Logic
— Pinout Compatible with ispLSI 2096V and 2096VE
•3.3V LOW VOLTAGE ARCHITECTURE
—Interfaces with Standard 5V TTL Devices
•HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 225MHz Maximum Operating Frequency
—tpd = 4.0ns Propagation Delay
—Electrically Erasable and Reprogrammable
— Non-Volatile
—100% Tested at Time of Manufacture
—Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
—Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
—Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
—Reprogram Soldered Devices for Faster Prototyping
•100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
•THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
—Enhanced Pin Locking Capability
—Three Dedicated Clock Input Pins
—Synchronous and Asynchronous Clocks
—Programmable Output Slew Rate Control
—Flexible Pin Placement
—Optimized Global Routing Pool Provides Global
Interconnectivity
•LEAD-FREE PACKAGE OPTIONS
Functional Block Diagram
Description
The ispLSI 2192VE is a High Density Programmable
Logic Device containing 192 Registers, nine or twelve
Dedicated Input pins, three Dedicated Clock Input pins,
two dedicated Global OE input pins and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2192VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2192VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2192VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 2192VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool
Output Routing Pool
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
CLK0
CLK1
CLK2
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool
Logic
Array
DQ
DQ
DQ
DQ
Global Routing Pool (GRP) GLB
0139/2192VE
Lead-
Free
Package
Options
Available!
Specifications ispLSI 2192VE
2
Functional Block Diagram
Figure 1. ispLSI 2192VE Functional Block Diagram
The 2192VE contains 96 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control. The signal
levels are TTL compatible voltages and the output drivers
can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5V signal levels to support
mixed-voltage systems.
Eight GLBs, 16 I/O cells, two dedicated inputs and an
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
2192VE device contains six Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2192VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock
can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2192VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
Output Routing Pool (ORP)
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool (ORP)
F7 F6 F5 F4 F3 F2 F1 F0
Input Bus
Output Routing Pool (ORP)
E7 E6 E5 E4 E3 E2 E1 E0
Input Bus
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Input Bus
Global
Routing
Pool
(GRP)
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool (ORP)
I/O
94
I/O
95 I/O
93 I/O
92 I/O
91 I/O
90 I/O
89I/O
88 I/O
87 I/O
86 I/O
85 I/O
84 I/O
83 I/O
82 I/O
81 I/O
80 IN
11* I/O
78
I/O
79 I/O
77 I/O
76 I/O
75 I/O
74 I/O
73I/O
72 I/O
71 I/O
70 I/O
69 I/O
68 I/O
67 I/O
66 I/O
65 I/O
64 IN
9
IN
10
I/O
17
I/O
16 I/O
18 I/O
19 I/O
20 I/O
21 I/O
22 I/O
23 I/O
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31
IN 3 I/O
33
I/O
32 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
44 I/O
45 I/O
46 Y0 Y1 Y2
I/O
47
IN 5*IN4
IN 7/TCK
IN 6/TDO
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
I/O 4
I/O 5
BSCAN
RESET
Input Bus Input Bus
lnput Bus
2192VE Block.eps
IN
8
GOE 0
GOE 1
IN 2*
*Note: Dedicated Inputs 2, 5 and 11 are not available with 128-pin packages.
CLK 0
CLK 1
CLK 2
Specifications ispLSI 2192VE
3
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
Erase Reprogram Specifications
Capacitance (TA=25°C, f=1.0 MHz)
CSYMBOL
Table 2-0006/2192VE
C
PARAMETER
I/O Capacitance 8
UNITSTYPICAL TEST CONDITIONS
1
2
8Dedicated Input Capacitance pf
pf V = 3.3V, V = 0.0V
V = 3.3V, V = 0.0V
CC
CC I/O
IN
CClock and Global Output Enable Capacitance 12
3
pf V = 3.3V, V = 0.0V
CC Y
Table 2-0008/2192VE
PARAMETER MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 10,000 — Cycles
T
A
= 0°C to + 70°C
SYMBOL
Table 2-0005/2192VE
VCC
VIH
VIL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
3.0
2.0
V – 0.5 3.6
5.25
0.8 V
V
V
SS
Commercial
Specifications ispLSI 2192VE
4
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
Table 2-0003/2192VE
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
≤ 1.5ns 10% to 90%
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from steady-state active level.
DC Electrical Characteristics
Over Recommended Operating Conditions
Output Load Conditions (see Figure 2)
TEST CONDITION R1 R2 CL
A 316Ω348Ω35pF
B
∞
348Ω35pF
316Ω348Ω35pF
Active High
Active Low
C316Ω348Ω5pF
∞
348Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004/2192VE
VOL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at V = 3.3V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .
Table 2-0007/2192VE
1
VOH
IIH
IIL
IIL-isp
PARAMETER
IIL-PU
IOS
2, 4
ICC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
BSCAN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 3.3V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN
IL
IN IL
CC OUT
CLOCK
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
275
0.4
–
10
10
-10
-150
-150
-100
–
V
V
µA
µA
µA
µA
µA
mA
mA
CC A
OUT
CC
CC
(V - 0.2)V ≤ V ≤ V
V ≤ V ≤ 5.25V
CC CC IN
IN
CC
+ 3.3V
R1
R2CL*
Device
Output Test
Point
*CL includes Test Fixture and Probe Capacitance.
0213A/2192VE
Specifications ispLSI 2192VE
5
External Timing Parameters
Over Recommended Operating Conditions
USE 2192VE-225 FOR
NEW DESIGNS
t
pd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2192VE
1
3
2
1
tsu2 + tco1
( )
DESCRIPTION#PARAMETER
A1Data Propagation Delay, 4PT Bypass, ORP Bypass ns
t
pd2 A2Data Propagation Delay ns
f
max A3Clock Frequency with Internal Feedback MHz
f
max (Ext.) –4Clock Frequency with External Feedback MHz
f
max (Tog.) –5Clock Frequency, Max. Toggle MHz
t
su1 –6GLB Reg. Setup Time before Clock, 4 PT Bypass ns
t
co1 A7GLB Reg. Clock to Output Delay, ORP Bypass ns
t
h1 –8GLB Reg. Hold Time after Clock, 4 PT Bypass ns
t
su2 –9GLB Reg. Setup Time before Clock ns
t
co2 A10GLB Reg. Clock to Output Delay ns
t
h2 –11GLB Reg. Hold Time after Clock ns
t
r1 A12Ext. Reset Pin to Output Delay, ORP Bypass ns
t
rw1 –13Ext. Reset Pulse Duration ns
t
ptoeen B14Input to Output Enable ns
t
ptoedis C15Input to Output Disable ns
t
goeen B16Global OE Output Enable ns
t
goedis C17Global OE Output Disable ns
t
wh –18External Synchronous Clock Pulse Duration, High ns
t
wl –19External Synchronous Clock Pulse Duration, Low ns
-180
MIN. MAX.
– 5.0
–
180 –
–
–
–
–
0.0
4.5
–
0.0
–
4.0
–
–
–
–
2.5 –
2.5 –
125
200
3.5 3.5
–
–
4.5
–
7.0
–
10.0
10.0
5.0
5.0
7.5
-225
MIN. MAX.
– 4.0
–
225 –
–
–
–
–
0.0
3.5
–
0.0
–
3.5
–
–
–
–
2.0 –
2.0 –
150
250
2.5 3.2
–
–
3.7
–
6.0
–
6.0
6.0
4.5
4.5
6.2
Specifications ispLSI 2192VE
6
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-135
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2192VE
1
3
2
1
tsu2 + tco1
( )
-100
MIN.MAX. MAX.
DESCRIPTION#PARAMETER
A1Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns
t
pd2 A2Data Propagation Delay – – ns
f
max A3Clock Frequency with Internal Feedback 135 – 100 – MHz
f
max (Ext.) –4Clock Frequency with External Feedback – – MHz
f
max (Tog.) –5Clock Frequency, Max. Toggle – – MHz
t
su1 –6GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
t
co1 A7GLB Reg. Clock to Output Delay, ORP Bypass – – ns
t
h1 –8GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
t
su2 –9GLB Reg. Setup Time before Clock 6.0 – ns
t
co2 A10GLB Reg. Clock to Output Delay – – ns
t
h2 –11GLB Reg. Hold Time after Clock 0.0 – ns
t
r1 A12Ext. Reset Pin to Output Delay, ORP Bypass – – ns
t
rw1 –13Ext. Reset Pulse Duration 5.0 – ns
t
ptoeen B14Input to Output Enable – – ns
t
ptoedis C15Input to Output Disable – – ns
t
goeen B16Global OE Output Enable – – ns
t
goedis C17Global OE Output Disable – – ns
t
wh –18External Synchronous Clock Pulse Duration, High 3.5 – – ns
t
wl –19External Synchronous Clock Pulse Duration, Low 3.5 – – ns
100
143
5.0 4.0
–
–
5.0
–
9.0
–
12.0
12.0
7.0
7.0
10.0
77
100
6.5
0.0
8.0
0.0
6.5
5.0
5.0
13.0
5.0
6.0
12.5
15.0
15.0
9.0
9.0
Specifications ispLSI 2192VE
7
USE 2192VE-225 FOR NEW DESIGNS
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036E/2192VE v0.1
Inputs
UNITS
-225
MIN. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay ns
t
din 21 Dedicated Input Delay ns
t
grp 22 GRP Delay ns
GLB
t
1ptxor 25 1 Product Term/XOR Path Delay ns
t
20ptxor 26 20 Product Term/XOR Path Delay ns
t
xoradj 27 XOR Adjacent Path Delay ns
t
gbp 28 GLB Register Bypass Delay ns
t
gsu 29 GLB Register Setup Time before Clock ns
t
gh 30 GLB Register Hold Time after Clock ns
t
gco 31 GLB Register Clock to Output Delay ns
3
t
gro 32 GLB Register Reset to Output Delay ns
t
ptre 33 GLB Product Term Reset to Register Delay ns
t
ptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns
t
ptck 35 GLB Product Term Clock Delay ns
ORP
t
ob 38 Output Buffer Delay ns
t
sl 39 Output Slew Limited Delay Adder ns
GRP
t
4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns
t
4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns
t
orp 36 ORP Delay ns
t
orpbp 37 ORP Bypass Delay ns
Outputs
t
oen 40 I/O Cell OE to Output Enabled ns
t
odis 41 I/O Cell OE to Output Disabled ns
t
goe 42 Global Output Enable ns
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
Clocks
t
gr 45 Global Reset to GLB
0.3
0.5
0.2
3.2
3.2
3.2
0.0
–
–
0.3
0.3
4.0
2.9
3.2
1.6
2.0
1.5
2.2
0.9
0.4
2.6
2.6
1.9
0.9
1.1
3.7
–
–
–
–
–
–
–
0.7
1.8
–
–
–
–
0.8
–
–
–
–
–
–
–
–
–
0.9
1.1
–ns
Global Reset
-180
MIN. MAX.
0.5
1.1
0.6
3.4
3.4
3.4
0.0
–
–
0.3
0.6
4.3
5.9
4.0
1.6
2.0
1.9
2.4
1.4
0.4
3.0
3.0
2.0
1.2
1.4
4.4
–
–
–
–
–
–
–
1.2
2.3
–
–
–
–
1.0
–
–
–
–
–
–
–
–
–
1.2
1.4
–
Specifications ispLSI 2192VE
8
Internal Timing Parameters1
Over Recommended Operating Conditions
tio
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036D/2192VE v0.1
Inputs
UNITS
-135
MIN.
-100
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay – ns
tdin 21 Dedicated Input Delay – ns
tgrp 22 GRP Delay –ns
GLB
t1ptxor 25 1 Product Term/XOR Path Delay – ns
t20ptxor 26 20 Product Term/XOR Path Delay – ns
txoradj 27 XOR Adjacent Path Delay – ns
tgbp 28 GLB Register Bypass Delay – ns
tgsu 29 GLB Register Setup Time before Clock 1.7 ns
tgh 30 GLB Register Hold Time after Clock 4.8 ns
tgco 31 GLB Register Clock to Output Delay – ns
3
tgro 32 GLB Register Reset to Output Delay – ns
tptre 33 GLB Product Term Reset to Register Delay – ns
tptoe 34 GLB Product Term Output Enable to I/O Cell Delay – ns
tptck 35 GLB Product Term Clock Delay 2.6 ns
ORP
tob 38 Output Buffer Delay – ns
tsl 39 Output Slew Limited Delay Adder – ns
GRP
t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) – ns
t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) – ns
torp 36 ORP Delay –ns
torpbp 37 ORP Bypass Delay – ns
Outputs
toen 40 I/O Cell OE to Output Enabled – ns
todis 41 I/O Cell OE to Output Disabled – ns
tgoe 42 Global Output Enable – ns
tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.4 ns
tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.6 ns
Clocks
tgr 45 Global Reset to GLB –
0.7
2.5
1.8
6.2
6.2
6.2
1.0
–
–
0.3
3.1
7.1
9.1
5.6
1.6
2.0
5.2
4.7
1.7
0.7
3.4
3.4
5.6
2.4
2.6
7.1
0.5
1.7
1.2
4.7
4.7
4.7
0.5
–
–
0.3
1.1
6.1
6.9
4.6
1.6
2.0
3.7
3.7
1.5
0.5
3.4
3.4
3.6
1.6
1.8
5.8
–
–
–
–
–
–
–
1.2
3.8
–
–
–
–
1.6
–
–
–
–
–
–
–
–
–
1.6
1.8
–ns
Global Reset
Specifications ispLSI 2192VE
9
ispLSI 2192VE Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29, 30,
31, 32
#38,
39
GOE 0 #42
#40, 41
0491/2192VE
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of tsu, th and tco from the Product Term Clock
=
=
=
=
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.3 + 0.2 + 3.2) + (0.7) - (0.3 + 0.2 + 0.8)
=
=
=
=
t
hClock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.3 + 0.2 + 3.2) + (1.8) - (0.3 + 0.2 + 3.2)
=
=
=
=
t
co
Note: Calculations are based upon timing specifications for the ispLSI 2192VE-225L.
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.3 + 0.2 + 3.2) + (0.3) + (0.9 + 1.6)
Table 2-0042A/2192VE v0.1
3.1ns
1.8ns
6.5ns
Specifications ispLSI 2192VE
10
Power Consumption
Power consumption in the ispLSI 2192VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 3 shows the relationship between power
and operating speed.
Figure 3. Typical Device Power Consumption vs fmax
0127/2192VE
ICC can be estimated for the ispLSI 2192VE using the following equation:
ICC = 25 + (# of PTs * 0.670) + (# of nets * max freq * 0.0051)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption
of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is
sensitive to operating conditions and the program in the device, the actual ICC should be verified.
300
250
400
04080120 160 200
f
max (MHz)
I
CC (mA)
Notes: Configuration of twelve 16-bit counters
Typical current at 3.3V, 25° C
450 ispLSI 2192VE
500
350
240
Specifications ispLSI 2192VE
11
RESET 15 G4
GOE 0, GOE 1 80, 17 F12, G2
Y0, Y1, Y2 14, 83, 78 F3, F10, G11
BSCAN 19 F1
TDI/IN 0 20 G3
TMS/IN 1 48 J6
TDO/IN 6 112 C7
TCK/IN 7 77 G12
IN 2-5, IN 8-11 —, 49, 82, —, 84, 113, 13, — M7, J7, F9, G10, E12, B6,
F2, E1
GND 18, 34, 50, 63, 79, 98, 111, A1, A12, D4, D9, E5, E8, F6,
127 F7, G6, G7, H5, H8, J4, J9,
M1, M12
VCC 2, 16, 31, 47, 66, 81, 95, 114 B1, B12, E6, E7, F5, F8, G5,
G8, H6, H7, L1, L12
NC1—K2
Signal Descriptions
RESET Active Low (0) Reset pin resets all the registers in the device.
GOE 0, GOE1 Global Output Enable input pins.
Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
BSCAN Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0 Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin
to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin.
TCK/IN 7 Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.
TMS/IN 1 Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for
the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.
TDO/IN 6 Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin
to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin.
IN 2-5, IN 8-11 Dedicated Input Pins to the device.
GND Ground (GND)
VCC Vcc
NC1No Connect
I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array.
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
Signal Name 128-Pin TQFP 144-Ball fpBGA
1. NC pins are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 2192VE
12
I/O Locations
I/O 0 21 H4
I/O 1 22 G1
I/O 2 23 H2
I/O 3 24 H1
I/O 4 25 H3
I/O 5 26 J1
I/O 6 27 J3
I/O 7 28 K1
I/O 8 29 J2
I/O 9 30 M2
I/O 10 32 L2
I/O 11 33 L3
I/O 12 35 K3
I/O 13 36 M3
I/O 14 37 L4
I/O 15 38 K4
I/O 16 39 M4
I/O 17 40 J5
I/O 18 41 M5
I/O 19 42 K5
I/O 20 43 L5
I/O 21 44 M6
I/O 22 45 L6
I/O 23 46 K6
I/O 24 51 L7
I/O 25 52 K7
I/O 26 53 J8
I/O 27 54 M8
I/O 28 55 L8
I/O 29 56 K8
I/O 30 57 M9
I/O 31 58 L9
I/O 32 59 K9
I/O 33 60 M10
I/O 34 61 L10
I/O 35 62 M11
I/O 36 64 K10
I/O 37 65 K11
I/O 38 67 L11
I/O 39 68 K12
I/O 40 69 J11
I/O 41 70 J12
I/O 42 71 J10
I/O 43 72 H9
I/O 44 73 H11
I/O 45 74 H12
I/O 46 75 H10
I/O 47 76 G9
128 144
Signal TQFP fpBGA
I/O 48 85 F11
I/O 49 86 D12
I/O 50 87 E9
I/O 51 88 E10
I/O 52 89 E11
I/O 53 90 C12
I/O 54 91 D10
I/O 55 92 D11
I/O 56 93 B11
I/O 57 94 C11
I/O 58 96 C10
I/O 59 97 A11
I/O 60 99 B10
I/O 61 100 A10
I/O 62 101 C9
I/O 63 102 B9
I/O 64 103 A9
I/O 65 104 D8
I/O 66 105 B8
I/O 67 106 C8
I/O 68 107 A8
I/O 69 108 B7
I/O 70 109 A7
I/O 71 110 D7
I/O 72 115 C6
I/O 73 116 A6
I/O 74 117 D6
I/O 75 118 B5
I/O 76 119 C5
I/O 77 120 A5
I/O 78 121 D5
I/O 79 122 C4
I/O 80 123 B4
I/O 81 124 A4
I/O 82 125 C3
I/O 83 126 B3
I/O 84 128 A3
I/O 85 1 C2
I/O 86 3 B2
I/O 87 4 D2
I/O 88 5 A2
I/O 89 6 D3
I/O 90 7 E2
I/O 91 8 C1
I/O 92 9 E3
I/O 93 10 E4
I/O 94 11 D1
I/O 95 12 F4
128 144
Signal TQFP fpBGA
Specifications ispLSI 2192VE
13
Pin Configuration
ispLSI 2192VE 128-Pin TQFP Pinout Diagram
VCC
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN10
Y0
RESET
VCC
GOE 1
GND
BSCAN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
VCC
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 8
Y1
IN4
VCC
GOE 0
Y2
TCK/IN 7
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
VCC
I/O 84
GND
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 9
GND
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
I/O 59
I/O 10
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
TMS/IN 1
IN3
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GND
ispLSI 2192VE
Top View
VCC
TDI/IN 0
I/O 58
TDO/IN 6
GND
I/O 37
I/O 11
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
64
96
122
I/O 36
VCC
0124-2192VE
Specifications ispLSI 2192VE
14
Signal Configuration
ispLSI 2192VE 144-Ball fpBGA Signal Diagram
101112 987654321
101112 987654321
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
I/O
59 I/O
61 I/O
64 I/O
68 I/O
70 I/O
73 I/O
77 I/O
81 I/O
84 I/O
88
GND
GND GND
GND
I/O
35 I/O
33 I/O
30 I/O
27 I/O
21 I/O
18 I/O
16 I/O
13 I/O
9
GND IN 2 GND
I/O
56 I/O
60 I/O
63 I/O
66 I/O
69 I/O
75 I/O
80 I/O
83 I/O
86
I/O
57
I/O
53 I/O
58 I/O
62 I/O
67 TDO/
IN 6 I/O
72 I/O
76 I/O
79 I/O
82 I/O
85 I/O
91
I/O
55
I/O
49 I/O
54 I/O
65 I/O
71 I/O
74 I/O
78 I/O
89 I/O
87 I/O
94
GNDIN 8 GND
Y0
VCC VCC
I/O
52 I/O
51 I/O
50 I/O
92
I/O
93 I/O
90
VCCY1 IN 4
IN 11
BSCAN
IN 10VCCGND GND
I/O
48
GOE
0I/O
95
VCCIN 5Y2
RESET
GOE 1VCCGND GND
I/O
47 I/O
1
TDI/
IN 0
TCK/
IN 7
GND GNDVCC VCC
I/O
43 I/O
3
I/O
2
I/O
4
I/O
0
I/O
45 I/O
44 I/O
46
GND GNDIN 3 I/O
5
I/O
8
I/O
6
TMS/
IN 1 I/O
17
I/O
41 I/O
40 I/O
42 I/O
26
I/O
7
I/O
12
I/O
23 I/O
19 I/O
15
I/O
39 I/O
37 I/O
36 I/O
32 I/O
29 I/O
25
VCC IN 9 VCC
I/O
38 I/O
34 I/O
31 I/O
28 I/O
24 I/O
22 I/O
20 I/O
14 I/O
11 I/O
10
VCC VCC
NC
1
1
NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
144-BGA/2192VE
ispLSI 2192VE
Bottom View
Specifications ispLSI 2192VE
15
Part Number Description
ispLSI 2192VE Ordering Information
COMMERCIAL
Table 2-0041D/2192VE
135 7.5 128-Pin TQFPispLSI 2192VE-135LT128
135 7.5 144-Ball fpBGAispLSI 2192VE-135LB144
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI
100 128-Pin TQFP10 ispLSI 2192VE-100LT128
100 144-Ball fpBGA10 ispLSI 2192VE-100LB144
180 128-Pin TQFP5.0 ispLSI 2192VE-180LT128*
225 144-Ball fpBGA4.0 ispLSI 2192VE-225LB144
225 128-Pin TQFP4.0 ispLSI 2192VE-225LT128
180 144-Ball fpBGA5.0 ispLSI 2192VE-180LB144*
*ispLSI 2192VE-225 recommended for new designs.
Table 2-0041A/2192VE
180 5.0 128-Pin TQFPispLSI 2192VE-180LT128I
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI
INDUSTRIAL
Device Number
ispLSI 2192VE XXX X XXXXX
Grade
Blank = Commercial
X
Speed
225 = 225 MHz fmax
180 = 180 MHz fmax*
135 = 135 MHz fmax
100 = 100 MHz fmax Power
L = Low
Package
-
Device Family
0212B/2192VE
T128 = 128-Pin TQFP
TN128 = Lead-Free 128-Pin TQFP
B144 = 144-Ball fpBGA
*ispLSI 2192VE-225 recommended for new designs.
I = Industrial
Conventional Packaging
Lead-Free Packaging
INDUSTRIAL
180 7.5 Lead-Free 128-Pin TQFPispLSI 2192VE-180LTN128I
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI
COMMERCIAL
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI 100 Lead-Free 128-Pin TQFP10 ispLSI 2192VE-100LTN128
135 Lead-Free 128-Pin TQFP7.5 ispLSI 2192VE-135LTN128
225 Lead-Free 128-Pin TQFP4.0 ispLSI 2192VE-225LTN128
