IS62WV5128EALL/EBLL/ECLL
IS65WV5128EBLL/ECLL
Integrated Silicon Solution, Inc.- www.issi.com 1
Rev. A4
04/18/2017
512Kx8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES
High-speed access time: 35ns, 45ns, 55ns
CMOS low power operation
– Operating Current: 22 mA (max) at 85°C
– CMOS Standby Current: 3.7uA (typ) at 25°C
TTL compatible interface levels
Single power supply
–1.65V-2.2V VDD (IS62/65WV5128EALL)
– 2.2V-3.6V VDD (IS62/65WV5128EBLL)
– 3.3V +/-5% VDD (IS62/65WV5128ECLL)
Three state outputs
Industrial and Automotive temperature support
Lead-free available
DESCRIPTION
The ISSI IS62/65WV5128EALL/BLL/CLL are high-
speed, 4M bit static RAMs organized as 512K words by
8 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS# is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs. The active LOW Write
Enable (WE#) controls both writing and reading of the
memory.
The IS62/65WV5128EALL/EBLL are packaged in the
JEDEC standard 32-pin TSOP (TYPE I/II), sTSOP
(TYPE I), SOP and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/O
CS#
WE#
OE#CONTROL
CIRCUIT
I/O
DATA
CIRCUIT
512K x 8
MEMORY
ARRAY
DECODER
VDD
GND
A0 – A18
I/O0 – I/O7
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
APRIL 2017
IS62WV5128EALL/EBLL/ECLL
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Rev. A4
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PIN CONFIGURATIONS
36-Pin mini BGA (6mm x 8mm)
A0 NCA1 A3 A6 A8
I/O4 WE#A2 A4 A7 I/O0
I/O5 NC A5 I/O1
GND VDD
VDD GND
I/O6 A18 A17 I/O2
I/O7 CS#OE# A16 A15 I/O3
A9 A11A10 A12 A13 A14
1 2 3 4 5 6
A
B
C
D
E
F
G
H
32-Pin TSOP (Type I)
32-Pin STSOP (Type I)
A11
A9
A8
A13
WE#
A18
A15
VDD
A17
A16
A14
A12
A7
A6
A5
A4
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O0
I/O1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
12
11
13
14
14
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
PIN DESCRIPTIONS
A0-A18
Address Inputs
I/O0-I/O7
Data Inputs/Outputs
CS#
Chip Enable Input
OE#
Output Enable Input
WE#
Write Enable Input
NC
No Connection
VDD
Power
GND
Ground
32-Pin SOP
32-Pin TSOP (Type II)
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VDD
A15
A18
WE#
A13
A8
A9
A11
OE#
A10
I/O7
CS#
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
12
11
13
14
14
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
IS62WV5128EALL/EBLL/ECLL
IS65WV5128EBLL/ECLL
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Rev. A4
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FUNCTION DESCRIPTION
SRAM is one of random access memories. SRAM has three different modes supported. Each function is described
below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-7) are placed in a high
impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input LOW. The input and output pins
(I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW.
READ MODE
Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output
buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
CS#
WE#
OE#
I/O0-I/O7
VDD Current
Not Selected
H
X
X
High-Z
ISB2
Output Disabled
L
H
H
High-Z
ICC,ICC1
Write
L
L
X
DIN
ICC,ICC1
Read
L
H
L
DOUT
ICC,ICC1
IS62WV5128EALL/EBLL/ECLL
IS65WV5128EBLL/ECLL
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Rev. A4
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ABSOLUTE MAXIMUM RATINGS
AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
Vterm
Terminal Voltage with Respect to GND
–0.5 to VDD + 0.5
V
VDD
VDD Related to GND
–0.3 to 4.0
V
tStg
Storage Temperature
–65 to +150
C
PT
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE(1)
Range
Ambient Temperature
Part Number
SPEED (max)
VDD(min)
VDD(typ)
VDD(max)
Commercial
0C to +70C
~EALL
55 ns
1.65V
1.8V
2.2V
Industrial
-40C to +85C
55 ns
1.65V
1.8V
2.2V
Automotive
-40C to +125C
55 ns
1.65V
1.8V
2.2V
Commercial
0C to +70C
~EBLL
45ns
2.2V
3.0V
3.6V
Industrial
-40C to +85C
45ns
2.2V
3.0V
3.6V
Automotive
-40C to +125C
55ns
2.2V
3.0V
3.6V
Commercial
0C to +70C
~ECLL
35ns
3.135V
3.3V
3.465V
Industrial
-40C to +85C
35ns
3.135V
3.3V
3.465V
Automotive
-40C to +125C
45ns
3.135V
3.3V
3.465V
Note:
1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE (1)
Parameter
Symbol
Test Condition
Max
Units
Input capacitance
CIN
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
6
pF
DQ capacitance (IO0–IO7)
CI/O
8
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Symbol
Rating
Units
Thermal resistance from junction to ambient (airflow = 1m/s)
RθJA
TBD
°C/W
Thermal resistance from junction to pins
RθJB
TBD
°C/W
Thermal resistance from junction to case
RθJC
TBD
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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Rev. A4
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
(1.65V~2.2V)
Unit
(2.2V~3.6V)
Unit
(3.3V +/-5%)
Input Pulse Level
0V to VDD
0V to VDD
0V to VDD
Input Rise and Fall Time
1V/ns
1V/ns
1V/ns
Output Timing Reference Level
0.9V
½ VDD
½ VDD + 0.05V
R1
13500
1005
1213
R2
10800
820
1378
VTM
1.8V
VDD
VDD
Output Load Conditions
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
R1
R2
VTM
OUTPUT 30pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
FIGURE 1 FIGURE 2
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Rev. A4
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DC ELECTRICAL CHARACTERISTICS
IS62(5)WV5128EALL
DC ELECTRICAL CHARACTERISTICS- I
(OVER THE OPERATING RANGE)
VDD = 1.65V ~ 2.2V
Symbol
Parameter
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
VIH
(1)
Input HIGH Voltage
1.4
VDD + 0.2
V
VIL
(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV5128EBLL
DC ELECTRICAL CHARACTERISTICS
- I (OVER THE OPERATING RANGE)
VDD = 2.2V ~ 3.6V
Symbol
Parameter
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.0
—
V
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.4
—
V
VOL
Output LOW Voltage
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
—
0.4
V
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
—
0.4
V
VIH
(1)
Input HIGH Voltage
2.2 ≤ VDD < 2.7
1.8
VDD + 0.3
V
2.7 ≤ VDD ≤ 3.6
2.0
VDD + 0.3
V
VIL
(1)
Input LOW Voltage
2.2 ≤ VDD < 2.7
–0.3
0.6
V
2.7 ≤ VDD ≤ 3.6
–0.3
0.8
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV5128ECLL
DC ELECTRICAL CHARACTERISTICS - I
(OVER THE OPERATING RANGE)
VDD = 3.3V +/-5%
Symbol
Parameter
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = -1.0 mA
2.4
—
V
VOL
Output LOW Voltage
IOL = 2.1 mA
—
0.4
V
VIH
(1)
Input HIGH Voltage
2.0
VDD + 0.3
V
VIL
(1)
Input LOW Voltage
–0.3
0.8
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
2. VDD=3.3V +/-5% is for high speed of 35ns device (ECLL).
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Rev. A4
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IS62(5)WV5128EALL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
55ns
Unit
Typ(1)
Max
ICC
VDD Dynamic
Operating
Supply Current
VDD = VDD(max), IOUT = 0mA,
f = fmax, CS# = VIL
Com.
-
20
mA
Ind.
-
22
Auto. A3
-
22
ICC1
VDD Static
Operating
Supply Current
VDD = VDD(max), IOUT = 0mA,
f = 0, CS# = VIL
Com.
-
5
mA
Ind.
-
5
Auto. A3
-
5
ISB2
CMOS Standby
Current (CMOS
Inputs)
VDD = VDD(max), f = 0,
CS# ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
25°C
3.7
6
µA
40°C
3.8
7
70°C
3.9
9
Ind.
85°C
4.1
10
Auto. A3
125°C
8.1
25
Note:
1. Typical values are measured at VDD = 1.8V, TA = 25C , and not 100% tested.
IS62(5)WV5128EBLL/ECLL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
35ns(1)
45/55ns
Unit
Typ(2)
Max
Typ(2)
Max
ICC
VDD Dynamic
Operating
Supply Current
VDD = VDD(max), IOUT = 0mA,
f = fmax, CS# = VIL
Com.
-
22
-
20
mA
Ind.
-
25
-
22
Auto. A3
-
-
-
22
ICC1
VDD Static
Operating
Supply Current
VDD = VDD(max), IOUT = 0mA,
f = 0, CS# = VIL
Com.
-
5
-
5
mA
Ind.
-
5
-
5
Auto. A3
-
-
-
5
ISB2
CMOS Standby
Current (CMOS
Inputs)
VDD = VDD(max), f = 0,
CS# ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD -
0.2V
Com.
25°C
3.7
6
3.7
6
µA
40°C
3.8
7
3.8
7
70°C
3.9
9
3.9
9
Ind.
85°C
4.1
10
4.1
10
Auto. A3
125°C
8.1
25
8.1
25
Notes:
1. 35 ns speed bin is for ECLL (VDD=3.3V +/-5%) only.
2. Typical values are measured at VDD = 3.0V, and not 100% tested.
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Rev. A4
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AC CHARACTERISTICS
(6)
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
35ns(7)
45ns
55ns
unit
notes
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
35
-
45
-
55
-
ns
1,5
Address Access Time
tAA
-
35
-
45
-
55
ns
1
Output Hold Time
tOHA
8
-
10
-
10
-
ns
1
CS# Access Time
tACS
-
35
-
45
-
55
ns
1
OE# Access Time
tDOE
-
18
-
20
-
25
ns
1
OE# to High-Z Output
tHZOE
-
12
-
15
-
20
ns
2
OE# to Low-Z Output
tLZOE
4
-
5
-
5
-
ns
2
CS# to High-Z Output
tHZCS
-
12
-
15
-
20
ns
2
CS# to Low-Z Output
tLZCS
10
-
10
-
10
-
ns
2
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
35ns(7)
45ns
55ns
unit
notes
Min
Max
Min
Max
Min
Min
Write Cycle Time
tWC
35
-
45
-
55
-
ns
1,3,5
CS# to Write End
tSCS
30
-
35
-
40
-
ns
1,3
Address Setup Time to Write End
tAW
30
-
35
-
40
-
ns
1,3
Address Hold from Write End
tHA
0
-
0
-
0
-
ns
1,3
Address Setup Time
tSA
0
-
0
-
0
-
ns
1,3
WE# Pulse Width
tPWE
30
-
35
-
40
-
ns
1,3,4
Data Setup to Write End
tSD
18
-
20
-
25
-
ns
1,3
Data Hold from Write End
tHD
0
-
0
-
0
-
ns
1,3
WE# LOW to High-Z Output
tHZWE
-
12
-
15
-
20
ns
2,3
WE# HIGH to Low-Z Output
tLZWE
4
-
5
-
5
-
ns
2,3
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of CS# = LOW, and WE# = LOW. All four conditions must be in valid states to initiate a Write,
but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the
signal that terminates the write.
4. tPWE > tHZWE + tSD when OE# is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
7. 35 ns speed bin is at VDD=3.3V +/-5% .
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TIMING DIAGRAM
READ CYCLE NO. 1(1) (ADDRESS CONTROLLED, CS# = OE# = LOW, WE# = HIGH)
tRC
Address
DOUT
tOHA tOHA
tAA
PREVIOUS DATA VALID DATA VALIDLOW-Z
Note:
1. The device is continuously selected.
READ CYCLE NO. 2(1) (OE# CONTROLLED)
OE#
CS#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tLZOE
tACS
tLZCS
tHZOE
tHZCS
HIGH-Z DATA VALIDLOW-Z HIGH-Z
Note:
1. Address is valid prior to or coincident with CS# LOW transition.
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WRITE CYCLE NO. 1 (1,2) (CS# Controlled, OE# = HIGH or LOW)
ADDRESS
CS#
WE#
DOUT
DIN
tWC
tHA
tAW tPWE
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before
Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
ADDRESS
CS#
WE#
DOUT
DIN
tWC
tHA
tAW tPWE
tSA
tHZOE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
OE#
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
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WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
ADDRESS
CS#
WE#
DOUT
DIN
tWC
tHA
tAW tPWE
tSA tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
Note:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
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Rev. A4
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DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
OPTION
Min
Typ
Max
Unit
VDR
VDD for Data
Retention
See Data Retention Waveform
1.5
-
3.6
V
IDR
Data Retention
Current
VDD= VDR(min),
CS# ≥ VDD – 0.2V
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
-
-
9
uA
Ind.
-
-
10
Auto
-
-
25
typ.(1)
3.6
tSDR
Data Retention
Setup Time
See Data Retention Waveform
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
-
ns
Note:
1. Typical values are measured at VDD=1.8V or 3V, TA = 25C , and not 100% tested.
2. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode.
DATA RETENTION WAVEFORM (CS# CONTROLLED)
GND CS#
VDR
VDD
CS# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
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ORDERING INFORMATION
IS62WV5128EALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
55
IS62WV5128EALL-55TLI
TSOP, Type I (8 x 20 mm), Lead-free
55
IS62WV5128EALL-55T2LI
TSOP, Type II, Lead-free
55
IS62WV5128EALL-55BI
mini BGA (6mm x 8mm)
55
IS62WV5128EALL-55BLI
mini BGA (6mm x 8mm), Lead-free
55
IS62WV5128EALL-55HLI
sTSOP (Type I), Lead-free (8 x 13.4 mm)
AUTOMOTIVE RANGE (A3): –40°C TO +125°C
*PLEASE CONTACT ISSI MARKETING
IS62WV5128EBLL (2.2V – 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
45
IS62WV5128EBLL-45TLI
TSOP, Type I (8 x 20 mm), Lead-free
45
IS62WV5128EBLL-45QLI
SOP, Lead-free
45
IS62WV5128EBLL-45T2LI
TSOP, Type II, Lead-free
45
IS62WV5128EBLL-45BI
mini BGA (6mm x 8mm)
45
IS62WV5128EBLL-45BLI
mini BGA (6mm x 8mm), Lead-free
45
IS62WV5128EBLL-45HLI
sTSOP (Type I), (8 x 13.4 mm), Lead-free
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
55
IS65WV5128EBLL-55CT2LA3
TSOP (Type II), Lead-free, Copper Lead-frame
55
IS65WV5128EBLL-55BLA3
mini BGA (6mm x 8mm), Lead-free
IS62WV5128EALL/EBLL/ECLL
IS65WV5128EBLL/ECLL
Integrated Silicon Solution, Inc.- www.issi.com 14
Rev. A4
04/18/2017
IS62WV5128ECLL (3.3V+/-5%)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
35
IS62WV5128ECLL-35TLI
TSOP, Type I (8 x 20 mm), Lead-free
35
IS62WV5128ECLL-35QLI
SOP, Lead-free
35
IS62WV5128ECLL-35T2LI
TSOP, Type II, Lead-free
35
IS62WV5128ECLL-35BI
mini BGA (6mm x 8mm)
35
IS62WV5128ECLL-35BLI
mini BGA (6mm x 8mm), Lead-free
35
IS62WV5128ECLL-35HLI
sTSOP (Type I), (8 x 13.4 mm), Lead-free
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
45
IS65WV5128ECLL-45CT2LA3
TSOP (Type II), Lead-free, Copper Lead-frame
45
IS65WV5128ECLL-45BLA3
mini BGA (6mm x 8mm), Lead-free
