Energy Metering IC with Integrated Oscillator and No-Load Indication ADE7769 FEATURES The ADE7769 specifications surpass the accuracy requirements of the IEC62053-21 standard. The AN-679 Application Note can be used as a basis for a description of an IEC61036 (equivalent to IEC62053-21) low cost, watt-hour meter reference design. On-chip oscillator as clock source High accuracy, supports 50 Hz/60 Hz IEC62053-21 Less than 0.1% error over a dynamic range of 500 to 1 Supplies average real power on frequency outputs F1 and F2 High frequency output CF calibrates and supplies instantaneous real power CF output remains logic high when ADE7769 is under no-load threshold Logic output REVP indicates a potential miswiring or negative power Direct drive for electromechanical counters and 2-phase stepper motors (F1 and F2) Proprietary ADCs and DSPs provide high accuracy over large variations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no-load threshold) On-chip reference 2.45 V (20 ppm/C typical) with external overdrive capability Single 5 V supply, low power (20 mW typical) Low cost CMOS process The only analog circuitry used in the ADE7769 is in the - ADCs and reference circuit. All other signal processing, such as multiplication and filtering, is carried out in the digital domain. This approach provides superior stability and accuracy over time and extreme environmental conditions. The ADE7769 supplies average real power information on the low frequency outputs, F1 and F2. These outputs can be used to directly drive an electromechanical counter or interface with an MCU. The high frequency CF logic output, ideal for calibration purposes, provides instantaneous real power information. The ADE7769 includes a power supply monitoring circuit on the VDD supply pin. The ADE7769 remains inactive until the supply voltage on VDD reaches approximately 4 V. If the supply falls below 4 V, the ADE7769 also remains inactive and the F1, F2, and CF outputs are in their nonactive modes. GENERAL DESCRIPTION The ADE77691 is a high accuracy electrical energy metering IC. It is a pin reduction version of the ADE7755 with an enhanced, precise oscillator circuit that serves as a clock source to the chip. The ADE7769 eliminates the cost of an external crystal or resonator, thus reducing the overall cost of a meter built with this IC. The chip directly interfaces with the shunt resistor. Internal phase matching circuitry ensures that the voltage and current channels are phase matched, while the HPF in the current channel eliminates dc offsets. An internal no-load threshold ensures that the ADE7769 does not exhibit creep when no load is present. During a no-load condition, the CF pin stays logic high. The ADE7769 has a 16-lead, narrow body SOIC package. 1 U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending. FUNCTIONAL BLOCK DIAGRAM VDD AGND 1 6 DGND 13 ADE7769 POWER SUPPLY MONITOR + V2N 3 - ADC SIGNAL PROCESSING BLOCK ...110101... MULTIPLIER PHASE CORRECTION V1N 4 V1P 5 + - ADC ...11011001... HPF DIGITAL-TO-FREQUENCY CONVERTER INTERNAL OSCILLATOR 2.5V REFERENCE LPF 4k 7 REFIN/OUT 11 RCLKIN 8 10 SCF S0 14 16 15 S1 REVP CF 9 12 F1 F2 05332-001 V2P 2 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. ADE7769 TABLE OF CONTENTS Specifications..................................................................................... 3 Internal Oscillator (OSC).......................................................... 14 Timing Characteristics ................................................................ 4 Transfer Function....................................................................... 14 Absolute Maximum Ratings............................................................ 5 Selecting a Frequency for an Energy Meter Application ...... 15 ESD Caution.................................................................................. 5 No-Load Threshold.................................................................... 16 Terminology ...................................................................................... 6 Negative Power Information..................................................... 16 Pin Configuration and Function Descriptions............................. 7 Evaluation Board and Reference Design Board ..................... 16 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 17 Functional Description .................................................................. 10 Ordering Guide .......................................................................... 17 Theory of Operation .................................................................. 10 Analog Inputs.............................................................................. 11 Power Supply Monitor ............................................................... 12 REVISION HISTORY 8/05--Sp0 to Rev. A Rev. A | Page 2 of 20 ADE7769 SPECIFICATIONS VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 k, 0.5% 50 ppm/C, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 1. Parameter ACCURACY 1 , 2 Measurement Error1 on Channel V1 Phase Error1 Between Channels V1 Phase Lead 37 (PF = 0.8 Capacitive) V1 Phase Lag 60 (PF = 0.5 Inductive) AC Power Supply Rejection1 Output Frequency Variation (CF) DC Power Supply Rejection1 Output Frequency Variation (CF) ANALOG INPUTS Channel V1 Maximum Signal Level Channel V2 Maximum Signal Level Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error1 OSCILLATOR FREQUENCY (OSC) Oscillator Frequency Tolerance1 Oscillator Frequency Stability1 REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient LOGIC INPUTS 3 SCF, S0, S1 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH Output Low Voltage, VOL CF Output High Voltage, VOH Output Low Voltage, VOL Frequency Output Error1, 2 (CF) Value Unit Test Conditions/Comments 0.1 % reading typ Channel V2 with full-scale signal (165 mV), 25C over a dynamic range 500 to 1, line frequency = 45 Hz to 65 Hz 0.1 0.1 Degrees () max Degrees () max 0.2 % reading typ S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms @ 50 Hz, ripple on VDD of 200 mV rms @ 100 Hz 0.3 % reading typ 30 165 320 7 18 mV max mV max k min kHz nominal mV max 4 % ideal typ 450 12 30 kHz nominal % reading typ ppm/C typ S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms, VDD = 5 V 250 mV See the Analog Inputs section V1P and V1N to AGND V2P and V2N to AGND OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% 50 ppm/C OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% 50 ppm/C See the Terminology and Typical Performance Characteristics sections External 2.5 V reference, V1 = 21.2 mV rms, V2 = 116.7 mV rms RCLKIN = 6.2 k, 0.5% 50 ppm/C 2.65 2.25 10 V max V min pF max 200 20 mV max ppm/C typ 2.4 0.8 1 10 V min V max A max pF max VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD 4.5 0.5 V min V max ISOURCE = 10 mA, VDD = 5 V, ISINK = 10 mA, VDD = 5 V 4 0.5 10 V min V max % ideal typ ISOURCE = 5 mA, VDD = 5 V, ISINK = 5 mA, VDD = 5 V 2.45 V nominal 2.45 V nominal 2.45 V nominal Rev. A | Page 3 of 20 External 2.5 V reference, V1 = 21.2 mV rms, V2 = 116.7 mV rms ADE7769 Parameter POWER SUPPLY VDD IDD Value Unit 4.75 5.25 5 V min V max mA max Test Conditions/Comments For specified performance 5 V - 5% 5 V + 5% Typically 4 mA 1 See the Terminology section for an explanation of specifications. 2 See the figures in the Typical Performance Characteristics section. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter. TIMING CHARACTERISTICS VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 k, 0.5% 50 ppm/C, TMIN to TMAX = -40C to +85C, unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter. See Figure 2. Table 2. Parameter 1 t1 t2 t3 t41, 2 t5 t6 2 Unit Test Conditions/Comments 120 See Table 6 1/2 t2 90 See Table 7 2 ms sec sec ms sec s F1 and F2 pulse width (logic low). Output pulse period. See the Transfer Function section. Time between the F1 and F2 falling edges. CF pulse width (logic high). CF pulse period. See the Transfer Function section. Minimum time between the F1 and F2 pulses. The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section. The CF pulse is always 35 s in high frequency mode. See the Frequency Outputs section and Table 7. t1 F1 t6 t2 F2 t3 t4 t5 05332-002 1 Specifications CF Figure 2. Timing Diagram for Frequency Outputs Rev. A | Page 4 of 20 ADE7769 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND, V1P, V1N, V2P, and V2N Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead Plastic SOIC, Power Dissipation JA Thermal Impedance 1 Package Temperature Soldering 1 Value -0.3 V to +7 V -0.3 V to +7 V -6 V to +6 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +150C 150C 350 mW 124.9C/W See J-STD-20 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. JEDEC 1S standard (2-layer) board data. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 20 ADE7769 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7769 is defined by the following formula: %Error = Energy Registered by ADE7769 - True Energy True Energy x 100% Phase Error Between Channels The high-pass filter (HPF) in the current channel (Channel V1) has a phase-lead response. To offset this phase response and equalize the phase response between channels, a phasecorrection network is also placed in Channel V1. The phasecorrection network matches the phase to within 0.1 over a range of 45 Hz to 65 Hz, and 0.2 over a range 40 Hz to 1 kHz (see Figure 23 and Figure 24). Power Supply Rejection (PSR) This quantifies the ADE7769 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supplies, and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading--see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supplies are then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error This refers to the small dc signal (offset) associated with the analog inputs to the ADCs. However, the HPF in Channel V1 eliminates the offset in the circuitry. Therefore, the power calculation is not affected by this offset. Frequency Output Error (CF) The frequency output error of the ADE7769 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7769 transfer function. Gain Error The gain error of the ADE7769 is defined as the difference between the measured output of the ADCs (minus the offset) and the ideal output of the ADCs. The difference is expressed as a percentage of the ideal of the ADCs. Oscillator Frequency Tolerance The oscillator frequency tolerance of the ADE7769 is defined as the part-to-part frequency variation in terms of percentage at room temperature (25C). It is measured by taking the difference between the measured oscillator frequency and the nominal frequency defined in the Specifications section. Oscillator Frequency Stability Oscillator frequency stability is defined as frequency variation in terms of the parts-per-million drift over the operating temperature range. In a metering application, the temperature range is -40C to +85C. Oscillator frequency stability is measured by taking the difference between the measured oscillator frequency at -40C and +85C and the measured oscillator frequency at +25C. Rev. A | Page 6 of 20 ADE7769 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 16 F1 V2P 2 15 F2 V2N 3 14 CF ADE7769 13 DGND TOP VIEW V1P 5 (Not to Scale) 12 REVP AGND 6 11 RCLKIN REFIN/OUT 7 10 S0 SCF 8 9 S1 05332-003 V1N 4 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD 2, 3 V2P, V2N 4, 5 V1N, V1P 6 AGND 7 REFIN/OUT 8 SCF 9, 10 S1, S0 Power Supply. This pin provides the supply voltage for the circuitry in the ADE7769. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled with a 10 F capacitor in parallel with a 100 nF ceramic capacitor. Analog Inputs for Channel V2 (Voltage Channel). These inputs provide a fully differential input pair. The maximum differential input voltage is 165 mV for specified operation. Both inputs have internal ESD protection circuitry; an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. Analog Inputs for Channel V1 (Current Channel). These inputs are fully differential voltage inputs with a maximum signal level of 30 mV with respect to the V1N pin for specified operation. Both inputs have internal ESD protection circuitry and, in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7769, that is, the ADCs and reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference for all analog circuitry, such as antialiasing filters, current and voltage sensors, and so forth. For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at only one point. A star ground configuration helps to keep noisy digital currents away from the analog circuits. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.45 V and a typical temperature coefficient of 20 ppm/C. An external reference source may also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F tantalum capacitor and a 100 nF ceramic capacitor. The internal reference cannot be used to drive an external load. Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. See Table 7. These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. With this logic input, designers have greater flexibility when designing an energy meter. See the Selecting a Frequency for an Energy Meter Application section. 11 RCLKIN To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a nominal value of 6.2 k must be connected from this pin to DGND. 12 REVP 13 DGND 14 CF 15, 16 F2, F1 This logic output goes high when negative power is detected, that is, when the phase angle between the voltage and current signals is greater than 90. This output is not latched and is reset when positive power is once again detected. The output goes high or low at the same time that a pulse is issued on CF. This pin provides the ground reference for the digital circuitry in the ADE7769, that is, the multiplier, filters, and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital ground plane is the ground reference for all digital circuitry, such as the counters (mechanical and digital), MCUs, and indicator LEDs. For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at one point only--a star ground. Calibration Frequency Logic Output. The CF logic output provides instantaneous real power information. This output is intended for calibration purposes. See the SCF pin description. This output stays high when the part is in a no-load condition. Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Function section. Rev. A | Page 7 of 20 ADE7769 TYPICAL PERFORMANCE CHARACTERISTICS VDD + 100nF 10F 1 VDD 602k 220V 200 150nF 200 40A TO 40mA 3 U1 F2 15 ADE7769 CF 14 2 3 K8 820 REVP 12 200 V1P 4 V1N 150nF 350 4 PS2501-1 150nF + 1 V2N 5 K7 U3 F1 16 V2P 2 6.2k RCLKIN 11 VDD 200 10k 150nF S1 9 REFIN/OUT 7 SCF 8 100nF 10nF AGND DGND 6 10nF 13 10nF 05332-004 + 1F S0 10 Figure 4. Test Circuit for Performance Curves 1.0 1.0 PF = 1 ON-CHIP REFERENCE 0.8 0.6 0.6 +85C 0.4 0.2 ERROR (% of Reading) +25C 0 -0.2 -40C -0.4 0.2 +25C 0 -0.2 +85C -0.4 -0.8 -1.0 0.1 1 10 -0.8 -1.0 0.1 100 CURRENT CHANNEL (% of Full Scale) 1 10 100 CURRENT CHANNEL (% of Full Scale) Figure 7. Error as a % of Reading over Temperature with External Reference (PF = 1) Figure 5. Error as a % of Reading over Temperature with On-Chip Reference (PF = 1) 1.0 1.0 PF = 0.5 IND ON-CHIP REFERENCE 0.8 0.6 0.6 ERROR (% of Reading) +85C, PF = 0.5 IND 0.4 0.2 +25C, PF = 1 0 -0.2 -40C, PF = 0.5 IND -0.4 PF = 0.5 IND EXTERNAL REFERENCE 0.8 -40C, PF = 0.5 IND 0.4 0.2 +25C, PF = 1 0 -0.2 +25C, PF = 0.5 IND -0.4 +25C, PF = 0.5 IND +85C, PF = 0.5 IND -0.6 -0.6 05332-020 ERROR (% of Reading) 05332-021 -0.6 05332-019 -0.6 -40C 0.4 -0.8 -1.0 0.1 1 10 05332-022 ERROR (% of Reading) PF = 1 EXTERNAL REFERENCE 0.8 -0.8 -1.0 0.1 100 1 10 CURRENT CHANNEL (% of Full Scale) CURRENT CHANNEL (% of Full Scale) Figure 6. Error as a % of Reading over Temperature with On-Chip Reference (PF = 0.5 IND) Figure 8. Error as a % of Reading over Temperature with External Reference (PF = 0.5 IND) Rev. A | Page 8 of 20 100 ADE7769 0.5 40 0.4 30 0.2 PF = 0.5 IND PF = 1 0.1 FREQUENCY ERROR (% of Reading) 0.3 DISTRIBUTION CHARACTERISTICS MEAN = 2.247828 EXTERNAL REFERENCE SDs = 1.367176 TEMPERATURE = 25C MIN = -2.09932 MAX = +5.28288 NO. OF POINTS = 100 0 -0.1 -0.2 20 PF = 0.5 CAP 10 -0.4 -0.5 45 50 55 60 05332-025 05332-018 -0.3 0 -5 -4 -3 -2 -1 65 1.0 40 0.4 3 4 5 6 7 8 9 DISTRIBUTION CHARACTERISTICS MEAN = -1.563484 SDs = 2.040699 EXTERNAL REFERENCE MIN = -6.82969 TEMPERATURE = 25C MAX = +2.6119 NO. OF POINTS = 100 5.25V FREQUENCY 0.2 5V 0 4.75V -0.2 30 20 -0.4 -0.6 05332-023 10 -0.8 -1.0 0.1 1 10 05332-026 ERROR (% of Reading) 2 50 PF = 1 ON-CHIP REFERENCE 0.6 0 100 -12 -10 -8 -6 CURRENT CHANNEL (% of Full Scale) -2 0 2 4 6 8 10 12 Figure 13. Channel V2 Offset Distribution 1.0 0.8 -4 CHANNEL V2 OFFSET (mV) Figure 10. PSR with On-Chip Reference, PF = 1 1000 PF = 1 EXTERNAL REFERENCE 0.6 800 0.4 FREQUENCY 5.25V 0.2 5V 0 -0.2 4.75V DISTRIBUTION CHARACTERISTICS MEAN = 0% EXTERNAL REFERENCE SDs = 1.55% TEMPERATURE = 25C MIN = -11.79% MAX = +6.08% NO. OF POINTS = 3387 600 400 -0.4 -0.6 -0.8 -1.0 0.1 1 10 05332-027 200 05332-024 ERROR (% of Reading) 1 Figure 12. Channel V1 Offset Distribution Figure 9. Error as a % of Reading over Input Frequency 0.8 0 CHANNEL V1 OFFSET (mV) FREQUENCY (Hz) 0 100 -10 CURRENT CHANNEL (% of Full Scale) -8 -6 -4 -2 0 2 4 6 8 DEVIATION FROM MEAN (%) Figure 11. PSR with External Reference, PF = 1 Figure 14. Part-to-Part CF Deviation from Mean Rev. A | Page 9 of 20 10 12 ADE7769 FUNCTIONAL DESCRIPTION THEORY OF OPERATION Power Factor Considerations The two ADCs in the ADE7769 digitize the voltage signals from the current and voltage sensors. These ADCs are 16-bit -s with an oversampling rate of 450 kHz. This analog input structure greatly simplifies sensor interfacing by providing a wide dynamic range for direct connection to the sensor and by simplifying the antialiasing filter design. A high-pass filter in the current channel removes any dc component from the current signal. This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals. The method used to extract the real power information from the instantaneous power signal, that is, by low-pass filtering, is still valid even when the voltage and current signals are not in phase. Figure 16 shows the unity power factor condition and a displacement power factor (DPF) = 0.5, that is, current signal lagging the voltage by 60. Assuming that the voltage and current waveforms are sinusoidal, the real power component of the instantaneous power signal (that is, the dc term) is given by The real power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals. To extract the real power component (the dc component), the instantaneous power signal is low-pass filtered. Figure 15 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. This scheme correctly calculates real power for sinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time. V x I x cos (60) 2 This is the correct real power calculation. ADC F2 HPF MULTIPLIER VxI 2 0V LPF TIME CURRENT VOLTAGE POWER INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL VxI COS (60) 2 DIGITAL-TOFREQUENCY ADC TIME 0V CF VOLTAGE INSTANTANEOUS POWER SIGNAL - p(t) 05332-006 CH2 INSTANTANEOUS REAL POWER SIGNAL INSTANTANEOUS POWER SIGNAL POWER DIGITAL-TOFREQUENCY F1 CH1 (1) CURRENT 60 INSTANTANEOUS REAL POWER SIGNAL Figure 16. DC Component of Instantaneous Power Signal Conveys Real Power Information, PF < 1 TIME TIME 05332-005 Nonsinusoidal Voltage and Current Figure 15. Signal Processing Block Diagram The low frequency outputs (F1 and F2) are generated by accumulating this real power information. This low frequency inherently means a long accumulation time between output pulses. Consequently, the resulting output frequency is proportional to the average real power. This average real power information is then accumulated (by a counter) to generate real energy information. Conversely, due to its high output frequency and shorter integration time, the CF output frequency is proportional to the instantaneous real power. This is useful for system calibration, which can be done faster under steady load conditions. The real power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications have some harmonic content. Using the Fourier transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content. v(t ) = V0 + 2 x Vh x sin(ht + h ) h0 where: v(t) is the instantaneous voltage. V0 is the average value. Vh is the rms value of voltage harmonic h. h is the phase angle of the voltage harmonic. Rev. A | Page 10 of 20 (2) ADE7769 i(t ) = IO + 2 x I h x sin(ht + h ) (3) ho where: i(t) is the instantaneous current. I0 is the dc component. Ih is the rms value of current harmonic h. h is the phase angle of the current harmonic. Figure 17 shows the maximum signal levels on V1P and V1N. The maximum differential voltage is 30 mV. The differential voltage signal on the inputs must be referenced to a common mode, for example, AGND. The maximum common-mode signal is 6.25 mV, as shown in Figure 17. Channel V2 (Voltage Channel) Using Equations 2 and 3, the real power (P) can be expressed in terms of its fundamental real power (P1) and harmonic real power (PH) as P = P1 + PH The output of the line voltage sensor is connected to the ADE7769 at this analog input. Channel V2 is a fully differential voltage input with a maximum peak differential signal of 165 mV. Figure 18 shows the maximum signal levels that can be connected to the ADE7769 Channel V2. V2 where: P1 = V1 x I 1 cos 1 (4) +165mV V2P 1 = 1 - 1 DIFFERENTIAL INPUT 165mV MAX PEAK V2 VCM COMMON-MODE 25mV MAX Vh x I h cos h (5) AGND -165mV h 1 Figure 18. Maximum Signal Levels, Channel V2 h = h - h In Equation 5, a harmonic real power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has previously been shown to be accurate in the case of a pure sinusoid. Therefore, the harmonic real power must also correctly account for the power factor because it is made up of a series of pure sinusoids. Note that the input bandwidth of the analog inputs is 7 kHz at the nominal internal oscillator frequency of 450 kHz. ANALOG INPUTS Channel V2 is usually driven from a common-mode voltage, that is, the differential voltage signal on the input is referenced to a common mode (usually AGND). The analog inputs of the ADE7769 can be driven with common-mode voltages of up to 25 mV with respect to AGND. However, best results are achieved using a common mode equal to AGND. Typical Connection Diagrams Figure 19 shows a typical connection diagram for Channel V1. A shunt is the current sensor selected for this example because of its low cost compared to other current sensors, such as the current transformer (CT). This IC is ideal for low current meters. RF Channel V1 (Current Channel) The voltage output from the current sensor is connected to the ADE7769 here. Channel V1 is a fully differential voltage input. V1P is the positive input with respect to V1N. SHUNT RF +30mV V1P PHASE NEUTRAL Figure 19. Typical Connection for Channel V1 B V1 VCM V1N VCM AGND 05332-007 -30mV CF Figure 20 shows a typical connection for Channel V2. Typically, the ADE7769 is biased around the phase wire, and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. Adjusting the ratio of RA, RB, and RF is also a convenient way of carrying out a gain calibration on a meter. V1 COMMON-MODE 6.25mV MAX V1N AGND The maximum peak differential signal on Channel V1 should be less than 30 mV (21 mV rms for a pure sinusoidal signal) for specified operation. DIFFERENTIAL INPUT 30mV MAX PEAK 30mV V1P CF 05332-009 PH = VCM 05332-008 and V2N Figure 17. Maximum Signal Levels, Channel V1 Rev. A | Page 11 of 20 ADE7769 RF CF 165mV V2N RF NEUTRAL PHASE Equation 6 shows how the power calculation is affected by the dc offsets in the current and voltage channels. V2P {V cos (t ) + VOS } x {I cos (t ) + I OS } CF *RA >> RB + RF = Figure 20. Typical Connections for Channel V2 + POWER SUPPLY MONITOR The ADE7769 contains an on-chip power supply monitor. The power supply (VDD) is continuously monitored by the ADE7769. If the supply is less than 4 V, the ADE7769 becomes inactive. This is useful to ensure proper device operation at power-up and power-down. The power supply monitor has built-in hysteresis and filtering, which provide a high degree of immunity to false triggering from noisy supplies. In Figure 21, the trigger level is nominally set at 4 V. The tolerance on this trigger level is within 5%. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5 V 5%, as specified for normal operation. VDD 5V 4V (6) V xI + VOS x IOS + VOS x I cos (t ) + IOS x V cos (t ) 2 V xI 2 x cos (2t ) DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION VOS x IOS VxI 2 IOS x V VOS x I 05332-012 RB 05332-010 RA * 0 FREQUENCY (RAD/s) Figure 22. Effect of Channel Offset on the Real Power Calculation The HPF in Channel V1 has an associated phase response that is compensated for on chip. Figure 23 and Figure 24 show the phase error between channels with the compensation network activated. The ADE7769 is phase compensated up to 1 kHz as shown. This ensures correct active harmonic power calculation even at low power factors. 0V 0.30 TIME 0.25 0.20 INACTIVE Figure 21. On-Chip Power Supply Monitor HPF and Offset Effects Figure 22 shows the effect of offsets on the real power calculation. As can be seen, offsets on Channel V1 and Channel V2 contribute a dc component after multiplication. Because this dc component is extracted by the LPF and used to generate the real power information, the offsets contribute a constant error to the real power calculation. This problem is easily avoided by the built-in HPF in Channel V1. By removing the offsets from at least one channel, no error component can be generated at dc by the multiplication. Error terms at the line frequency () are removed by the LPF and the digital-to-frequency conversion (see the Digital-to-Frequency Conversion section). Rev. A | Page 12 of 20 0.15 0.10 0.05 0 -0.05 05332-013 ACTIVE PHASE (Degrees) INACTIVE 05332-011 INTERNAL ACTIVATION -0.10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (Hz) Figure 23. Phase Error Between Channels (0 Hz to 1 kHz) ADE7769 F1 DIGITAL-TOFREQUENCY F1 0.20 V 0.15 MULTIPLIER 0.10 I F2 TIME LPF DIGITAL-TOFREQUENCY CF LPF TO EXTRACT REAL POWER (DC TERM) 0.05 TIME VxI 2 0 COS (2) ATTENUATED BY LPF 05332-014 -0.05 -0.10 45 50 55 60 65 70 FREQUENCY (Hz) 0 2 FREQUENCY (RAD/s) INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN) Figure 24. Phase Error Between Channels (40 Hz to 70 Hz) Digital-to-Frequency Conversion Figure 25. Real Power-to-Frequency Conversion As previously described, the digital output of the low-pass filter after multiplication contains the real power information. However, because this LPF is not an ideal brick wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, that is, cos(ht) where h = 1, 2, 3, ... and so on. The magnitude response of the filter is given by H(f ) = 05332-015 40 CF FREQUENCY PHASE (Degrees) 0.25 FREQUENCY 0.30 1 (7) f2 1+ 4.452 For a line frequency of 50 Hz, this gives an attenuation of the 2 (100 Hz) component of approximately 22 dB. The dominating harmonic is twice the line frequency (2) due to the instantaneous power calculation. Figure 25 shows the instantaneous real power signal at the output of the LPF that still contains a significant amount of instantaneous power information, that is, cos(2t). This signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. The accumulation of the signal suppresses or averages out any non-dc components in the instantaneous real power signal. The average value of a sinusoidal signal is zero. Thus, the frequency generated by the ADE7769 is proportional to the average real power. Figure 25 shows the digital-tofrequency conversion for steady load conditions, that is, constant voltage and current. In Figure 25, the frequency output, CF, varies over time, even under steady load conditions. This frequency variation is primarily due to the cos(2t) component in the instantaneous real power signal. The output frequency on CF can be up to 2048 times higher than the frequency on F1 and F2. This higher output frequency is generated by accumulating the instantaneous real power signal over a much shorter time while converting it to a frequency. This shorter accumulation period means less averaging of the cos(2t) component. Consequently, some of this instantaneous power signal passes through the digital-to-frequency conversion. This is not a problem in the application. Where CF is used for calibration purposes, the frequency should be averaged by the frequency counter, which removes any ripple. If CF is being used to measure energy, for example in a microprocessor based application, the CF output should also be averaged to calculate power. Because the F1 and F2 outputs operate at a much lower frequency, much more averaging of the instantaneous real power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output. Connecting to a Microcontroller for Energy Measurement The easiest way to interface the ADE7769 to a microcontroller is to use the CF high frequency output with the output frequency scaling set to 2048 x F1, F2. This is done by setting SCF = 0 and S0 = S1 = 1 (see Table 7). With full-scale ac signals on the analog inputs, the output frequency on CF is approximately 2.867 kHz. Figure 26 shows one scheme that could be used to digitize the output frequency and carry out the necessary averaging mentioned in the previous section. Rev. A | Page 13 of 20 ADE7769 CF INTERNAL OSCILLATOR (OSC) FREQUENCY RIPPLE The nominal internal oscillator frequency is 450 kHz when used with RCLKIN, with a nominal value of 6.2 k. The frequency outputs are directly proportional to the oscillator frequency, thus RCLKIN must have low tolerance and low temperature drift to ensure stability and linearity of the chip. The oscillator frequency is inversely proportional to the RCLKIN, as shown in Figure 27. Although the internal oscillator operates when used with RCLKIN values between 5.5 k and 20 k, choosing a value within the range of the nominal value, as shown in Figure 27, is recommended. 10% TIME MCU ADE7769 COUNTER TIMER 05332-016 CF 490 480 Figure 26. Interfacing the ADE7769 to an MCU 470 Average Frequency = Average Power = FREQUENCY (kHz) As shown in Figure 26, the frequency output, CF, is connected to an MCU counter or port. This counts the number of pulses in a given integration time, which is determined by an MCU internal timer. The average power proportional to the average frequency is given by 450 440 430 420 Counter Time (8) 410 400 5.8 The energy consumed during an integration period is given by Energy = Average Power x Time = 460 Power Measurement Considerations Calculating and displaying power information always has some associated ripple, which depends on the integration period used in the MCU to determine average power and also on the load. For example, at light loads, the output frequency may be 10 Hz. With an integration period of 2 seconds, only about 20 pulses are counted. The possibility of missing one pulse always exists, because the ADE7769 output frequency is running asynchronously to the MCU timer. This results in a 1-in-20, or 5%, error in the power measurement. 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 RESISTANCE (k) Counter x Time = Counter (9) Time For the purpose of calibration, this integration time could be 10 seconds to 20 seconds to accumulate enough pulses to ensure correct averaging of the frequency. In normal operation, the integration time could be reduced to 1 or 2 seconds, depending, for example, on the required update rate of a display. With shorter integration times on the MCU, the amount of energy in each update may still have some small amount of ripple, even under steady load conditions. However, over a minute or more the measured energy has no ripple. 05332-017 AVERAGE FREQUENCY Figure 27. Effect of RCLKIN on Internal Oscillator Frequency (OSC) TRANSFER FUNCTION Frequency Outputs F1 and F2 The ADE7769 calculates the product of two voltage signals (on Channel V1 and Channel V2) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active low pulses. The pulse rate at these outputs is relatively low, for example, 0.175 Hz maximum for ac signals with S0 = S1 = 0 (see Table 6). This means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The averaging of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation: Freq = 494.75 x V1rms x V2rms x F1-4 VREF 2 (10) where: Freq is the output frequency on F1 and F2 (Hz). V1rms is the differential rms voltage signal on Channel V1 (V). V2rms is the differential rms voltage signal on Channel V2 (V). VREF = is the reference voltage (2.45 V 200 mV) (V). F1-4 = are one of four possible frequencies selected by using the S0 and S1logic inputs (see Table 5). Rev. A | Page 14 of 20 ADE7769 Table 5. F1-4 Frequency Selection S1 0 0 1 1 1 2 S0 0 1 0 1 OSC Relation OSC/219 OSC/218 OSC/217 OSC/216 1 Table 7. Maximum Output Frequency on CF F1-4 at Nominal OSC (Hz) 0.86 1.72 3.43 6.86 2 F1-4 is a binary fraction of the internal oscillator frequency. Values are generated using the nominal frequency of 450 kHz. Example In this example, with ac voltages of 30 mV peak applied to V1 and 165 mV peak applied to V2, the expected output frequency is calculated as 1 If the on-chip reference is used, actual output frequencies may vary from device to device due to the reference tolerance of 200 mV. 494.75 x 0.03 x 0.165 x F1 2 x 2 x 2.45 2 = 0.204 x F1 = 0.175 (11) Table 6. Maximum Output Frequency on F1 and F2 S1 0 0 1 1 1 S0 0 1 0 1 OSC Relation 0.204 x F1 0.204 x F2 0.204 x F3 0.204 x F4 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 CF Max for AC Signals (Hz)1 128 x F1, F2 = 22.4 64 x F1, F2 = 11.2 64 x F1, F2 = 22.4 32 x F1, F2 = 11.2 32 x F1, F2 = 22.4 16 x F1, F2 = 11.2 16 x F1, F2 = 22.4 2048 x F1, F2 = 2.867 kHz Values are generated using the nominal frequency of 450 kHz. SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION F1-4 = OSC/219 Hz, S0 = S1 = 0 V1rms = 0.03/2 V V2rms = 0.165/2 V VREF = 2.45 V (nominal reference value) Freq = SCF 1 0 1 0 1 0 1 0 Max Frequency1 or AC Inputs (Hz) 0.175 0.35 0.70 1.40 Values are generated using the nominal frequency of 450 kHz. Frequency Output CF The pulse output CF (calibration frequency) is intended for calibration purposes. The output pulse rate on CF can be up to 2048 times the pulse rate on F1 and F2. The lower the F1-4 frequency selected, the higher the CF scaling (except for the high frequency mode SCF = 0, S1 = S0 = 1). Table 7 shows how the two frequencies are related, depending on the states of the logic inputs S0, S1, and SCF. Due to its relatively high pulse rate, the frequency at the CF logic output is proportional to the instantaneous real power. As with F1 and F2, CF is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this real power information is accumulated over a much shorter time. Therefore, less averaging is carried out in the digital-tofrequency conversion. With much less averaging of the real power signal, the CF output is much more responsive to power fluctuations (see the signal processing block diagram shown in Figure 15). As shown in Table 5, the user can select one of four frequencies. This frequency selection determines the maximum frequency on F1 and F2. These outputs are intended for driving an energy register (electromechanical or other). Because only four different output frequencies can be selected, the available frequency selection has been optimized for a meter constant of 100 imp/kWh with a maximum current of between 10 A and 120 A. Table 8 shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V. In all cases, the meter constant is 100 imp/kWh. Table 8. F1 and F2 Frequency at 100 imp/kWh IMAX (A) 12.5 25.0 40.0 60.0 80.0 120.0 F1 and F2 (Hz) 0.076 0.153 0.244 0.367 0.489 0.733 The F1-4 frequencies allow complete coverage of this range of output frequencies (F1, F2). When designing an energy meter, the nominal design voltage on Channel V2 (voltage) should be set to half-scale to allow for calibration of the meter constant. The current channel should also be no more than half scale when the meter sees maximum load. This allows overcurrent signals and signals with high crest factors to be accommodated. Table 9 shows the output frequency on F1 and F2 when both analog inputs are half scale. The frequencies in Table 9 align very well with those in Table 8 for maximum load. Table 9. F1 and F2 Frequency with Half-Scale AC Inputs S1 S0 F1-4 (Hz) Frequency on F1 and F2-- CH1 and CH2 Half-Scale AC Input1 0 0 1 1 0 1 0 1 0.86 1.72 3.43 6.86 0.051 x F1 0.051 x F2 0.051 x F3 0.051 x F4 1 0.044 Hz 0.088 Hz 0.176 Hz 0.352 Hz Values are generated using the nominal frequency of 450 kHz. Rev. A | Page 15 of 20 ADE7769 The no-load condition is indicated with CF output pulse remaining logic high, as shown in Figure 28. MAGNITUDE When selecting a suitable F1-4 frequency for a meter design, the frequency output at IMAX (maximum load) with a meter constant of 100 imp/kWh should be compared with Column 4 of Table 9. The closest frequency in Table 9 determines the best choice of frequency (F1-4). For example, if a meter with a maximum current of 25 A is being designed, the output frequency on F1 and F2 with a meter constant of 100 imp/kWh is 0.153 Hz at 25 A and 220 V (from Table 8). In Table 9 the closest frequency to 0.153 Hz in Column 4 is 0.176 Hz. Therefore, as shown in Table 5, F3 (3.43 Hz) is selected for this design. ACTIVE POWER NO-LOAD THRESHOLD TIME 0W CF FREQUENCY PROPORTIONAL TO POWER Frequency Outputs The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 90-ms-wide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table 7. As with F1 and F2, if the period of CF (t5) falls below 180 ms, the CF pulse width is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulse width is 25 ms. When high frequency mode is selected (that is, SCF = 0, S1 = S0 = 1), the CF pulse width is fixed at 35 s. Therefore, t4 is always 35 s, regardless of output frequency on CF. NO-LOAD THRESHOLD The ADE7769 includes a no-load threshold and start-up current feature, which eliminates any creep effects in the meter. The ADE7769 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency does not cause a pulse to be issued on F1 or F2. The minimum output frequency is given as 0.00244% for each of the F1-4 frequency selections (see Table 5). CF 05332-028 Figure 2 shows a timing diagram for the various frequency outputs. The F1 and F2 outputs are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating low frequency pulses. The F1 and F2 pulse widths (t1) are set such that if they fall below 240 ms (0.24 Hz), they are set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table 6. Figure 28. No-Load Indication Using ADE7769 NEGATIVE POWER INFORMATION The ADE7769 detects when the current and voltage channels have a phase shift greater than 90. This mechanism can detect an incorrect meter connection or the generation of negative power. The REVP pin output goes active high when negative power is detected and active low if positive power is detected. The REVP pin output changes state as a pulse is issued on CF. EVALUATION BOARD AND REFERENCE DESIGN BOARD An evaluation board can be used to verify the functionality and the performance of the ADE7769. Download the documentation for the board from http://www.analog.com/ADE7769. In addition, the reference design board ADE7769ARN-REF and Application Note AN-679 can be used in the design of a low cost watt-hour meter that surpasses IEC62053-21 accuracy specifications. The application note can be downloaded from http://www.analog.com/ADE7769. For example, for an energy meter with a meter constant of 100 imp/kWh on F1, F2 using F3 (3.43 Hz), the minimum output frequency at F1 or F2 would be 0.00244% of 3.43 Hz or 8.38 x 10-5 Hz. This would be 2.68 x 10-3 Hz at CF (32 x F1 Hz) when SCF = S0 = 1, S1 = 0. In this example, the no-load threshold would be equivalent to 3 W of load or a start-up current of 13.72 mA at 220 V. Compare this value to the IEC62053-21 specification which states that the meter must start up with a load equal to or less than 0.4% Ib. For a 5 A (Ib) meter, 0.4% of Ib is equivalent to 20 mA. Rev. A | Page 16 of 20 ADE7769 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 16 9 1 8 1.27 (0.0500) BSC 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.50 (0.0197) x 45 0.25 (0.0098) 8 0.51 (0.0201) SEATING 0.25 (0.0098) 0 1.27 (0.0500) PLANE 0.31 (0.0122) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 29. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADE7769AR ADE7769AR-RL ADE7769ARZ 1 ADE7769ARZ-RL1 EVAL-ADE7769EB ADE7769AR-REF 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] REEL 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] REEL Evaluation Board Reference Design Board Z = Pb-free part. Rev. A | Page 17 of 20 Package Option R-16 R-16 R-16 R-16 ADE7769 NOTES Rev. A | Page 18 of 20 ADE7769 NOTES Rev. A | Page 19 of 20 ADE7769 NOTES (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05332-0-8/05(A) Rev. A | Page 20 of 20