MACH 4 CPLD Family I MAC nclude s H Adv anc 4A Fam e In form ily atio n High Performance EE CMOS Programmable Logic FEATURES High-performance, EE CMOS 3.3-V & 5-V CPLD families Flexible architecture for rapid logic designs -- Excellent First-Time-FitTM and refit feature -- SpeedLockingTM performance for guaranteed fixed timing -- Central, input and output switch matrices for 100% routability and 100% pin-out retention High speed -- 5.0ns tPD Commercial and 7.5ns tPD Industrial -- 182MHz fCNT 32 to 512 macrocells; 32 to 768 registers 44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages Advanced capabilities for easy system integration -- 3.3-V & 5-V JEDEC-compliant operations -- JTAG (IEEE 1149.1) compliant for boundary scan testing -- 3.3-V & 5-V JTAG in-system programming -- PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades) -- Safe for mixed supply voltage system designs -- Programmable pull-up or Bus-FriendlyTM inputs and I/Os -- Hot-socketing -- Programmable security bit -- Individual output slew rate control Flexible architecture for a wide range of design styles -- D/T registers and latches -- Synchronous or asynchronous mode -- Dedicated input registers -- Programmable polarity -- Reset/ preset swapping Advanced EE CMOS process provides high-performance, cost-effective solutions Supported by Vantis DesignDirectTM software for rapid logic development -- Supports HDL design methodologies with results optimized for Vantis -- Flexibility to adapt to user requirements -- Software partnerships that ensure customer success Lattice/Vantis and third-party hardware programming support -- Lattice/VantisPROTM (formerly known as MACHPRO(R)) software for in-system programmability support on PCs and automated test equipment -- Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# 17466 Amendment/0 Rev: J Issue Date: May 1999 Table 1. MACH 4 Device Features1,2 M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128 Macrocells 32 64 96 128 128 192 256 Maximum User I/O Pins 32 32 48 64 64 96 128 tPD (ns) 7.5 7.5 7.5 7.5 7.5 7.5 7.5 fCNT (MHz) 111 111 111 111 111 111 111 tCOS (ns) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 tSS (ns) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Static Power (mA) 25 25 50 70 70 85 100 JTAG Compliant Yes Yes Yes Yes No Yes Yes PCI Compliant Yes Yes Yes Yes Yes Yes Yes Feature Notes: 1. For information on the M4-96/96 device, please refer to the M4-96/96 datasheet at www.vantis.com. 2. "M4-xxx" is for 5-V devices. "M4LV-xxx" is for 3.3-V devices. 2 MACH 4 Family Table 2. MACH 4A Device Features1 3.3 V Devices Feature M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512 Macrocells 32 64 96 128 192 256 384 512 User I/O options 32 32/64 48 64/96/128 68/96/128 128/192 132/160/192 132/160/192/ 256 tPD (ns) 5.0 5.0 5.0 5.0 5.0 5.0 6.5 6.5 fCNT (MHz) 182 182 182 182 182 182 154 154 tCOS (ns) 4.0 4.0 4.0 4.0 4.0 4.0 4.5 4.5 tSS (ns) 3.0 3.0 3.0 3.0 3.0 3.0 4.0 4.0 Static Power (mA) TBD TBD TBD TBD TBD TBD TBD TBD JTAG Compliant Yes Yes Yes Yes Yes Yes Yes Yes PCI Compliant Yes Yes Yes Yes Yes Yes Yes Yes M4A5-32 M4A5-64 M4A5-96 M4A5-128 M4A5-192 M4A5-256 Macrocells 32 64 96 128 192 256 User I/O options 32 32 48 64 96 128 5 V Devices Feature tPD (ns) 5.0 5.0 5.0 5.0 5.0 6.5 fCNT (MHz) 182 182 182 182 182 154 tCOS (ns) 4.0 4.0 4.0 4.0 4.0 4.5 tSS (ns) 3.0 3.0 3.0 3.0 3.0 4.0 Static Power (mA) TBD TBD TBD TBD TBD TBD JTAG Compliant Yes Yes Yes Yes Yes Yes PCI Compliant Yes Yes Yes Yes Yes Yes Notes: 1. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on availability. MACH 4 Family 3 GENERAL DESCRIPTION The MACH(R) 4 family from Lattice/Vantis offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. Both the MACH 4 and the MACH 4A families offer 5-V (M4-xxx and M4A5-xxx) and 3.3-V (M4LVxxx and M4A3-xxx) operation. MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing capability also allows product testability on automated test equipment for device connectivity. All MACH 4 family members deliver First-Time Fit and easy system integration with pin-out retention after any design change and refit. With multi-tiered central switch matrices, enhanced logic arrays, intelligent logic allocators with an XOR gate and multi-clocking, the MACH 4 family has D or T-type registers and latches as well as synchronous/asynchronous logic and flexible set/reset capabilities. For both 3.3-V and 5-V operations, MACH 4 products can deliver guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output (Tables 3 and 4). Table 3. MACH 4 Speed Grades Speed Grade1 Device -7 -10 -12 -14 -15 -18 M4-32/32 M4LV-32/32 C C, I C, I I C I M4-64/32 M4LV-64/32 C C, I C, I I C I M4-96/48 M4LV-96/48 C C, I C, I I C I M4-128/64 M4LV-128/64 C C, I C, I I C I M4-128N/64 M4LV-128N/64 C C, I C, I I C I M4-192/96 M4LV-192/96 C C, I C, I I C I M4-256/128 M4LV-256/128 C C, I C, I I C I Note: 1. C = Commercial, 4 I = Industrial MACH 4 Family Table 4. MACH 4A Speed Grades Speed Grade1, 2 Device -5 -55 -6 -65 -7 -10 -12 -14 M4A3-32 M4A5-32 C C C C C, I C, I C, I I M4A3-64 M4A5-64 C C C C C, I C, I C, I I M4A3-96 M4A5-96 C C C C C, I C, I C, I I M4A3-128 M4A5-128 C C C C C, I C, I C, I I M4A3-192 M4A5-192 C C C C C, I C, I C, I I M4A3-256 C C C C C, I C, I C, I I M4A5-256 C C C, I C, I I M4A3-384 C C C, I C, I I M4A3-512 C C C, I C, I I Notes: 1. C = Commercial, I = Industrial 2. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on availability. The MACH 4 family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), and finepitch BGA (fpBGA) packages ranging from 44 to 352 pins (Tables 5 and 6). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5V devices do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/ Os, a programmable power-down mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition. Table 5. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table) M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 44-pin PLCC 32+2 32+2 44-pin TQFP 32+2 32+2 48-pin TQFP 32+2 32+2 Package M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 84-pin PLCC 100-pin TQFP 100-pin PQFP M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128 64+6 48+8 64+6 64+6 144-pin TQFP 96+16 208-pin PQFP 128+14 256-ball BGA 128+14 MACH 4 Family 5 Table 6. MACH 4A Package and I/O Options1 (Number of I/Os and dedicated inputs in Table) 3.3 V Devices M4A3-32 M4A3-64 44-pin PLCC Package 32+2 32+2 44-pin TQFP 32+2 32+2 48-pin TQFP 32+2 32+2 100-pin TQFP 64+6 M4A3-96 48+8 100-pin PQFP M4A3-128 M4A3-192 64+6 68+2 M4A3-256 M4A3-384 M4A3-512 132 132 160 160 192 192 64+6 100-ball fpBGA 64+6 64+6 68+2 144-pin TQFP 96+16 96+16 144-ball fpBGA 96+16 96+16 176-pin TQFP 128+4 128+4 128+4 200-ball fpBGA 128+4 128+4 128+4 208-pin PQFP 128+14, 160 320-ball fpBGA 192 256-ball BGA 128+14 352-ball BGA 256 5 V Devices Package M4A5-32 M4A5-64 44-pin PLCC 32+2 32+2 44-pin TQFP 32+2 32+2 48-pin TQFP 32+2 32+2 100-pin TQFP 100-pin PQFP M4A5-96 M4A5-128 48+8 64+6 M4A5-192 M4A5-256 64+6 144-pin TQFP 96+16 208-pin PQFP 128+14 256-ball BGA 128+14 Note: 1. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on availability. 6 MACH 4 Family Lattice/Vantis offers software design support for MACH devices in both the MACHXL(R) and DesignDirect development systems. The DesignDirect development system is Vantis' implementation software that includes support for all Vantis CPLD, FPGA and SPLD devices. This system is supported under Windows '95, '98 and NT as well as Sun Solaris and HPUX. DesignDirect software is designed for use with design entry, simulation and verification software from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model Technology , Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists, generates JEDEC files for Vantis PLDs and creates industry-standard EDIF, Verilog, VITALcompliant VHDL and SDF simulation netlist for design verification. DesignDirect software is also available in product configurations that include VHDL and Verilog synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided. MACH 4 Family 7 FUNCTIONAL DESCRIPTION The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple optimized PAL(R) blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices. The key to being able to make effective use of these devices lies in the interconnect schemes. In MACH 4 architecture, the macrocells have been decoupled from the product terms through the logic allocator, and the I/O pins have been decoupled from the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently. PAL Block 4 Dedicated Input Pins Central Switch Matrix Note 3 33/ 34/ 36 Logic Array Input Switch Matrix 16 Logic Allocator with XOR Output/ Buried Macrocells 16 16 8 Note 1 16 I/O Cells Clock/Input Pins Output Switch Matrix Note 2 Clock Generator I/O Pins I/O Pins PAL Block PAL Block I/O Pins 17466G-001 Figure 1. MACH 4 Block Diagram and PAL Block Structure Notes: 1. 16 for MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page). 2. Block clocks do not go to I/O cells in M4(LV)-32/32 or M4A(3,5)-32/32. 3. M4(LV)-192/96, M4(LV)-256/128, M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix. 8 MACH 4 Family Table 7. Architectural Summary of MACH 4 devices MACH 4A Devices M4-64/32, M4LV-64/32 M4-96/48, M4LV-96/48 M4-128/64, M4LV-128/64 M4-128N/64, M4LV-128N/64 M4-192/96, M4LV-192/96 M4-256/128, M4LV-256/128 M4-32/32 M4LV-32/32 2:1 1:1 Input Switch Matrix Yes Yes Input Registers Yes No Central Switch Matrix Yes Yes Output Switch Matrix Yes Yes Macrocell-I/O Cell Ratio Table 8. Architectural Summary of MACH 4A devices MACH 4A Devices M4A3-64/32, M4A5-64/32 M4A3-96/48, M4A5-96/48 M4A3-128/64, M4A5-128/64 M4A3-192/96, M4A5-192/96 M4A3-256/128, M4A5-256/128 M4A3-384 M4A3-512 M4A3-32/32 M4A5-32/32 M4A3-64/64 M4A3-128/96, M4A3-128/128 M4A3-256/160 M4A3-256/192 M4A3-192/68, M4A3-192/128 Macrocell-I/O Cell Ratio 2:1 1:1 Input Switch Matrix Yes Yes Input Registers Yes No Central Switch Matrix Yes Yes Output Switch Matrix Yes Yes The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells internally in a PAL block (Tables 7 and 8). The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the central switch matrix. This mechanism ensures that PAL blocks in MACH 4 devices communicate with each other with consistent, predictable delays. The central switch matrix makes a MACH 4 device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device. MACH 4 Family 9 Each PAL block consists of: Product-term array Logic allocator Macrocells Output switch matrix I/O cells Input switch matrix Clock generator Product-Term Array The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the central switch matrix (Table 9), and are provided in both true and complement forms for efficient logic implementation. Table 9. PAL Block Inputs Device Number of Inputs to PAL Block M4-32/32 and M4LV-32/32 M4-64/32 and M4LV-64/32 M4-96/48 and M4LV-96/48 M4-128/64 and M4LV-128/64 M4-128N/64 and M4LV-128N/64 33 33 33 33 33 M4-192/96 and M4LV-192/96 M4-256/128 and M4LV-256/128 34 34 M4A3-32/32 and M4A5-32/32 M4A3-64/32 and M4A5-64/32 M4A3-96/48 and M4A5-96/48 M4A3-128/64 and M4A5-128/64 33 33 33 33 M4A3-192/96 and M4A5-192/96 M4A3-256/128 and M4A5-256/128 34 34 M4A3-64/64 M4A3-128/96 and M4A3-128/128 M4A3-192/68 and M4A3-192/128 M4A3-256/160 and M4A3-256/192 M4A3-384 M4A3-512 36 36 36 36 36 36 Because the number of product terms available for a given logic function is not fixed, the full sum of products is not realized in the array. The product terms drive the logic allocator, which allocates the appropriate number of product terms to generate the function. Logic Allocator Within the logic allocator, product terms are allocated to macrocells in "product term clusters." The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block. The size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. Yet when few product terms are used, there will be a minimal number 10 MACH 4 Family of unused--or wasted--product terms left over. The product term clusters available to each macrocell within a PAL block are shown in Tables 10 and 11. Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration of the associated macrocell. When the macrocell is used in synchronous mode (Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a different macrocell, the allocator configuration is not determined by the mode of the macrocell actually being driven. The configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing. In addition, there is an extra product term that can either join the basic cluster to give an extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18 product terms. When the extra product term is used to extend the cluster, the value of the second XOR input can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are shown in Figures 3 and 4. MACH 4 Family 11 Table 10. Logic Allocator for All MACH 4 and MACH 4A Devices (except M4(LV)-32/32 and M4A(3,5)-32/32) Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 Table 11. Logic Allocator for M4(LV)-32/32 and M4A(3,5)-32/32 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Logic Allocator n n To n+1 0 Default From n+1 From n+2 0 Default Extra Product Term Available Clusters C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 To Macrocell n Basic Product Term Cluster From n-1 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7 C6, C7 To n-1 To n-2 Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Prog. Polarity 17466G-005 n Logic Allocator n 0 Default To n+1 Extra Product Term From n+1 From n+2 0 Default To Macrocell n Basic Product Term Cluster From n-1 To n-1 To n-2 a. Synchronous Mode Prog. Polarity b. Asynchronous Mode Figure 2. Logic Allocator: Configuration of Cluster "n" Set by Mode of Macrocell "n" 12 MACH 4 Family 17466G-006 a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low 0 d. Basic cluster routed away; single-product-term, active high e. Extended cluster routed away 17466G-007 Figure 3. Logic Allocator Configurations: Synchronous Mode a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low 0 d. Basic cluster routed away; single-product-term, active high e. Extended cluster routed away 17466G-008 Figure 4. Logic Allocator Configurations: Asynchronous Mode Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All configurations have the same delay. This means that designers do not have to decide between optimizing resources or speed; both can be optimized. If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flipflop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell. Product term clusters do not "wrap" around a PAL block. This means that the macrocells at the ends of the block have fewer product terms available. MACH 4 Family 13 Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell. Power-Up Reset PAL-Block Initialization Product Terms SWAP Common PAL-block resource Individual macrocell resources AP D/T/L From Logic Allocator From PAL-Clock Generator AR Q To Output and Input Switch Matrices Block CLK0 Block CLK1 Block CLK2 Block CLK3 17466G-009 a. Synchronous mode Power-Up Reset Individual Initialization Product Term AP AR D/T/L Q From Logic Allocator From PAL-Block Clock Generator To Output and Input Switch Matrices Block CLK0 Block CLK1 Individual Clock Product Term b. Asynchronous mode 17466G-010 Figure 5. Macrocell In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator. 14 MACH 4 Family The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 12. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs are HIGH. AP AR D Q AP AR D Q b. D-type with programmable D polarity a. D-type with XOR L AP AR L Q AP AR Q G G c. Latch with XOR d. Latch with programmable D polarity AP AR T Q f. Combinatorial with XOR e. T-type with programmable T polarity g. Combinatorial with programmable polarity 17466G-011 Figure 6. Primary Macrocell Configurations MACH 4 Family 15 Table 12. Register/Latch Operation Input(s) CLK/LE 1 Q+ D-type Register D=X D=0 D=1 0,1, () () () Q 0 1 T-type Register T=X T=0 T=1 0, 1, () () () Q Q Q D-type Latch D=X D=0 D=1 1(0) 0(1) 0(1) Q 0 1 Configuration Note: 1. Polarity of CLK/LE can be programmed Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be programmed. The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode. The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire PAL block. Power-Up Reset Power-Up Preset PAL-Block Initialization Product Terms PAL-Block Initialization Product Terms AP D/T/L AR Q AP D/L b. Power-up preset a. Power-up reset 17466G-012 Figure 7. Synchronous Mode Initialization Configurations 16 AR Q MACH 4 Family 17466G-013 A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset. Power-Up Preset Power-Up Reset Individual Preset Product Term Individual Reset Product Term AP D/L/T AP D/L/T AR Q a. Reset AR Q b. Preset 17466G-014 17466G-015 Figure 8. Asynchronous Mode Initialization Configurations Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization functionality of the flip-flops is illustrated in Table 13. The macrocell sends its data to the output switch matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired. The input switch matrix can send the signal back to the central switch matrix as feedback. Table 13. Asynchronous Reset/Preset Operation AR AP CLK/LE1 Q+ 0 0 X See Table 12 0 1 X 1 1 0 X 0 1 1 X 0 Note: 1. Transparent latch is unaffected by AR, AP Output Switch Matrix The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. In MACH 4 and MACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells as I/O cells. The MACH 4 output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells; each macrocell has a choice of four I/O cells. The MACH 4 and MACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/ O cells (Figure 9). MACH 4 Family 17 M0 I/O0 M0 I/O0 M1 M1 I/O1 M1 I/O1 M2 M2 I/O2 M2 I/O2 M3 M3 I/O3 M3 I/O3 I/O4 M4 I/O0 M4 I/O4 M4 M5 I/O1 M5 I/O5 M5 I/O5 M6 I/O2 M6 I/O6 M6 I/O6 M7 I/O3 M7 I/O7 M7 I/O7 M8 I/O4 M8 I/O8 M8 I/O8 M9 I/O5 M9 I/O9 M9 I/O9 M10 I/O6 M10 I/O10 M10 I/O10 M11 I/O7 M11 I/O11 M11 I/O11 M12 M12 I/O12 M12 I/O12 M13 M13 I/O13 M13 I/O13 M14 M14 I/O14 M14 I/O14 M15 M15 I/O15 M15 I/O15 I/O cell MUX macrocells Each I/O cell can choose one of 8 macrocells in all MACH 4 and MACH 4A devices. M0 Each macrocell can drive one of 4 I/O cells in MACH 4 and MACH 4A devices with 2:1 macrocell-I/O cell ratio. Each macrocell can drive one of 8 I/O cells in MACH 4A devices with 1:1 macrocell-I/O cell ratio except M4A(3, 5)-32/32 devices. Each macrocell can drive one of 8 I/O cells in M4(LV)-32/32 and M4A(3, 5)-32/32 devices. Figure 9. MACH 4 Output Switch Matrix Table 14. Output Switch Matrix Combinations for MACH 4 and MACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio 18 Macrocell Routable to I/O Cells M0, M1 I/O0, I/O5, I/O6, I/O7 M2, M3 I/O0, I/O1, I/O6, I/O7 M4, M5 I/O0, I/O1, I/O2, I/O7 M6, M7 I/O0, I/O1, I/O2, I/O3 M8, M9 I/O1, I/O2, I/O3, I/O4 M10, M11 I/O2, I/O3, I/O4, I/O5 M12, M13 I/O3, I/O4, I/O5, I/O6 M14, M15 I/O4, I/O5, I/O6, I/O7 I/O Cell Available Macrocells I/O0 M0, M1, M2, M3, M4, M5, M6, M7 I/O1 M2, M3, M4, M5, M6, M7, M8, M9 I/O2 M4, M5, M6, M7, M8, M9, M10, M11 I/O3 M6, M7, M8, M9, M10, M11, M12, M13 I/O4 M8, M9, M10, M11, M12, M13, M14, M15 I/O5 M0, M1, M10, M11, M12, M13, M14, M15 MACH 4 Family Table 14. Output Switch Matrix Combinations for MACH 4 and MACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio Macrocell Routable to I/O Cells I/O6 M0, M1, M2, M3, M12, M13, M14, M15 I/O7 M0, M1, M2, M3, M4, M5, M14, M15 Table 15. Output Switch Matrix Combinations for MACH 4 and MACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio except M4(LV)-32/32 and M4A(3,5)-32/32 Macrocell Routable to I/O Cells M0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M5 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M8 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M9 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M10 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M11 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M12 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M13 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M14 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M15 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O Cell Available Macrocells I/O0 M0 M1 M2 M3 M4 M5 M6 M7 I/O1 M0 M1 M2 M3 M4 M5 M6 M7 I/O2 M0 M1 M2 M3 M4 M5 M6 M7 I/O3 M0 M1 M2 M3 M4 M5 M6 M7 I/O4 M0 M1 M2 M3 M4 M5 M6 M7 I/O5 M0 M1 M2 M3 M4 M5 M6 M7 I/O6 M0 M1 M2 M3 M4 M5 M6 M7 I/O7 M0 M1 M2 M3 M4 M5 M6 M7 I/O8 M8 M9 M10 M11 M12 M13 M14 M15 I/O9 M8 M9 M10 M11 M12 M13 M14 M15 I/O10 M8 M9 M10 M11 M12 M13 M14 M15 I/O11 M8 M9 M10 M11 M12 M13 M14 M15 I/O12 M8 M9 M10 M11 M12 M13 M14 M15 I/O13 M8 M9 M10 M11 M12 M13 M14 M15 I/O14 M8 M9 M10 M11 M12 M13 M14 M15 I/O15 M8 M9 M10 M11 M12 M13 M14 M15 MACH 4 Family 19 Table 16. Output Switch Matrix Combinations for M4(LV)-32/32 and M4A(3,5)-32/32 Macrocell 20 Routable to I/O Cells M0, M1, M2, M3, M4, M5, M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M8, M9, M10, M11, M12, M13, M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 I/O Cell Available Macrocells I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M0, M1, M2, M3, M4, M5, M6, M7 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M8, M9, M10, M11, M12, M13, M14, M15 MACH 4 Family I/O Cell The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio.) An individual output enable product term is provided for each I/O cell. The feedback signal drives the input switch matrix. Individual Output Enable Product Term From Output Switch Matrix To Input Switch Matrix Individual Output Enable Product Term From Output Switch Matrix Q D/L Block CLK0 Block CLK1 Block CLK2 Block CLK3 To Input Switch Matrix Power-up reset 17466G-017 17466G-018 Figure 10. I/O Cell for MACH 4 and MACH 4A Devices Figure 11. I/O Cell for MACH 4 and MACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio with 1:1 Macrocell-I/O Cell Ratio The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of the input are sent to the input switch matrix. This allows for such functions as "time-domain-multiplexed" data comparison, where the first data value is stored, and then the second data value is put on the I/O pin and compared with the previous stored value. Note that the flip-flop used in the MACH 4 I/O cell is independent of the flip-flops in the macrocells. It powers up to a logic low. Zero-Hold-Time Input Register The MACH 4 devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. Input Switch Matrix The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix. MACH 4 Family 21 17466G-002 Figure 12. MACH 4 and MACH 4A with 2:1 Macrocell-I/O Cell Ratio - Input Switch Matrix From I/O Pin From Macrocell To Central Switch Matrix Registered/Latched Direct From Macrocell 2 From Macrocell 1 To Central Switch Matrix From Input Cell 17466G-003 Figure 13. MACH 4 and MACH 4A with 1:1 Macrocell-I/O Cell Ratio - Input Switch Matrix PAL Block Clock Generation Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used anywhere in the PAL block. These four PAL block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. Table 17 lists the possible combinations. GCLK0 Block CLK0 (GCLK0 or GCLK1) GCLK1 Block CLK1 (GCLK1 or GCLK0) GCLK2 Block CLK2 (GCLK2 or GCLK3) GCLK3 Block CLK3 (GCLK3 or GCLK2) 17466G-004 Figure 14. PAL Block Clock Generator 1 Note: 1. M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1. 22 MACH 4 Family Table 17. PAL Block Clock Combinations1 Block CLK0 GCLK0 GCLK1 GCLK0 GCLK1 X X X X Block CLK1 GCLK1 GCLK1 GCLK0 GCLK0 X X X X Block CLK2 Block CLK3 X X X X GCLK2 (GCLK0) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK3 (GCLK1) X X X X GCLK3 (GCLK1) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK2 (GCLK0) Note: 1. Values in parentheses are for the M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32. This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows latches to be driven with either polarity of latch enable, and in a master-slave configuration. MACH 4 Family 23 MACH 4 TIMING MODEL The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH 4 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an "i". By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 4 timing model is shown in Figure 15. Refer to the Technical Note entitled MACH 4 Timing and High Speed Design for a more detailed discussion about the timing parameters. (External Feedback) (Internal Feedback) COMB/DFF/TFF/ LATCH/SR*/JK* tPL tSS(T) tSA(T) tH(S/A) tS(S/A)L tH(S/A)L tSRR INPUT REG/ INPUT LATCH tSIRS tHIRS tSIL tHIL tSIRZ tHIRZ tSILZ tHILZ tPDILi tICOSi tIGOSi tPDILZi tSLW *emulated Central Switch Matrix IN tPDi Q tPDLi tCO(S/A)i tGO(S/A)i tSRi S/R Q OUT tBUF tEA tER BLK CLK 17466G-025 Figure 15. MACH 4 Timing Model SPEEDLOCKING FOR GUARANTEED FIXED TIMING The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an XOR gate without incurring additional timing delays. The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required by the design. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs easy access to the performance required in today's designs. 24 MACH 4 Family IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACH 4 devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. MACH 4 devices can be programmed across the commercial temperature and voltage range. Vantis provides its free PC-based Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO takes the JEDEC file output produced by Vantis' design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, Lattice/VantisPRO software can output files in formats understood by common automated test equipment. This equpment can then be used to program MACH 4 devices during the testing of a circuit board. For more information about in-system programming, refer to the separate document entitled MACH ISP Manual. PCI COMPLIANT MACH 4(A) devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS Both the 3.3-V and 5-V VCC MACH 4 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixedvoltage design capability. PULL UP OR BUS-FRIENDLY INPUTS AND I/OS All MACH 4 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a MACH 4 Family 25 logic level "1." For the circuit diagram, please refer to the Input/Output Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data Book. All MACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are weakly pulled up. For the circuit diagram, please refer to the Input/Output Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data Book. POWER MANAGEMENT Each individual PAL block in MACH 4 devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. PROGRAMMABLE SLEW RATE Each MACH 4 device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the MACH 4 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. HOT SOCKETING MACH 4A devices are well-suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH devices be minimal on active signals. 26 MACH 4 Family CLK0 CLK1 CLK2 CLK3 M4(LV)-64/32, M4A(3, 5)-64/32 M4A3-384 M4(LV)-192/96, M4(3, 5)-192/96 M4(LV)-96/48, M4A(3, 5)-96/48 M4(LV)-256/128, M4(3, 5)-256/128 M4A3-512 M4(LV)-128/64, M4A(3, 5)-128/64 CLOCK GENERATOR A A B 4 16 17 17 17 18 18 0 M0 C0 MACROCELL M0 M1 C1 M1 MACROCELL M2 MACROCELL M3 C3 OUTPUT SWITCH MATRIX LOGIC ALLOCATOR CENTRAL SWITCH MATRIX M7 M7 MACROCELL M8 MACROCELL M8 M9 MACROCELL M10 MACROCELL M11 MACROCELL M12 MACROCELL C15 89 O4 I/O CELL O5 I/O CELL O6 I/O CELL O7 I/O CELL I/O3 I/O4 I/O5 M12 M13 C14 I/O CELL I/O2 M10 M11 C13 O3 I/O1 M6 MACROCELL M6 M9 C12 I/O CELL MACROCELL M5 C6 C11 O2 I/O0 M4 M5 C10 I/O CELL MACROCELL M4 C5 C9 O1 MACROCELL M3 C4 C8 I/O CELL M2 C2 C7 O0 M13 MACROCELL M14 MACROCELL I/O6 M14 M15 I/O7 MACROCELL M15 B 16 24 INPUT SWITCH MATRIX 16 Figure 16. PAL Block for MACH 4 and MACH 4A with 2:1 Macrocell - I/O Cell Ratio 17466H-40 MACH 4 Family 27 Figure 17. PAL Block for MACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32) 17466H-41 28 MACH 4 Family CLK0/I0 CLK0/I1 CLOCK GENERATOR 16 2 0 M0 M0 MACROCELL M1 MACROCELL M2 MACROCELL M3 MACROCELL M4 MACROCELL C5 M5 MACROCELL C6 M6 MACROCELL M7 MACROCELL M8 MACROCELL M9 MACROCELL M10 MACROCELL M11 MACROCELL M12 MACROCELL M13 MACROCELL M14 MACROCELL M15 MACROCELL C0 O0 I/O CELL O1 I/O CELL O2 I/O CELL O3 I/O CELL O4 I/O CELL O5 I/O CELL O6 I/O CELL O7 I/O CELL O8 I/O CELL O9 I/O CELL O10 I/O CELL O11 I/O CELL O12 I/O CELL O13 I/O CELL M1 C1 M3 C3 M4 C4 C7 C8 M6 LOGIC ALLOCATOR CENTRAL SWITCH MATRIX M5 OUTPUT SWITCH MATRIX M2 C2 M7 M8 M9 C0 M10 M11 C0 C0 M12 M13 C0 C0 OUTPUT SWITCH MATRIX C0 M14 O14 I/O CELL O15 I/O CELL M15 C0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 97 17 16 32 INPUT SWITCH MATRIX 16 Figure 18. PAL Block for M4(LV)-32/32 and M4A (3,5)-32/32 17466H-042 MACH 4 Family 29 BLOCK DIAGRAM - M4(LV)-32/32 AND M4A(3,5)-32/32 Block A I/O8-I/O15 I/O0-I/O7 8 8 I/O Cells Clock Generator I/O Cells 8 8 8 Output Switch Matrix 8 4 8 8 Output Switch Matrix 8 4 8 8 Macrocells OE 2 8 Input Switch Matrix OE Macrocells Input Switch Matrix 8 66 X 98 AND Logic Array and Logic Allocator 16 16 33 Central Switch Matrix 2 2 33 16 Input Switch Matrix 16 OE 8 2 Input Switch Matrix 66 X 98 AND Logic Array and Logic Allocator OE CLK0/I0, CLK1/I1 8 8 Macrocells Macrocells 8 4 8 8 Output Switch Matrix 8 8 Clock Generator 8 I/O Cells 4 8 8 8 Output Switch Matrix 8 I/O Cells 8 8 I/O16-I/O23 I/O24-I/O31 Block B 17466H-019 30 MACH 4 Family BLOCK DIAGRAM - M4(LV)-64/32 AND M4A(3,5)-64/32 Block A Block D I/O0-I/O7 I/O24-I/O31 8 8 I/O Cells 8 8 Output Switch Matrix 16 4 16 16 8 4 Output Switch Matrix 8 16 4 16 Macrocells OE 16 Input Switch Matrix OE 16 66 X 90 AND Logic Array and Logic Allocator 2 24 33 33 24 Central Switch Matrix 2 2 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 2 33 24 66 X 90 AND Logic Array and Logic Allocator 2 OE OE 16 Macrocells 4 Output Switch Matrix 8 16 Clock Generator 16 8 16 Macrocells 16 4 24 Input Switch Matrix 33 Clock Generator CLK0/I0, CLK1/I1 Macrocells 66 X 90 AND Logic Array and Logic Allocator 2 16 Input Switch Matrix 4 Clock Generator Clock Generator I/O Cells I/O Cells 16 4 16 8 4 Output Switch Matrix 16 8 I/O Cells 8 8 I/O8-I/O15 I/O16-I/O23 Block B Block C 17466H-020 MACH 4 Family 31 4 MACH 4 Family OE OE 4 Block E 8 I/O Cells 8 Output Switch Matrix I/O32-I/O39 4 8 Block D 16 Clock Generator I/O24-I/O31 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 24 16 16 Input Switch Matrix 8 OE 4 24 4 4 4 8 4 4 8 OE 16 Input Switch Matrix 16 OE Macrocells 4 16 16 Central Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 4 Block F I/O40-I/O47 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 I/O Cells 8 I/O0-I/O7 Block A 16 16 24 24 16 16 Input Switch Matrix 4 24 4 4 8 8 OE 16 66 X 90 AND Logic Array and Logic Allocator 33 24 Input Switch Matrix 33 16 16 Clock Generator 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 4 I/O Cells 8 Input Switch Matrix 4 Clock Generator Input Switch Matrix 4 8 8 I/O Cells 8 Block B I/O8-I/O15 Clock Generator 4 4 4 Block C I/O16-I/O23 4 BLOCK DIAGRAM - M4(LV)-96/48 AND M4A(3,5)-96/48 I2, I3, I6, I7 Clock Generator Clock Generator CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 17466G-021 32 33 4 4 Clock Generator OE CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 MACH 4 Family 4 Block F 8 I/O Cells 8 I/O40-I/O47 4 Output Switch Matrix Block E Clock Generator I/O32-I/O39 8 I/O Cells 8 8 16 16 16 Input Switch Matrix 16 OE 4 4 4 8 16 Block G I/O48-I/O55 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 24 16 16 4 4 4 4 4 8 8 OE Output Switch Matrix Input Switch Matrix 16 OE 16 16 4 66 X 90 AND Logic Array and Logic Allocator 33 24 Input Switch Matrix 8 OE Macrocells 24 33 16 16 4 Block A Block H I/O56-I/O63 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 I/O Cells 8 I/O0-I/O7 16 16 24 24 16 16 Input Switch Matrix 4 OE Macrocells 4 66 X 90 AND Logic Array and Logic Allocator 33 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator Central Switch Matrix 24 4 4 8 Output Switch Matrix 8 OE 16 66 X 90 AND Logic Array and Logic Allocator 24 16 4 OE 33 Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 Input Switch Matrix 24 Clock Generator 4 4 8 Output Switch Matrix 8 8 I/O Cells Input Switch Matrix 33 16 16 4 Clock Generator 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 8 I/O Cells Block B I/O8-I/O15 Input Switch Matrix 4 8 8 I/O Cells Block C I/O16-I/O23 Clock Generator 4 4 4 Block D I/O24-I/031 2 BLOCK DIAGRAM - M4(LV)-128N/64, M4(LV)-128/64 AND M4A(3,5)-128/64 I2, I5 Clock Generator Clock Generator Clock Generator 17466H-022 BLOCK DIAGRAM - M4(LV)-192/96 AND M4A(3,5)-192/96 68 X 90 AND Logic Array and Logic Allocator 24 4 Clock Generator 4 Output Switch Matrix 16 16 Macrocells 68 X 90 AND Logic Array and Logic Allocator 24 34 8 Macrocells 16 Input Switch Matrix 16 Input Switch Matrix 16 Macrocells 4 16 OE 16 16 8 I/O Cells 8 4 OE 4 16 4 8 Clock Generator 16 8 Output Switch Matrix OE 4 8 Clock Generator 8 Output Switch Matrix 8 I/O Cells I/O Cells 34 8 4 8 4 16 Macrocells 16 16 68 X 90 AND Logic Array and Logic Allocator 4 24 34 Output Switch Matrix 16 16 16 68 X 90 AND Logic Array and Logic Allocator 4 4 Clock Generator I/O Cells 4 4 8 Block K I/O80-I/O87 OE 8 Block L I/O88-I/O95 CLK0-CLK3 Input Switch Matrix Block A I/O0-I/O7 Input Switch Matrix Block B I/O8-I/O15 24 34 I/O72-I/O79 Block J I/O64-I/O71 Block I Block C I/O16-I/O23 Block D I/O24-I/O31 8 8 8 8 16 16 Output Switch Matrix 8 4 8 4 Output Switch Matrix 8 I/O Cells 8 8 I/O40-I/O47 Block F 8 4 8 4 8 I/O Cells 16 I0-I15 34 8 I/O48-I/O55 Block G 16 16 4 8 4 Input Switch Matrix 16 Macrocells 16 16 24 68 X 90 AND Logic Array and Logic Allocator Input Switch Matrix OE Output Switch Matrix 24 34 4 16 16 68 X 90 AND Logic Array and Logic Allocator 4 16 16 4 16 Macrocells 24 Macrocells 4 Clock Generator Clock Generator 4 Output Switch Matrix 16 OE 4 4 24 68 X 90 AND Logic Array and Logic Allocator Macrocells I/O Cells I/O32-I/O39 Block E OE 34 16 16 Clock Generator 34 68 X 90 AND Logic Array and Logic Allocator 8 16 68 X 90 AND Logic Array and Logic Allocator 34 8 4 16 Input Switch Matrix Input Switch Matrix 16 16 16 34 16 Macrocells Output Switch Matrix Clock Generator 4 4 OE 68 X 90 AND Logic Array and Logic Allocator 8 4 4 I/O Cells 8 4 Macrocells Clock Generator Input Switch Matrix 24 Central Switch Matrix OE 34 16 68 X 90 AND Logic Array and Logic Allocator 24 34 24 16 16 4 Input Switch Matrix 24 Macrocells OE Input Switch Matrix 16 68 X 90 AND Logic Array and Logic Allocator 4 16 16 Macrocells Clock Generator 16 16 OE 4 16 4 8 OE 16 8 Output Switch Matrix Clock Generator 4 8 Clock Generator 8 Output Switch Matrix I/O Cells I/O Cells Input Switch Matrix I/O Cells Output Switch Matrix 16 8 I/O Cells 8 I/O56-I/O63 Block H 17466G-064 MACH 4 Family 34 BLOCK DIAGRAM - M4(LV)-256/128 AND M4A(3,5)-256/128 4 8 I/O Cells 8 8 8 I/O Cells 4 16 16 Output Switch Matrix 8 Input Switch Matrix 16 4 8 4 Clock Generator Clock Generator OE 68 X 90 AND Logic Array and Logic Allocator 4 4 8 I/O Cells 8 8 I/O56-I/O63 Block H 8 4 8 4 Input Switch Matrix Input Switch Matrix Input Switch Matrix Input Switch Matrix Clock Generator OE Output Switch Matrix 8 I/O Cells 14 I0-I13 8 I/O64-I/O71 Block I 24 34 34 24 68 X 90 AND Logic Array and Logic Allocator 4 16 Macrocells 16 16 4 8 4 16 16 68 X 90 AND Logic Array and Logic Allocator 4 16 16 16 Macrocells 16 16 4 Output Switch Matrix 16 16 24 Macrocells 4 8 4 24 68 X 90 AND Logic Array and Logic Allocator Macrocells Output Switch Matrix OE 68 X 90 AND Logic Array and Logic Allocator 34 8 4 16 34 I/O Cells I/O48-I/O55 Block G 16 16 34 16 16 8 4 4 4 I/O Cells Output Switch Matrix 34 16 Macrocells Clock Generator Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator 16 16 24 I/O104-I/O111 Block N I/O96-I/O103 Block M I/O88-I/O95 Block L I/O80-I/O87 Block K 8 4 OE 34 24 8 I/O Cells 8 Macrocells 68 X 90 AND Logic Array and Logic Allocator 24 34 Input Switch Matrix 24 4 16 8 OE OE 68 X 90 AND Logic Array and Logic Allocator 4 16 4 Output Switch Matrix 8 Macrocells OE Input Switch Matrix 16 8 16 16 Macrocells 4 16 8 8 OE 4 8 Output Switch Matrix 16 I/O Cells Clock Generator 8 16 Clock Generator 4 Output Switch Matrix 8 I/O Cells 8 16 4 I/O Cells 8 16 8 16 16 4 I/O Cells Block C I/O16-I/O23 Block D I/O24-I/O31 Block E I/O32-I/O39 Block F I/O40-I/O47 Output Switch Matrix Clock Generator OE 8 16 Input Switch Matrix Output Switch Matrix 16 4 24 Macrocells 16 OE 16 4 4 OE 4 8 16 34 68 X 90 AND Logic Array and Logic Allocator 16 Macrocells Macrocells 24 34 Clock Generator 8 4 16 16 68 X 90 AND Logic Array and Logic Allocator 4 Clock Generator 4 4 16 Macrocells 24 68 X 90 AND Logic Array and Logic Allocator Output Switch Matrix 16 16 Clock Generator 16 34 Clock Generator Output Switch Matrix Input Switch Matrix 16 Macrocells 16 16 34 68 X 90 AND Logic Array and Logic Allocator 8 4 24 34 Central Switch Matrix Input Switch Matrix 16 4 4 8 4 16 68 X 90 AND Logic Array and Logic Allocator 4 34 24 68 X 90 AND Logic Array and Logic Allocator 16 16 OE 34 24 Output Switch Matrix Macrocells 68 X 90 AND Logic Array and Logic Allocator 24 34 Input Switch Matrix 24 4 8 4 Macrocells Clock Generator OE 68 X 90 AND Logic Array and Logic Allocator 4 16 Clock Generator Input Switch Matrix 16 16 16 Macrocells 8 16 OE 16 16 Clock Generator 4 8 I/O Cells 8 4 OE 8 16 4 OE 16 8 Output Switch Matrix Clock Generator 4 Clock Generator 8 Output Switch Matrix 8 I/O Cells I/O Cells Input Switch Matrix I/O Cells 4 4 8 Block O I/O112-I/O119 Input Switch Matrix 8 Block P I/O120-I/O127 CLK0-CLK3 Input Switch Matrix Block A I/O0-I/O7 Block B I/O8-I/O15 Output Switch Matrix 16 8 I/O Cells 8 I/O72-I/O79 Block J 17466G-024 35 MACH 4 Family BLOCK DIAGRAM - M4A3-384/192 Block B I/O8-I/O15 CLK0-CLK3 Block A I/O0-I/O7 Block HX I/O184-I/O191 Block GX I/O176-I/O183 4 8 Output Switch Matrix 4 8 16 16 Output Switch Matrix 4 8 4 8 I/O Cells 8 8 Block G I/O48-I/O55 Block J I/O72-I/O79 Block H I/O56-I/O63 Block I I/O64-I/O71 4 16 Macrocells 16 16 8 Input Switch Matrix 24 Input Switch Matrix Clock Generator 36 72 X 90 AND Logic Array and Logic Allocator OE Output Switch Matrix 4 24 36 16 4 16 16 4 8 Output Switch Matrix 4 16 8 I/O Cells I/O Cells 8 Block D I/O24-I/O31 Block E I/O32-I/O39 OE OE OE Macrocells 16 16 16 72 X 90 AND Logic Array and Logic Allocator 4 16 I/O Cells Block C I/O16-I/O23 Block F I/O40-I/O47 Input Switch Matrix Clock Generator Clock Generator Macrocells 4 Macrocells 24 72 X 90 AND Logic Array and Logic Allocator Output Switch Matrix 16 16 Clock Generator 4 4 Clock Generator 16 36 Central Switch Matrix Input Switch Matrix Input Switch Matrix Macrocells 16 16 36 16 8 4 24 36 72 X 90 AND Logic Array and Logic Allocator 8 4 16 72 X 90 AND Logic Array and Logic Allocator 4 4 16 16 36 OE Input Switch Matrix 4 8 Macrocells 72 X 90 AND Logic Array and Logic Allocator 24 16 Output Switch Matrix 4 OE OE 36 72 X 90 AND Logic Array and Logic Allocator 8 I/O Cells 8 4 Macrocells 24 36 24 4 16 4 Clock Generator Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator 8 16 16 16 16 16 4 Output Switch Matrix OE 4 8 Macrocells 24 8 I/O Cells Clock Generator 8 Clock Generator 4 Output Switch Matrix 16 16 4 I/O Cells 8 16 4 8 I/O Cells Input Switch Matrix 8 Detail A 8 8 I/O168-I/O175 Block FX I/O144-I/O151 Block CX I/O160-I/O167 Block EX I/O152-I/O159 Block DX Repeat Detail A I/O128-I/O135 Block AX I/O120-I/O127 Block P 8 I/O80-I/O87 Block K 4 8 4 Output Switch Matrix 8 4 8 4 OE 8 I/O Cells I/O Cells 8 8 I/O88-I/O95 Block L 36 I/O196-I/O103 Block M 24 72 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 24 36 OE Output Switch Matrix 16 72 X 90 AND Logic Array and Logic Allocator 4 16 16 4 8 4 16 Input Switch Matrix Clock Generator Clock Generator OE OE 8 4 16 16 4 16 16 4 Output Switch Matrix Macrocells 24 Macrocells Macrocells 16 16 Clock Generator OE 36 72 X 90 AND Logic Array and Logic Allocator 4 4 16 Clock Generator 8 I/O Cells 36 4 8 24 36 72 X 90 AND Logic Array and Logic Allocator 8 4 16 72 X 90 AND Logic Array and Logic Allocator 4 Clock Generator Output Switch Matrix Input Switch Matrix 16 4 16 16 36 16 Macrocells 16 16 Input Switch Matrix Input Switch Matrix 16 4 Macrocells 72 X 90 AND Logic Array and Logic Allocator 24 4 Output Switch Matrix 8 OE OE 36 16 4 16 24 36 8 I/O Cells 8 4 Macrocells 16 4 72 X 90 AND Logic Array and Logic Allocator 4 Output Switch Matrix OE Input Switch Matrix 16 72 X 90 AND Logic Array and Logic Allocator 24 16 16 Macrocells 24 8 Clock Generator 4 16 16 Clock Generator 8 Clock Generator 16 4 Output Switch Matrix I/O Cells I/O Cells 8 I/O136-I/O143 Block BX I/O112-I/O119 Block O 8 Input Switch Matrix I/O Cells 8 Input Switch Matrix 8 Input Switch Matrix 8 Output Switch Matrix 16 8 I/O Cells 8 I/O104-I/O111 Block N 17466G-067 MACH 4 Family 36 BLOCK DIAGRAM - M4A3-512/256 Block B I/O8-I/O15 CLK0-CLK3 Block A I/O0-I/O7 Block PX I/O248-I/O255 Block OX I/O240-I/O247 4 8 Output Switch Matrix 4 8 16 16 Output Switch Matrix 4 8 4 8 I/O Cells 8 8 Output Switch Matrix 4 Block G I/O48-I/O55 Block J I/O72-I/O79 Block H I/O56-I/O63 Block I I/O64-I/O71 Block K I/O80-I/O87 Block N I/O104-I/O111 Block L I/O88-I/O95 Block M I/O96-I/O103 16 Macrocells 16 16 8 Input Switch Matrix Clock Generator 4 Input Switch Matrix 24 72 X 90 AND Logic Array and Logic Allocator 16 16 4 8 Output Switch Matrix 4 16 8 I/O Cells I/O Cells 8 Block D I/O24-I/O31 Block E I/O32-I/O39 36 16 4 24 36 OE OE Macrocells 16 16 16 72 X 90 AND Logic Array and Logic Allocator 4 16 I/O Cells Block C I/O16-I/O23 Block F I/O40-I/O47 OE OE 4 Input Switch Matrix Clock Generator Clock Generator Macrocells Macrocells 24 72 X 90 AND Logic Array and Logic Allocator Output Switch Matrix 16 16 Clock Generator 4 4 Clock Generator 16 36 Central Switch Matrix Input Switch Matrix Input Switch Matrix Macrocells 16 16 36 16 8 4 24 36 72 X 90 AND Logic Array and Logic Allocator 8 4 16 72 X 90 AND Logic Array and Logic Allocator 4 4 16 16 36 OE Input Switch Matrix 4 8 Macrocells 72 X 90 AND Logic Array and Logic Allocator 24 16 Output Switch Matrix 4 OE OE 36 72 X 90 AND Logic Array and Logic Allocator 8 I/O Cells 8 4 Macrocells 24 36 24 4 16 4 Clock Generator Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator 8 16 16 16 16 16 4 Output Switch Matrix OE 4 8 Macrocells 24 8 I/O Cells Clock Generator 8 Clock Generator 4 Output Switch Matrix 16 16 4 I/O Cells 8 16 4 8 I/O Cells Input Switch Matrix 8 Detail A 8 8 I/O224-I/O231 Block MX I/O216-I/O223 Block LX I/O232-I/O239 Block NX I/O208-I/O215 Block KX I/O192-I/O199 Block IX I/O184-I/O191 Block HX I/O200-I/O207 Block JX I/O176-I/O183 Block GX Repeat Detail A Repeat Detail A I/O160-I/O167 Block EX I/O152-I/O159 Block DX 8 I/O112-I/O119 Block O 8 4 Output Switch Matrix 8 4 Macrocells 8 4 Output Switch Matrix 8 I/O Cells I/O Cells 8 8 I/O120-I/O127 Block P 36 I/O128-I/O135 Block AX 16 4 16 Macrocells 16 16 4 8 4 Input Switch Matrix 24 72 X 90 AND Logic Array and Logic Allocator 16 16 4 24 36 16 16 16 16 72 X 90 AND Logic Array and Logic Allocator 4 OE OE 4 Output Switch Matrix 16 24 Macrocells 8 4 16 24 72 X 90 AND Logic Array and Logic Allocator Macrocells 4 8 OE OE 36 4 Clock Generator Clock Generator Clock Generator OE 36 16 16 72 X 90 AND Logic Array and Logic Allocator 4 8 4 16 36 72 X 90 AND Logic Array and Logic Allocator 16 16 Clock Generator 8 I/O Cells 4 4 Clock Generator Output Switch Matrix Input Switch Matrix 16 4 36 16 Macrocells 16 16 Input Switch Matrix Input Switch Matrix 16 16 24 4 Output Switch Matrix 8 OE 36 4 Macrocells 72 X 90 AND Logic Array and Logic Allocator I/O Cells 8 Macrocells 24 36 72 X 90 AND Logic Array and Logic Allocator 4 16 4 8 16 OE 72 X 90 AND Logic Array and Logic Allocator 4 Output Switch Matrix OE Input Switch Matrix 16 24 16 16 Macrocells 24 8 Clock Generator 4 16 16 Clock Generator 8 Clock Generator 16 4 Output Switch Matrix I/O Cells I/O Cells 8 8 Input Switch Matrix I/O Cells I/O168-I/O175 Block FX I/O144-I/O151 Block CX 8 Input Switch Matrix 8 Input Switch Matrix 8 Output Switch Matrix 16 8 I/O Cells 8 I/O136-I/O143 Block BX 17466G-068 37 MACH 4 Family ABSOLUTE MAXIMUM RATINGS OPERATING RANGES M4 and M4A5 Commercial (C) Devices Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +70C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55C to +100C Device Junction Temperature . . . . . . . . . . . . . +130C Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = -40C to +85C). . . . . . . 200 mA Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.50 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. 5-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Test Conditions IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL Min Typ Max 2.4 Unit V IOH = 0 mA, VCC = Max, VIN = VIH or VIL 3.3 V Output LOW Voltage IOL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) -10 A IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) 10 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) 2.0 -30 V -10 A -160 mA Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. MACH 4 Family 38 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES M4LV and M4A3 Commercial (C) Devices Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +70C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55C to +100C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V Device Junction Temperature . . . . . . . . . . . . . +130C Industrial (I) Devices Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +4.5 V Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V Latchup Current (TA = -40C to +85C). . . . . . . 200 mA Operating ranges define those limits between which the functionality of the device is guaranteed. Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. 3.3-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol VOH VOL Parameter Description Test Conditions Output HIGH Voltage VCC = Min VIN = VIH or VIL Output LOW Voltage VCC = Min VIN = VIH or VIL (Note 1) Min Typ Max Unit IOH = -100 A VCC - 0.2 V IOH = -3.2 mA 2.4 V IOL = 100 A 0.2 V IOL = 24 mA 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs 2.0 5.5 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs -0.3 0.8 V IIH Input HIGH Leakage Current VIN = 3.6 V, VCC = Max (Note 2) 5 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -5 A IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) 5 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -5 A ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -160 mA -15 Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. 39 MACH 4 Family MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 -7 -10 -12 -14 -15 -18 Min Max Min Max Min Max Min Max Min Max Min Max Unit Combinatorial Delay: tPDi Internal combinatorial propagation delay 5.5 8.0 10.0 12.0 13.0 16.0 ns tPD Combinatorial propagation delay 7.5 10.0 12.0 14.0 15.0 18.0 ns Registered Delays: tSS Synchronous clock setup time, D-type register 5.5 6.0 7.0 10.0 10.0 12.0 ns tSST Synchronous clock setup time, T-type register 6.5 7.0 8.0 11.0 11.0 13.0 ns tSA Asynchronous clock setup time, D-type register 3.5 4.0 5.0 8.0 8.0 10.0 ns tSAT Asynchronous clock setup time, T-type register 4.5 5.0 6.0 9.0 9.0 11.0 ns tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns tHA Asynchronous clock hold time 3.5 4.0 5.0 8.0 8.0 10.0 ns tCOSi Synchronous clock to internal output 3.5 tCOS Synchronous clock to output 5.5 tCOAi Asynchronous clock to internal output 7.5 tCOA Asynchronous clock to output 9.5 12.0 4.5 6.0 8.0 8.0 10.0 ns 6.5 8.0 10.0 10.0 12.0 ns 10.0 12.0 16.0 16.0 18.0 ns 14.0 18.0 18.0 20.0 ns Latched Delays: tSSL Synchronous Latch setup time 6.0 7.0 8.0 10.0 10.0 12.0 ns tSAL Asynchronous Latch setup time 4.0 4.0 5.0 8.0 8.0 10.0 ns tHSL Synchronous Latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns tHAL Asynchronous Latch hold time 4.0 4.0 5.0 8.0 8.0 10.0 ns tPDLi Transparent latch to internal output 8.0 10.0 12.0 15.0 15.0 18.0 ns tPDL Propagation delay through transparent latch to output 10.0 12.0 14.0 17.0 17.0 20.0 ns tGOSi Synchronous Gate to internal output 4.0 5.5 8.0 9.0 9.0 10.0 ns tGOS Synchronous Gate to output 6.0 7.5 10.0 11.0 11.0 12.0 ns tGOAi Asynchronous Gate to internal output 9.0 11.0 14.0 17.0 17.0 20.0 ns tGOA Asynchronous Gate to output 11.0 13.0 16.0 19.0 19.0 22.0 ns Input Register Delays: tSIRS Input register setup time 2.0 tHIRS Input register hold time 3.0 tICOSi Input register clock to internal feedback 2.0 2.0 3.0 3.5 2.0 3.0 4.5 2.0 4.0 6.0 2.0 4.0 6.0 ns 4.0 6.0 ns 6.0 ns Input Latch Delays: tSIL Input latch setup time 2.0 2.0 2.0 tHIL Input latch hold time 3.0 tIGOSi Input latch gate to internal feedback 4.0 4.0 4.0 5.0 5.0 6.0 ns tPDILi Transparent input latch to internal feedback 2.0 2.0 2.0 2.0 2.0 2.0 ns 3.0 2.0 3.0 2.0 4.0 2.0 4.0 ns 4.0 ns Input Register Delays with ZHT Option: tSIRZ Input register setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 ns tHIRZ Input register hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 ns MACH 4 Family 40 MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -7 -10 -12 -14 -15 -18 Min Max Min Max Min Max Min Max Min Max Min Max Unit Input Latch Delays with ZHT Option: tSILZ Input latch setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 ns tHILZ Input latch hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 ns tPDILZi Transparent input latch to internal feedback - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 ns Output Delays: tBUF Output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 ns tSLW Slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 ns tEA Output enable time 9.5 10.0 12.0 15.0 15.0 17.0 ns tER Output disable time 9.5 10.0 12.0 15.0 15.0 17.0 ns 2.5 2.5 2.5 2.5 2.5 2.5 ns 10.0 12.0 14.0 18.0 18.0 20.0 ns 22.0 ns Power Delay: tPL Power-down mode delay adder Reset and Preset Delays: tSRi Asynchronous reset or preset to internal register output tSR Asynchronous reset or preset to register output tSRR Asynchronous reset and preset register recovery time 8.0 8.0 10.0 15.0 15.0 17.0 ns tSRW Asynchronous reset or preset width 10.0 10.0 12.0 15.0 15.0 17.0 ns 12.0 14.0 16.0 20.0 20.0 Clock/LE Width: tWLS Global clock width low 3.0 5.0 6.0 6.0 6.0 7.0 ns tWHS Global clock width high 3.0 5.0 6.0 6.0 6.0 7.0 ns tWLA Product term clock width low 4.0 5.0 8.0 9.0 9.0 10.0 ns tWHA Product term clock width high 4.0 5.0 8.0 9.0 9.0 10.0 ns tGWS Global gate width low (for low transparent) or high (for high transparent) 5.0 5.0 6.0 6.0 6.0 7.0 ns tGWA Product term gate width low (for low transparent) or high (for high transparent) 4.0 5.0 6.0 9.0 9.0 11.0 ns tWIRL Input register clock width low 4.5 5.0 6.0 6.0 6.0 7.0 ns tWIRH Input register clock width high 4.5 5.0 6.0 6.0 6.0 7.0 ns tWIL Input latch gate width 5.0 5.0 6.0 6.0 7.0 ns 41 MACH 4 Family 6.0 MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -7 -10 -12 -14 -15 -18 Min Max Min Max Min Max Min Max Min Max Min Max Unit Frequency: fMAXS fMAXA fMAXI External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) 90.9 80.0 66.7 50.0 50.0 41.7 MHz External feedback, T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOS) 83.3 74.1 62.5 47.6 47.6 40.0 MHz Internal feedback (fCNT), D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi) 111.1 95.2 76.9 55.6 55.6 45.5 MHz Internal feedback (fCNT), T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi) 100.0 87.0 71.4 52.6 52.6 43.5 MHz No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or 153.8 1/(tSST + tHS) 100.0 83.3 83.3 83.3 71.4 MHz External feedback, D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA) 76.9 62.5 52.6 38.5 38.5 33.3 MHz External feedback, T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOA) 71.4 58.8 50.0 37.0 37.0 32.3 MHz Internal feedback (fCNTA), D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOAi) 90.9 71.4 58.8 41.7 41.7 35.7 MHz Internal feedback (fCNTA), T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi) 83.3 66.7 55.6 40.0 40.0 34.5 MHz No feedback2, Min of 1/(tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA) 125.0 100.0 62.5 55.6 55.6 50.0 MHz Maximum input register frequency, Min of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS) 111.0 100.0 83.3 83.3 83.3 71.4 MHz Notes: 1. See "Switching Test Circuit" in the General Information Section of the Vantis 1999 Data Book. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 -5 -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Combinatorial Delay: tPDi Internal combinatorial propagation delay 3.5 4.0 4.0 4.5 5.0 7.0 9.0 11.0 ns tPD Combinatorial propagation delay 5.0 5.5 6.0 6.5 7.5 10.0 12.0 14.0 ns Registered Delays: tSS Synchronous clock setup time, D-type register 3.0 3.5 4.0 4.0 5.5 6.0 7.0 10.0 ns tSST Synchronous clock setup time, T-type register 4.0 4.0 4.5 4.5 6.5 7.0 8.0 11.0 ns tSA Asynchronous clock setup time, D-type register 2.5 2.5 3.0 3.0 3.5 4.0 5.0 8.0 ns tSAT Asynchronous clock setup time, T-type register 3.0 3.0 3.5 3.5 4.5 5.0 6.0 9.0 ns tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns MACH 4 Family 42 MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tHA Asynchronous clock hold time tCOSi Synchronous clock to internal output 2.5 2.5 2.5 2.5 2.5 2.5 3.5 3.5 ns tCOS Synchronous clock to output 4.0 4.0 4.5 4.5 5.0 5.5 6.5 6.5 ns tCOAi Asynchronous clock to internal output 5.0 5.0 5.0 5.0 6.0 8.0 10.0 12.0 ns tCOA Asynchronous clock to output 6.5 6.5 7.0 7.0 8.5 11.0 13.0 15.0 ns 2.5 2.5 3.0 3.0 3.5 4.0 5.0 8.0 ns Latched Delays: tSSL Synchronous latch setup time 4.0 4.0 4.5 4.5 6.0 7.0 8.0 10.0 ns tSAL Asynchronous latch setup time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns tHSL Synchronous latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHAL Asynchronous latch hold time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns tPDLi Transparent latch to internal output 5.5 5.5 6.0 6.0 7.5 9.0 11.0 12.0 ns tPDL Propagation delay through transparent latch to output 7.0 7.0 8.0 8.0 10.0 12.0 14.0 15.0 ns tGOSi Synchronous gate to internal output 3.0 3.0 3.0 3.0 3.5 4.5 7.0 8.0 ns tGOS Synchronous gate to output 4.5 4.5 5.0 5.0 6.0 7.5 10.0 11.0 ns tGOAi Asynchronous gate to internal output 6.0 6.0 6.0 6.0 8.5 10.0 13.0 15.0 ns tGOA Asynchronous gate to output 7.5 7.5 8.0 8.0 11.0 13.0 16.0 18.0 ns Input Register Delays: tSIRS Input register setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns tHIRS Input register hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns tICOSi Input register clock to internal feedback 3.0 3.0 3.0 3.0 3.5 4.5 6.0 6.0 ns Input Latch Delays: tSIL Input latch setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns tHIL Input latch hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns tIGOSi Input latch gate to internal feedback 3.5 3.5 4.0 4.0 4.0 4.0 4.0 5.0 ns tPDILi Transparent input latch to internal feedback 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns MACH 4 Family 43 MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Input Register Delays with ZHT Option: tSIRZ Input register setup time ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns tHIRZ Input register hold time ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns Input Latch Delays with ZHT Option: tSILZ Input latch setup time ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns tHILZ Input latch hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tPDILZi Transparent input latch to internal feedback - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns Output Delays: tBUF Output buffer delay 1.5 1.5 2.0 2.0 2.5 3.0 3.0 3.0 ns tSLW Slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns tEA Output enable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns tER Output disable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns Power Delay: tPL Power-down mode delay adder Reset and Preset Delays: tSRi Asynchronous reset or preset to internal register output 7.5 7.7 8.0 8.0 9.5 11.0 13.0 16.0 ns tSR Asynchronous reset or preset to register output 9.0 9.2 10.0 10.0 12.0 14.0 16.0 19.0 ns tSRR Asynchronous reset and preset register recovery time 7.0 7.0 7.5 7.5 8.0 8.0 10.0 15.0 ns tSRW Asynchronous reset or preset width 7.0 7.0 8.0 8.0 10.0 10.0 12.0 15.0 ns Clock/LE Width: tWLS Global clock width low 2.0 2.0 2.5 2.5 3.0 5.0 6.0 6.0 ns tWHS Global clock width high 2.0 2.0 2.5 2.5 3.0 5.0 6.0 6.0 ns tWLA Product term clock width low 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns tWHA Product term clock width high 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns tGWS Global gate width low (for low transparent) or high (for high transparent) 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns tGWA Product term gate width low (for low transparent) or high (for high transparent) 4.0 4.0 4.5 4.5 5.0 5.0 6.0 9.0 ns tWIRL Input register clock width low 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns 44 MACH 4 Family MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tWIRH Input register clock width high 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns tWIL Input latch gate width 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) 143 133 118 118 95.2 87.0 74.1 60.6 MHz External feedback, T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOS) 125 125 111 111 87.0 80.0 69.0 57.1 MHz Internal feedback (fCNT), D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi) 182 167 154 154 125 100 83.3 74.1 MHz Internal feedback (fCNT), T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi) 154 154 143 143 111 105 87.0 69.0 MHz No feedback2, Min of 1/ (tWLS + tWHS), 1/(tSS + tHS) or 1/(tSST + tHS) 250 250 200 200 154 125 100 83.3 MHz External feedback, D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA) 111 111 100 100 83.3 66.7 55.6 43.5 MHz External feedback, T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOA) 105 105 95.2 95.2 76.9 62.5 52.6 41.7 MHz Internal feedback (fCNTA), D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOAi) 133 133 125 125 105 83.3 66.7 50.0 MHz Internal feedback (fCNTA), T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi) 125 125 118 118 95.2 76.9 62.5 47.6 MHz No feedback2, Min of 1/ (tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA) 167 167 143 143 125 100 62.5 55.6 MHz Maximum input register frequency, Min of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS) 167 167 143 143 125 100 83.3 83.3 MHz Frequency: fMAXS fMAXA fMAXI Notes: 1. See "Switching Test Circuit" in the General Information Section of the Vantis 1999 Data Book. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. MACH 4 Family 45 CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input capacitance VIN=2.0 V 3.3 V or 5 V, 25C, 1 MHz 6 pF CI/O Output capacitance VOUT=2.0V 3.3 V or 5 V, 25C, 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where this parameter may be affected. ICC vs. FREQUENCY These curves represent the typical power consumption for a particular device at system frequency. The selected "typical" pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. VCC = 5 V or 3.3 V, TA = 25 C 350 M4(LV)-256/128 300 M4(LV)-192/96 ICC (mA) 250 200 M4(LV)-128/64 150 M4(LV)-96/48 M4(LV)-64/32 100 M4(LV)-32/32 50 Frequency (MHz) 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 17466G-066 Figure 19. ICC Curves at High Power Mode 17466G-044 46 MACH 4 Family VCC = 5 V or 3.3 V, TA = 25 C 350 300 250 ICC (mA) M4(LV)-256/128 200 M4(LV)-192/96 150 M4(LV)-128/64 M4(LV)-96/48 100 M4(LV)-64/32 M4(LV)-32/32 50 120 110 100 90 80 70 60 50 40 30 20 0 10 0 Frequency (MHz) 17466G-065 Figure 20. ICC Curves at Low Power Mode VCC = 3.3V, TA = 25C M4A3-256/128 (HP) HP: High Power LP: Low Power 300 250 200 M4A3-256/128 (LP) Icc (mA) 150 M4A3-128/64 (HP) 100 M4A3-128/64 (LP) M4A3-32/32 (HP) 50 M4A3-32/32 (LP) 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 Frequency (MHz) Figure 21. MACH 4A Device Dynamic Icc Curves at High and Low Power Modes 17466H-066 MACH 4 Family 47 44-PIN PLCC CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 AND M4A(3,5)-64/32) Top View A5 A6 A7 B7 B6 B5 B4 I/O2 A5 I/O1 A6 I/O0 A7 I/O31 D7 I/O30 D6 I/O29 D5 I/O28 D4 5 4 3 2 VCC A4 6 GND A3 I/O3 A4 M4(LV)-64/32 M4A(3,5)-64/32 I/O4 A3 44-Pin PLCC M4(LV)-64/32 M4A(3,5)-64/32 1 44 43 42 41 40 A2 A2 I/O5 7 39 I/O27 D3 B3 A1 A1 I/O6 8 38 I/O26 D2 B2 37 I/O25 D1 B1 D0 B0 A0 A0 M4(LV)-32/32 M4A(3,5)-32/32 A8 A9 I/O7 9 TDI 10 36 I/O24 CLK0/I0 11 35 TDO GND 12 34 GND TCK 13 33 CLK1/I1 I/O8 14 32 TMS 15 31 I/O23 C0 B8 30 I/O22 C1 B9 29 I/O21 C2 B10 B0 B1 I/O9 A10 B2 I/O10 16 A11 B3 I/O11 17 M4(LV)-32/32 M4A(3,5)-32/32 C6 I/O17 C5 I/O18 C4 I/O19 C3 I/O20 B14 B13 B12 B11 GND B7 I/O15 A15 C7 I/O16 B6 I/O14 A14 B15 B5 I/O13 VCC B4 I/O12 A13 M4(LV)-64/32 M4A(3,5)-64/32 A12 18 19 20 21 22 23 24 25 26 27 28 M4(LV)-64/32 M4A(3,5)-64/32 17466G-026 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select C I/O Cell (0-7) PAL Block (A-D) TDO = Test Data Out 48 7 MACH 4 Family 44-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 AND M4A(3,5)-64/32) Top View A3 A4 A5 A6 A7 B7 B6 B5 B4 D7 D6 D5 D4 M4(LV)-64/32 M4A(3,5)-64/32 44 43 42 41 40 39 38 37 36 35 34 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 M4(LV)-64/32 M4A(3,5)-64/32 A3 A4 A5 A6 A7 44-Pin TQFP A2 A1 A0 M4(LV)-32/32 M4A(3,5)-32/32 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2 B3 B2 B1 B0 M4(LV)-32/32 M4A(3,5)-32/32 B8 B9 B10 B4 B5 B6 B7 C7 C6 C5 C4 C3 A12 A13 A14 A15 B15 B14 B13 B12 B11 M4(LV)-64/32 M4A(3,5)-64/32 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 12 13 14 15 16 17 18 19 20 21 22 A8 A9 A10 A11 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 B0 I/O9 B1 B2 I/O10 B3 I/O11 A2 A1 A0 M4(LV)-64/32 M4A(3,5)-64/32 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select C 7 I/O Cell (0-7) PAL Block (A-D) TDO = Test Data Out MACH 4 Family 49 48-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 AND M4A(3,5)-64/32) Top View A3 A4 A5 A6 A7 B7 B6 B5 B4 D7 D6 D5 D4 M4(LV)-64/32 M4A(3,5)-64/32 48 47 46 45 44 43 42 41 40 39 38 37 I/O4 I/O3 I/O2 I/O1 I/O0 GND NC VCC I/O31 I/O30 I/O29 I/O28 M4(LV)-64/32 M4A(3,5)-64/32 A3 A4 A5 A6 A7 48-Pin TQFP I/O5 I/O6 I/O7 TDI CLK0/I0 NC GND TCK B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 A2 A1 A0 A2 A1 A0 M4(LV)-32/32 M4A(3,5)-32/32 36 35 34 33 32 31 30 29 28 27 26 25 I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND NC CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2 B3 B2 B1 B0 M4(LV)-32/32 M4A(3,5)-32/32 B8 B9 B10 C7 C6 C5 C4 C3 M4(LV)-64/32 M4A(3,5)-64/32 B15 B14 B13 B12 B11 B4 B5 B6 B7 A12 A13 A14 A15 M4(LV)-64/32 M4A(3,5)-64/32 I/O12 I/O13 I/O14 I/O15 VCC NC GND I/O16 I/O17 I/O18 I/O19 I/O20 13 14 15 16 17 18 19 20 21 22 23 24 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 17466G-028 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output VCC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select C 7 I/O Cell (0-7) PAL Block (A-D) TDO = Test Data Out 50 MACH 4 Family 100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-96/48 AND M4A(3,5)-96/48) Top View F7 F6 F5 F4 F3 F2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND NC NC I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I7 VCC GND NC NC I6 NC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 NC NC GND A2 A3 A4 A5 A6 A7 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC TDO NC NC NC I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND VCC I4/CLK2 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 NC NC NC NC F1 F0 E0 E1 E2 E3 E4 E5 E6 E7 D0 D1 17466G-029 D7 D6 D5 D4 D3 D2 C2 C3 C4 C5 C6 C7 GND NC NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I2 NC NC GND VCC I3 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 NC NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC TDI NC NC A1 I/O6 A0 I/O7 B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 I0/CLK0 VCC GND I1/CLK1 B4 I/O12 B5 I/O13 B6 I/O14 B7 I/O15 C0 I/O16 C1 I/O17 NC NC TMS TCK NC PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select C 7 I/O Cell (0-7) PAL Block (A-F) TDO = Test Data Out MACH 4 Family 51 84-PIN PLCC CONNECTION DIAGRAM (M4(LV)-128N/64) Top View H0 H1 H2 H3 H4 H5 H6 H7 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 A7 A6 A5 A4 A3 A2 A1 A0 84-Pin PLCC B7 B6 B5 B4 B3 B2 B1 B0 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 72 14 71 15 70 16 17 69 68 18 67 19 66 20 21 65 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 GND I/O55 G7 I/O54 G6 I/O53 G5 I/O52 G4 I/O51 G3 I/O50 G2 I/O49 G1 I/O48 G0 CLK3/I4 GND VCC CLK2/I3 I/O47 F0 I/O46 F1 I/O45 F2 I/O44 F3 I/O43 F4 I/O42 F5 I/O41 F6 I/O40 F7 E0 E1 E2 E3 E4 E5 E6 E7 D7 D6 D5 D4 D3 D2 D1 D0 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC GND CLK1/I1 C0 I/O16 I/O17 C1 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 GND 17466G-030 Note: Pin-compatible with the MACH131, MACH231, MACH435. PIN DESIGNATIONS CLK/I = Clock or Input C 7 GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage 52 I/O Cell (0-7) PAL Block (A-H) MACH 4 Family 100-PIN PQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64) Top View H0 H1 H2 H3 H4 H5 H6 H7 (82) (81) (80) (79) (78) (77) (76) (75) 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 (73) 76 (72) 75 (71) 74 (70) 73 (69) 72 (68) 71 (67) 70 (66) 69 (65) 68 67 66 65 64 (62) 63 (61) 62 (60) 61 (59) 60 (58) 59 (57) 58 (56) 57 (55) 56 (54) 55 (41) 54 53 52 51 31 (33) 32 (34) 33 (35) 34 (36) 35 (37) 36 (38) 37 (39) 38 (40) 39 40 41 42 43 (45) 44 (46) 45 (47) 46 (48) 47 (49) 48 (50) 49 (51) 50 (52) 1 2 3 4 (83) 5 (12) 6 (13) 7 (14) 8 (15) 9 (16) 10 (17) 11 (18) 12 (19) 13 (20) 14 15 16 17 18 (23) 19 (24) 20 (25) 21 (26) 22 (27) 23 (28) 24 (29) 25 (30) 26 (31) 27 28 29 30 GND GND TD0 TRST G7 I/O55 G6 I/O54 G5 I/O53 G4 I/O52 G3 I/O51 G2 I/O50 G1 I/O49 G0 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 F0 I/O47 F1 I/O46 F2 I/O45 F3 I/O44 F4 I/O43 F5 I/O42 F6 I/O41 F7 I/O40 I2 ENABLE GND GND E0 E1 E2 E3 E4 E5 E6 E7 D7 D6 D5 D4 D3 D2 D1 D0 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 VCC VCC GND GND I1/CLK1 C0 I/O16 C1 I/O17 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 TMS TCK GND GND (10) 100 (9) 99 (8) 98 (7) 97 (6) 96 (5) 95 (4) 94 (3) 93 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 A7 A6 A5 A4 A3 A2 A1 A0 100-Pin PQFP 17466G-031 Note: The numbers in parentheses reflect compatible pin numbers for 84-pin PLCC. PIN DESIGNATIONS I/CLK = Input or Clock GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select C 7 I/O Cell (0-7) PAL Block (A-H) TDO = Test Data Out TRST = Test Reset ENABLE = Program MACH 4 Family 53 100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64) Top View H0 H1 H2 H3 H4 H5 H6 H7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND A7 A6 A5 A4 A3 A2 A1 A0 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND TDO TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND G7 G6 G5 G4 G3 G2 G1 G0 F0 F1 F2 F3 F4 F5 F6 F7 17466G-032 E0 E1 E2 E3 E4 E5 E6 E7 D7 D6 D5 D4 D3 D2 D1 D0 GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND TDI B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 I0/CLK0 VCC GND I1/CLK1 C0 I/O16 C1 I/O17 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 TMS TCK GND PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select C I/O Cell (0-7) PAL Block (A-H) TDO = Test Data Out TRST = Test Reset ENABLE = Program 54 7 MACH 4 Family 144-PIN TQFP CONNECTION DIAGRAM (M4(LV)-192/96 AND M4A(3,5)-192/96) Top View L0 L1 L2 L3 L4 L5 L6 L7 A7 A6 A5 A4 A3 A2 A1 A0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 I1 I0 CLK0 GND VCC CLK3 I15 I14 I13 I/O79 I/O78 I/O77 I/O76 I/O75 I/O74 I/O73 I/O72 GND B7 B6 B5 B4 B3 B2 B1 B0 144-Pin TQFP D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GND TDO NC I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 I12 VCC GND I11 I10 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND VCC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 NC GND K0 K1 K2 K3 K4 K5 K6 K7 J0 J1 J2 J3 J4 J5 J6 J7 I0 I1 I2 I3 I4 I5 I6 I7 H0 H1 H2 H3 H4 H5 H6 H7 G0 G1 G2 G3 G4 G5 G6 G7 F7 F6 F5 F4 F3 F2 F1 F0 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I5 I6 I7 CLK1 GND VCC CLK2 I8 I9 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 VCC GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 E7 E6 E5 E4 E3 E2 E1 E0 GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I2 I3 VCC GND I4 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND VCC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND 17466G-033 PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select C 7 I/O Cell (0-7) PAL Block (A-L) TDO = Test Data Out MACH 4 Family 55 176-PIN TQFP CONNECTION DIAGRAM - M4A3-256/128, M4A3-192/128, M4A3-128/128, AND M4A3-384/132 Top View 1 TDI 2 3 GND TDI TDI I/O C7 I/O17 I/O C6 I/O17 C5 I/O18 I/O C5 C4 I/O19 I/O C4 C3 I/O20 I/O C2 I/O21 C1 C0 GX7 GND GND GND 133 O7 GX6 I/O115 I/O112 134 I/O GX5 O6 GX4 I/O116 I/O113 135 I/O I/O117 O5 GX3 I/O118 I/O I/O114 136 I/O I/O115 137 O4 I/O119 I/O116 138 O3 GX2 I/O120 I/O GX1 I/O121 O2 GX0 I/O122 I/O O1 I/O117 EX7 GND 139 I/O I/O I/O118 140 GND I/O119 141 O0 GND 142 EX6 VCC VCC VCC M4A3-384/132 143 EX5 I/O123 I/O I/O124 I/O I/O120 144 P7 I/O121 145 P6 EX4 I/O125 I/O122 146 I/O EX3 P5 EX2 I/O126 I/O123 147 I/O I/O127 P4 EX1 I/O128 I/O I/O124 148 I/O I/O125 149 P3 I/O129 P2 EX0 I/O130 I/O I/O126 P1 I/O131 HX6 CLK3 150 I/O I/O127 151 P0 GND CLK3 152 I3*(I3) 153 I CLK3 GND GND 154 GND GND 155 GND D0 VCC CLK0 VCC 156 VCC CLK0 157 CLK0 D1 I/O0 I/O0 158 I/O D2 A0 D3 I/O1 I/O1 159 I/O I/O2 A1 D4 I/O3 I/O I/O2 160 I/O I/O3 161 A2 I/O4 I/O4 162 A3 D5 I/O5 I/O D6 I/O6 A4 D7 I/O7 I/O I/O5 A5 VCC 163 I/O I/O6 I/O I/O7 164 VCC VCC 165 A6 B0 166 A7 B1 GND GND 167 GND B2 I/O8 I/O I/O9 I/O I/O8 168 B0 I/O9 169 B1 B3 I/O10 I/O10 170 I/O B4 B2 B5 I/O11 I/O11 171 I/O I/O12 B3 B6 I/O13 I/O I/O12 172 I/O I/O13 173 B4 I/O14 B5 B7 I/O15 I/O I/O14 174 B6 I/O15 175 I/O GND 176 GND GND I/O16 GND I/O16 B7 GND 176-Pin TQFP M4A3-128/128 & M4A3-192/128 M4A3-256/128 132 GND GND GND 131 TDO TDO TDO VCC VCC 130 TRST 4 129 I/O111 N7 I/O I/O114 FX7 I/O18 5 128 I/O110 N6 I/O I/O113 FX6 I/O19 6 127 I/O109 N5 I/O I/O112 FX5 C3 I/O20 7 126 I/O108 N4 I/O I/O111 FX4 I/O C2 I/O21 8 125 I/O107 N3 I/O I/O110 FX3 I/O22 I/O C1 I/O22 9 124 I/O106 N2 I/O I/O109 FX2 I/O23 I/O C0 I/O23 10 123 I/O105 N1 I/O I/O108 FX1 VCC VCC VCC 11 122 I/O104 N0 I/O I/O107 FX0 GND GND GND 12 121 VCC VCC VCC F7 I/O24 I/O D7 I/O24 13 120 GND GND GND F6 I/O25 I/O D6 I/O25 14 119 I/O103 M7 I/O I/O106 CX7 F5 I/O26 I/O D5 I/O26 15 118 I/O102 M6 I/O I/O105 CX6 F4 I/O27 I/O D4 I/O27 16 117 I/O101 M5 I/O I/O104 CX5 F3 I/O28 I/O D3 I/O28 17 116 I/O100 M4 I/O I/O103 CX4 F2 I/O29 I/O D2 I/O29 18 115 I/O99 M3 I/O I/O102 CX3 F1 I/O30 I/O D1 I/O30 19 114 I/O98 M2 I/O I/O101 CX2 F0 I/O31 I/O D0 I/O31 20 113 I/O97 M1 I/O I/O100 CX1 GND GND GND 21 112 I/O96 M0 I/O I/O99 CX0 VCC VCC VCC 22 110 VCC VCC VCC 109 GND GND GND 108 I/O95 L0 I/O I/O97 BX0 107 I/O94 L1 I/O I/O96 BX1 106 I/O93 L2 I/O I/O95 BX2 105 I/O92 L3 I/O I/O94 BX3 104 I/O91 L4 I/O I/O93 BX4 103 I/O90 L5 I/O I/O92 BX5 102 I/O89 L6 I/O I/O91 BX6 L7 I/O I/O90 BX7 C7 C6 RECOMMEND TO TIE TO VCC PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE Clock Ground Input ( ) shows equivalent pin in M4A3-256/128 (208PQFP) Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select C 7 Test Data Out Test Reset I/O Cell (0-7) Program PAL Block (A-HX) = = = = = = = = = = = = 111 I2*(I1) H5 I/O32 G0 I/O33 I/O E0 I/O32 24 G1 I/O34 I/O E1 I/O33 25 G2 I/O35 I/O E2 I/O34 26 G3 I/O36 I/O E3 I/O35 27 G4 I/O37 I/O E4 I/O36 28 G5 I/O38 I/O E5 I/O37 29 G6 I/O39 I/O E6 I/O38 30 G7 I/O40 I/O E7 I/O39 31 GND GND GND 32 101 I/O88 I0*(I4) 23 I I/O98 I DX5 VCC VCC VCC 33 100 GND GND GND J0 I/O41 I/O F0 I/O40 34 99 VCC VCC VCC J1 I/O42 I/O F1 I/O41 35 98 I/O87 K0 I/O I/O89 O0 J2 I/O43 I/O F2 I/O42 36 97 I/O86 K1 I/O I/O88 O1 J3 I/O44 I/O F3 I/O43 37 96 I/O85 K2 I/O I/O87 O2 J4 I/O45 I/O F4 I/O44 38 95 I/O84 K3 I/O I/O86 O3 J5 I/O46 I/O F5 I/O45 39 94 I/O83 K4 I/O I/O85 O4 J6 I/O47 I/O F6 I/O46 40 93 I/O82 K5 I/O I/O84 O5 J7 I/O48 I/O F7 I/O47 41 92 I/O81 K6 I/O I/O83 O6 TMS TMS TMS 42 91 I/O80 K7 I/O I/O82 O7 TCK TCK TCK 43 GND GND GND 44 GND GND 89 GND GND GND 88 ENABLE GND 87 I/O79 90 I/O GND I/O81 GND N7 J7 86 I/O78 J6 I/O80 N6 I/O 85 84 I/O76 I/O77 J5 J4 I/O79 N5 I/O I/O78 N4 I/O 83 I/O75 J3 I/O77 N3 I/O 82 I/O74 J2 I/O76 N2 I/O 81 80 79 GND I/O72 I/O73 J1 J0 I/O GND I/O75 N1 GND I/O74 N0 VCC VCC I/O 78 VCC 77 76 I/O70 I/O71 I7 I/O73 P7 I6 I/O I/O72 P6 I/O 75 I/O69 I5 I/O71 P5 I/O 74 I/O68 I4 I/O70 P4 I/O 73 72 I/O66 I/O67 I3 I2 I/O69 P3 I/O I/O68 P2 I/O 71 I/O65 I1 I/O67 P1 I/O 70 I0 VCC CLK2 VCC CLK2 I/O GND GND I/O66 GND GND I/O66 P0 CLK1 CLK1 I I/O I/O64 I0 L6 I/O64 69 68 VCC CLK2 66 67 GND GND 65 CLK1 I1*(I6) 64 63 I/O63 H0 62 I/O62 H1 I/O63 I1 I/O 61 60 I/O60 I/O61 H2 H3 I/O62 I2 I/O I/O61 I3 I/O 59 I/O59 H4 I/O60 I4 I/O 58 I/O58 H5 I/O59 I5 I/O 57 56 55 VCC I/O56 I/O57 H6 H7 I/O VCC I/O58 I6 VCC I/O57 I7 GND GND I/O 54 GND 53 52 I/O54 I/O55 G0 I/O56 K0 G1 I/O I/O55 K1 I/O 51 I/O53 G2 I/O54 K2 I/O 50 I/O52 G3 I/O53 K3 I/O 49 48 I/O50 I/O51 G4 G5 I/O52 K4 I/O I/O51 K5 I/O 47 I/O49 G6 I/O50 K6 I/O GND 46 I/O GND GND I/O49 K7 G7 I/O48 45 RECOMMEND TO TIE TO GND 17466G-042 56 MACH 4 Family 208-PIN PQFP CONNECTION DIAGRAM - M4A3-256/128, M4A5-256/128, M4-256/128, M4LV-256/128, AND M4A3-384/160 Top View 208-Pin PQFP PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input ( ) shows equivalent pin in M4A3-256/128 (208PQFP) Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select C 7 Test Data Out Test Reset I/O Cell (0-7) Program PAL Block (A-HX) 17466G-044 MACH 4 Family 57 256-BALL BGA CONNECTION DIAGRAM (M4(LV)-256/128 AND M4A(3,5)-256/128) Bottom View 256-Ball BGA PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell (0-7) PAL Block (A-P) 17466G-045 58 MACH 4 Family 256-BALL BGA CONNECTION DIAGRAM - M4A3-384/192 Bottom View 256-Ball BGA PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out C 7 I/O Cell (0-7) PAL Block (A-HX) 17466G-046 MACH 4 Family 59 MACH 4 PRODUCT ORDERING INFORMATION MACH 4 Devices Commercial & Industrial - 3.3V and 5V Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: M4- 256 / 128 -7 Y C FAMILY TYPE M4- = MACH 4 Family (5-V VCC) M4LV- = MACH 4 Family Low Voltage (3.3-V VCC) 48 OPERATING CONDITIONS C = Commercial (0C to +70C) I = Industrial (-40 C to +85 C) MACROCELL DENSITY 32 = 32 Macrocells 128N = 128 Macrocells, Non-ISP 64 = 64 Macrocells 192 = 192 Macrocells 96 = 96 Macrocells 256 = 256 Macrocells 128 = 128 Macrocells I/Os /32 /48 /64 /96 /128 = = = = = PACKAGE TYPE A = Ball Grid Array (BGA) J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP 48 I/Os in 100-pin TQFP 64 I/Os in 84-pin PLCC, 100-pin PQFP or 100-pin TQFP 96 I/Os in 144-pin TQFP 128 I/Os in 208-pin PQFP or 256-ball BGA SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -15 = 15 ns tPD -18 = 18 ns tPD Valid Combinations Valid Combinations M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128 -7, -10, -12, -15 M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128 JC, VC, VC48 JC, VC, VC48 JC, VC, VC48 JC, VC, VC48 VC VC YC, VC YC, VC JC JC VC VC YC, AC YC, AC All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4-256/128-7YC-10YI 60 = 48-pin TQFP for M4(LV)-32/32 or M4(LV)-64/32 -10, -12, -14, -18 JI, VI, VI48 JI, VI, VI48 JI, VI, VI48 JI, VI, VI48 VI VI YI, VI YI, VI JI JI VI VI YI, AI YI, AI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH 4 Family MACH 4A PRODUCT ORDERING INFORMATION MACH 4A Devices Commercial and Industrial - 3.3V and 5V Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: M4A3- 256 / 128 -7 Y FAMILY TYPE M4A3- = MACH 4 Family Low Voltage Advanced Feature (3.3-V VCC) M4A5- = MACH 4 Family Advanced Feature (5-V VCC) MACROCELL DENSITY 32 = 32 Macrocells 64 = 64 Macrocells 96 = 96 Macrocells 128 = 128 Macrocells I/Os /32 /48 /64 /68 /96 /128 = = = = = = /132 /160 /192 /256 = = = = 192 256 384 512 = = = = 192 256 384 512 48 Macrocells Macrocells Macrocells Macrocells 3.3V Commercial Combinations JC, VC, VC48 JC, VC, VC48 VC, FAC VC YC, VC, FAC VC, FAC -5, -55, -6, -65, VC, FAC -7, -10, -12 VC, FAC VC, FAC VC, FAC YC, VC, AC, FAC YC AC VC YC AC VC -65, -7, -10, -12 YC AC AC = 48-pin TQFP for M4A3-32/32 or M4A3-64/32 M4A5-32/32 or M4A5-64/32 OPERATING CONDITIONS C = Commercial (0C to +70C) I = Industrial (-40 C to +85 C) PACKAGE TYPE A = Ball Grid Array (BGA) J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) FA = Fine-pitchBallGridArray0.8mm (fpBGA) 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP 48 I/Os in 100-pin TQFP 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball fpBGA 68 I/Os in 100-pin TQFP or 100-ball fpBGA 96 I/Os in 144-pin TQFP or 144-ball fpBGA 128 I/Os in 176-pin TQFP, 200-ball fpBGA, 208-pin PQFP, or 256-ball BGA 132 I/Os in 176-pin TQFP 160 I/Os in 208-pin PQFP 192 I/Os in 256-ball BGA or 320-ball fpBGA 256 I/Os in 352-ball BGA M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64 M4A3-128/96 M4A3-128/128 M4A3-192/68 M4A3-192/96 M4A3-192/128 M4A3-256/128 M4A3-256/160 M4A3-256/192 M4A3-384/132 M4A3-384/160 M4A3-384/192 M4A3-512/132 M4A3-512/160 M4A3-512/192 M4A3-512/256 C SPEED -5 = -55 = -6 = -65 = -7 = -10 = -12 = -14 = M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64 M4A3-128/96 M4A3-128/128 M4A3-192/68 M4A3-192/96 M4A3-192/128 M4A3-256/128 M4A3-256/160 M4A3-256/192 M4A3-384/132 M4A3-384/160 M4A3-384/192 M4A3-512/132 M4A3-512/160 M4A3-512/192 M4A3-512/256 MACH 4 Family 5.0 ns tPD 5.5 ns tPD 6.0 ns tPD 6.5 ns tPD 7.5 ns tPD 10 ns tPD 12 ns tPD 14 ns tPD 3.3V Industrial Combinations JI, VI, VI48 JI, VI, VI48 VI VI YI, VI VI VI -7, -10, -12, -14 VI VI VI YI, VI, AI YI AI VI YI AI VI -10, -12, -14 YI AI AI 61 M4A5-32/32 M4A5-64/32 M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 5V Commercial Combinations JC, VC, VC48 JC, VC, VC48 -5, -55, -6, -65, VC -7, -10, -12 YC, VC VC -65, -7, -10, -12 YC, VC, AC M4A5-32/32 M4A5-64/32 M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 5V Industrial Combinations JI, VI, VI48 JI, VI, VI48 VI -7, -10, -12, -14 YI, VI VI -10, -12, -14 YI, VI, AI Most MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4A3256/128-7YC-10YI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. Trademarks Copyright (c) 1999 Lattice Semiconductor. All rights reserved. Vantis, the Vantis logo, and combinations thereof, First-Time-Fit, SpeedLocking, Bus-Friendly, DesignDirect, and Lattice/VantisPRO are trademarks, and MACHPRO, MACHXL, and PAL are registered trademarks of Lattice Semiconductor Corporation. Other product names used in this publication are for indentification purposes only and may be trademarks of their respective companies. 62 MACH 4 Family