R1LV1616HSA-I Series Wide Temperature Range Version 16 M SRAM (1-Mword 16-bit / 2-Mword 8-bit) REJ03C0195-0102 Rev. 1.02 Feb.23.2017 Description The R1LV1616HSA-I Series is 16-Mbit static RAM organized 1-Mword 16-bit / 2-Mword 8-bit with embedded ECC. R1LV1616HSA-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48-pin plastic TSOPI for high density surface mounting. Features Single 3.0 V supply: 2.7 V to 3.6 V Fast access time: 45/55 ns (max) Power dissipation: Active: 9 mW/MHz (typ) Standby: 1.5 W (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. 2 chip selection for battery backup Temperature range: 40 to +85C Byte function (x8 mode) available by BYTE# & A-1 Embedded ECC (error checking and correction) for single-bit error correction Rev.1.02, Feb.23.2017, page 1 of 19 R1LV1616HSA-I Series Ordering Information Type No. Access time R1LV1616HSA-4SI 45 ns R1LV1616HSA-5SI 55 ns Rev.1.02, Feb.23.2017, page 2 of 19 Package 48-pin plastic TSOPI R1LV1616HSA-I Series Pin Arrangement 48-pin TSOP A15 1 48 A16 A14 2 47 BYTE# A13 3 46 Vss A12 4 45 I/O15/A-1 A11 5 44 I/O7 A10 6 43 I/O14 A9 7 42 I/O6 A8 8 41 I/O13 A19 9 40 I/O5 NC 10 39 I/O12 WE# 11 38 I/O4 CS2 12 37 Vcc NU 13 36 I/O11 UB# 14 35 I/O3 LB# 15 34 I/O10 A18 16 33 I/O2 A17 17 32 I/O9 A7 18 31 I/O1 A6 19 30 I/O8 A5 20 29 I/O0 A4 21 28 OE# A3 22 27 Vss A2 23 26 CS1# A1 24 25 A0 (Top view) Rev.1.02, Feb.23.2017, page 3 of 19 R1LV1616HSA-I Series Pin Description (TSOP) Pin name Function A0 to A19 Address input (word mode) A-1 to A19 Address input (byte mode) I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 WE# (WE) Write enable OE# (OE) Output enable LB# (LB) Lower byte select UB# (UB) Upper byte select BYTE# (BYTE) Byte enable VCC Power supply VSS Ground NC No connection NU*1 Not used (test mode pin) Note: 1. This pin should be connected to a ground (VSS), or not be connected (open). Rev.1.02, Feb.23.2017, page 4 of 19 R1LV1616HSA-I Series Block Diagram (TSOP) LSB A15 A14 A13 A12 A11 A10 A9 A8 A18 A16 A19 A4 A5 MSB VCC VSS Row decoder I/O0 Memory matrix Input data control 8,192 x 128 x 16 8,192 x 256 x 8 ECC encoder Column I/O ECC decoder Column decoder I/O15 MSB A17 A7 A6 A3 A2 A1 A0 A-1 BYTE# CS2 CS1# LB# UB# WE# Control logic OE# Rev.1.02, Feb.23.2017, page 5 of 19 LSB R1LV1616HSA-I Series Operation Table (TSOP) Byte mode CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 I/O8 to I/O14 I/O15 Operation H L High-Z High-Z High-Z Standby L L High-Z High-Z High-Z Standby L H H L L Dout High-Z A-1 Read L H L L Din High-Z A-1 Write L H H H L High-Z High-Z High-Z Output disable I/O8 to I/O14 I/O15 Operation Note: H: VIH, L: VIL, : VIH or VIL Word mode CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 H H High-Z High-Z High-Z Standby L H High-Z High-Z High-Z Standby H H H High-Z High-Z High-Z Standby L H H L L L H Dout Dout Dout Read L H H L H L H Dout High-Z High-Z Lower byte read L H H L L H H High-Z Dout Dout Upper byte read L H L L L H Din Din Din Write L H L H L H Din High-Z High-Z Lower byte write L H L L H H High-Z Din Din Upper byte write L H H H H High-Z High-Z High-Z Output disable Note: H: VIH, L: VIL, : VIH or VIL Rev.1.02, Feb.23.2017, page 6 of 19 R1LV1616HSA-I Series Absolute Maximum Ratings Parameter Symbol Value VCC 0.5 to +4.6 Power supply voltage relative to VSS 0.5*1 to VCC + Unit V 0.3*2 Terminal voltage on any pin relative to VSS VT V Power dissipation PT 1.0 Storage temperature range Tstg 55 to +125 C Storage temperature range under bias Tbias 40 to +85 C W Notes: 1. VT min: 2.0 V for pulse half-width 10 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Supply voltage Symbol Min Typ Max Unit VCC 2.7 3.0 3.6 V VSS 0 0 0 V Note Input high voltage VIH 2.2 VCC + 0.3 V Input low voltage VIL 0.3 0.6 V 1 Ambient temperature range Ta 40 +85 C Note: 1. VIL min: Rev.1.02, 2.0 V for pulse half-width 10 ns. Feb.23.2017, page 7 of 19 R1LV1616HSA-I Series DC Characteristics Parameter Unit Test conditions*2 Symbol Min Typ Max Input leakage current |ILI| 1 A Vin = VSS to VCC Output leakage current |ILO| 1 A CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Operating current ICC 20 mA CS1# = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA ICC1 (READ) 22*1 35 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL ICC1 30*1 50 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL ICC2*3 (READ) 3*1 8 mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL Address increment scan or decrement scan ICC2*3 20*1 30 mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Address increment scan or decrement scan ICC3 3*1 8 mA Cycle time = 1 s, duty = 100%, II/O = 0 mA, CS1# 0.2 V, CS2 VCC 0.2 V VIH VCC 0.2 V, VIL 0.2 V Standby current ISB 0.1*1 0.5 Standby current ISB1 0.5*1 8 A 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1# VCC 0.2 V, CS2 VCC 0.2 V or (3) LB# = UB# VCC 0.2 V, CS2 VCC 0.2 V, CS1# 0.2 V Average value Output high voltage VOH 2.4 V IOH = 1 mA VOH VCC V IOH = 100 A Average operating current mA CS2 = VIL 0.2 Output low voltage Rev.1.02, Feb.23.2017, VOL 0.4 V IOL = 2 mA VOL 0.2 V IOL = 100 A page 8 of 19 R1LV1616HSA-I Series Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. BYTE# VCC 0.2 V or BYTE# 0.2 V 3. ICC2 is the value measured while the valid address is increasing or decreasing by one bit. Word mode: LSB (least significant bit) is A0. Byte mode: LSB (least significant bit) is A-1. Capacitance (Ta = +25C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.1.02, Feb.23.2017, page 9 of 19 R1LV1616HSA-I Series AC Characteristics (Ta = 40 to +85C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions Input pulse levels: VIL = 0.4 V, VIH = 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.4 V Output load: See figures (Including scope and jig) 1.4V RL = 500 Dout 50 pF Rev.1.02, Feb.23.2017, page 10 of 19 R1LV1616HSA-I Series Read Cycle R1LV1616HSA-I -4SI Parameter -5SI Symbol Min Max Min Max Unit Read cycle time tRC 45 55 ns Address access time tAA 45 55 ns tACS1 45 55 ns tACS2 45 55 ns Chip select access time Notes Output enable to output valid tOE 30 35 ns Output hold from address change tOH 10 10 ns LB#, UB# access time tBA 45 55 ns tCLZ1 10 10 ns 2, 3 Chip select to output in low-Z tCLZ2 10 10 ns 2, 3 LB#, UB# enable to low-Z tBLZ 5 5 ns 2, 3 Output enable to output in low-Z tOLZ 5 5 ns 2, 3 Chip deselect to output in high-Z tCHZ1 0 20 0 20 ns 1, 2, 3 tCHZ2 0 20 0 20 ns 1, 2, 3 LB#, UB# disable to high-Z tBHZ 0 15 0 20 ns 1, 2, 3 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2, 3 Notes Write Cycle R1LV1616HSA-I -4SI Parameter Symbol -5SI Min Max Min Max Unit Write cycle time tWC 45 55 ns Address valid to end of write tAW 45 50 ns Chip selection to end of write tCW 45 50 ns 5 Write pulse width tWP 35 40 ns 4 LB#, UB# valid to end of write tBW 45 50 ns Address setup time tAS 0 0 ns 6 Write recovery time tWR 0 0 ns 7 Data to write time overlap tDW 25 25 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2 Write to output in high-Z tWHZ 0 15 0 20 ns 1, 2 Rev.1.02, Feb.23.2017, page 11 of 19 R1LV1616HSA-I Series Byte Control R1LV1616HSA-I -4SI Parameter -5SI Symbol Min Max Min Max Unit BYTE# setup time tBS 5 5 ms BYTE# recovery time tBR 5 5 ms Notes Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Rev.1.02, Feb.23.2017, page 12 of 19 R1LV1616HSA-I Series Timing Waveform Read Cycle*1 t RC Address*2 Valid address tAA tACS1 CS1# tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 tCHZ2 tBHZ tBA LB#, UB# tBLZ tOHZ tOE OE# tOLZ High impedance Dout*3 Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.02, Feb.23.2017, page 13 of 19 tOH Valid data R1LV1616HSA-I Series Write Cycle (1)*1 (WE# Clock) tWC Valid address Address*2 tWR tCW CS1# tCW CS2 tBW LB#, UB# tAW tWP tAS WE# tDW tDH Valid data Din*3 tWHZ tOW High impedance Dout*3 Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.02, Feb.23.2017, page 14 of 19 R1LV1616HSA-I Series Write Cycle (2)*1 (CS1#, CS2 Clock, OE# = VIH) tWC Valid address Address*2 tAW tAS tCW tAS tCW tWR CS1# CS2 tBW LB#, UB# tWP WE# tDW Din*3 Valid data High impedance Dout*3 Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.02, Feb.23.2017, page 15 of 19 tDH R1LV1616HSA-I Series Write Cycle (3)*1 (LB#, UB# Clock, OE# = VIH) tWC Valid address Address tAW tCW tWR CS1# tCW CS2 tAS tBW UB# (LB#) tBW LB# (UB#) tWP WE# tDW Din-UB (Din-LB) Valid data tDW Din-LB (Din-UB) Valid data High impedance Dout Note: 1. BYTE# > VCC - 0.2 V Rev.1.02, tDH Feb.23.2017, page 16 of 19 tDH R1LV1616HSA-I Series Byte Control (TSOP) CS2 CS1# tBS BYTE# Rev.1.02, Feb.23.2017, page 17 of 19 tBR R1LV1616HSA-I Series Low VCC Data Retention Characteristics (Ta = 40 to +85C) Parameter Test conditions*2, 3 Symbol Min Typ Max Unit VCC for data retention VDR 1.5 3.6 V Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC 0.2 V, CS1# VCC 0.2 V or (3) LB# = UB# VCC 0.2 V, CS2 VCC 0.2 V, CS1# 0.2 V Data retention current ICCDR 0.5*1 8 A VCC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC 0.2 V, CS1# VCC 0.2 V or (3) LB# = UB# VCC 0.2 V, CS2 VCC 0.2 V, CS1# 0.2 V Average value Chip deselect to data retention time tCDR 0 ns See retention waveforms tR 5 ms Operation recovery time Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. BYTE# VCC 0.2 V or BYTE# 0.2 V 3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 VCC 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. Rev.1.02, Feb.23.2017, page 18 of 19 R1LV1616HSA-I Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) Data retention mode t CDR tR V CC 2.7 V 2.2 V V DR CS1# 0V CS1# VCC - 0.2 V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode tR V CC 2.7 V CS2 V DR 0.6 V 0 V < CS2 < 0.2 V 0V Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled) t CDR Data retention mode V CC 2.7 V 2.2 V V DR LB#, UB# V CC - 0.2 V LB#, UB# 0V Rev.1.02, Feb.23.2017, page 19 of 19 tR Revision History Rev. R1LV1616HSA-I Series Data Sheet Date Contents of Modification Page Description 1.00 Apr.22.2004 1.01 Nov.18.2004 Addition of 2-Mword x 8-bit function 1.02 Feb.23.2017 p.1,p.5 Disclosed embedded ECC features p.2 Initial issue Deleted previous package code (48P3R-B) All trademarks and registered trademarks are the property of their respective owners. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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