GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: June 2004 Document No. 522 - 41 - 08
DATA SHEET
GS9035A
FEATURES
• adjustment-free operation
• auto-rate selection for 5 SMPTE data rates: 143, 177,
270, 360, 540Mb/s
• data rate i nd ication output
• serial data outp ut mute when PLL is not locked
• immune to harmonic locking
• operation independent of SAV/EAV sync signals
• low jitter, low power
• single external VCO resistor for operation with five
input data rates
• large input jitter tolerance: typically 0.45 UI beyond
loop bandwidth
• power savings mode (output serial clock disable)
• system friendly: serial c loc k remai ns active when data
outputs muted
• robust lock detect
• Pb-free an d Gr ee n
APPLICATIONS
The GS9035A is used for Clock and Data recovery, and
Jitter elimination for all high speed serial digital interface
applications involving SMPTE 259M and other data
standards.
DESCRIPTION
The GS9035A is a high performance clock and data
recovery IC designed for serial digital data. The GS9035A
receives either single-ended or differential PECL data and
outputs differential PECL clock and retimed data signals.
The GS9035A can operate in either auto or manual rate
selection mode. In auto mode the GS9035A is ideal for
multi-rate serial data protocols such as SMPTE 259M. In this
mode the GS9035A automatically detects and locks onto
the incoming data signal. For single rate data systems, the
GS9035A can be configured to operate in manual mode. In
both modes, the GS9035A requires only one external
resistor to set the VCO centre frequency and provides
adjustment-free operation.
The GS9035A has dedicated pins to indicate LOCK and
data rate. In addition, an internal muting function forces the
serial data outputs to a static state when input data is not
present or when the PLL is not locked. The serial clock
outputs can also be disabled resulting in a 10% power
savings.
The GS9035A is packaged in a 28 pin PLCC and operates
from a single +5 or -5 volt power supply.
BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER PACKAGE TEMPERATURE Pb-FREE AND GREEN
GS9035ACPJ 28 pin PLCC 0°C to 70°C No
GS9035ACTJ 28 pin PLCC Tape 0°C to 70°C No
GS9035ACPJE3 28 pin PLCC 0°C to 70°C Yes
GS9035ACTJE3 28 pin PLCC Tape 0°C to 70°C Yes
DDI/DDI
LF+ LFS LF- CBG RVCO
CARRIER DETECT
PHASELOCK
HARMONIC
FREQUENCY
ACQUISITION
VCO
DIVISION 3 BIT
COUNTER
LOCK
SDO
SDO
CLK_EN
SCO
SCO
SMPTE
AUTO/MAN
SSO
SS1
SS2
2
PHASE
DETECTOR
CHARGE
PUMP DECODER
LOGIC
COSC
GENLINX ™II GS9035A
Serial Digital Reclocker
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GS9035A
ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE
Supply Voltage (VS) 5.5V
Input Voltage Range (any input) VCC + 0.5 to VEE - 0.5V
Operating Temperature Range 0°C ≤ TA ≤ 70°C
Storage Temperature Range -65°C ≤ TS ≤ 150°C
Lead Temperature (soldering, 10 sec) 260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF.
PARAMETER CONDITION MIN TYPICAL1MAX UNITS NOTES TEST
LEVEL
Supply Voltage 4.75 5.00 5.25 V 3
Supply Current CLK_EN = 0 - 90 110 mA 3
CLK_EN = 1 - 105 120 mA 3
DDI/DDI Common Mode Input
Voltage Range
VEE + (VDIFF/2) 0.4 to 4.6 VCC - (VDIFF/2) V 2 3
DDI/DDI Differential Input
Drive
200 800 2000 mV 3
AUTO/MAN, SMPTE High 2.0 - - V 3
Low - - 0.8
CLK_EN Input Voltage High 2.5 - - V 3
Low - - 0.8
LOCK Output Low Voltage ΙOH = 500µA - 0.25 0.4 V 3 1
SS{2:0} Output Voltage HIGH, ΙOH = -180µA,
Auto Mode
4.4 4.8 - V 1
LOW, ΙOL = 600µA,
Auto Mode
-0.30.4
SS{2:0} Input Voltage HIGH, Manual Mode 2 - - V 3
LOW, ManualMode - - 0.8
CLK_EN Source Current Low, VIL = 0V - 26 55 µA 1
NOTES
1. TYPICAL - measured on EB-RD35A board.
2. VDIFF is the differential input signal swing.
3. LOCK is an open collector output and requires an
external pull-up resistor.
4. Pins SS[2:0] are outputs in AUTO mode and inputs in
MANUAL mode.
TEST LEVELS
1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges
using correlated test.
3. Production test at room temperature and nominal supply
voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
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GS9035A
AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER CONDITION MIN TYPICAL1MAX UNITS NOTES TEST
LEVEL
Serial Data Rate SDI 143 - 540 Mb/s 3
Intrinsic Jitter
Psuedorandom (223 - 1)
270Mb/s - 185 See Figure 6 ps p-p 2 4
540Mb/s - 164
Intrinsic Jitter
Pathological
(SDI checkfield)
270Mb/s - 462 See Figure 7 ps p-p 2 3
360Mb/s - 308
540Mb/s - 260
Input Jitter Tolerance 270Mb/s 0.40 0.56 - UI p-p 3 9
540Mb/s 0.35 0.43 -
Lock Time Synchronous
Switch
tSWITCH < 0.5µs, 270Mb/s - 1 - µs 4 7
0.5µs < tSWITCH < 10ms - 1 - ms
tSWITCH > 10ms - 4 - ms
Lock Time
Asynchronous Switch
Loop Bandwidth = 6MHz at 540 Mb/s - 10 - ms 5 7
SDO MUTE Time 0.5 1 2 µs 6 7
SDO to SCO
Synchronization
-200 0 200 ps 7
SDO, SCO Output Signal
Swing
75Ω DC load 600 800 1000 mV p-p 1
SDO, SCO Rise and Fall
Times
20% - 80% 200 300 400 ps 7
NOTES
1. TYPICAL - measured on EB-RD35A board, TA = 25°C.
2. Characterized 6 sigma rms.
3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz).
4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie: line 10
switching for component NTSC).
5. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate.
6. SDO MUTE Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed.
TEST LEVEL
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test
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GS9035A
Fig. 1 Jitter Measurement Test Setup
PIN CONNECTIONS
PIN DESCRIPTIONS
NUMBER SYMBOL TYPE DESCRIPTION
1,7,8,11,27 VEE I Most negative power supply connection.
2 COSC I Timing control capacitor for internal system clock.
3 LOCK O Lock indication. When HIGH, the GS9035A is locked. LOCK is an open collector output and
requires an external 10k pullup resistor.
4 SMPTE I SMPTE/Other rate select.
5, 6 DDI/DDI I Digital data input (Differential ECL/PECL).
9V
CC1 I Most positive power supply connection.
10 AUTO/MAN I Auto or Manual mode select. TTL/CMOS compatible input.
12 LF+ I Loop filter component connection.
13 LFS I Loop filter component connection.
14 LF- I Loop filter component connection.
15 RVCO_RTN I RVCO return.
PATTERN 223-1
CLK DATA
DI
DI SDO
CH-1 TRIG
TEKTRONIX
GIGABERT 1400 GENNUM
TEST BOARD TEKTRONIX
CSA803
DDI
DDI
VEE
VEE
VCC1
AUTO/MAN
VEE
SDO
SDO
SCO
SCO
SSO
SS1
SS2
SMPTE
LOCK
COSC
VEE
CLK_EN
VEE
VCC3
GS9035A
TOP VIEW
LF+
LFS
LF-
RVCO_RTN
RVCO
CBG
VCC2
25
24
23
22
21
20
19
5
6
7
8
9
10
1112 13 14 15 16 17 18
4 3 2 1 28 27 26
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GS9035A
TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25°C unless otherwise shown.)
Fig. 2 Intrinsic Jitter (223-1 Pattern) 30Mb/s
Fig. 3 Intrinsic Jitter (223-1 Pattern) 143Mb/s
Fig. 4 Intrinsic Jitter (223-1 Pattern) 270Mb/s
Fig. 5 Intrinsic Jitter (223-1 Pattern) 540Mb/s
16 RVCO I Frequency setting resistor.
17 CBG I Internal bandgap voltage filter capacitor.
18 VCC2 I Most positive power supply connection.
19 - 21 SS[2:0] I/O Data rate indication (Auto mode) or data rate select (Manual mode). TTL/CMOS compatible I/O. In
auto mode these pins can be left unconnected.
22, 23 SCO/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω
pullup resistors.
24, 25 SDO/SDO O Serial data output. SDO/SDO are differential current mode outputs and require external 75Ω pullup
resistors.
26 VCC3 I Most positive power supply connection.
28 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled.
PIN DESCRIPTIONS (continued)
NUMBER SYMBOL TYPE DESCRIPTION
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GS9035A
Fig. 6 Intrin sic Jitter - Pseudorandom (223 -1)
Fig. 7 Intrinsic Jitter - Pathological SDI Checkfield
Fig. 8 Typical Input Jitter Tolerance (Characterized)
Fig. 9 Typical IJT vs. Temperatu re (VCC=5.0 V) (Character ized)
DETAILED DESCRIPTION
The GS9035A receives either a single-ended or differential
PECL serial data stream at the DDI and DDI inputs. It locks
an internal clock to the incoming data and outputs the
differential PECL retimed data signal and recovered clock
on outputs SDO/SDO and SCO/SCO respectively. The
timing between the input, output, and clock signals is
shown below.
Fig. 10 Input/Output Clock Signal Timing
The GS9035A reclocker contains four main functional
blocks: the Phase Locked Loop, Auto/Manual Data Rate
Select, Frequency Acquisition, and Logic Circuit.
1. PHASE LOCKED LOOP (PLL)
The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.
0
200
400
600
800
1000
1200
1400
1600
1800
2000
100 200 300 400 500 600
SDI DATA RATE (Mb/s)
JITTER (ps)
Max
Typical
Min
TA=0 to 70˚C, VCC=4.75 to 5.25V for the typical range
Typical Range, Characterized
0
200
400
600
800
1000
1200
1400
1600
1800
2000
100 200 300 400 500 600
SDI DATA RATE (Mb/s)
Typical
Min
JITTER (ps p-p)
Max
TA = 0 to 70˚C, VCC = 4.75 to 5.25V for the typical range
Typical Range, Characterized
0
0.1
0.2
0.3
0.4
0.5
0.6
100 200 300 400 500 600
DATA RATE (Mb/s)
IJT (UI)
T
A
= 0 to 70˚C, V
CC
= 4.75 to 5.25V
0.200
0.250
0.300
0.350
0.400
0.450
0.500
0.550
0.600
0 10203040506070
TEMPERATURE (C˚)
IJT (UI)
143Mb/s
177Mb/s
270Mb/s
360Mb/s
540Mb/s
DDI
SDO
SCO 50%
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GS9035A
Fig. 11 Simplified Diagram of the PLL
1.1 VCO
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO center frequency. The VCO
operates between 30 and 540Mb/s and has a pull range of
-13 +25% about the center frequency depending on the
signal data rate. A single low impedance external resistor,
RVCO, sets the VCO center frequency (see Figure 12). The
low impedance RVCO minimizes thermal noise and reduces
the PLL's sensitivity to PCB noise.
For a given RVCO value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO center
frequency corresponds to the ƒL curve. For all other
SMPTE/SS0 combinations, the VCO center frequency
corresponds to the ƒH curve (ƒH is approximately 1.5 x ƒL).
Fig. 12 VCO Frequency vs. RVCO
The recommended RVCO value for auto rate SMPTE 259M
applications is 365Ω.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 540Mb/s. The divider modulus is set
by the AUTO/MAN, SMPTE, and SS[2:0] pin (see
Auto/Manual Data Rate Select section for further details). In
addition, a manually selectable modulus 8 divider allows
operation at data rates as low as 30Mb/s.
When the input data stream is removed for an excessive
period of time (see AC electrical characteristics table), the
VCO frequency can drift from the previously locked
frequency up to the maximum shown in Table 1.
1.2 Phase Detector
The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function between the input phase
and output timing pulses maximizing the input jitter
tolerance of the PLL.
1.3 Charge Pump
The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design ensures that the output phase does not drift when
data transitions are sparse. This makes the GS9035A ideal
for SMPTE 259M applications where pathological signals
have data transition densities of 0.05.
1.4 Loop Filter
The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential giving the GS9035A increased immunity
to PCB board noise.
The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in the PLL Design
Guidelines section. Recommended values for SMPTE 259M
applications are shown in the Typical Application Circuit
diagram.
DDI/DDI
LF+ LFS LF- RVCO
VCO
DIVISION
RLF CLF1
CLF2
2PHASE
DETECTOR
INTERNAL
PLL CLOCK
CHARGE
PUMP
LOOP
FILTER
0
100
200
300
400
500
600
700
800
0 200 400 600 800 1000 1200 1400 1600 1800
VCO FREQUENCY (MHz)
R
VCO
(Ω)
ƒH
ƒL
SMPTE=1
SSO=1
TABLE 1: Frequency Drift Range (when PLL loses lock)
LOSES LOCK FROM MIN (%) MAX(%)
143Mb/s lock -21 21
177Mb/s lock -12 26
270Mb/s lock -13 28
360 Mb/s lock -13 24
540 Mb/s lock -13 28
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GS9035A
2. FREQUENCY ACQUISITION
The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock to data rates outside of the capture range,
the GS9035A uses a frequency acquisition circuit.
The frequency acquisition circuit sweeps the VCO control
voltage such that the VCO frequency changes from -10% to
+10% of the center frequency. Figure 13 shows a typical
sweep waveform.
Fig. 13 Typical Sweep For m
The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The system is
designed such that the probability of locking within one
cycle period is greater than 0.999. If the system does not
lock within one cycle period, it will attempt to lock in the
subsequent cycle. In manual mode, the divider modulus is
fixed for all cycles. In auto mode, each subsequent cycle is
based on a different divider moduli as determined by the
internal 3-bit counter.
The average sweep time, tswp, is determined by the loop
filter component, CLF1, and the charge pump current, ΙCP:
The nominal sweep time is approximately 121µs when
CLF1 = 15nF and ΙCP = 165µA (RVCO = 365Ω).
An internal system clock determines tsys (see section 7,
Logic Circuit).
3. LOGIC CIRCUIT
The GS9035A is controlled by a finite state logic circuit which
is clocked by an asynchronous system clock. That is, the
system clock is completely independent of the incoming data
rate. The system clock runs at low frequencies, relative to the
incoming data rate, and thus reduces interference to the PLL.
The period of the system clock is set by the COSC capacitor
and is
tsys = 9.6 x 104 x COSC [seconds]
The recommended value for tsys is 450µs (COSC = 4.7nF).
4. AUTO/MANUAL DATA RATE SELECT
The GS9035A can operate in either auto or manual data
rate select mode. The mode of operation is selected by a
single input pin (AUTO/MAN).
4.1 Auto Mode (AUTO/MAN = 1)
In auto mode, the GS9035A uses a 3-bit counter to
automatically cycle through five (SMPTE=1) or three
(SMPTE=0) different divider moduli as it attempts to acquire
lock. In this mode, the SS[2:0] pins are outputs and indicate
the current value of the divider moduli according to Table 2.
Note that for SMPTE = 0 and divider moduli of 2 and 4, the
PLL can correctly lock for two values of SS[2:0].
4.2 Manual Mode (AUTO/MAN = 0)
In manual mode, the GS9035A divider moduli is fixed. In
this mode, the SS[2:0] pins are inputs and set the divider
moduli according to Table 3.
V
LF
t
swp
T
cycle
T
cycle
= t
swp
+ t
sys
t
sys
A
t
swp = 4
3
C
Ι[seconds]
LF1
LF1
TABLE 2: Data Rate Indication in Auto Mode
AUTO/MAN = 1 (Auto Mode)
ƒH, ƒL = VCO center frequency as per Figure 12
SMPTE SS[2:0] DIVIDER
MODULI PLL CLOCK
10004ƒ
H/4
10012ƒ
L/2
10102ƒ
H/2
10111 ƒ
L
11001 ƒ
H
1101- -
1110- -
1111- -
00004ƒ
H/4
00014ƒ
H/4
00102ƒ
H/2
00112ƒ
H/2
01001 ƒ
H
0101- -
0110- -
0111- -
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GS9035A
5. LOCKING
The GS9035A indicates lock when three conditions are
satisfied:
1. Input data is detected.
2. The incoming data signal and the PLL clock are phase
locked.
3. The system is not locked to a harmonic.
The GS9035A defines the presence of input data when at
least one data transition occurs every 1µs.
The GS9035A assumes that it is NOT locked to a harmonic
if the pattern ‘101’ or ‘010’ (in the reclocked data stream)
occurs at least once every tsys/3 seconds. Using the
recommended component values, this corresponds to
approximately 150µs. (In an harmonically locked system, all
bit cells are double clocked and the above patterns
become ‘110011’ and ‘001100’, respectively.)
5.1 Lock Time
The lock time of the GS9035A depends on whether the
input data is switching synchronously or asynchronously.
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase). Asynchronous
switching refers to the case where the input data to the
GS9035A is changed from one source to another source
which is at a different data rate.
When input data to the GS9035A is removed, the GS9035A
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9035A begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9035A locks
very quickly. The nominal lock time depends on the
switching time and is summarized in the table below:
In asynchronous switching applications (including power
up) the lock time is determined by the frequency acquisition
circuit as described in section 2, Frequency Acquisition. In
manual mode, the frequency acquisition circuit may have to
sweep over an entire cycle (depending on initial conditions)
to acquire lock resulting in a maximum lock time of 2Tcycle +
2tsys. In auto tune mode, the maximum lock time is 6Tcycle +
2tsys since the frequency acquisition circuit may have to
cycle through 5 possible counter states (depending on
initial conditions) to acquire lock. The nominal value of Tcycle
for the GS9035A operating in a typical SMPTE 259M
application is approximately 1.3ms.
The GS9035A has a dedicated LOCK output (pin 3)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5µs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
5.2 DVB-ASI
Design Note: For DVB-ASI applications having significant
instances of few bit transitions or when only K28.5 idle bits
are transmitted, the wide-band PLL in the GS9035A may
lock at 243MHz being the first 27MHz sideband below
270MHz. In this case, when normal bit density signals are
transmitted, the PLL will correctly lock onto the proper
270MHz carrier.
TABLE 3: Data Rate Select in Manual Mode
AUTO/MAN = 0 (Manual Mode)
ƒH, ƒL = VCO center frequency as per Figure 8
SMPTE SS[2:0] DIVIDER
MODULI PLL CLOCK
1 000 4 ƒH/4
1 001 2 ƒL/2
1 010 2 ƒH/2
1 011 1 ƒL
1 100 1 ƒH
1 101 8 ƒL/8
1 110 8 ƒH/8
1 111 - -
0 000 4 ƒH/4
0 001 4 ƒH/4
0 010 2 ƒH/2
0 011 2 ƒH/2
0 100 1 ƒH
0 101 1 ƒH
0 110 8 ƒH/8
0 111 - -
TABLE 4: Lock Time Relative to Switching Time
SWITCHING TIME LOCK TIME
<0.5µs 10µs
0.5µs - 10ms 2tsys
> 10ms 2Tcycle + 2tsys
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GS9035A
6. OUTPUT DATA MUTING
The GS9035A internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data. The output data muting timing is
shown in Figure 14.
Fig. 14 Output Data Muting Timing
7. CLOCK ENABLE
When CLK_EN is high, the GS9035A SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
set to a high Z state and float to VCC. Disabling the clock
outputs results in a power savings of 10%. It is
recommended that the CLK_EN input be hard wired to the
desired state. For applications which do not require the
clock output, connect CLK_EN to Ground and connect the
SCO/SCO outputs to VCC.
8. STRESSFUL DATA PATTERNS
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of zeros or
ones (low data transition densities for a long period of time).
The GS9035A is designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).
9. PLL DESIGN GUIDELINES
The performance of the GS9035A is primarily determined
by the PLL. Thus, it is important that the system designer is
familiar with the basic PLL design equations.
A model of the GS9035A PLL is shown below. The main
components are the phase detector, the VCO, and the
external loop filter components.
Fig. 15 PLL Model
9.1 Transfer Function
The transfer function of the PLL is defined as Øo/Øi and can
be approximated as
Equation 1
where
N is the divider modulus
D is the data density (=0.5 for NRZ data)
ΙCP is the charge pump current in Amps
Kƒ is the VCO gain in Hz/V
This response has 1 zero (wZ) and three poles (wP1, wBW,
wP2) where
The bode plot for this transfer function is plotted in Figure 16.
LOCK
DDI
SDO VALID
DATA
NO DATA TRANSITIONS
VALID
DATA
OUTPUTS MUTED
LOOP
FILTER
Ø
i
Ø
o
VCO
Ι
CP
R
LF
K
PD
C
LF1
C
LF2
PHASE
DETECTOR
2πK
f
+
-
N
s
Øo
Øi
-------sCLF1RLF 1+
sC
LF1RLF
L
RLF
----------–
1+
----------------------------------------------------------------1
s2CLF2Ls
L
RLF
--------- 1++
---------------------------------------------------------
=
LN
DICPKƒ
--------------------=
wZ
1
CLF1RLF
-----------------------=
w
P1
1
CLF1RLF
L
RLF
---------–
---------------------------------------=
wBW
RLF
L
---------=
wP2
1
CLF2RLF
-----------------------=
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GS9035A
Fig. 16 Bode Plot for PLL Tra nsfer Function
The 3dB bandwidth of the transfer function is approximately
9.2 Transfer Function Peaking
There are two causes of peaking in the PLL transfer function
given by Equation 1.
The first is the quadratic
which has
and
This response is critically damped for Q = 0.5.
Thus, to avoid peaking:
or
Therefore,
wP2 > 4 wBW
However, it is desirable to keep wP2 as low as possible to
reduce the high frequency content on the loop filter.
The second is the zero-pole combination:
This causes lift in the transfer function given by
To keep peaking to less than 0.05dB,
wZ < 0.0057 wBW
9.3 Selection of Loop Filter Components
Based on the above analysis, select the loop filter
components for a given PLL bandwidth, ƒ3dB, as follows:
1. Calculate
where
ΙCP is the charge pump current and is a function of the
RVCO resistor and is obtained from Figure 17.
Kƒ = 90MHz/V for VCO frequencies corresponding to
the ƒL curve.
Kƒ = 140MHz/V for VCO frequencies corresponding to
the ƒH curve.
N is the divider modulus.
(ƒL, ƒH and N can be obtained from Table 2 or Table 3).
2. Choose RLF = 2(3.14) ƒ3dB (0.78)L
3. Choose CLF1 = 174 L / (RLF)2
4. Choose CLF2 = L/4(RLF)2
Fig. 17 Charge Pump Current vs. RVCO
W
Z
0
W
P1
W
BW
W
P2
FREQUENCY
AMPLITUDE (dB)
w3dB
wBW
12
wBW
wP2
------------
–wBW wP2
⁄()
2
12
wBW
wP2
------------
–
----------------------------------+
---------------------------------------------------------------------- wBW
0.78
------------
≈=
s2CLF2Ls
L
RLF
--------- 1++
wO
1
CLF2L
--------------------=QR
LF
CLF2
L
-------------=
RLF
CLF2
L
-------------1
2
---
<
1
RLFCLF2
-----------------------L
RLF
--------- 4>
sCLF1RLF 1+
sC
LF1RLF
L
RLF
-----------–
1+
-----------------------------------------------------------
s
wZ
-------1+
s
wP1
----------1+
--------------------=
20 LOGwP1
wZ
----------20 LOG 1
1wZ
wBW
------------–
---------------------
=
0
50
100
150
200
250
300
350
400
0 200 400 600 800 1000 1200 1400 1600 1800
CHARGE PUMP CURRENT (µA)
R
VCO
(Ω)
2N
ΙCPKƒ
L =
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GS9035A
9.4 Spice Simulations
More detailed analysis of the GS9035A PLL can be done
using SPICE. A SPICE model of the PLL is shown below:
Fig. 18 SPICE Model of PLL
The model consists of a voltage controlled current source
(G1), the loop filter components (RLF
, CLF1, and CLF2), a
voltage controlled voltage source (E1), and a voltage
source (V1). R2 is necessary to create a DC path to ground
for Node 1.
V1 is used to generate the input phase waveform. G1
compares the input and output phase waveforms and
generates the charge pump current, ΙCP
. The loop filter
components integrate the charge pump current to establish
the loop filter voltage. E1 creates the output phase
waveform (PHIO) by multiplying the loop filter voltage by
the value of the Laplace transform (2pKƒ/Ns).
The netlist for the model is given below. The .PARAM
statements are used to set values for ΙCP
, Kƒ, N, and D. ΙCP
is determined by the RVCO resistor and is obtained from
Figure 17.
SPICE NETLIST * GS9035A PLL Model
.PARAM ICP = 165E-6 KF= 90E+6
.PARAM N = 1 D = 0.5
.PARAM PI = 3.14
.IC V(Phio) = 0
.ac dec 30 1k 10meg
RLF 1 LF 1000
CLF1 1 0 15n
CLF2 0 LF 15p
E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)}
G1 0 LF VALUE{D * ICP/(2 *pi)*V(Phii, Phio)}
V1 2 0 DC 0V AC 1V
R2 0 1 1g
.END
10. I/O DESCRIPTION
10.1 High Speed Inputs (DDI/DDI)
DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:
1. Input signal amplitudes are between 200 and 2000mV
2. The common mode input voltage range is as specified
in the DC Characteristics table.
Commonly used interface examples are shown in
Figures 19 and 20.
Figure 19 illustrates the simplest interface to the GS9035A.
In this example, the driving device generates the PECL
level signals (800mV amplitudes) having a common mode
input range between 0.4 and 4.6V. This scheme is
recommended when the trace lengths are less than 1in. The
value of the resistors and the DC connection (VCC or
Ground), depends on the output driver circuitry of the
previous device.
Fig. 19 Simple Interface to the GS9035A
When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface for differential signals is shown in Figure 20. In this
case, a parallel resistor (RLOAD) is placed near the GS9035A
inputs to terminate the controlled impedance trace. The
value of RLOAD should be twice the value of the
characteristic impedance of the trace. Both traces should
be in a symmetric arrangement and same physical
transmission line dimensions since common-mode signals
or common-mode noise is not terminated. In addition,
series resistors, RSOURCE, can be placed near the driving
chip to serve as source terminations. They should be equal
to the value of the trace impedance. Assuming 800mV
output swings at the driver, RLOAD =100Ω, RSOURCE =50Ω
and ZO = 50Ω.
Fig. 20 Recommended Interface for Differential Signals
Figure 21 shows the recommended interface when the
GS9035A is driven single-endedly. In this case, the input
must be AC-coupled and a matching resistor (ZO) must be
used.
PHII
PHIO
R2
E1
RLF
CLF1 CLF2
G1
V1 2πKƒ
IN+
IN- Ns
1
LF
NOTE: PHII, PHIO, LF and 1 are node names in the SPICE netlist.
DDI
DDI
V
CC
or GND
V
CC
or GND
GS9035A
DDI
DDI
RSOURCE
RLOAD
RSOURCE
ZO
ZO
GS9035A
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GS9035A
Fig. 21 Recommended Interface for Single-Ended Dr iver
10.2 High Speed Outputs (SDO/SDO and SCO/SCO)
SDO/SDO and SCO/SCO are current mode outputs that
require external pullup resistors (see Figure 22). To
calculate the output sink current use the following
relationship:
Output Sink Current = Output Signal Swing / Pullup Resistor
A diode can be placed between Vcc and the pullup resistors
to reduce the common mode voltage by approximately 0.7
volts.When the output traces are longer than 1in, controlled
impedance traces should be used. The pullup resistors
should be placed at the end of the output traces as they
terminate the trace in its characteristic impedance (75Ω).
Fig. 22 High Speed Outputs with External Pullu ps
TYPICAL APPLICATION CIRCUIT
The figure below shows the GS9035A connected in a typical auto rate select SMPTE 259M application. Table 4 summarizes
the relevant system parameters.
DDI
DDI
ZOGS9035A
VCC
SDO
SDO
SCO
SCO
75Ω75Ω
VCC
75Ω75Ω
GS9035A
VCC
VCC
VCC
VCC
VCC
VCC VCC
VCC VCC
4 x 75
To
GS90201
To LED
Driver
(optional)
10k
1800 15n
3.3p
4.7n
0.1µ
0.1µ
}
From
GS9024
RVCO
RLF CLF1
CLF2
DDI
DDI
VEE
VEE
VCC1
AUTO/MAN
VEE
SMPTE
LOCK
COSC
VEE
CLK_EN
VEE
VCC3
GS9035A
TOP VIEW
LF+
LFS
LF-
RVCO_RTN
RVCO
CBG
VCC2
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12 13 14 15 16 17 18
4 3 2 1 28 27 26
SDO
SDO
SCO
SCO
SSO
SS1
SS2
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
Power supply decoupling
capacitors are not shown.
See application note "EB9035A"
for details on PCB artwork.
NOTE
1. The 75Ω pullup resistors on SDO/SDO and
SCO/SCO are not required when interfacing
the GS9035A to the GS9020 since the GS9020
has internal 75Ω resistors.
365
(1%)
522 - 41 - 08
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GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku,
Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright July 1999 Gennum Corporation. All rights reserved. Printed in Canada.
GS9035A
PACKAGE DIMENSIONS
TABLE 5: System Parameters
RVCO = 365Ω, ƒH = 540MHz, ƒL = 360MHz
SMPTE SS[2:0] DATA RATE (Mb/s) LOOP BANDWIDTH
1 000 143 1.2MHz
1 001 177 1.9MHz
1 010 270 3.0MHz
1 011 360 4.5MHz
1 100 540 6.0MHz
12.319
MIN
11.582 MAX
11.430 MIN
12.573
MAX
1.270
x 45
1.219
1.067
SEATING
PLANE
MIN 0.508
4.572 MAX
4.115 MIN
3.048 MAX
2.286 MIN
11.582 MAX
11.430 MIN
12.319
MIN
12.573
MAX
10.922 MAX
9.906 MIN
All dimensions in millimetres.
28 pin PLCC (QM)
REVISION NOTES:
Added lead-free and green information.
For latest product information, visit www.gennum.com
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
